NoC-oriented simulation system, simulation method, computer program and physical host

Abstract

The embodiment of the invention provides an NoC-oriented simulation system, a simulation method, a computer program and a physical host, and the simulation system comprises at least one simulation virtual machine which is deployed on a virtualization platform and is dispatched and operated by a processor core; the simulation virtual machine is used for executing a simulation service program; the virtual network-on-chip is used for intercepting a communication transaction which is sent by the processor core and needs to be transmitted through the NoC, and if the communication transaction is identified as a target communication transaction triggered by the simulation virtual machine, the target communication transaction is forwarded to the system simulation control layer; the system simulation control layer is used for performing simulation processing on the target communication transaction based on the NoC simulation network structure to form a simulation result of the target communication transaction; and the clock adjuster is used for synchronously controlling the clock of the simulation virtual machine, the clock of the virtual network-on-chip and the clock of the system simulation control layer so as to align the time sequence. According to the embodiment of the invention, the simulation speed and precision can be considered, and the NoC-oriented simulation speed and simulation precision are improved.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of processor technology, and more particularly to a NoC-oriented simulation system, simulation method, computer program, and physical host. Background Art

[0002] The Network on Chip (NoC) is a fundamental communication network within a chip that enables communication between various modules. It serves a wide range of latency- and bandwidth-sensitive applications. For example, a NoC can connect multiple processor cores, memory controllers, and other on-chip functional modules. The NoC has become a key factor in determining performance, power consumption, and scalability in multi-core processor systems. Therefore, exploring NoC architectures has become a crucial step in chip design.

[0003] NoC architecture exploration relies on simulation technology. Mainstream software simulators provide cycle-accurate modeling capabilities and can simulate NoC internal communication behaviors. However, the simulation speed is significantly slower than the actual processor hardware, making it difficult to efficiently explore large-scale NoC architectures. Therefore, FPGAs (Field Programmable Gate Arrays) can be introduced for simulation acceleration. Although FPGA simulation speeds are improved compared to pure software simulators, the high device development cost, complex design verification, and long iteration cycles of FPGAs limit their application in NoC architecture exploration.

[0004] Therefore, how to provide a NoC-oriented simulation solution that takes into account both simulation speed and accuracy has become a technical problem that technical personnel in this field urgently need to solve. Summary of the Invention

[0005] In view of this, embodiments of the present application provide a NoC-oriented simulation system, simulation method, computer program, and physical host to balance simulation speed and accuracy, thereby improving NoC-oriented simulation speed and simulation accuracy.

[0006] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides a NoC-oriented simulation system, including:

[0008] At least one simulated virtual machine is deployed on the virtualization platform and scheduled to run by the processor core; the simulated virtual machine is used to execute a simulated business program, which is a partial program extracted from a real machine program;

[0009] The virtual on-chip network is used to intercept communication transactions sent by the processor core that need to be transmitted through the NoC. If the communication transaction is identified as a target communication transaction triggered by the simulation virtual machine, the target communication transaction is forwarded to the system simulation control layer;

[0010] The system simulation control layer is used to simulate the network structure based on NoC, simulate the target communication transaction, and generate the simulation results of the target communication transaction;

[0011] A clock adjuster is used to synchronize the clocks of the simulated virtual machine, the virtual on-chip network, and the system simulation control layer, so as to align the timing between the simulated virtual machine, the virtual on-chip network, and the system simulation control layer when the virtual on-chip network intercepts the target communication transaction and when the system simulation control layer completes the simulation processing of the target communication transaction.

[0012] In a second aspect, an embodiment of the present application provides a NoC-oriented simulation method, which is applied to the NoC-oriented simulation system described in the first aspect. The simulation method includes:

[0013] Intercept communication transactions from processor cores that need to be transmitted through the NoC;

[0014] Identifying whether the communication transaction is a target communication transaction triggered by a simulated virtual machine; wherein at least one simulated virtual machine is deployed on a virtualization platform and scheduled to run by a processor core, the simulated virtual machine is used to execute a simulated business program, and the simulated business program is a partial program extracted from a real machine program;

[0015] If the communication transaction is a target communication transaction triggered by a simulation virtual machine, the target communication transaction is simulated based on the simulation network structure of the NoC to generate a simulation result of the target communication transaction;

[0016] Furthermore, when the target communication transaction is intercepted and the simulation processing of the target communication transaction is completed, the clocks involved in the target communication transaction are synchronously controlled to align the timing.

[0017] In a third aspect, an embodiment of the present application provides a computer program, comprising computer-executable instructions, which, when executed by a processor, implement the NoC-oriented simulation method as described in the second aspect above.

[0018] In a fourth aspect, an embodiment of the present application provides a physical host, wherein the NoC-oriented simulation system as described in the first aspect above and the cooperating components of the simulation system are deployed on the physical host;

[0019] The mating assembly comprises:

[0020] Virtual machine manager, which provides a virtualization environment to support the deployment of simulated virtual machines;

[0021] Ordinary programs run by the processor core;

[0022] Real NoC;

[0023] Memory and peripherals.

[0024] The NoC-oriented simulation system provided by the embodiment of the present application, by deploying a simulation virtual machine on a virtualization platform, the simulation virtual machine loads and executes the simulation business program, and the simulation business program is a part of the program extracted from the real machine program, which enables the simulation system to directly reproduce the communication transactions that need to be transmitted through the NoC in the real scene without constructing artificial test cases, that is, the triggering timing and program logic of the communication transactions that need to be transmitted through the NoC are consistent with the real scene, thereby improving the accuracy of the NoC architecture simulation. On this basis, the embodiment of the present application introduces a virtual on-chip network to intercept the communication transactions that need to be transmitted through the NoC issued by the processor core. Since the simulation virtual machine is scheduled and run by the processor core, the communication transactions that need to be transmitted through the NoC during the execution of the simulation business program by the simulation virtual machine will also be intercepted by the virtual on-chip network. If the virtual on-chip network identifies the intercepted communication transaction as the target communication transaction triggered by the simulation virtual machine, the target communication transaction is regarded as a task that needs to be modeled by the simulation system and is handed over to the system simulation control layer for high-precision simulation processing. At this time, the system simulation control layer can combine the simulation network structure of the NoC to simulate the target communication transaction and form a simulation result of the target communication transaction. At the same time, a clock adjuster coordinates and manages the clocks of the simulation virtual machine, virtual network on chip, and system simulation control layer to ensure timing alignment and achieve precision-controlled NoC communication behavior modeling. Therefore, the embodiments of the present application not only achieve high-precision simulation processing of target communication transactions, but also reduce unnecessary simulation computing overhead, providing a simulation solution for NoC architecture exploration that balances real load, flexibility, and efficiency, and improves the simulation speed and accuracy for NoC.

[0025] Specifically, the virtual network on chip of the embodiment of the present application is essentially a transaction interception mechanism, which can be regarded as an extended application of the trap mechanism in NoC simulation. That is, when the processor core schedules the simulation virtual machine to run, all communication transactions that need to be transmitted through the NoC are intercepted by the virtual network on chip on the communication path. When the intercepted communication transaction is identified as the target communication transaction triggered by the simulation virtual machine, the system simulation control layer is trapped to simulate the target communication transaction, thereby realizing on-demand simulation modeling of the target communication transaction. This mechanism avoids the performance bottleneck brought about by the cycle-level modeling of the full amount of communication transactions, ensures the exploration of NoC architecture with controllable accuracy and cost, and takes into account both simulation efficiency and simulation accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0027] Figure 1 This is the connection topology diagram of NoC.

[0028] Figure 2 An example diagram of a simulation system that collaborates with software and hardware.

[0029] Figure 3 An example diagram of the permission level mechanism and instruction execution process transition in virtualization technology.

[0030] Figure 4 This is an example diagram of a NoC-oriented simulation system provided in an embodiment of the present application.

[0031] Figure 5 This is an example diagram of the identification and diversion of communication transactions.

[0032] Figure 6 This is an example diagram of the deployment of the physical host of the application simulation system provided in an embodiment of the present application.

[0033] Figure 7 This is an example diagram of the NoC-oriented simulation process provided in an embodiment of the present application.

[0034] Figure 8 Another example diagram of the NoC-oriented simulation process provided in an embodiment of the present application.

[0035] Figure 9 A flowchart of a NoC-oriented simulation method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] With the continuous evolution of high-performance processor design, the scope for processor architecture exploration is expanding. Processors contain numerous components, such as L1 cache, L2 cache, L3 cache, branch predictors, and cache prefetchers. The optimal design of these components, including their organization, structural parameters, and communication paths, often requires evaluation through simulation technology. However, for complex processor models, the execution of a single instruction requires multiple stages, including instruction fetch, decode, execute, writeback, and commit. This is extremely time-consuming in simulation environments, especially for cycle-accurate simulators.

[0038] Furthermore, as process technology approaches physical limits, relying on increasing the main frequency to enhance processor performance is unsustainable. Therefore, current performance improvements rely more on microarchitecture optimization and multi-core parallel expansion. However, the widespread deployment of multi-core processors has also significantly increased the communication pressure on the processors. Traditional bus structures such as the ring bus are no longer able to meet the communication bandwidth and latency requirements when dealing with a large number of processor cores. As a result, more complex interconnect architectures such as mesh and hybrid structures have been gradually proposed and are collectively classified as NoC. NoC technology has gradually become a decisive factor in improving processor performance.

[0039] For ease of understanding, Figure 1 The NoC connection topology diagram is shown as an example. The NoC connection topology structure can be applied to a multi-core on-chip computing system with NoC as the communication backbone. The multi-core on-chip computing system can be deployed on a physical host, such as a terminal device, a server device, etc. Figure 1 ,The connection topology of a NoC can include:

[0040] Multiple processor cores, where the processor core is used to execute computing tasks and process instruction streams, and is the main computing resource of the multi-core on-chip computing system;

[0041] Memory controller, used to manage access requests to off-chip memory and implement data communication between on-chip and off-chip memory;

[0042] Input / output (IO) modules, such as peripheral controllers and bus interfaces, are used for data exchange between multi-core on-chip computing systems and IO devices.

[0043] NoC, as the communication infrastructure between the above modules, is responsible for completing tasks such as data packet routing, flow control, and priority scheduling.

[0044] As can be seen, the NoC serves as the core communication hub of multi-core on-chip computing systems, connecting functional modules such as processor cores, memory controllers, and input / output modules, interconnecting these modules to support concurrent data transmission. On this basis, the NoC not only provides high-bandwidth, low-latency communication paths but also ensures data transmission efficiency and overall system performance in multi-task concurrent execution scenarios through mechanisms such as congestion control, path scheduling, and quality of service management. NoC design not only requires high bandwidth and low latency but also supports complex load scheduling, consistency protocols, and multi-tenant task management. The design complexity of the NoC approaches or even exceeds that of the processor core itself.

[0045] In the above context, the architectural exploration of NoC becomes particularly critical. In order to conduct structural verification and performance evaluation before chip tape-out, simulation technology is widely used to evaluate the performance of NoC.

[0046] However, although mainstream software simulators have cycle-accurate capabilities, their simulation speed is thousands of times slower than that of real processors, making it difficult to support large-scale structural exploration and real-world load analysis of NoCs. Therefore, FPGA hardware combined with software simulation can be used for simulation acceleration, thereby supporting the modeling of more processor cores within resource constraints and achieving simulation speeds dozens of times faster than pure software simulators. Figure 2 An example diagram of a software-hardware collaborative simulation system is shown, which integrates an FPGA hardware acceleration platform with a software simulation platform to accelerate the simulation process.

[0047] like Figure 2 As shown, the hardware-software collaborative simulation system includes: an FPGA platform and a software platform; wherein, the FPGA platform is a hardware simulation acceleration system built using FPGA, and the software platform is a software-based simulation control system. The FPGA platform and the software platform exchange data and synchronize states through the underlying communication mechanism, and collaboratively constitute a hardware-software joint simulation system.

[0048] The FPGA platform configuration has the following components:

[0049] The Timing Partition component is used to model the timing behavior of processor instructions, such as simulating pipeline stages such as fetch, decode, and execute, to ensure the timing accuracy of instruction execution;

[0050] Functional Partition component, used to model the functional behavior of the processor, such as the operation of the arithmetic logic unit (ALU) and memory access logic, and cooperates with the timing partition component to realize the functional simulation of the processor;

[0051] The Control component is used to control the execution process, such as enabling signal scheduling and operation sequence management. It is the core coordination and control unit on the FPGA side.

[0052] The platform interface connects the upper-layer timing partitioning components and functional partitioning components with the lower-layer communication structure, enabling interaction between the processor model (the processor model is simulated by the timing partitioning components and functional partitioning components) and the FPGA virtual platform;

[0053] The FPGA virtual platform (Virtual Platform) is located between the platform interface and the FPGA physical platform, supporting the collaborative operation between the upper-level modules and the underlying hardware. The FPGA virtual platform can be configured with the following sub-modules: Scratchpad Memory, used to cache shared data or temporary variables; Remote Memory, used to access memory resources outside the FPGA; Standard Input / Output (STDIO) module, used for input and output interaction, such as redirecting the output information of the processor model to the software platform; RRR (Remote Request Response) module, used to establish request and response communication between the software platform and the FPGA platform; Channel module, used to transmit data streams, including instructions, memory status, register information, etc.

[0054] The FPGA physical platform is regarded as the underlying FPGA hardware resources, such as boards, which implement the operation of simulation logic on physical devices.

[0055] The software platform is configured with the following components:

[0056] The Software Services component, the core operating logic of the software platform, is responsible for executing high-level tasks related to simulation. The Software Services component can be configured with the following submodules: the Emulate module, which provides system-level or instruction-level behavior modeling; the Memory State management module, which manages virtual memory states; and the Streams module, which handles data stream interactions.

[0057] The Control component is used for software task scheduling and state control, including simulation task startup, pause, timeout processing, and retry logic;

[0058] The software virtual platform, located between the software service component and the software physical platform, serves as the interface layer for software and hardware communication. The software virtual platform can be configured with the following submodules: an RRR module for sending requests and receiving responses; and a Channel module for transmitting data streams. Modules in the software service component can be connected to the RRR module in the software virtual platform via interfaces, and control components can be connected to the RRR module in the software virtual platform via signal paths.

[0059] The software-physical platform is considered as the host hardware environment for running software simulation, which is used to execute control logic, run simulation tools, and communicate with the FPGA physical platform through the underlying interface.

[0060] In this collaborative hardware-software simulation platform, the FPGA and software platforms jointly build the functional and timing modeling capabilities of the processor architecture. The FPGA platform handles the modeling of computationally intensive and timing-sensitive modules within the processor model (e.g., modules involved in pipeline stages like instruction fetch, decode, and execution). Through the RRR and Channel mechanisms within the FPGA virtual platform module, it maintains communication with the software platform, accelerating the simulation process. This division of labor between hardware and software improves overall simulation performance to a certain extent, alleviating the low efficiency of pure software simulators.

[0061] However, FPGA-accelerated simulation models also face many challenges. On the one hand, their design and deployment rely on RTL (Register Transfer Level) development, which has a long development cycle, complex debugging, poor flexibility, and difficulty supporting rapid iteration. On the other hand, as the complexity of processor architectures increases, relying on FPGA hardware acceleration still cannot cover large-scale structural exploration and dynamic behavior modeling driven by real loads, and simulation systems are prone to resource bottlenecks.

[0062] Based on this, the simulation system can introduce hardware-assisted paravirtualization technology (such as KVM, Kernel-based Virtual Machine) to build a collaborative execution mechanism that combines virtualization promotion with simulation switching. This mechanism improves simulation efficiency by directly handing over most instructions to the underlying processor core for execution and switching to simulation mode only when entering the key analysis stage of the simulation.

[0063] For ease of understanding, Figure 3 The following is an example diagram showing the transition of the permission level mechanism and instruction execution process in virtualization technology, as shown in FIG. Figure 3As shown in the figure, in the hardware-level privilege management mechanism provided by the processor, there are four CPU privilege levels, namely Ring0 to Ring3; among them, Ring0 is the highest privilege level, used for the operating system (OS, Operating System) kernel, which can directly access all hardware resources and execute all privileged instructions; Ring1 is the second highest privilege level, used for drivers, which can access some restricted resources; Ring2 is the medium privilege level, used for device service programs, and Ring2 can be the theoretically reserved CPU privilege level; Ring3 is the lowest privilege level, used for application programs (APP, Application Program);

[0064] Combine Figure 3 As shown in the figure, in a virtualized environment, Ring0 permissions are taken over by the VMM (Virtual Machine Monitor), so that the execution permissions of the operating system are downgraded to Ring1, forming a Ring-downgraded virtualization mode; at this time, the privileged instructions of the operating system cannot directly access the underlying physical resources, but are intercepted and executed in simulation through the VMM; specifically, when the operating system executes privileged instructions in Ring1, a trap mechanism is triggered, causing the processing flow to be transferred from the operating system to the VMM, and the VMM running in Ring0 processes the privileged instructions of the operating system in simulation. This process is called trap simulation, and the trap simulation mechanism is the basis of hardware-assisted paravirtualization technology.

[0065] With the help of hardware-assisted paravirtualization technology, the simulation system can advance program execution at speeds close to those of a real machine. When the program reaches the critical analysis stage of the simulation (for example, when executing a program segment that requires simulation analysis), a trap mechanism switches the execution context to the simulator, enabling detailed simulation and observation of the underlying behavior, thereby maximizing processor resource utilization and improving execution efficiency. Therefore, hardware-assisted paravirtualization technology is suitable for use as a program advancer in simulation systems, that is, it is used to quickly advance program execution to the critical analysis stage of the simulation and then switch to the simulator for analysis.

[0066] However, virtualization technologies like KVM, originally optimized for server and desktop virtualization, lack controllability and observability of underlying hardware resources, making them difficult to meet microarchitecture-level modeling requirements. Furthermore, in the context of NoC architecture exploration, the challenges are more complex than exploring the static structure of processor cores. On the one hand, the design space for NoCs is extensive, encompassing multiple dimensions such as topology, routing protocols, cache coherence, and task mapping. On the other hand, under real-world loads, communication behavior in NoCs exhibits highly dynamic behavior and nonlinear bottlenecks, making it difficult to accurately predict through static modeling.

[0067] Therefore, considering the challenges of NoC architecture exploration, it is particularly important to provide a NoC-oriented simulation solution that takes both simulation efficiency and accuracy into consideration.

[0068] Based on this, an embodiment of the present application proposes a simulation system for NoC architecture exploration, aiming to solve the problems of low simulation efficiency, insufficient simulation accuracy, and inability to balance real load and communication modeling in NoC architecture exploration, and provide a simulation solution that balances simulation speed and accuracy.

[0069] As an optional implementation, Figure 4 The example diagram of the NoC-oriented simulation system provided in the embodiment of the present application is shown as an example, and the simulation system is used to perform high-precision performance modeling and timing behavior simulation on the NoC in the chip such as SoC (System on Chip) on a virtualized platform. Figure 4 As shown, the simulation system may include at least:

[0070] Simulated Virtual Machine (SVM) 410 , Virtual Network on Chip (VNoC) 420 , Simulation System Control Layer (SSCL) 430 , and Timing Regulator (TR) 440 .

[0071] The simulation virtual machine 410 is deployed on a virtualization platform and is scheduled and run by a processor core; the simulation virtual machine is used to execute simulation business programs, which are partial programs extracted from real machine programs.

[0072] Specifically, a simulated virtual machine (SVM) is a virtual machine instance deployed by the simulation system on a virtualization platform (such as KVM). It runs in a virtualization environment built by the virtual machine manager, which can provide the SVM with operating characteristics similar to those of a real physical host (such as instruction set support, virtual memory management, system call interface simulation, etc.). At the same time, the processor core, as the underlying computing resource, not only executes the operating system and user programs (such as ordinary programs), but also undertakes the scheduling and running tasks of the simulated virtual machines deployed in the virtualization platform, thereby driving the simulated virtual machines to run simulated business programs. In other words, although the simulated virtual machine is deployed on the virtualization platform, the processor core is the underlying hardware computing resource, and all running instructions of the simulated virtual machine are actually scheduled and executed by the processor core. Therefore, the communication transactions initiated by the simulated virtual machine are ultimately output by the processor core.

[0073] In an embodiment of the present application, a simulation virtual machine loads and executes a simulation business program, which is a partial program extracted from a real machine program, so that the simulation business program loaded and executed by the simulation virtual machine can also be referred to as a real machine load (Real Workload, RWL). For example, the simulation business program can be obtained by slicing, pattern extraction, traffic analysis or behavior modeling of the real machine program, such as slicing or pattern extraction or traffic extraction of the real machine program to obtain a simulation business program, i.e., a real machine load, thereby truly reflecting the NoC communication load characteristics generated during the operation of the real machine program, for driving the simulation process. In other words, the real machine program is an application program running in a real processor or a real operating system, involving various complex logics, IO calls, network communications, etc., and the simulation business program (i.e., real machine load) is derived from the real machine program and can truly reflect the NoC communication load characteristics during the operation of the real machine program. Tasks, thereby deploying the real machine load in the simulation virtual machine to run, to generate communication transactions involving NoC, for use in simulation system modeling and performance evaluation.

[0074] In an optional implementation, based on the specific simulation business scenario of the simulation system, the embodiment of the present application can arrange at least one (one or more) simulation virtual machines, that is, the number of simulation virtual machines in the simulation system can be one or more. At the same time, the simulation business program loaded and executed by the simulation virtual machine can also be based on the specific simulation business scenario. For example, when testing the performance of the simulation network structure of the NoC under the peripheral access scenarios such as memory access and IO device access of the simulation virtual machine, the simulation system can arrange a single simulation virtual machine and load the simulation business programs related to peripheral access such as memory access and IO device access; for example, when testing the performance of the simulation network structure of the NoC under the communication scenario between the client and the server, the simulation system can arrange multiple simulation virtual machines and divide the client simulation virtual machine and the server simulation virtual machine, and the client simulation virtual machine loads the client-related simulation business program, and the server simulation virtual machine loads the server-related simulation business program. The deployment of simulation virtual machines and the simulation process under specific simulation business scenarios will be explained in detail later.

[0075] The virtual network on chip (VNoC) 420 is used to intercept communication transactions sent by the processor core that need to be transmitted through the NoC. If the communication transaction is identified as a target communication transaction triggered by the emulated virtual machine, the target communication transaction is forwarded to the system emulation control layer 430.

[0076] In an optional implementation, a virtual network on chip (VNoC) is logically deployed on the communication path of the processor core and is located before the real NoC, acting as an interceptor and simulation agent for communication transactions. Specifically, relative to the processor core, the resources accessed by the processor core are mainly divided into:

[0077] Cache resources, including private caches owned by processor cores (such as L1 and L2 caches) and shared caches shared between processor cores (such as L3 caches). Cache resources are integrated into or tightly coupled with the processor cores and are used for high-speed data access by the processor cores.

[0078] Peripheral resources, such as memory and I / O devices. Memory is managed by a memory controller, and the processor core accesses the memory controller through the NoC to read and write data to the memory. Various peripheral controllers are connected to various I / O devices, and the processor core accesses the peripheral controllers through the NoC to read and write data to the I / O devices.

[0079] In other words, the processor core cannot directly access peripherals such as memory and IO devices. The processor core's request to access memory, IO devices and other peripherals must be routed through the NoC to the corresponding controller (such as a memory controller or peripheral controller, etc.). For example, the processor core's request to access memory must be routed through the NoC to the memory controller, and the processor core's request to access IO devices must be routed through the NoC to the corresponding peripheral controller. Therefore, when the processor core accesses data, if the accessed data hits the private cache or shared cache, the NoC request will not be triggered; if the accessed data does not hit the cache, a NoC request will be triggered, and the NoC request will be routed to the corresponding controller (such as a memory controller or peripheral controller, etc.) through the NoC. Therefore, the virtual on-chip network logically deployed on the communication path of the processor core's communication transaction can intercept the communication transaction issued by the processor core that needs to be transmitted through the NoC.

[0080] Specifically, when testing the performance of the NoC's simulated network structure in peripheral access scenarios such as memory access and IO device access of the simulated virtual machine, the simulated virtual machine can load simulated business programs related to peripheral access such as memory access and IO device access. Therefore, in the process of the simulated virtual machine executing the simulated business programs, the processor core will initiate peripheral communication transactions to access peripherals such as memory or IO devices through the NoC. The peripheral communication transactions need to be sent to the memory controller or peripheral controller through the NoC, and the virtual on-chip network can intercept and filter the peripheral communication transactions before they enter the transmission path of the real NoC, and forward them to the system simulation control layer for simulation processing, thereby realizing fine simulation of NoC communication behavior in peripheral access scenarios such as memory access and IO device access.

[0081] Specifically, when testing the performance of the NoC's simulated network structure in a communication scenario between a client and a server, there is a need for communication between the client's simulated virtual machine and the server's simulated virtual machine. Therefore, during the execution of their respective simulated business programs by the client's simulated virtual machine and the server's simulated virtual machine, the processor core initiates communication transactions between the simulated virtual machines through the NoC. The virtual on-chip network can then intercept and filter these communication transactions before they enter the transmission path of the real NoC, and forward them to the system simulation control layer for simulation processing, thereby achieving a fine simulation of the NoC's communication behavior in the communication scenario between the client and the server. Furthermore, if the client's simulated virtual machine and the server's simulated virtual machine are deployed on different processor cores, the communication between the simulated virtual machines is considered to be communication between processor cores, enabling a fine simulation of the NoC's communication behavior in the communication scenario between processor cores.

[0082] It should be noted that the virtual network-on-chip (NOC) can exist as a software module within the simulation system. Interception logic is embedded at the trigger point where the processor core initiates a communication transaction that needs to be transmitted through the NoC. This intercepts the communication transactions issued by the processor core, filters the target communication transactions triggered by the simulation virtual machine from the intercepted communication transactions, and redirects the target communication transactions of the simulation virtual machine to the system simulation control layer for processing, thereby achieving modeling and analysis of the NoC interconnect structure. In other words, the virtual NOC is logically deployed along the communication path where the processor core issues the communication transaction. This does not refer to a physical hardwired deployment, but rather a path proxy at the logical or software level. In other words, the virtual NOC is not inserted between the processor core and the real NoC in hardware form, nor is it connected between the processor core and the real NoC at the physical connection level. Instead, it intercepts the communication transaction at the logical point in the path at the software layer or virtualization system through mechanisms such as hooks, interrupts, page table protection, and device proxies, forming a logical proxy layer that acts as a virtual NOC, thereby intercepting the communication transactions issued by the processor core.

[0083] It's important to explain that the processor core, as the underlying execution entity, runs both standard programs executed under the operating system and simulated virtual machines deployed on the virtualization platform. Standard programs primarily refer to non-simulation-related system tasks or applications, whose communication transactions do not require simulation analysis and can be directly transmitted to the real NoC for processing. The simulated virtual machine, on the other hand, runs simulated business programs, which are derived from real-machine programs and constructed through slicing, abstraction, or reconstruction of the real-machine programs. Their purpose is to reproduce NoC-related behaviors such as memory access, I / O reads and writes, and inter-core communication in a simulated environment.

[0084] On this basis, because the virtual on-chip network is logically deployed on the communication path of the processor core's communication transactions and is located before the real NoC, it has the ability to intercept and identify all communication transactions from the processor core, including communication transactions involving the NoC issued by ordinary programs running on the processor core and communication transactions involving the NoC issued by the simulated virtual machine running on the processor core. In other words, the communication transactions intercepted and received by the virtual on-chip may include:

[0085] Communication transactions generated during the execution of normal programs by the processor core are identified as types that do not require simulation and can be directly released and transmitted to the real NoC for processing;

[0086] The processor core runs a simulated virtual machine, and the simulated virtual machine generates communication transactions during the execution of the simulated business program. In this case, some or all of the communication transactions generated by the simulated virtual machine that need to be transmitted through the NoC are regarded as target communication transactions triggered by the simulated virtual machine; thus, the virtual on-chip network can transfer the target communication transactions issued by the simulated virtual machine to the system simulation control layer for simulation processing, thereby realizing communication modeling and performance analysis of the simulated network structure of the NoC.

[0087] It should be noted that the type of target communication transaction triggered by the simulated virtual machine can depend on the specific simulation business scenario, and the embodiments of the present application do not set any limitations. For example, when using a single simulated virtual machine to test the performance of the simulated network structure of the NoC in peripheral access scenarios such as memory access and IO device access, the target communication transaction triggered by the simulated virtual machine can be a peripheral communication transaction for the simulated virtual machine to access memory or IO devices; in this case, the non-peripheral communication transactions of the simulated virtual machine are regarded as non-target communication transactions and are not simulated, but are transmitted to the real NoC for processing.

[0088] For example, when using a client emulation virtual machine and a server emulation virtual machine to test the performance of the NoC emulation network structure in a communication scenario between the client and the server, the target communication transaction triggered by the emulation virtual machine may include any of the following:

[0089] Before the server-side emulation virtual machine and the client-side emulation virtual machine have no communication interaction, the server-side emulation virtual machine accesses the memory or peripheral communication transactions of the IO device;

[0090] The client simulates the server communication transaction initiated by the virtual machine;

[0091] After the client emulation virtual machine initiates the first server communication transaction, the server emulation virtual machine initiates the communication transaction that needs to be transmitted through the NoC.

[0092] Furthermore, when the virtual network on chip intercepts the target communication transaction issued by the simulated virtual machine, the embodiment of the present application can also suspend the operation of the simulated virtual machine to ensure that the simulated virtual machine can be suspended at the transaction point corresponding to the target communication transaction, and wait for the system simulation control layer to complete the simulation processing before resuming execution, thereby ensuring the accuracy of the NoC communication modeling of the target communication transaction. Specifically, when the virtual network on chip intercepts the target communication transaction issued by the simulated virtual machine, it indicates that the simulation has entered the key analysis stage. If the simulated virtual machine is not suspended, and the simulated virtual machine continues to execute subsequent instructions, the simulation system may not be able to complete the transaction model inversion corresponding to the target communication transaction in time, resulting in inconsistent timing and unrealistic modeling. Therefore, in order to ensure the consistency and accuracy of the simulation, the virtual network on chip can suspend the execution of the simulated virtual machine to prevent timing disorder, thereby waiting for the system simulation control layer to complete the simulation processing corresponding to the target communication transaction, and then resume the execution process of the simulated virtual machine to ensure the consistency and accuracy of the simulation.

[0093] In a further optional implementation, the embodiment of the present application can identify whether the communication transaction intercepted by the virtual on-chip network is a target communication transaction through the identification information of the communication transaction, and then when it is identified that the communication transaction is a non-target communication transaction (such as the communication transaction of an ordinary program, etc.), the communication transaction is transmitted to the real NoC. When it is identified that the communication transaction is a target communication transaction triggered by a simulated virtual machine (the transaction type of the target communication transaction can refer to the example in the corresponding part of the previous text), the communication transaction is forwarded to the system simulation control layer for simulation processing, and the operation of the simulated virtual machine is suspended.

[0094] In an optional implementation, the identification information of the communication transaction includes at least one of the following:

[0095] The virtual machine identifier or program identifier that initiates the communication transaction;

[0096] The access target address of the communication transaction;

[0097] The transaction type of the communication transaction.

[0098] For example, taking the simulation scenario of the client and the server as an example, if the virtual machine identifier of the initiating communication transaction is the client simulation virtual machine, and the access target address falls within the address mapping range of the server simulation virtual machine, then the communication transaction is a server communication transaction initiated by the client simulation virtual machine and is regarded as a target communication transaction; further, through the number of times the client simulation virtual machine initiates the server communication transaction, it can be identified whether the server communication transaction currently initiated by the client simulation virtual machine is the first server communication transaction. After the client simulation virtual machine initiates the first server communication transaction, all communication transactions initiated by the server simulation virtual machine that need to be transmitted through the NoC are regarded as target communication transactions. At this time, the virtual machine identifier and access target address of the communication transaction can be used to determine whether the communication transaction is a communication transaction between the server simulation virtual machine and the client simulation virtual machine, or a peripheral communication transaction between the server simulation virtual machine and peripherals such as memory and IO devices.

[0099] It can be seen that in the embodiment of the present application, all communication transactions of the processor core will first enter the virtual on-chip network after being issued, rather than directly entering the real NoC; the virtual on-chip network determines the source, access target and purpose of the communication transaction based on the identification information of the communication transaction (such as ID information, etc.); if the communication transaction is confirmed to be from an ordinary program based on the identification information of the communication transaction, no simulation processing is required, and the communication transaction is transmitted to the real NoC for processing; if the communication transaction is confirmed to be a target communication transaction triggered by a simulated virtual machine based on the identification information of the communication transaction, it is considered that this is the critical analysis stage of the simulation, and the execution of the simulated virtual machine is suspended, and the target communication transaction is transferred to the system simulation control layer for simulation processing.

[0100] For further understanding, Figure 5 The following diagram exemplifies the identification and diversion of communication transactions. Figure 5As shown in the figure, the objects run by the processor core include SVM0 and ordinary program 1. SVM0 is a simulated virtual machine that runs a real machine load. Both SVM0 and ordinary program 1 may issue communication transactions during operation. All communication transactions are uniformly pre-processed and diverted through the virtual on-chip network. The flow path of the target communication transaction of SVM0 is shown as the solid arrow in the figure, and the flow path of the communication transaction of ordinary program 1 is shown as the dotted arrow in the figure. Assume that the ID of SVM0 is 0 and the ID of ordinary program 1 is 1. Therefore, after intercepting a communication transaction, the virtual on-chip network can read the identification information in the communication transaction and determine the source, access target and purpose of the communication transaction. If the identification information in the communication transaction indicates ID=1, the communication transaction originates from Ordinary programs do not need to participate in simulation and are transparently transmitted to the real NoC for processing; if the transaction identification information in the communication transaction indicates ID = 0, the communication transaction originates from SVM0. At this time, it is further determined whether the access target address of the communication transaction corresponds to the access target address of the target communication transaction (the access target address of the target communication transaction depends on the specific simulation business scenario, such as the peripheral address in the scenario where a single virtual machine accesses memory, IO devices and other peripherals, the address of the server-side simulation virtual machine in the scenario where the client-side simulation virtual machine accesses the server-side simulation virtual machine, etc.). If so, the communication transaction is the target communication transaction, and the virtual on-chip network transfers the communication transaction to the system simulation control layer for simulation processing. At the same time, the operation of SVM0 is suspended and the simulation result feedback is waited for.

[0101] In a further optional implementation, the virtual on-chip network may forward the target communication transaction to the system simulation control layer by:

[0102] The virtual network on chip writes the target communication transaction into the cache area of ​​the virtual network on chip to temporarily store the target communication transaction, and sends an interrupt notification to the system simulation control layer to remind the system simulation control layer that there is currently a simulation transaction to be processed; so that after receiving the interrupt notification, the system simulation control layer can read the target communication transaction in the cache area of ​​the virtual network on chip to enable the virtual network on chip to forward the target communication transaction to the system simulation control layer.

[0103] That is to say, the virtual on-chip network can first write the target communication transaction into the cache area of ​​the virtual on-chip network (such as the transaction queue of the virtual on-chip network) and suspend the execution of the simulated virtual machine. At the same time, the virtual on-chip network sends an interrupt notification to the system simulation control layer, prompting the system simulation control layer to read the target communication transaction from the cache area of ​​the virtual on-chip network (such as the transaction queue) for simulation processing, so as to wait for the system simulation control layer to complete the simulation processing before resuming the execution process of the simulated virtual machine to ensure the consistency and accuracy of the simulation.

[0104] The system simulation control layer 430 is used to simulate the target communication transaction based on the simulation network structure of the NoC to generate a simulation result of the target communication transaction.

[0105] The system simulation control layer is the core processing module of the simulation system. It is mainly responsible for simulating the target communication transactions triggered by the simulation virtual machine during the execution of the simulation business program, ensuring that the simulation process can reflect the communication behavior of the NoC.

[0106] In an optional implementation, the system simulation control layer can be implemented as a software module with simulation processing and simulation result feedback capabilities. During the simulation execution process, the system simulation control layer receives target communication transactions forwarded by the virtual on-chip network and simulates the target communication transactions based on the simulated network structure of the NoC (such as a simulated Mesh, Torus, or other NoC topology). This includes, but is not limited to, forwarding path simulation between NoC nodes, bus conflict and queuing simulation, etc., so that the simulation process can reflect the communication behavior of the NoC. After the simulation processing is completed, the system simulation control layer generates simulation results corresponding to the target communication transactions.

[0107] For example, if the target communication transaction is a peripheral communication transaction, the system simulation control layer can call the access behavior model that matches the peripheral communication transaction based on the simulation network structure of the NoC, perform simulation processing of the peripheral communication transaction, and form a simulation result of the peripheral communication transaction. That is, based on the simulation network structure of the NoC and the access behavior model of the peripheral communication transaction, the software simulation processing of the peripheral communication transaction is performed through the simulation network structure of the NoC to the peripheral or memory, the peripheral communication transaction is completed from the simulation perspective, and the simulation result is generated.

[0108] Specifically, if the target communication transaction is a peripheral communication transaction accessing peripherals or memory, the system simulation control layer can perform detailed modeling of the peripheral communication transaction based on the currently configured NoC's simulated network structure. This modeling process simulates the latency, routing, and congestion of the peripheral communication transaction on the NoC's internal paths. It also calls the corresponding access behavior model based on the type of peripheral communication transaction (memory access or I / O device access) to reflect the peripheral's response logic to the peripheral communication transaction.

[0109] For example, if the target communication transaction is a communication transaction between a client-side simulation virtual machine and a server-side simulation virtual machine, the system simulation control layer can treat the communication transaction between the client-side simulation virtual machine and the server-side simulation virtual machine as a peripheral communication transaction and simulate it in the simulation processing method of the peripheral communication transaction; for example, when the system simulation control layer simulates the server-side communication transaction initiated by the client-side simulation virtual machine, the server-side communication transaction is treated as a peripheral communication transaction and simulated in the simulation processing method of the peripheral communication transaction. At this time, the process of the server-side communication transaction reaching the server-side simulation virtual machine through the simulation network structure of the NoC can be software simulated through the simulation processing method of the peripheral communication transaction.

[0110] Furthermore, the system simulation control layer may also have the following responsibilities:

[0111] Simulation resource management, which is responsible for allocating program images and runtime resources to the simulation virtual machine and coordinating the runtime sequence, such as starting, suspending, and resuming the simulation virtual machine on demand;

[0112] Interrupt and transaction completion notification: After completing the simulation, the system simulation control layer can notify the simulation virtual machine through the interrupt mechanism, so that the simulation virtual machine can clearly understand that the target communication transaction has been completed. It also cooperates with the clock adjuster to advance the timing to ensure that the simulation virtual machine resumes execution at the correct time.

[0113] Simulation path delay measurement: During the simulation processing of the target communication transaction, the system simulation control layer can record the time consumed to complete the simulation processing (i.e., simulation processing time VLat) and the theoretical network delay of the NoC simulation network structure (i.e., simulation network delay SLat) as the basis for subsequent comparative analysis.

[0114] It should be noted that the simulated network delay SLat of the target communication transaction can be less than the simulation processing time VLat of the system simulation control layer, wherein the simulated network delay of the target communication transaction is the simulated network structure based on NoC, the theoretical network transmission time of the target communication transaction, and the simulation processing time is the time taken by the system simulation control layer to perform simulation processing of the target communication transaction through software simulation.

[0115] The clock adjuster 440 is used to synchronize the clocks of the simulated virtual machine, the virtual on-chip network, and the system simulation control layer, so as to align the timing between the simulated virtual machine, the virtual on-chip network, and the system simulation control layer when the virtual on-chip network intercepts the target communication transaction and when the system simulation control layer completes the simulation processing of the target communication transaction.

[0116] In an embodiment of the present application, the clock adjuster is a coordination control module used to ensure the timing accuracy of the simulation process, mainly by synchronizing the clocks involved in the target communication transaction (such as synchronizing the clocks of each module of the simulation system) to align the timing.

[0117] As an optional implementation, the clock adjuster can monitor and control the following clocks: the clock of the simulated virtual machine, the clock of the virtual on-chip network, and the clock of the system simulation control layer; specifically, when the virtual on-chip network intercepts the target communication transaction, the clock adjuster can at least suspend the clock of the simulated virtual machine, the clock of the virtual on-chip network, and the clock of the system simulation control layer; when the system simulation control layer completes the simulation processing of the target communication transaction, the clock adjuster can adjust the clock of the virtual on-chip network and the clock of the system simulation control layer based on the simulation network delay of the target communication transaction evaluated by the system simulation control layer, and advance the clock of the simulated virtual machine.

[0118] For example, in a scenario where a single virtual machine accesses peripherals such as memory or IO devices, when the simulated virtual machine initiates a peripheral communication transaction to access the memory or IO device, the peripheral communication transaction is considered a target communication transaction and is intercepted by the virtual on-chip network. At this time, the clock adjuster can intervene and simultaneously suspend the clocks of the simulated virtual machine, virtual on-chip network, and system simulation control layer to ensure that the target communication transaction does not produce inconsistent timing advancement in the different stages corresponding to the simulated virtual machine, virtual on-chip network, and system simulation control layer (that is, during the process of initiating, intercepting, and emulating the communication transaction), thereby preventing the simulation behavior from being out of sync with the actual NoC behavior.

[0119] Furthermore, after obtaining the target communication transactions intercepted by the virtual on-chip network, the system simulation control layer can simulate the target communication transactions based on the NoC's simulated network structure and the corresponding access behavior model, and evaluate the simulation processing time (VLat) consumed by the simulation processing, as well as the theoretical transmission delay of the target communication transactions, namely the simulated network delay (SLat). The clock adjuster adjusts the clocks of the virtual on-chip network and the system simulation control layer respectively based on the simulated network delay (SLat), ensuring that the processing progress of the virtual on-chip network and the system simulation control layer matches theoretical expectations.

[0120] Subsequently, after the system simulation control layer completes the simulation processing of the target communication transaction, the simulation results will be written into the transaction queue. At this time, the clock adjuster restarts the clock of the simulation virtual machine based on the simulation network delay SLat, so that the simulation virtual machine resumes execution when it advances to the time point aligned with the simulation network delay SLat, ensuring the timing correctness of the target communication transaction between the initiation, interception, and simulation processing stages, and meeting the timing requirements of the simulation.

[0121] Therefore, in the embodiments of this application, the clock adjuster is not just a simple time recorder, but a cross-module and cross-stage simulation time synchronization controller. By coordinating the clock states of the simulation virtual machine, virtual network on chip, and system simulation control layer, the clock adjuster ensures the logical timing alignment and behavioral synchronization of the target communication transaction in the simulation system, from generation to simulation processing.

[0122] To facilitate further understanding, the following examples illustrate the physical host on which the simulation system provided in the embodiments of the present application is deployed, as well as the simulation process in various simulation business scenarios.

[0123] As an optional implementation, Figure 6 The following is an example diagram showing the deployment of a physical host of an application simulation system provided by an embodiment of the present application. This example diagram shows how the simulation system is deployed on a physical host (such as a server or terminal device). The physical host where the simulation system is deployed can be regarded as a computing platform for the simulation system. Figure 6 As shown, the physical host may include a simulation system and cooperating components of the simulation system;

[0124] The simulation system includes:

[0125] Multiple emulated virtual machines, such as Figure 6 SVM0 and SVM1 are shown. SVM0 and SVM1 are two simulated virtual machines running on a virtualization platform. They are scheduled by the processor core and load and execute real machine workloads. During operation, they generate communication transactions that need to be transmitted through the NoC. Let Timer0 be the clock of SVM0 and Timer1 be the clock of SVM1.

[0126] The virtual network on chip intercepts the communication transactions sent by the processor core and determines whether the communication transactions are the target communication transactions triggered by the simulation virtual machine based on the identification information of the communication transactions. After identifying the target communication transactions, the target communication transactions are temporarily stored in the transaction queue (EVTQ, Event Queue) and an interrupt notification is initiated to the system simulation control layer. Timer2 is set as the clock of the virtual network on chip.

[0127] The transaction queue is an event buffer structure located inside the virtual network on chip, which is used to temporarily store the target communication transactions intercepted by the virtual network on chip, waiting for simulation processing by the system simulation control layer;

[0128] The system simulation control layer is responsible for simulating the target communication transactions (for example, modeling the access behavior model based on the NoC's simulated network structure, memory access, or IO device access) and generating simulation results. The system simulation control layer mainly models the communication behavior of the target communication transactions in the NoC's simulated network structure. Furthermore, the system simulation control layer calculates Slat and Vlat and controls the resumption of the simulated virtual machine. Timer3 is the clock of the system simulation control layer.

[0129] The clock adjuster, as a timing synchronization module, controls the clocks of each simulated virtual machine (such as Timer0 of SVM0 and Timer1 of SVM1), Timer2 of the virtual on-chip network, and Timer3 of the system simulation control layer. It also calibrates the clocks in the simulation system according to the transaction progress of the target communication transaction to achieve timing alignment and calibration.

[0130] The physical host also includes components that support the simulation system, such as the underlying computing environment or other components that the simulation system relies on to operate and interact with the simulation system. These components include but are not limited to:

[0131] Virtual machine manager, which provides a virtualization environment to support the deployment of simulated virtual machines;

[0132] Ordinary programs are run by the processor core. For example, non-simulation-related real machine programs can have their communication transactions directly transparently transmitted to the real NoC.

[0133] Real NoC;

[0134] Memory and peripherals.

[0135] As an optional implementation, taking the scenario where a single simulated virtual machine accesses peripherals such as memory or IO devices as an example, an example of the NoC-oriented simulation process can be as follows: Figure 7 As shown, Figure 7 The simulation process of the example mainly performs simulation modeling and timing analysis of NoC communication in the scenario of a single simulated virtual machine accessing peripherals such as memory or IO devices. For example, if you want to verify the communication efficiency and bottleneck of the NoC topology under peripheral access, you can simulate the communication path involving NoC in the virtual machine system and measure indicators such as latency. In this case, you can use Figure 7 In the simulation process of the example, in the scenario where a single simulated virtual machine accesses peripherals such as memory or IO devices, the target communication transaction can be the peripheral communication transaction of the simulated virtual machine accessing the memory or IO device. Figure 7 As shown, the specific simulation process may include the following steps.

[0136] Step S701: Initialize the simulated virtual machine and its clock.

[0137] Taking SVM0 as an example of a single virtual machine that accesses peripherals such as memory or IO devices, the embodiment of the present application can create and configure SVM0, and allocate multiple virtual CPU cores to SVM0 to realize the setting of multi-core SVM0, that is, SVM0 is a simulation virtual machine instance with multiple virtual cores in the simulation system; the created SVM0 will run real machine loads in the simulation system (such as simulation business programs related to peripheral access) and is the source of simulation key data; at the same time, initialize the clock Timer0 of SVM0.

[0138] Step S702: Configure the virtual network on chip and its clock.

[0139] Specifically, the virtual network on chip is initialized and deployed, and the clock Timer2 is configured for the virtual network on chip.

[0140] Step S703: Setting the system simulation control layer and the clock of the simulation control layer, and setting the real machine load.

[0141] For example, the system simulation control layer serves as the core logic module of the simulation system. In the embodiment of the present application, the system simulation control layer and its clock Timer3 can be set up, and a real machine load for simulation can be prepared.

[0142] Step S704: The system simulation control layer sets up data and program channels of memory and peripherals to the real Internet of the simulation service host.

[0143] The simulation service host refers to the physical host where the simulation system is deployed. The real Internet network of the simulation service host refers to the interconnected resource environment built by the physical host. The system simulation control layer needs to set up memory and peripheral data and program channels to the real Internet network of the simulation service host to prepare the access path required for the simulation virtual machine to access memory data and call peripheral interfaces, ensuring that the simulation virtual machine can successfully initiate communication transactions when running the real machine load.

[0144] That is to say, before the simulation task begins, the system simulation control layer can configure the resource path accessible to the simulated virtual machine on the physical host in advance based on the communication requirements of the real machine load, including but not limited to: mapping virtual memory channels to support data reading and writing, setting peripheral communication channels to simulate IO behavior, and injecting program code into the running environment of the simulated virtual machine, thereby ensuring that the simulated virtual machine can successfully initiate access tasks to memory, peripherals, etc. during operation, providing a basis for the triggering and modeling analysis of subsequent simulation transactions.

[0145] Step S705: The system simulation control layer loads the program image of the real machine into the simulation virtual machine and starts the simulation virtual machine.

[0146] For example, the system simulation control layer can load the program image of the real machine load into SVM0, so that SVM0 can run the real machine load. Then the system simulation control layer starts SVM0. At this time, the simulation officially enters the program execution stage, that is, using SVM0 to run the real machine load, and begins to simulate the execution of the real machine load in the multi-core processor, preparing for the generation and interception of subsequent communication transactions.

[0147] It should be noted that the virtual machine can be actually created and run by the virtual machine manager. In the embodiment of the present application, the system simulation control layer, as the upper-level simulation coordinator of the simulation system, can indirectly start and control the simulated virtual machine through the virtual machine manager. For example, the system simulation control layer controls and calls the interface of the virtual machine manager to start the simulated virtual machine, load the program image of the real machine load for the simulated virtual machine, etc.

[0148] Step S706: The virtual machine is simulated to run the real machine load.

[0149] Step S707: When the simulated virtual machine is running the real machine load, if the data accessed by the simulated virtual machine hits in the cache, the clock of the simulated virtual machine is used as the reference clock to promote the real machine load to continue running, and the clock adjuster is used to adjust the clock of the virtual on-chip network and the clock of the system simulation control layer to synchronize with the clock of the simulated virtual machine.

[0150] For example, when SVM0 is running a real machine load, if the data to be accessed is already stored in the cache, for example, the data to be accessed by SVM0 hits the L1 cache, L2 cache, or L3 cache, then there is no need to access the memory or IO device. At this time, the NoC communication transaction will not be triggered, and the virtual on-chip network does not need to intervene. Therefore, the clock Timer0 of SVM0 can be used as the reference clock to promote the continued operation of the real machine load; although the communication transaction simulation is not performed at this time, the simulation system needs to maintain clock synchronization between modules. Therefore, the clock adjuster needs to synchronize the clock Timer2 of the virtual on-chip network and the clock Timer3 of the system simulation control layer based on the clock Timer0 of SVM0, so that the simulation times of SVM0, virtual on-chip network, and system simulation control layer are consistent to prevent timing errors.

[0151] That is to say, in the process of the simulated virtual machine executing the real machine load, if the current stage does not trigger a communication transaction involving the NoC due to a cache hit, the reference clock of the simulation system is driven by the clock of the simulated virtual machine, indicating that the real machine load continues to operate normally. At this time, although other modules of the simulation system (virtual on-chip network, system simulation control layer) do not participate in the simulation transaction processing, the clocks of the virtual on-chip network and the system simulation control layer are still coordinated by the clock adjuster to keep them synchronized with the clock of the simulated virtual machine, establishing a timing basis for the simulation processing of subsequent transactions.

[0152] Step S708: During the process of running the real machine load, if the simulated virtual machine needs to access the memory or IO device, a peripheral communication transaction is triggered.

[0153] When the simulated virtual machine is running the real machine load, if the data accessed by the simulated virtual machine does not hit in the cache, the simulated virtual machine needs to access peripherals such as memory or IO devices. At this time, the simulated virtual machine triggers a peripheral communication transaction, that is, the simulated virtual machine initiates a peripheral communication transaction to transmit the peripheral communication transaction to the memory or IO devices through the NoC to access the data.

[0154] Step S709: The virtual network on chip intercepts the communication transaction sent by the processor core. If the communication transaction is identified as a peripheral communication transaction of the simulated virtual machine, the peripheral communication transaction is stored in the transaction queue, an interrupt notification is sent to the system simulation control layer, and the clock regulator is used to suspend the clock of the simulated virtual machine, the clock of the virtual network on chip, and the clock of the system simulation control layer.

[0155] The virtual on-chip network is logically deployed on the communication path where the processor core issues communication transactions. When the simulated virtual machine triggers a peripheral communication transaction, the virtual on-chip network can intercept and identify the peripheral communication transaction of the simulated virtual machine (identify the peripheral communication transaction through the identification information of the communication transaction), thereby storing the peripheral communication transaction in the transaction queue (EVTQ) of the virtual on-chip network and initiating an interrupt notification to the system simulation control layer.

[0156] At the same time, the clock adjuster is used to suspend the clock of the simulation virtual machine, the clock of the virtual on-chip network, and the clock of the system simulation control layer to uniformly freeze the timing state, ensure the timing accuracy during the simulation transaction processing, and prevent the simulation virtual machine from advancing prematurely.

[0157] For example, when SVM0 needs to read memory or IO devices, SVM0 will initiate a peripheral communication transaction. The virtual on-chip network intercepts the peripheral communication transaction of SVM0, stores it in the transaction queue, and initiates an interrupt notification to the system simulation control layer; at the same time, the clock regulator suspends Timer0 of SVM0, Timer2 of the virtual on-chip network, and Timer3 of the system simulation control layer.

[0158] Step S710: The system simulation control layer obtains the peripheral communication transaction from the transaction queue, calls the access behavior model matching the peripheral communication transaction based on the simulation network structure of the NoC, performs simulation processing of the peripheral communication transaction, and generates a simulation result of the peripheral communication transaction.

[0159] In an optional implementation, the system simulation control layer obtains a peripheral communication transaction from a transaction queue and determines the access object of the peripheral communication transaction based on transaction information such as the target address, transaction type, and virtual machine identifier contained in the peripheral communication transaction. Specifically, the system simulation control layer can determine the access object of the peripheral communication transaction based on the address range of the peripheral communication transaction. The access object of the peripheral communication transaction may be, for example, a memory controller, a network card controller, a UART interface, or other peripheral controllers. In combination with the preset NoC simulation network structure, the system simulation control layer determines the specific location of the access object of the peripheral communication transaction in the NoC simulation network structure.

[0160] Furthermore, the system simulation control layer invokes the access behavior model that matches the peripheral communication transaction to simulate the routing of the peripheral communication transaction from the NoC's simulated network structure to the access object of the peripheral communication transaction, thereby performing node-level simulation processing of the peripheral communication transaction. Specifically, for peripheral communication transactions accessing memory, a memory access behavior model (e.g., memory access logic) can be used to model the access latency, bandwidth bottleneck, and other characteristics of the peripheral communication transaction routed from the NoC's simulated network structure to the memory controller. For peripheral communication transactions accessing peripheral controllers, the peripheral access behavior model can be used, combined with preset protocol response logic, to model the routing characteristics of the peripheral communication transaction from the NoC's simulated network structure to the peripheral controller, and simulate the peripheral's state changes and response process. Based on this, the system simulation control layer, combined with the NoC's simulated network structure, performs communication transaction path selection, transmission delay calculation, network congestion modeling, and other processes, thereby simulating the transmission path and timing of the peripheral communication transaction in the NoC's simulated network structure.

[0161] Finally, after completing the node-level access behavior modeling of peripheral communication transactions and the NoC transmission path simulation, the system simulation control layer generates corresponding simulation results.

[0162] Step S711: The system simulation control layer stores the simulation results in the transaction queue, and uses the clock adjuster to adjust the clock of the virtual on-chip network and the clock of the system simulation control layer based on the simulation network delay evaluated by the system simulation control layer, wherein the simulation network delay is less than the simulation processing time.

[0163] After obtaining the simulation results, the system simulation control layer can store the simulation results in the transaction queue and use them as input for the simulation virtual machine when the simulation virtual machine resumes operation. Therefore, the transaction queue serves as a structure for managing simulation communication transactions. It can store target communication transactions initiated by the simulation virtual machine, and the corresponding simulation results can also be filled in by the system simulation control layer after the simulation processing is completed, so as to realize the complete life cycle management of the transaction status and result feedback.

[0164] During the simulation process, the system simulation control layer can evaluate the simulated network latency. The simulated network latency refers to the theoretical network transmission time of the target communication transaction based on the simulated network structure of the NoC. That is, using the simulated network structure of the NoC, the target communication transaction should consume time to transmit in the NoC, thereby inferring the ideal transaction completion time of the target communication transaction to provide an accurate reference time. The simulated network latency can be expressed as SLat (Simulated Latency);

[0165] Based on the simulated network delay SLat, the embodiment of the present application can use a clock adjuster to adjust the clock Timer2 of the virtual on-chip network and the clock Timer3 of the system simulation control layer. Specifically, the system simulation control layer may take a long time to actually complete the simulation processing, but the system simulation control layer estimates that the theoretical network transmission time of the communication transaction transmitted in the NoC is the simulated network delay SLat. Therefore, the clock adjuster can rewind or calibrate the clock Timer2 of the virtual on-chip network and the clock Timer3 of the system simulation control layer to a moment that only consumes the simulated network delay SLat, thereby ensuring timing correctness and consistency, that is, using the simulated network delay SLat as a reference, correcting the time drift of the virtual on-chip network and the system simulation control layer caused by the excessive software simulation time during the simulation process;

[0166] In a more specific explanation, the simulation processing time is the time it takes for the system simulation control layer to perform simulation processing of the target communication transaction through software simulation, that is, the time it takes for the system simulation control layer to actually complete the simulation processing of the target communication transaction. The simulation processing time can be expressed as VLat (Virtual Latency); the simulation processing time VLat is generally greater than the simulation network delay SLat, that is, the simulation network delay SLat is less than the simulation processing time VLat. This is because the simulation network delay SLat is the theoretical network transmission time of the target communication transaction, and the simulation processing time VLat is the time consumed to execute the complete simulation logic at the software level. Although the simulation processing time is long, the simulation system needs to use the theoretical network transmission time of the target communication transaction as a reference benchmark to call back the clocks of each module in the simulation system, that is, based on the simulation network delay, adjust the clock of the virtual on-chip network and the clock of the system simulation control layer to ensure the correctness of the time logic.

[0167] It should be noted that since different target communication transactions may access different objects and their specific locations in the NoC's simulated network structure may differ, the simulated network latency (SLat) and simulated processing time (VLat) of different target communication transactions may differ. In other words, different target communication transactions (such as different peripheral communication transactions) may have different access target locations, which will affect the communication path, network resource usage, and simulation processing complexity, resulting in different SLat (theoretical transmission latency under the simulated network structure) and VLat (software simulation processing time) for different target communication transactions.

[0168] For example, taking a peripheral communication transaction as an example, since the objects accessed by a peripheral communication transaction may include different types of peripherals (such as memory, hard disk, network interface card, etc.), and these peripherals are located in different locations within the NoC simulation network structure, each peripheral communication transaction will have a different transmission path, number of nodes traversed, and potential arbitration or congestion conditions within the NoC simulation network structure. This results in differences in the simulated network latency (SLat). For example, a peripheral communication transaction accessing a remote controller may need to traverse multiple NoC nodes, and its SLat may be higher than a peripheral communication transaction accessing a local MMIO (Memory Mapped Input / Output) controller. At the simulation processing level, the system simulation control layer needs to invoke the corresponding access behavior model based on the specific peripheral being accessed. Some peripheral access behaviors are relatively simple (such as a one-time read of a fixed address) and have a small corresponding VLat. However, some peripheral access behaviors (such as burst DMA writes and synchronous transactions with multi-cycle responses) involve complex simulation processes and may require processing multiple state transitions and response interactions. Their simulation processing time (VLat) may be higher, resulting in different VLats for different target communication transactions.

[0169] Step S712: The clock adjuster advances the clock of the simulated virtual machine based on the simulated network delay, and when the clock advancement time of the simulated virtual machine corresponds to the simulated network delay, the system simulation control layer notifies the simulated virtual machine to read the simulation result from the transaction queue.

[0170] The clock adjuster can advance the clock of the simulated virtual machine based on the simulated network delay SLat, so that the clock of the simulated virtual machine moves forward, and the clock advancement time of the simulated virtual machine corresponds to the simulated network delay, thereby matching the time position at which the peripheral communication transaction should theoretically complete the transmission, ensuring that the resumption time of the simulated virtual machine is consistent with the theoretical transmission behavior of the peripheral communication transaction.

[0171] For example, when SVM0 initiates a peripheral communication transaction, the virtual on-chip network intercepts the peripheral communication transaction of SVM0 and the clock adjuster suspends Timer0 of SVM. When the system simulation control layer completes the simulation processing of the peripheral communication transaction after the simulation processing takes VLat, in order to ensure that the operating logic of SVM0 is aligned with the theoretical simulation network delay SLat, the clock adjuster can advance the clock of SVM0 from Timer0 to Timer0+SLat. Therefore, when the clock of SVM0 advances to Timer0+SLat, the system simulation control layer can notify SVM0 through the interrupt mechanism: the peripheral communication transaction has been completed; then SVM0 resumes execution and reads the simulation results of the peripheral communication transaction from the transaction queue to continue the operation of the real machine load.

[0172] Furthermore, after the simulation virtual machine reads the simulation result of the peripheral communication transaction from the transaction queue, the corresponding transaction entry in the transaction queue can be deleted. For example, the transaction queue can have at least one transaction entry, and a transaction entry records a target communication transaction of the simulation virtual machine and the corresponding simulation result. When the simulation virtual machine reads the simulation result of a target communication transaction from the transaction queue, the transaction entry where the simulation result is located can be deleted to release the queue space of the transaction queue.

[0173] Step S713: Repeat steps S707 to S712 until the simulated virtual machine completes running or exits running the real machine load.

[0174] For example, the simulation system can continuously monitor the communication transactions issued by the processor core, and when monitoring the new peripheral communication transactions of the simulated virtual machine, it will re-process the above corresponding steps, and repeat this cycle until the simulated virtual machine completes the operation or exits the real machine load. In other words, the embodiment of the present application can continuously monitor whether the simulated virtual machine has initiated a new peripheral communication transaction. If so, the virtual on-chip network will intercept it again and transfer it to the system simulation control layer for simulation processing, and perform clock alignment control of each module through the clock adjuster. The specific process can be referred to the description above; this cycle continues until the real machine load is executed or the real machine load exits the operation.

[0175] In the above process, the embodiment of the present application can evaluate the difference between the theoretical performance of NoC and the processing efficiency of the simulation system based on the simulated network delay SLat and the simulated processing time VLat. Specifically, the simulated network delay SLat reflects the theoretical transmission capacity of the target communication transaction under the simulated NoC architecture, and the simulated processing time VLat is the actual software simulation processing time. Therefore, by comparing the simulated network delay SLat and the simulated processing time VLat, not only can the performance of the simulated network structure of NoC under various types of target communication transactions (such as various types of peripheral communication transactions) be evaluated, but also the simulation efficiency and resource bottleneck of the simulation system can be measured, thereby providing a dual basis for the structural optimization of NoC and the design of the simulation framework.

[0176] In other words, by introducing the evaluation mechanism of simulation network delay SLat and simulation processing time VLat, it is possible to conduct differentiated analysis of the theoretical performance and actual processing efficiency of the simulation system for the same target communication transaction under different NoC architectures, and to conduct differentiated analysis of the theoretical performance and actual processing efficiency of the simulation system for different types of target communication transactions under the same NoC architecture. The above differentiated analysis can not only support the evaluation of the design pros and cons of the NoC architecture, but also reflect whether the processing capacity of the simulation system itself has become a bottleneck for architectural exploration; thereby effectively dealing with the problems faced in NoC architecture design, such as high-complexity load simulation, huge architectural space, and difficult performance and resource trade-offs, and providing a more efficient and controllable simulation exploration method for the on-chip interconnection structure of multi-core processors.

[0177] As an optional implementation, taking the communication interaction scenario between the client simulation virtual machine and the server simulation virtual machine as an example, another example of the NoC-oriented simulation process can be as follows: Figure 8 As shown, Figure 8 The simulation process of the example mainly focuses on the business scenarios of the client and the server, analyzing the requests initiated by the client to the server, as well as the transaction modeling and timing coordination control during the simulation process. Figure 7 The simulation process of peripheral communication transactions of a single virtual machine is shown in the example. Figure 8 The simulation process of the example introduces a multi-virtual machine collaboration mechanism to support the evaluation of the performance of the NoC's simulated network structure in multi-virtual machine collaborative communication scenarios, thereby realizing complex business load simulation support; in the communication interaction scenario between the client simulated virtual machine and the server simulated virtual machine, the target communication transaction may include but is not limited to any of the following: before the server simulated virtual machine and the client simulated virtual machine have no communication interaction, the server simulated virtual machine accesses the memory or IO device's peripheral communication transaction; the client simulated virtual machine initiates the server communication transaction; after the client simulated virtual machine initiates the first server communication transaction, the server simulated virtual machine initiates the communication transaction that needs to be transmitted through the NoC.

[0178] like Figure 8 As shown, the specific simulation process may include the following steps.

[0179] Step S801: Create a server-side simulation virtual machine and a client-side simulation virtual machine.

[0180] Step S802: Load the server-side simulation business program into the server-side simulation virtual machine, and load the client-side simulation business program into the client-side simulation virtual machine.

[0181] For example, the embodiment of the present application can create two simulated virtual machines SVM0 and SVM1, corresponding to the server and client respectively, for assuming the business roles of the server and client respectively. That is, SVM0, as a server instance, is responsible for receiving requests from the client and providing corresponding processing logic; SVM1, as a client instance, will actively initiate business requests to SVM0 during the simulation process. The simulation business program (i.e., the real machine load) can be divided into a server simulation business program and a client simulation business program according to the logic of the server and the client. The system simulation control layer can load the server simulation business program for SVM0 and the client simulation business program for SVM1, so that SVM0 and SVM1 can simulate the real interaction between the server and the client in subsequent execution.

[0182] Step S803: The system simulation control layer starts the server simulation virtual machine and the client simulation virtual machine.

[0183] For example, the system simulation control layer can start SVM0 and SVM1 respectively through the virtual machine manager, and SVM0 and SVM1 run independently before there is no communication interaction.

[0184] Step S804 : For the non-server communication transactions of the client emulated virtual machine, the virtual on-chip network transmits the non-server communication transactions to the real NoC for processing.

[0185] In the embodiment of the present application, not all communication transactions issued by the client-simulated virtual machine need to be simulated, but some communication transactions bypass the simulation modeling and are directly processed in the real NoC. Specifically, the non-server-side communication transactions of the client-simulated virtual machine do not need to be simulated and are directly processed in the real NoC; wherein, the non-server-side communication transactions of the client-simulated virtual machine refer to communication transactions initiated by the client-simulated virtual machine whose access target is not the server-side simulated virtual machine, such as peripheral communication transactions initiated by the client-simulated virtual machine to access peripherals such as memory and IO devices. The non-server-side communication transactions of the client-simulated virtual machine do not trigger the service interaction process and are not the target communication transactions that need to be modeled and simulated in the client-server interaction scenario.

[0186] That is, the client emulated virtual machine (SVM1) may initiate multiple NoC communication transactions, only some of which involve interaction with the server emulated virtual machine (SVM0), as server communication transactions, and are considered as target communication transactions referred to in the embodiments of this application. That is, for communication transactions initiated by the client emulated virtual machine (SVM1) whose target address does not point to the server emulated virtual machine, the embodiments of this application regard them as communication transactions that do not require simulation processing (such as peripheral communication transactions of the client emulated virtual machine), and are directly transmitted by the virtual on-chip network to the real NoC for processing.

[0187] Specifically, the virtual on-chip network can intercept communication transactions issued by the processor core. If the virtual machine identifier of the communication transaction corresponds to the client simulation virtual machine and the target address is not the address of the server simulation virtual machine (for example, the target address points to peripherals such as memory and IO devices), the communication transaction is regarded as a non-server communication transaction of the client simulation virtual machine and is transmitted to the real NoC for processing.

[0188] Step S805: Before the server-side emulation virtual machine and the client-side emulation virtual machine have no communication interaction, the peripheral communication transaction of the server-side emulation virtual machine is used as the target communication transaction, and the virtual on-chip network intercepts it and transfers it to the system emulation control layer for emulation processing.

[0189] Before the server-side emulated virtual machine and the client-side emulated virtual machine have no communication interaction, if the data accessed by the server-side emulated virtual machine (SVM0) does not hit the cache, it will trigger a peripheral communication transaction to access the memory or IO device. At this time, the peripheral communication transaction of the server-side emulated virtual machine is regarded as a target communication transaction, so that the virtual on-chip network intercepts the peripheral communication transaction of the server-side emulated virtual machine (SVM0) and hands it over to the system simulation control layer for simulation processing. Specifically, the virtual on-chip network can intercept the communication transaction issued by the processor core. If the virtual machine identifier of the communication transaction corresponds to the server-side emulated virtual machine, the target address points to peripherals such as memory or IO devices, and the server-side emulated virtual machine and the client-side emulated virtual machine have not yet communicated, then the communication transaction is a peripheral communication transaction of the server-side emulated virtual machine, and it occurs before the server-side emulated virtual machine and the client-side emulated virtual machine communicate and interact, and is regarded as a target communication transaction. Figure 7 The process shown is simulated.

[0190] Step S806: For the first server communication transaction of the client emulation virtual machine, the virtual on-chip network stores the first server communication transaction in the transaction queue, sends an interrupt notification to the system emulation control layer, and uses the clock adjuster to pause the clocks of the client emulation virtual machine and the server emulation virtual machine.

[0191] The first server communication transaction of the client simulation virtual machine refers to: the communication transaction corresponding to the first time the client simulation virtual machine initiates a server communication request, that is, the communication transaction initiated for the first time by the client simulation virtual machine (SVM1) and the target is the server simulation virtual machine (SVM0); this first server communication transaction is an interaction event between the client and the server and needs to be modeled and simulated; thus, the virtual on-chip network intercepts the first server communication transaction, stores the first server communication transaction in the transaction queue, and notifies the system simulation control layer through an interrupt that there is a simulation transaction to be processed.

[0192] Specifically, the virtual on-chip network can intercept communication transactions issued by the processor core. If the virtual machine identifier of the communication transaction corresponds to the client emulation virtual machine, the target address is the address of the server emulation virtual machine, and the client emulation virtual machine initiates a communication transaction to the server emulation virtual machine for the first time, then the communication transaction is considered the first server communication transaction of the client emulation virtual machine and is stored in the transaction queue. At the same time, the clock adjuster is used to pause the clock Timer1 of the client emulation virtual machine (SVM1) and the clock Timer0 of the server emulation virtual machine (SVM0), that is, to freeze the time advancement of the client emulation virtual machine (SVM1) and the server emulation virtual machine (SVM0), and wait for the simulation processing of the first server communication transaction to complete before resuming, to ensure timing consistency.

[0193] Step S807: The system simulation control layer obtains the first server communication transaction from the transaction queue, takes the first server communication transaction as the peripheral communication transaction, and performs simulation processing of the peripheral communication transaction based on the simulation network structure of the NoC to form a simulation result of the first server communication transaction. The system simulation control layer also evaluates the simulation network delay and simulation processing time of the first server communication transaction.

[0194] In the embodiment of the present application, from the modeling perspective of the simulation system, the communication transactions involving the NoC are uniformly modeled as peripheral communication transactions for simulation processing, so that for the first server communication transaction of the client simulation virtual machine, the system simulation control layer simulates the first server communication transaction in a peripheral access modeling manner, that is, the first server communication transaction is treated as a peripheral communication transaction, and the system simulation control layer performs simulation processing of the peripheral communication transaction based on the simulation network structure of the NoC to form a simulation result of the first server communication transaction. For example, based on the simulation network structure of the NoC, by requesting a peripheral response, the client simulation virtual machine simulates the access of the server simulation virtual machine to the server simulation virtual machine, thereby realizing the simulation processing of the first server communication transaction in a peripheral access modeling manner.

[0195] During the simulation processing of the first server-side communication transaction, the system simulation control layer can evaluate the simulation network delay SLat and simulation processing time VLat of the first server-side communication transaction. The simulation network delay SLat of the first server-side communication transaction represents the theoretical network transmission time of the first server-side communication transaction in the simulation network structure of NoC, and represents an ideal evaluation indicator of NoC communication performance; the simulation processing time VLat of the first server-side communication transaction represents the time consumed by the system simulation control layer to complete the simulation processing of the first server-side communication transaction at the software level. VLat is generally greater than SLat.

[0196] Step S808: The clock adjuster advances the clocks of the server-side simulated virtual machine and the client-side simulated virtual machine based on the simulated network delay of the first server-side communication transaction.

[0197] For example, based on the simulated network delay SLat of the first server communication transaction, the clock adjuster can advance the clock of the server simulation virtual machine (SVM0) to Time0+SLat and advance the clock of the client simulation virtual machine (SVM1) to Time1+SLat to simulate the time point when the first server communication transaction of the client simulation virtual machine is theoretically transmitted.

[0198] Step S809: The system simulation control layer triggers the server simulation virtual machine through an interruption to notify the server simulation virtual machine to perform response processing for the first server communication transaction, and at the same time controls the client simulation virtual machine to continue running.

[0199] After completing the clock advancement of the server-side simulation virtual machine and the client-side simulation virtual machine, the system simulation control layer triggers the server-side simulation virtual machine (SVM0) to execute the response processing for the first server-side communication transaction through an interrupt, and at the same time releases the pause control of the client-side simulation virtual machine (SVM1), allowing the client-side simulation virtual machine (SVM1) to continue running, thereby realizing the synchronous simulation of the first server-side communication transaction.

[0200] It should be noted that the system simulation control layer treats the first server communication transaction as a peripheral communication transaction and performs simulation processing of the peripheral communication transaction, mainly simulating the transmission process of the first server communication transaction in the NoC; and the response processing of the server simulation virtual machine for the first server communication transaction is that the system simulation control layer simulates the transmission process of the first server communication transaction in the NoC, and then notifies the server simulation virtual machine through the interrupt mechanism to enter the business service processing of the first server communication transaction, that is, the first server communication transaction is processed through the server simulation business program of the server simulation virtual machine.

[0201] That is to say, the system simulation control layer regards the first server communication transaction as a peripheral communication transaction, and performs network transmission simulation processing based on the NoC's simulation network structure, mainly used to model the process of the first server communication transaction being transmitted from the client simulation virtual machine to the server simulation virtual machine through the NoC, such as path selection, routing delay evaluation, and communication congestion modeling, which is regarded as transaction transmission simulation; after the system simulation control layer completes the simulation, the system simulation control layer does not directly process the business response of the first server communication transaction, but notifies the server simulation virtual machine through the interrupt mechanism to enter the business processing process, so that the server simulation virtual machine performs protocol parsing, business response, data processing and other server-side logic-level processing on the first server communication transaction through the server simulation business program it loads.

[0202] Step S810: After the client emulation virtual machine initiates the first server communication transaction, all communication transactions that the server emulation virtual machine needs to transmit through the NoC are regarded as target communication transactions and are simulated; and all server communication transactions of the client emulation virtual machine are regarded as target communication transactions and are simulated.

[0203] For example, after the client-side simulation virtual machine (SVM1) initiates the first server-side communication transaction, the server-side simulation virtual machine (SVM0) begins to participate in the client's transaction interaction, so that all communication transactions that the server-side simulation virtual machine needs to transmit through the NoC are regarded as target communication transactions and are simulated; for example, after the first server-side communication transaction is initiated, the communication transactions involving the NoC generated by the server-side simulation virtual machine (SVM0), such as accessing memory, calling IO devices, and communicating with the client-side simulation virtual machine (SVM1), are all regarded as target communication transactions and need to be simulated, such as intercepting them using the virtual on-chip network, executing simulation processing through the system simulation control layer, and using the clock adjuster for timing control. That is to say, after initiating the first server-side communication transaction, all communication transactions generated by the server-side simulation virtual machine in the process of running the server-side simulation business program and needing to be transmitted through the NoC are simulated. At this time, in order to ensure the consistency of the simulation, each time the server-side simulation virtual machine initiates a communication transaction that needs to be transmitted through the NoC, the clock adjuster will suspend the clocks of the relevant virtual machines and the virtual on-chip network until the transaction simulation is completed, such as pausing the clock Timer0 of the server-side simulation virtual machine (SVM0), pausing the clock Timer1 of the client-side simulation virtual machine (SVM1), pausing the clock Timer2 of the virtual on-chip network, etc.

[0204] At the same time, all server-side communication transactions of the client-simulated virtual machine are regarded as target communication transactions and are simulated. For example, starting from the first server-side communication transaction of the client-simulated virtual machine, all subsequent communication transactions accessing the server-side simulation virtual machine are considered target communication transactions and must be intercepted by the virtual on-chip network and handed over to the system simulation control layer for simulation processing. The simulation process of any server-side communication transaction of the client-simulated virtual machine can refer to the simulation process of the first server-side communication transaction of the client-simulated virtual machine, which will not be expanded here.

[0205] Figure 8 The interactive communication transactions between the client simulation virtual machine and the server simulation virtual machine involved in the process are in a continuous state. The virtual on-chip network and the system simulation control layer will continue to monitor and process the simulation transactions until the simulation system completes the performance evaluation task of the simulation process of the client and the server, that is, the communication evaluation task between the client and the server is completed, or the test time of the client simulation virtual machine initiating the server communication transaction reaches the preset test duration. For example, starting from step S803, until the simulation system completes the communication evaluation task between the client and the server, or the client simulation virtual machine reaches the test termination condition according to its test configuration (for example, the test time of the client simulation virtual machine initiating the server communication transaction reaches the preset test duration), the simulation process ends.

[0206] The above process mainly uses the interactive business between the client and the server as the load. The embodiment of the present application can perform performance evaluation of the simulated network structure of the NoC based on the number of tasks or task completion time of the server communication transactions initiated by the client simulation virtual machine during the simulation process. For example, the number of requests for server communication transactions successfully completed by the client simulation virtual machine is used as a performance evaluation indicator to reflect the processing capacity and throughput of the simulated network structure of the NoC. The time taken to complete all server communication transactions during the simulation process (i.e., task completion time) is used as another performance evaluation indicator to reflect the response speed and delay performance of the simulated network structure of the NoC, and then the communication efficiency, network bottleneck, delay characteristics, etc. of the simulated network structure of the NoC under the interactive business load between the client and the server are evaluated.

[0207] It can be seen that the NoC-oriented simulation system provided by the embodiment of the present application, by deploying a simulation virtual machine on a virtualization platform, the simulation virtual machine loads and executes the simulation business program, and the simulation business program is a part of the program extracted from the real machine program, which enables the simulation system to directly reproduce the communication transactions that need to be transmitted through the NoC in the real scene without constructing artificial test cases, that is, the triggering timing and program logic of the communication transactions that need to be transmitted through the NoC are consistent with the real scene, thereby improving the accuracy of the NoC architecture simulation. On this basis, the embodiment of the present application introduces a virtual on-chip network to intercept the communication transactions that need to be transmitted through the NoC issued by the processor core. Since the simulation virtual machine is scheduled and run by the processor core, the communication transactions that need to be transmitted through the NoC during the execution of the simulation business program by the simulation virtual machine will also be intercepted by the virtual on-chip network. If the virtual on-chip network identifies the intercepted communication transaction as the target communication transaction triggered by the simulation virtual machine, the target communication transaction is regarded as a task that needs to be modeled by the simulation system and is handed over to the system simulation control layer for high-precision simulation processing. At this time, the system simulation control layer can combine the simulation network structure of the NoC to simulate the target communication transaction and form a simulation result of the target communication transaction. At the same time, a clock adjuster coordinates and manages the clocks of the simulation virtual machine, virtual network on chip, and system simulation control layer to ensure timing alignment and achieve precision-controlled NoC communication behavior modeling. Therefore, the embodiments of the present application not only achieve high-precision simulation processing of target communication transactions, but also reduce unnecessary simulation computing overhead, providing a simulation solution for NoC architecture exploration that balances real load, flexibility, and efficiency, and improves the simulation speed and accuracy for NoC.

[0208] Specifically, the virtual network on chip of the embodiment of the present application is essentially a transaction interception mechanism, which can be regarded as an extended application of the trap mechanism in NoC simulation. That is, when the processor core schedules the simulation virtual machine to run, all communication transactions that need to be transmitted through the NoC are intercepted by the virtual network on chip on the communication path. When the intercepted communication transaction is identified as the target communication transaction triggered by the simulation virtual machine, the system simulation control layer is trapped to simulate the target communication transaction, thereby realizing on-demand simulation modeling of the target communication transaction. This mechanism avoids the performance bottleneck brought about by the cycle-level modeling of the full amount of communication transactions, ensures the exploration of NoC architecture with controllable accuracy and cost, and takes into account both simulation efficiency and simulation accuracy.

[0209] Compared to traditional software simulators, which can provide cycle-accurate modeling capabilities and reproduce NoC internal communication details, the simulation speed is low, making it difficult to support rapid NoC architecture exploration, especially under complex multi-core loads. The solution provided in the embodiments of the present application only models and simulates target communication transactions triggered by the simulated virtual machine, while other non-target communication transactions are transparently transmitted to the real NoC for processing, thus avoiding the performance bottleneck caused by the full modeling of traditional software simulators, taking into account both modeling granularity and simulation efficiency, and significantly improving the efficiency of NoC architecture exploration.

[0210] Compared to FPGA acceleration platforms, while FPGAs offer speeds closer to real hardware, they are expensive to develop and complex to verify for NoC architecture exploration. Each round of modifications requires re-synthesis and re-deployment, resulting in long iteration cycles. However, the system in this application, based on virtualization and software configurability, can quickly replace simulated workloads (i.e., simulated business programs), adjust communication models, and evaluate architectural parameters without requiring modifications to the underlying hardware, offering greater development flexibility and verification efficiency.

[0211] In a further optional implementation, based on the NoC-oriented simulation system provided in the embodiment of the present application, the embodiment of the present application further provides a NoC-oriented simulation method, which can be applied to the simulation system provided in the embodiment of the present application. Figure 9 The flowchart of the NoC-oriented simulation method provided in the embodiment of the present application is shown as an example. Figure 9 The detailed introduction and optional implementation of the process shown can be referred to in conjunction with the previous description and will not be expanded here.

[0212] like Figure 9 As shown, the process of the simulation method may include the following steps.

[0213] Step S910: intercepting a communication transaction sent by a processor core that needs to be transmitted through the NoC.

[0214] Optionally, step S910 may be executed by a virtual network on chip, and the relevant content may refer to the above description.

[0215] Step S920: Identify whether the communication transaction is a target communication transaction triggered by the emulated virtual machine.

[0216] Among them, at least one simulation virtual machine is deployed on the virtualization platform and scheduled to run by the processor core. The simulation virtual machine is used to execute the simulation business program, and the simulation business program is a partial program extracted from the real machine program.

[0217] Optionally, step S920 may be executed by a virtual network on chip, and the relevant content may refer to the above description.

[0218] Step S930 : If the communication transaction is a target communication transaction triggered by a simulated virtual machine, the target communication transaction is simulated based on the simulated network structure of the NoC to generate a simulation result of the target communication transaction.

[0219] Optionally, step S930 may be executed by the system simulation control layer, and the relevant content may refer to the above description.

[0220] Step S940: When the target communication transaction is intercepted and the simulation processing of the target communication transaction is completed, the clocks involved in the target communication transaction are synchronously controlled to align the timing.

[0221] Optionally, step S940 may be performed using a clock adjuster, and the relevant content may refer to the above description.

[0222] In a further optional implementation, the virtual on-chip network, the system simulation control layer, and the clock adjuster can be implemented as software functional modules and implemented through a program (such as a simulation program). Furthermore, the embodiment of the present application also provides a computer program, such as a simulation program that implements the simulation method provided in the embodiment of the present application. The computer program includes computer-executable instructions. When the computer-executable instructions are executed by a processor, the NoC-oriented simulation method provided in the embodiment of the present application is implemented.

[0223] Furthermore, an embodiment of the present application also provides a storage medium, which stores computer-executable instructions. When the computer-executable instructions are executed by a processor, the NoC-oriented simulation method provided in the embodiment of the present application is implemented.

[0224] The above describes multiple embodiment schemes provided by the embodiments of the present application. The various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open in the embodiments of the present application.

[0225] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A NoC-oriented simulation system, characterized in that: include: At least one simulated virtual machine is deployed on the virtualization platform and scheduled to run by the processor core; the simulated virtual machine is used to execute a simulated business program, which is a partial program extracted from a real machine program; The virtual on-chip network is used to intercept communication transactions sent by the processor core that need to be transmitted through the NoC. If the communication transaction is identified as a target communication transaction triggered by the simulation virtual machine, the target communication transaction is forwarded to the system simulation control layer; The system simulation control layer is used to simulate the network structure based on NoC, simulate the target communication transaction, and generate the simulation results of the target communication transaction; A clock adjuster is used to synchronize the clocks of the simulated virtual machine, the virtual on-chip network, and the system simulation control layer, so as to align the timing between the simulated virtual machine, the virtual on-chip network, and the system simulation control layer when the virtual on-chip network intercepts the target communication transaction and when the system simulation control layer completes the simulation processing of the target communication transaction.

2. The simulation system according to claim 1, wherein: The clock adjuster is specifically used for: When the virtual network on chip intercepts the target communication transaction, at least the clock of the simulation virtual machine, the clock of the virtual network on chip, and the clock of the system simulation control layer are paused; When the system simulation control layer completes the simulation processing of the target communication transaction, based on the simulation network delay of the target communication transaction evaluated by the system simulation control layer, the clock of the virtual on-chip network and the clock of the system simulation control layer are adjusted, and the clock of the simulation virtual machine is advanced; Among them, the simulated network delay of the target communication transaction is less than the simulation processing time of the system simulation control layer. The simulated network delay of the target communication transaction is the simulated network structure based on NoC, the theoretical network transmission time of the target communication transaction, and the simulation processing time is the time taken by the system simulation control layer to simulate the target communication transaction through software simulation.

3. The simulation system according to claim 2, wherein: The at least one simulated virtual machine is a single virtual machine, and the target communication transaction is a peripheral communication transaction in which the simulated virtual machine accesses a memory or an IO device; The system simulation control layer is used to simulate the target communication transaction based on the NoC simulation network structure, and the simulation results of the target communication transaction are generated, including: Based on the NoC simulation network structure, the access behavior model matching the peripheral communication transaction is called, the simulation processing of the peripheral communication transaction is performed, and the simulation result of the peripheral communication transaction is formed.

4. The simulation system according to claim 3, characterized in that The clock adjuster is further configured to: If the data accessed by the simulated virtual machine hits the cache, the simulated virtual machine's clock is used as the reference clock to advance the continued execution of the simulated business program, and the clock of the virtual on-chip network and the clock of the system simulation control layer are adjusted to synchronize with the clock of the simulated virtual machine.

5. The simulation system according to claim 3, characterized in that: When the simulation virtual machine completes the execution of the simulation business program or exits the execution of the simulation business program, the simulation process of the simulation system ends, and the simulation network delay of the target communication transaction and the simulation processing time of the system simulation control layer are used to evaluate the difference between the theoretical performance of the NoC simulation network structure and the processing efficiency of the simulation system.

6. The simulation system according to claim 2, characterized in that: The at least one simulation virtual machine is a plurality of simulation virtual machines, wherein the plurality of simulation virtual machines include a server simulation virtual machine and a client simulation virtual machine, wherein the server simulation virtual machine loads and executes the server simulation business program, and the client simulation virtual machine loads and executes the client simulation business program; The target communication transaction includes any one of the following: Before the server-side emulation virtual machine and the client-side emulation virtual machine have no communication interaction, the server-side emulation virtual machine accesses the memory or peripheral communication transactions of the IO device; The client simulates the server communication transaction initiated by the virtual machine; After the client emulation virtual machine initiates the first server communication transaction, the server emulation virtual machine initiates the communication transaction that needs to be transmitted through the NoC.

7. The simulation system according to claim 6, characterized in that: When the system simulation control layer simulates the server communication transaction initiated by the client simulation virtual machine, the server communication transaction is treated as a peripheral communication transaction and simulated in the simulation processing mode of the peripheral communication transaction.

8. The simulation system according to claim 6, characterized in that: The target communication transaction is a server communication transaction initiated by the client emulation virtual machine; the system emulation control layer is further used to: After completing the simulation processing of the server communication transaction initiated by the client simulation virtual machine, and advancing the clocks of the server simulation virtual machine and the client simulation virtual machine with the simulation network delay of the server communication transaction, the server simulation virtual machine is triggered by an interrupt to notify the server simulation virtual machine to respond to the server communication transaction, and at the same time control the client simulation virtual machine to continue running.

9. The simulation system according to claim 6, characterized in that: When the communication evaluation task between the client simulation virtual machine and the server simulation virtual machine is completed, or the test time of the server communication transaction initiated by the client simulation virtual machine reaches the preset test time, the simulation process of the simulation system ends, and the task number or task completion time of the server communication transaction initiated by the client simulation virtual machine is used for the performance evaluation of the simulated network structure of the NoC.

10. The simulation system according to claim 2, wherein: The virtual on-chip network is used to forward the target communication transaction to the system simulation control layer, including: storing the target communication transaction in the transaction queue of the virtual network on chip, and sending an interrupt notification to the system simulation control layer so that the system simulation control layer can obtain the target communication transaction from the transaction queue; The system simulation control layer is also used for: Temporarily store the simulation results in the transaction queue; When the clock advancement time of the simulation virtual machine corresponds to the simulation network delay, the simulation virtual machine is notified by interruption so that the simulation virtual machine can read the simulation result from the transaction queue; The transaction queue has at least one transaction entry, and one transaction entry records a target communication transaction of the simulation virtual machine and a corresponding simulation result. When the simulation virtual machine reads the simulation result from the transaction queue, the transaction entry containing the simulation result is deleted.

11. The simulation system according to any one of claims 1 to 10, characterized in that: The virtual on-chip network is further configured to: If the communication transaction is a non-target communication transaction, the communication transaction is transmitted to the real NoC for processing; Wherein, whether the communication transaction is a target communication transaction is identified by identification information of the communication transaction; the identification information of the communication transaction includes at least one of the following: The virtual machine identifier or program identifier that initiates the communication transaction; The access target address of the communication transaction; The transaction type of the communication transaction.

12. A NoC-oriented simulation method, characterized in that: The NoC-oriented simulation system according to any one of claims 1 to 11, wherein the simulation method comprises: Intercept communication transactions from processor cores that need to be transmitted through the NoC; Identifying whether the communication transaction is a target communication transaction triggered by a simulated virtual machine; wherein at least one simulated virtual machine is deployed on a virtualization platform and scheduled to run by a processor core, the simulated virtual machine is used to execute a simulated business program, and the simulated business program is a partial program extracted from a real machine program; If the communication transaction is a target communication transaction triggered by a simulation virtual machine, the target communication transaction is simulated based on the simulation network structure of the NoC to generate a simulation result of the target communication transaction; Furthermore, when the target communication transaction is intercepted and the simulation processing of the target communication transaction is completed, the clocks involved in the target communication transaction are synchronously controlled to align the timing.

13. The simulation method according to claim 12, characterized in that: The at least one simulated virtual machine is a single virtual machine, and the target communication transaction is a peripheral communication transaction in which the simulated virtual machine accesses a memory or an IO device; or, The at least one emulated virtual machine is a plurality of emulated virtual machines, the plurality of emulated virtual machines including a server emulated virtual machine and a client emulated virtual machine, wherein the server emulated virtual machine loads and executes a server emulated service program, and the client emulated virtual machine loads and executes a client emulated service program; and the target communication transaction includes any one of the following: Before the server-side emulation virtual machine and the client-side emulation virtual machine have no communication interaction, the server-side emulation virtual machine accesses the memory or peripheral communication transactions of the IO device; The client simulates the server communication transaction initiated by the virtual machine; After the client emulation virtual machine initiates the first server communication transaction, the server emulation virtual machine initiates the communication transaction that needs to be transmitted through the NoC.

14. A computer program, characterized in that The method comprises computer-executable instructions, which, when executed by a processor, implement the NoC-oriented simulation method according to any one of claims 12 to 13.

15. A physical host, characterized in that: The physical host is deployed with the NoC-oriented simulation system according to any one of claims 1 to 11, and the matching components of the simulation system; The mating components include: Virtual machine manager, which provides a virtualization environment to support the deployment of simulated virtual machines; Normal programs run by the processor core; Real NoC; Memory and peripherals.

Images