Circuit design verification method and device, verification equipment and storage medium

Abstract

The present disclosure provides a circuit design verification method and device, a verification equipment and a storage medium. The circuit design verification method comprises: in response to the design completion of a target function module in a plurality of function modules included in a physical module simulation, obtaining the target function module; determining the module physical constraint information of the target function module based on the target function module, the initial layout of the physical module and the physical module netlist, wherein the target function module is different from each function module existing in the initial layout in circuit logic, and the physical module netlist comprises the communication relationship between each function module in the physical module; and performing timing evaluation on the target function module based on the module physical constraint information to verify the corresponding circuit design of the target function module. The circuit design verification method realizes the separate timing evaluation of any function module in the physical module, and accelerates the process of circuit design verification.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a circuit design verification method and device, a verification device and a storage medium. BACKGROUND

[0002] In the design of integrated circuits, due to the large number of circuit modules and the complex interrelation between the circuit modules, a long iteration cycle (several days to several weeks) is often required when designing and verifying the integrated circuits. In addition, due to the high performance requirements of integrated circuits, multiple rounds of iteration optimization are often required for verification, which further lengthens the iteration cycle and seriously affects the iteration efficiency and delivery of the entire product. SUMMARY

[0003] At least one embodiment of the present disclosure provides a circuit design verification method, which comprises: in response to a target function module in a plurality of function modules included in a physical module simulation being designed, obtaining the target function module; determining module physical constraint information of the target function module based on the target function module, an initial layout of the physical module and a physical module netlist, wherein the target function module is different from each function module in the initial layout in circuit logic, and the physical module netlist comprises a communication relationship between each function module in the physical module; and performing timing evaluation on the target function module based on the module physical constraint information to verify the corresponding circuit design of the target function module.

[0004] At least one embodiment of the present disclosure also provides a circuit design verification device, which comprises: an obtaining unit, a determining unit and a verification unit. The obtaining unit is configured to obtain a target function module in response to the target function module being designed in a plurality of function modules included in a physical module simulation; the determining unit is configured to determine module physical constraint information of the target function module based on the target function module, an initial layout of the physical module and a physical module netlist, wherein the target function module is different from each function module in the initial layout in circuit logic, and the physical module netlist comprises a communication relationship between each function module in the physical module; and the verification unit is configured to perform timing evaluation on the target function module based on the module physical constraint information to verify the corresponding circuit design of the target function module.

[0005] At least some embodiments of the present disclosure also provide a verification device, which comprises: at least one memory and at least one processor, the at least one memory is configured to store computer executable instructions; and the at least one processor is configured to execute the computer executable instructions, wherein the computer executable instructions are executed by the at least one processor to implement the circuit design verification method provided by any embodiment of the present disclosure.

[0006] The disclosure at least some embodiments also provide a non-transitory storage medium, which non-transitorily stores computer-executable instructions, wherein when the computer-executable instructions are executed by at least one processor, the circuit design verification method provided by any of the embodiments of the disclosure is implemented. BRIEF DESCRIPTION OF DRAWINGS

[0007] In order to more clearly illustrate the technical solutions of the embodiments of the disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are merely related to some of the embodiments of the disclosure, and not a limitation of the disclosure.

[0008] Figure 1 A flowchart of a verification method is shown;

[0009] Figure 2 A flowchart of a circuit design verification provided by at least one embodiment of the disclosure is shown;

[0010] Figure 3 An exemplary flowchart of a circuit design verification provided by at least one embodiment of the disclosure is shown;

[0011] Figure 4 (a) in FIG. 1 shows an exemplary schematic diagram of an initial physical boundary range provided by at least one embodiment of the disclosure;

[0012] Figure 4 (b) in FIG. 1 shows an exemplary schematic diagram of an occupied first window provided by at least one embodiment of the disclosure;

[0013] Figure 4 (c) in FIG. 1 shows an exemplary schematic diagram of a target physical boundary range provided by at least one embodiment of the disclosure;

[0014] Figure 5 An exemplary schematic diagram of a window provided by at least one embodiment of the disclosure is shown;

[0015] Figure 6 An exemplary flowchart of determining a target physical boundary range provided by at least one embodiment of the disclosure is shown;

[0016] Figure 7 An exemplary schematic diagram of determining pin information provided by at least one embodiment of the disclosure is shown;

[0017] Figure 8 An exemplary flowchart of determining pin information provided by at least one embodiment of the disclosure is shown;

[0018] Figure 9 A flowchart of a circuit design verification provided by at least one embodiment of the disclosure is shown;

[0019] Figure 10 A block diagram of a circuit design verification apparatus is shown.

[0020] Figure 11 A block diagram of a verification device is shown.

[0021] Figure 12 A schematic diagram of a non-transitory storage medium is shown. DETAILED DESCRIPTION

[0022] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0023] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning of the terms to a person of ordinary skill in the art to which the present disclosure belongs. The terms “first”, “second” and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. Similarly, the terms “one”, “a” or “the” and similar terms do not denote quantity restriction, but denote existence of at least one. The terms “include”, “contain” and similar terms mean that the components or objects before the terms encompass the components or objects listed after the terms and their equivalents, and do not exclude other components or objects. The terms “connect” or “connected” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper”, “lower”, “left”, “right” and the like only represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0024] The present disclosure will be described below through several specific embodiments. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of known functions and known components. When any component of the embodiments of the present disclosure appears in more than one figure, the component is denoted by the same or similar reference numeral in each figure.

[0025] With the increasing scale of integrated circuit design, especially for large and complex chips, in order to meet the timing requirements of high performance design, front-end design engineers need to work with back-end design engineers to complete the chip design. Each front-end design engineer usually implements the specific function of the functional module (Module) responsible for the function by using hardware description language (Verilog or HDL), and delivers the functional module design code (referred to as code, such as register transfer level code, RTL); Each back-end design engineer is usually responsible for the physical implementation integration and verification of the physical module (Tile) responsible for the chip (for example, performing physical logic synthesis on the physical module to evaluate the timing of the physical module). Before the formal production of large and complex chips, the front-end design engineers need to modify and optimize the design according to the timing of the back-end physical implementation to ensure that the chip can achieve the expected performance indicators.

[0026] Physical logic synthesis is a link in the design process of large integrated circuits (such as chips), which can combine the logical design (layout and wiring) of the circuit and the physical information (chip size, pin position, layout planning information, etc.) of the corresponding circuit to generate a netlist (Netlist) of the corresponding circuit.

[0027] There are mainly two scenarios for the chip design verification by the front-end design engineers:

[0028] (1) The code delivered by the front-end design engineer is found to have problems in the front-end verification (such as functional logic verification of the functional module), and needs to be corrected (such as functional logic correction) and re-timed after the code is corrected.

[0029] (2) The code delivered by the front-end design engineer has passed the front-end verification, but in the physical implementation verification of the back-end, it is found that the physical module where the functional module is located cannot complete the timing convergence, and the corresponding functional module needs to be found from the physical module to modify and optimize the code and re-timed.

[0030] Figure 1 A flowchart of a verification method is shown to Figure 1For example, in a traditional verification process, after a front-end engineer finishes the design of a function module (e.g., Module X) in a physical module (e.g., Tile X), the engineer delivers the code Module X.v (step 101). The engineer then needs to wait until all other function modules in the physical module are designed (e.g., step 102 obtains Another.v) and then integrates the SOC (chip system) (step 103). After the integration, the physical code file Tile X.v of the corresponding physical module is obtained from the integrated code of the entire chip (step 104). The physical constraint information (e.g., the design exchange format file of the physical module, Tile X.def, obtained in step 105) of the physical module is included in the physical code file Tile X.v, and physical logic synthesis (step 106) is performed on the physical code file Tile X.v to generate the netlist Tile X.netlist of the physical module (step 107). Then, the physical design (Tile X PD, Physical Design) of the physical module is performed (step 108), and the timing evaluation (e.g., step 109 static timing analysis, Tile X STA, Static Timing Analysis) of the physical module is performed to obtain the timing evaluation Module X STA of the corresponding function module Module X in the physical module (step 110).

[0031] Because of the differences in design size and structure, a physical module often contains multiple function modules, and there is a relatively complex spatial layout relationship. Therefore, after the front-end design engineer finishes the design of a function module, the engineer needs to wait until the code design of other function modules in the physical module is completed, and then integrates and verifies the SOC (chip system) as a whole. After the back-end design engineer obtains the code after the SOC integration of the entire chip, the engineer needs to flatten the entire chip structure through the top-level design and perform global optimization, so as to divide the chip into different physical code files (e.g., Tile X.v) according to different physical modules, and then perform further physical implementation (e.g., physical logic synthesis, physical design PD, and static timing analysis Tile X STA) of the corresponding physical module.

[0032] Therefore, in the chip design verification process, the front-end design engineer as a function module designer needs to wait for a long time (several days to several weeks) to know the timing situation (e.g., whether the timing requirement can be met) of the function module in the physical implementation. In high-performance and large-scale complex chip design, because more rounds of front-end and back-end iterative optimization are often required, the iteration period of chip design is further lengthened, which seriously affects the iteration efficiency of chip design and the efficiency of chip production, resulting in a long delivery cycle of the chip.

[0033] The inventors of the present disclosure notice that, in the chip design verification process, the front-end design engineers hope to quickly know the timing conditions of the functional modules designed by themselves when the chip is physically implemented after submitting the codes, so as to quickly find the timing problems of the functional modules. However, as shown in the verification method, due to the time difference and information difference between the front-end and the back-end of the chip design, and the complexity of the functional modules in the physical modules due to the mutual logical dependence, it is difficult for the front-end design engineers to timely obtain the timing evaluation results of the physical modules in the physical implementation of the chip, thereby affecting the efficiency of the design optimization of the functional modules responsible. Figure 1

[0034] The inventors of the present disclosure notice that, in the chip design verification process, the front-end design engineers hope to quickly know the timing conditions of the functional modules designed by themselves when the chip is physically implemented after submitting the codes, so as to quickly find the timing problems of the functional modules. However, as shown in the verification method, due to the time difference and information difference between the front-end and the back-end of the chip design, and the complexity of the functional modules in the physical modules due to the mutual logical dependence, it is difficult for the front-end design engineers to timely obtain the timing evaluation results of the physical modules in the physical implementation of the chip, thereby affecting the efficiency of the design optimization of the functional modules responsible.

[0035] The present disclosure provides a circuit design verification method, which comprises the following steps: in response to the design completion of a target functional module in a plurality of functional modules included in a physical module, obtaining the target functional module; determining module physical constraint information of the target functional module based on the target functional module, an initial layout of the physical module, and a physical module netlist, wherein the target functional module is different from each functional module in the initial layout in circuit logic, and the physical module netlist comprises the communication relationship between each functional module in the physical module; and performing timing evaluation on the target functional module based on the module physical constraint information, to verify the corresponding circuit design of the target functional module.

[0036] In the circuit design verification method of the above-mentioned embodiments of the present disclosure, the corresponding module physical constraint information of the determined target functional module can be directly obtained, so that the timing evaluation of the target functional module can be independently performed when there is a logical dependence between the target functional module and other functional modules in the physical module, thereby realizing the separate timing evaluation of any functional module in the physical module. In this way, the module physical constraint information at the functional module level can be obtained without going through the whole timing evaluation of the physical module each time, thereby accelerating the process of circuit design verification, improving the quality of circuit design, and shortening the research and development cycle of the circuit.

[0037] ​Further, when the scenario (1) occurs, the front-end design engineer can also consider the timing conditions of the physical implementation when modifying the function logic of the function module, so as to make a function logic modification with minimal impact on the timing, thereby improving the efficiency of design optimization of the function module. Further, since the front-end design engineer can verify the function module after the function module is designed to ensure that the timing evaluation of the delivered function module passes, when the back-end design engineer obtains the function modules for physical implementation, integration and verification, there is no need to return to the front-end, further improving the efficiency.

[0038] The various embodiments of the present disclosure will be described below in conjunction with specific examples.

[0039] As shown in the figure, in some embodiments of the present disclosure, the circuit design verification method comprises steps S20-S22. Figure 2

[0040] Step S20: in response to the design completion of a target function module in a plurality of function modules included in a physical module, the target function module is obtained.

[0041] Step S21: based on the target function module, the initial layout of the physical module and the physical module netlist, the module physical constraint information of the target function module is determined.

[0042] The target function module is different from each function module already existing in the initial layout in circuit logic, and the physical module netlist includes the communication relationship between each function module in the physical module.

[0043] Step S22: based on the module physical constraint information, the timing evaluation of the target function module is performed to verify the corresponding circuit design of the target function module.

[0044] The target function module is any function module in the plurality of function modules included in the physical module, and the target function module can be a function module included in the physical module but not included in the initial layout, or a function module already included in the initial layout but modified in circuit logic.

[0045] For example, the target function module can be implemented through function module design code. The function module design code (hereinafter also referred to as code) can be a code for implementing the specific function of the function module (Module) responsible for the function module through a hardware description language (Verilog or HDL), for example, the function module design code can be an RTL (Register Transfer Level) code. It should be noted that the implementation method of the target function module described above is only an example, and the implementation method of the specific target function module is not limited in the present disclosure.

[0046] ​The target function module design completion can be a function design completion (e.g., code writing completion) of the target function module or a modification completion (e.g., code modification completion) of the target function module. For example, the code modification can be a function logic update or a timing modification of the target function module.

[0047] The initial layout is a layout of the physical module corresponding to the target function module between the target function module design completion. Since the iterations of the function modules of the chip are progressive during the development of the integrated circuit (e.g., chip), the design layout of the initial layout can be adjusted and optimized, so as to gradually realize the timing convergence (satisfy the timing requirement) of the chip. For example, since there is a certain continuity in the physical constraints between the front and back versions (e.g., the initial layout and the next layout of the initial layout) of the chip design, when the target function module is optimized, the module physical constraint information of the target function module can be determined according to the physical implementation of the physical module in the last version (e.g., the initial layout), so as to perform timing evaluation on the target function module.

[0048] Since the physical module includes multiple function modules, and there can be a logical dependency between the function modules, for example, there are several function modules in the physical module that need to communicate with each other to jointly implement the same complete function, when the module physical constraint information of the target function module is determined, the communication relationship between the other function modules and the target function module can be determined through the physical module netlist (Tile netlist) recording the communication relationship between the function modules in the physical module.

[0049] In some embodiments of the present disclosure, the module physical constraint information includes a target physical boundary range of the target function module and pin information of the target function module; in this case, the above circuit design verification method includes: determining the target physical boundary range according to the target function module and the initial layout; and determining the pin information according to the target physical boundary range and the physical module netlist.

[0050] For example, after the target function module is loaded into the initial layout, the module physical constraint information of the target function module can be obtained by excluding other modules in the initial layout except the target function module. For example, after the target function module is loaded into the initial layout, the target physical boundary range can be determined by excluding the boundary range of the target function module in the initial layout. For example, after the target function module is loaded into the initial layout, the pin information can be determined according to the target physical boundary range by excluding the timing path information irrelevant to the target function module according to the physical module netlist.

[0051] For example, the circuit design verification can be performed on the target function module of a certain project that needs to be iterated and modified, Figure 3An exemplary flowchart of a circuit design verification is shown, and the following will be described in detail in combination with Figure 3 The above case will be described in detail.

[0052] The physical design information of the physical module can be acquired according to the initial layout (step 301), wherein the physical design information includes the size of the initial layout of the physical module, the placement position of each standard cell in the initial layout, the timing path information (Route) between each functional module in the initial layout, and the pin information of each functional module in the initial layout.

[0053] For example, the target functional module to be acquired can be selected according to the module list in the physical module (for example, the target functional module with iteration / modification requirement to be paid attention to by the project is acquired in step 302), and the target functional module can be determined according to the identification of the functional module. The module list records which functional modules are included in the initial layout of the physical module, for example, the identification (name) of the functional module.

[0054] According to the acquired target functional module, the target physical boundary range of the target functional module on the initial layout can be determined (step 303), and then the pin information of the target functional module can be determined according to the target physical boundary range and the physical module netlist (step 304), so as to determine the module physical constraint information of the target functional module. For example, the target physical boundary range can be the physical boundary range corresponding to the target functional module determined in the initial layout by a layout tool according to the functional module design code for realizing the target functional module, and the layout tool can be an integrated circuit layout processing tool such as an electronic design automation tool (EDA), and the present disclosure does not limit the specific layout tool.

[0055] For example, the corresponding file including the module physical constraint information can be output (step 305), for example, the module design exchange format file (for example, Module A.def) of the target functional module can be output.

[0056] In some cases, since the position distribution of the standard cells of the target functional module is often irregular, the target physical boundary range obtained directly according to the target functional module is also often irregular, which will cause that when the layout tool (for example, EDA) is used to capture the target functional module, a very complex polygon area will be captured, thereby affecting the processing of the layout tool.

[0057] In some embodiments of the present disclosure, the circuit design verification method comprises: determining an initial physical boundary range of the target function module in the initial layout according to the target function module by using a layout tool; and optimizing the initial physical boundary range to determine a target physical boundary range.

[0058] In order to avoid the difficulty in processing the target function module by the layout tool due to the complex boundary, the boundary range obtained by loading the target function module in the initial layout after the design of the target function module is completed can be used as the initial physical boundary range. By optimizing the initial boundary range, a target physical boundary range with a relatively regular boundary range is determined, so that the processing of the target function module by the layout tool is more efficient and more accurate.

[0059] In some embodiments of the present disclosure, the initial layout including the initial physical boundary range is divided into a plurality of windows, and a first window is a window that overlaps with the initial physical boundary range among the plurality of windows. In this case, the circuit design verification method comprises:

[0060] According to the size of the overlapping part of each first window and the initial physical boundary range, a corresponding occupation state of each first window is determined, and the occupation state includes occupied and unoccupied.

[0061] According to the first window with the occupied occupation state and the initial physical boundary range, a correction number and a correction direction of a second window are determined, wherein the second window is a window for correcting the boundary range formed by the occupied first window among the plurality of windows.

[0062] According to the second window and the occupied first window, the target physical boundary range is determined.

[0063] The shape of the window can be, for example, a square, a rectangle, etc., and the present disclosure does not limit the shape of the window.

[0064] Taking the target function module Module A as an example, Figure 4 (a) of FIG. 1 shows an exemplary schematic diagram of an initial physical boundary range provided by at least one embodiment of the present disclosure; Figure 4 (b) of FIG. 1 shows an exemplary schematic diagram of an occupied first window provided by at least one embodiment of the present disclosure.

[0065] As shown in (a) of FIG. 1, Figure 4 The initial layout of the physical module Tile Axx has an irregular initial physical boundary range O-Module A (the shaded part) of the target function module Module A. For example, the initial layout including the initial physical boundary range O-Module A can be divided into a plurality of windows of the same size. After the window division, as shown in Figure 4The initial physical boundary range O-Module A shown in (a) in the above figure overlaps with some of the panes, and the panes that include the initial physical boundary range O-Module A are the first panes.

[0066] For example, the occupancy state of each first pane can be determined according to how much (i.e., the size of the overlapping part) of the initial physical boundary range is included in each first pane. For example, the occupancy state can be determined by judging whether the size of the overlapping part reaches a certain preset occupancy ratio. For example, the corresponding first pane can be marked as occupied if the size of the overlapping part reaches the preset occupancy ratio, and the corresponding first pane can be marked as unoccupied if the size of the overlapping part does not reach the preset occupancy ratio. Figure 4 As shown in (b) in the above figure, after marking the occupancy state, the occupied first pane F-Module A is determined.

[0067] For example, the number of corrections and the correction direction of the second pane can be determined according to the first pane with the occupancy state of occupied and the initial physical boundary range. The second pane is a pane in the plurality of panes for correcting the boundary range formed by the occupied first pane.

[0068] The number of corrections includes the number of second panes for correcting the boundary range formed by the occupied first pane and the corresponding correction operation (increase or decrease). For example, the number of corrections can be an integer, for example, a positive integer indicating how many second panes are added to the occupied first pane, and a negative integer indicating how many second panes are reduced from the occupied first pane. For example, the number of corrections -1 can indicate that one second pane is reduced from the occupied first pane, and the number of corrections +1 can indicate that one second pane is added to the occupied first pane.

[0069] The correction direction indicates where the corresponding second pane with the number of corrections is to be corrected in the boundary range formed by the occupied first pane.

[0070] In some embodiments of the present disclosure, the above circuit design verification method comprises:

[0071] In response to the number of corrections indicating that the corresponding number of second panes is reduced from the occupied first pane, the occupancy state of the second pane is marked as unoccupied; or, in response to the number of corrections indicating that the corresponding number of second panes is added to the occupied first pane, the occupancy state of the second pane is marked as occupied; and the panes with the occupancy state of unoccupied corresponding to the target functional module are shielded to determine the target physical boundary range.

[0072] In Figure 4(c) of FIG. 1 shows an exemplary schematic diagram of a target physical boundary range according to at least one embodiment of the present disclosure.

[0073] For example, the correction number of the second pane is 0, and the target physical boundary range of the target function module Module A is the same as the occupied first pane F-Module A, as shown in (c) of FIG. 1. Figure 4 As shown in (c) of FIG. 1, the target physical boundary range of the target function module Module A can be separated in the initial layout. For example, the occupation state of the pane in the separated layout corresponding to the target function module can be marked as an unoccupied pane (i.e., the occupation state of the pane corresponding to the target function module is an unoccupied pane). For example, the unoccupied pane can be covered by a blockage mark blockage (such as the grid part shown in the figure, for example, it can also be covered by a red blockage, etc.). After the blockage, the remaining panes that are not blocked are the target physical boundary range of Module A. For example, a module design exchange format file (for example, Module A.def) including the target physical boundary range of the target function module can be output after the blockage.

[0074] Figure 5 An exemplary schematic diagram of a pane is shown according to at least one embodiment of the present disclosure.

[0075] For example Figure 5 The pane shown in FIG. 1 is a first pane, the pane height (also referred to as pane length hereinafter) of the first pane is Y, and the pane width of the first pane is X. The boxes in the first pane are positions that can accommodate standard cells. For example, the total area of the standard cells that can be accommodated in the first pane can be denoted as S win For example Figure 5 the total area of all white boxes and dark boxes in FIG. 1), the total area of the standard cells in the first pane corresponding to the size of the overlapping part of the initial physical boundary range can be denoted as S std For example Figure 5 the total area of all dark boxes in FIG. 1), and the preset standard cell occupation rate is denoted as Q. The above circuit design verification method comprises:

[0076] In response to S std / S win ≥ Q, the occupation state of the first pane is marked as occupied; or, in response to S std / S win < Q, the occupation state of the first pane is marked as unoccupied.

[0077] The preset standard cell occupancy rate Q can be preset, and the specific setting value and setting manner are not limited by the present disclosure. Since the size of each pane in the plurality of panes is the same, the area of other panes in the plurality of panes is equal to the area of the standard cells that can be accommodated in the first pane, that is, S win .

[0078] For example, the actual occupancy rate in the first pane can be denoted as P, P = S std / S win , and the occupancy state of the corresponding first pane is determined by comparing the actual occupancy rate P in each first pane and the preset standard cell occupancy rate Q. The occupancy state indicates whether the corresponding first pane is occupied by the target function module.

[0079] For example, the size of the overlapping part in one of the first panes includes N standard cells (Std Cell), and N is a positive integer. The total area of the standard cells corresponding to the size of the overlapping part of the initial physical boundary range is S std = S std 1 + S std 2 +... + S std N.

[0080] For example, the occupancy state can be marked by an occupancy value, such as an occupancy value F, where the occupancy value F = 1 represents occupied, and the occupancy value F = 0 represents not occupied. The above circuit design verification method comprises: determining the residual area S win of each of the n first panes according to the area S std of the standard cells that can be accommodated in the first pane, the area S fix_n of the standard cells corresponding to the size of the overlapping part of the initial physical boundary range in the first pane, and the occupancy value F, where n is a positive integer.

[0081] For example, the preset standard cell occupancy rate Q is set to 0.5. If the actual occupancy rate P of a first pane is ≥0.5, the occupancy value F of the first pane is recorded as F = 1, indicating that the first pane has been occupied by the target function module. If the actual occupancy rate P of a first pane is <0.5, the occupancy value F of the first pane is recorded as F = 0, indicating that the first pane has not been occupied by the target function module.

[0082] The residual area S fix_n of each first pane is recorded, where n is the number of first panes, and n is a positive integer. For example, the residual area S fix_n of the first pane is S std - (S win * F).

[0083] For example, according to the above formula, when the first pane has been occupied, the residual area Sfix_n is negative, the value of the residual area represents the sum of areas of standard cells not belonging to the target function module within the first pane; when the first pane is occupied, the residual area S fix_n of the first pane is positive, the value of the residual area represents the sum of areas of standard cells belonging to the target function module within the first pane.

[0084] According to the residual area of each first pane, a residual area sum S fix_sum is determined. fix_sum = S fix_1 + S fix_2 +... + S fix_n .

[0085] According to the residual area sum S fix_sum , a correction number of a second pane is determined.

[0086] The residual area sum S fix_sum may represent a difference range between the boundary range formed by the occupied first pane and the real physical boundary range (initial physical boundary range) of the target function module, so that in the case of a larger difference range, the boundary range formed by the occupied first pane is corrected by the corresponding correction number of the second pane.

[0087] In some embodiments of the present disclosure, the above circuit design verification method further comprises: determining a standard cell average area S avg of each pane in the physical module; and determining the correction number of the second pane according to a modulo calculation result of the residual area sum S fix_sum and the standard cell average area S avg .

[0088] The standard cell average area S avg may be determined according to an average utilization rate U std_avg of standard cells in the physical module multiplied by the area of the first pane, which is equal to the pane height Y of the first pane multiplied by the pane width X of the first pane. The standard cell average area S avg = U std_avg * X* Y.

[0089] For example, the correction number of the second pane can be determined according to the remainders after modulo operation of the standard cell average area S avg of each pane in the physical module and the residual area sum S fix_sum . For example, the correction number of the second pane is denoted as C fix , then the correction number C fix = floor (S fix_sum % S avg ., is a modulo symbol.

[0090] For example, the circuit design verification method further includes: according to the arrangement of the occupied first window in the first direction and the second direction, determining the direction in which the occupied first window is arranged in a smaller number as the correction direction of the second window.

[0091] The first direction and the second direction are different directions in which the windows are arranged in the initial layout. For example, the first direction can be the horizontal direction, and the second direction can be the vertical direction; or the first direction is the vertical direction, and the second direction is the horizontal direction. The specific directions of the first direction and the second direction are related to the arrangement direction of the plurality of windows divided in the initial layout, and the present disclosure does not limit this.

[0092] The determination of the second window correction direction is described below taking the horizontal direction and the vertical direction as examples. For example, in the boundary range formed by the occupied first window, the maximum window number of the first window arranged in the horizontal direction is C H , and the maximum window number of the first window arranged in the vertical direction is C V .

[0093] For example, C H > C V , it can be determined that the second window corresponding to the correction number is supplemented to the vertical edge of the occupied first window, and the maximum window number of the first window arranged in the vertical direction after correction is updated to C V_fix = C V + C fix .

[0094] For example, C V > C F , it can be determined that the second window corresponding to the correction number is supplemented to the horizontal edge of the occupied first window, and the maximum window number of the first window arranged in the horizontal direction after correction is updated to C H_fix = C H + C fix .

[0095] By determining the correction number of the second window according to the total residual area sum, the area difference between the determined target physical boundary range and the initial physical boundary range is very small (the error is approximately within one window), and the irregularity of the initial physical boundary range is optimized, so that the discrete arrangement in the irregular initial physical boundary range is regularized, the difficulty of processing the target function model by the layout tool is reduced, thereby avoiding the error processing of the layout tool, and ensuring the consistency of the obtained module physical constraint information and the actual physical constraint information of the target function module in actual design.

[0096] For example, the size of the plurality of windows is determined according to the number of windows divided in the initial layout and the area ratio of the target functional module in the physical module.

[0097] For example, when the layout tool (for example, the EDA tool) determines the target physical boundary range of the target functional module, it can be determined within a certain number of windows to achieve the expected processing effect. For example, it can be determined that the number of windows of the plurality of windows is within 40-80 to achieve the expected processing effect, for example, the number of windows of the plurality of windows is marked as j, and the number of windows of the plurality of windows j=60 can be taken.

[0098] For example, the ideal number of standard cells in one physical module is about 3 million (million), and the ratio of the functional module (for example, the target functional module) to be verified in the entire physical module is marked as k, for example, the ratio of the target functional module in the entire physical module k=0.2.

[0099] For example, the proportional relationship between the height and the width of the standard cell can be determined according to the empirical value of the size of different standard cells, for example, it can be determined that the width of the standard cell is about 4 times the height. For example, the size relationship between the window and the standard cell can be set as follows: the height Y of the window is equal to x times the height of the standard cell, then according to the equation x*(x / 4)*j / k=3000000 (3 million), x=200 is obtained, which means that the height of the window is equal to 200 times the height of the standard cell, and the width of the window is equal to 200 times the width of the standard cell.

[0100] Through the window size determination method of the above embodiment, the size of the window can be adaptively adjusted according to the size of different standard cells, so that the size division of the window can better adapt to the boundary optimization demand of the target functional module.

[0101] Figure 6 An exemplary flowchart for determining a target physical boundary range is shown. The following is an example of determining a target physical boundary range according to the flowchart shown. Figure 6 The flowchart shown is an example of the overall process of determining the target physical boundary range.

[0102] First, the physical module is divided into a plurality of windows with length X and width Y, and the area of any one window is determined as S win (step 601), for example, the first window is determined according to the initial physical boundary range of the target functional module Module A in the plurality of windows.

[0103] All standard cells in the first window are traversed, and the sum of the areas of all standard cells of the functional module in the first window S std = S std 1 + Sstd 2 +… S std N (Step 602).

[0104] For example, setting the preset standard unit occupancy rate Q to 0.5, and determining S for each first pane. std / S win (P)≥0.5 (Q) is true (step 603).

[0105] Based on the judgment result, the occupancy status of the first pane is marked by the occupancy value. If not, as in step 604, the corresponding first pane occupancy value is set to 0 (unoccupied); if yes, as in step 605, the corresponding first pane occupancy value F is set to 1 (occupied).

[0106] After marking the occupancy status of all first panes, iterate through and determine the residual area S of each first pane. fix_n = S std – (S win * F) (Step 606).

[0107] Next, determine the difference between the boundary range formed by the occupied first pane and the actual physical boundary range (initial physical boundary range) of the target functional module, which is the sum of the residual areas: S fix_sum = S fix_1 + S fix_2 + ... +S fix_n The correction amount for the second pane is determined to be: C fix =S fix_sum % S avg The second pane corresponding to the corrected quantity is placed in the direction where the number of first panes occupied in the horizontal and vertical directions is less (step 607).

[0108] For example, if the number of horizontal panes in the occupied first pane is greater than the number of vertical panes, it can be determined that a second pane with the corresponding corrected number will be added to the vertical edge of the occupied first pane.

[0109] Subsequently, in response to the quantity correction instruction, the number of second panes is reduced by the corresponding number based on the number of occupied first panes, and the occupancy status of the second panes is marked as unoccupied.

[0110] Alternatively, in response to a quantity adjustment instruction, a corresponding number of second panes are added to the already occupied first pane, and the occupied status of the second panes is marked as occupied.

[0111] At this time, the target physical boundary range can be determined according to the second window and the occupied first window. Since the windows corresponding to the target physical boundary range of the target function module have been marked as occupied through the above steps, the part including the occupied windows corresponding to the target function module can be separated from the initial layout, and the corresponding unoccupied windows in the separated part are marked with a blockage, so as to determine the target physical boundary range of the target function module (step 608).

[0112] For example, a module design exchange format file Module A.def of the target function module can be output, which includes the target physical boundary range of the target function module.

[0113] In some embodiments of the present disclosure, the circuit design verification method further includes: determining the timing path information between the target function module and other function modules in the physical module netlist based on the physical module netlist, wherein the timing path information includes the input-to-register timing path and / or the register-to-output timing path; and determining the pin information of the target function module based on the target physical boundary range and the timing path information.

[0114] The physical module netlist records the communication relationship between the target function module and other function modules, so the timing path information between the target function module and other function modules can be determined.

[0115] For example, the input-to-register timing path and / or the register-to-output timing path between the target function module and other function modules can be obtained, the overlapping part of each timing path in the target physical boundary range is determined, so as to plan the pin position of the target function module, and the pin information of the target function module is determined according to the pin position.

[0116] In some embodiments of the present disclosure, the circuit design verification method further includes: obtaining the target physical edge of the target physical boundary range; and determining the pin information of the target function module according to the intersection of the input-to-register timing path and / or the register-to-output timing path and the target physical edge.

[0117] The pin information is used to determine the interface that must be passed through when other modules communicate with the target function module. After the pin information is determined, the timing evaluation of the target function module will obtain more accurate evaluation results closer to the actual situation, avoiding the situation that the position of the pin that the target function module can actually communicate is ignored when the timing is evaluated, and the timing evaluation result is overly optimistic and lacks practical reference significance. For example, when the necessary interface is ignored, the timing path of the communication between other modules and the internal register of the target function module becomes shorter (for example, the situation of direct connection bypassing the necessary interface occurs), which leads to inaccurate and overly optimistic timing evaluation, and lacks practical reference significance.

[0118] Figure 7 An exemplary schematic diagram for determining pin information is shown; Figure 8 An exemplary flowchart for determining pin information is shown. Figure 7 and Figure 8 are described in detail below.

[0119] As Figure 7 shown, taking the target physical boundary range of a certain target function module (for example, Module A) as an example, the target physical boundary range of the target function module is shown as the shaded area in Figure 7 . The target physical boundary of the target physical boundary range is denoted as Boundary, and the endpoints of the target physical boundary include endpoint a (x1, y1), endpoint b (x2, y2), endpoint c (x3, y3), and endpoint d (x4, y4). For example, Figure 7 The target physical boundary in may be denoted as Boundary (x1, y1)-(x2, y2)-(x3, y3)-(x4, y4), that is, the boundary formed by the connection of endpoint a (x1, y1), endpoint b (x2, y2), endpoint c (x3, y3), and endpoint d (x4, y4).

[0120] The timing paths of the target function module Module A to other modules include two timing paths, namely, the timing path of the register to the output reginA-pinA-regoutA and the timing path of the input to the register reginB-pinB-regoutB.

[0121] For example, the position of the pin information can be determined through the steps shown in Figure 8 . After obtaining the target physical boundary range of the target function module, all timing path information of the target function module to other function modules can be obtained (step 801), for example, the two timing paths shown in Figure 7 may be obtained.

[0122] The positions of the start registers of the timing paths can be obtained (step 802), for example, the positions of the start and end registers of the paths on the initial layout are obtained, for example, the coordinates reginA(x 1A ,y 1A ), regoutA(x 2A ,y 2A ) and reginB(x 1B ,y 1B ), regoutB(x 2B ,y 2B ) of the start and end registers can be obtained.

[0123] The edge of the target physical boundary range can be determined as the target physical edge of the target functional module. For example, the target physical edge is determined according to the connection of the end point coordinates of the target physical boundary range. For example, the target physical edge Boundary (x1, y1)-(x2, y2)-(x3, y3)-(x4, y4) in the above Figure 7

[0124] When the Boundary intersects the connection of the timing path corresponding to the start register, the intersection point is determined as the pin coordinate of the target functional module, for example, the pin coordinates pinA(x 3A ,y 3A ) and pinB(x 3B ,y 3B ), and the pin coordinates are determined as the pin information of the target functional module (step 803).

[0125] For example, a pin design exchange format file Pin A.def of the target functional module can be generated according to all the pin information of the target functional module, and the file is output (step 804).

[0126] The pin information of the target physical module is constructed efficiently and quickly by performing intersection point operation on the connection of the timing path corresponding to the hint register and the target physical edge.

[0127] For example, the circuit design verification method further includes: performing physical logic synthesis based on the module physical constraint information to generate a netlist of the target functional module; and performing timing evaluation based on the netlist of the target functional module and the module physical constraint information to obtain a timing evaluation result; wherein the timing evaluation result is used to verify whether the circuit design corresponding to the target functional module meets the expectation.

[0128] For example, the expectation can be whether the circuit design can be timing-converged, whether the circuit design meets the delay requirement, etc. The expectation for the circuit design can be set differently according to different circuit conditions, which is not limited in the present disclosure.​

[0129] For example, in the step of physical logic synthesis, the logic design corresponding to the target function module and the module physical constraint information of the target function module are synthesized to generate a target function module netlist corresponding to the target function module.

[0130] For example, if the circuit corresponding to the target function module does not meet the expectation, it means that the target function module needs to be adjusted, for example, the function module design code for implementing the target function module can be modified. The modified target function module can also continue to be verified by the circuit design verification method of any one of the embodiments of the present disclosure until the expectation is met.

[0131] Figure 9 A flowchart of a circuit design verification method is shown.

[0132] As shown in Figure 9 When the target function module Module A is designed, the function module design code Module A.v of Module A is obtained (step 901), the module design exchange format file ModuleA.def including the target physical boundary range, and the pin design exchange format file Pin A.def including the pin information of the target function module (step 902) are used for physical logic synthesis (step 903).

[0133] After physical logic synthesis, the target function module netlist Module A netlist is generated (step 904), and then the physical design (PD, Physical Design) of the target function module Module A (step 905) and the timing evaluation of the target function module Module A (for example, STA, Static Timing Analysis, of step 906) are performed, so that the traditional verification process needs to wait for other function modules when verifying a certain target function module in the physical module, and the steps of physical logic synthesis at the physical module level, physical design at the physical module level, and timing evaluation at the physical module level in the traditional verification process are also avoided, so that the accurate timing evaluation of the target function module is directly obtained to verify whether the circuit design corresponding to the target function module meets the expectation. Through the above method, the verification efficiency and iteration speed of the function module level are greatly improved.

[0134] The present disclosure at least one embodiment also provides a circuit design verification device, Figure 10 A block diagram of a circuit design verification device is shown, and the following will be described in detail. Figure 10 ​

[0135] The circuit design verification apparatus 1000 comprises an acquisition unit 1010, a determination unit 1020, and a verification unit 1030.

[0136] The acquisition unit 1010 is configured to acquire a target function module from a plurality of function modules included in a physical module in response to completion of design of the target function module.

[0137] The determination unit 1020 is configured to determine module physical constraint information of the target function module based on the target function module, an initial layout of the physical module, and a physical module netlist, wherein the target function module is different from each function module in the initial layout in circuit logic, and the physical module netlist comprises a communication relationship between each function module in the physical module.

[0138] The verification unit 1030 is configured to perform timing evaluation on the target function module based on the module physical constraint information, so as to verify a corresponding circuit design of the target function module.

[0139] For example, the module physical constraint information comprises a target physical boundary range of the target function module and pin information of the target function module; the determination unit 1020 is further configured to determine the target physical boundary range according to the target function module and the initial layout, and determine the pin information according to the target physical boundary range and the physical module netlist.

[0140] For example, the determination unit 1020 is further configured to determine an initial physical boundary range of the target function module in the initial layout by a layout tool according to the target function module, and optimize the initial physical boundary range to determine the target physical boundary range.

[0141] For example, the initial layout comprising the initial physical boundary range is divided into a plurality of panes, and a first pane is a pane in the plurality of panes which has an overlapping part with the initial physical boundary range; the determination unit 1020 is further configured to determine a corresponding occupation state of each first pane according to a size of the overlapping part of each first pane and the initial physical boundary range, wherein the occupation state comprises occupied and unoccupied; determine a correction number and a correction direction of a second pane according to the initial physical boundary range and the first pane whose occupation state is occupied, wherein the second pane is a pane in the plurality of panes which is used to correct a boundary range formed by the first pane whose occupation state is occupied; and determine the target physical boundary range according to the second pane and the first pane whose occupation state is occupied.

[0142] For example, a total sum of standard cell areas that can be accommodated in the first pane is S win , a total sum of standard cell areas corresponding to the size of the overlapping part of the initial physical boundary range in the first pane is S std , and a preset standard cell occupation rate of the first pane is Q; the determination unit 1020 is further configured to determine the target physical boundary range in response to S std / S win ≥Q, mark the first pane as occupied, or respond to S std / S win <Q, marks the first pane as unoccupied.

[0143] For example, the occupancy status is marked by an occupancy value F, where F=1 indicates that the unit is occupied and F=0 indicates that it is not occupied; the determining unit 1020 is also configured to determine the total area S of the standard units that can be accommodated within the first pane. win The sum of the standard cell areas S corresponding to the overlapping portion within the first pane of the window and the initial physical boundary. std Given the occupancy value F, determine the residual area S for each of the n first panes. fix_n Where n is a positive integer; determine the total residual area S based on the residual area of ​​each first pane. fix_sum The total residual area S fix_sum = S fix_1 + S fix_2 + ... + S fix_n According to the sum of residual areas S fix_sum Determine the amount of correction required for the second pane.

[0144] For example, the determining unit 1020 is also configured to determine the average area S of the standard cells in each pane of the physical module. avg According to the sum of residual areas S fix_sum Compared with the average area S of the standard unit avg The modulus calculation results are used to determine the correction amount for the second pane.

[0145] For example, the determining unit 1020 is further configured to determine the direction with fewer occupied first panes in the first and second directions as the corrected direction for the second pane, based on the arrangement of the occupied first panes in the first and second directions.

[0146] For example, the determining unit 1020 is further configured to, in response to a correction quantity indication, reduce the number of second panes by a corresponding number based on the occupied first pane, and mark the occupancy status of the second pane as unoccupied; or, in response to a correction quantity indication, increase the number of second panes by a corresponding number based on the occupied first pane, and mark the occupancy status of the second pane as occupied; and mask the panes corresponding to the target functional module whose occupancy status is unoccupied, so as to determine the target physical boundary range.

[0147] In some embodiments of this disclosure, the size of the multiple panes is determined based on the number of panes divided in the initial layout and the area ratio of the target functional module in the physical module.

[0148] For example, the determining unit 1020 is further configured to determine, based on the physical module netlist, timing path information between the target function module and other function modules in the physical module, wherein the timing path information comprises a timing path from input to register and / or a timing path from register to output; and determine pin information of the target function module based on the target physical boundary range and the timing path information.

[0149] For example, the determining unit 1020 is further configured to obtain a target physical edge of the target physical boundary range; and determine the pin information of the target function module according to an intersection of the timing path from input to register and / or the timing path from register to output and the target physical edge.

[0150] For example, the verifying unit 1030 is further configured to generate a target function module netlist based on the physical logic synthesis based on the module physical constraint information; perform timing evaluation based on the target function module netlist and the module physical constraint information to obtain a timing evaluation result; and verify whether the circuit design corresponding to the target function module meets the expectation based on the timing evaluation result.

[0151] The technical effects of the circuit design verification apparatus of the above-mentioned embodiments of the present disclosure are the same as those of the above-mentioned circuit design verification method, and thus will not be repeated.

[0152] Figure 11 A block schematic diagram of a verification device provided by at least one embodiment of the present disclosure is shown.

[0153] At least one embodiment of the present disclosure further provides a verification device, as shown in Figure 11 The verification device 1100 comprises at least one memory 1110 and at least one processor 1120.

[0154] The above-mentioned memory 1110 is configured to store computer executable instructions.

[0155] The above-mentioned processor 1120 is configured to execute the computer executable instructions, and the computer executable instructions, when executed by the at least one processor, implement the circuit design verification method provided by any embodiment of the present disclosure.

[0156] The above-mentioned memory 1110 may, for example, comprise a semiconductor storage unit, such as a dynamic random access memory (DRAM), a random access memory (RAM), a static random access memory (SRAM), or any memory having a storage function.

[0157] The processor 1120 can be any processing circuitry having processing capability implemented by hardware or firmware, for example, a central processing unit (CPU) or a co-processor, a microcontroller unit (MCU) or a digital signal processor (DSP), for example, the co-processor can be an accelerator (for example, a graphics accelerator or a digital signal processing unit), a graphics processing unit (GPU), a programmable logic array, or any other processor having an instruction execution function, and the like. Embodiments of the present disclosure do not limit the implementation of the at least one memory 1110 and the at least one processor 1120.

[0158] The technical effects of the verification device of the above-mentioned embodiments of the present disclosure are the same as those of the above-mentioned circuit design verification method, and therefore will not be repeated.

[0159] At least one embodiment of the present disclosure also provides a non-transitory storage medium, which non-transitorily stores computer executable instructions. For example, when the computer executable instructions are executed by a processor, a circuit design verification method provided by at least one embodiment of the present disclosure is implemented.

[0160] Figure 12 FIG. 12 is a schematic diagram of a non-transitory storage medium provided by some embodiments of the present disclosure. As shown in FIG. 12, the non-transitory storage medium 1200 can non-transitorily store computer executable instructions 1210, which, when executed by a computer, implement a circuit design verification method provided by any embodiment of the present disclosure. Figure 12

[0161] For the present disclosure, the following points need to be explained:

[0162] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can be referred to the general design.

[0163] (2) In the case of no conflict, the features in the same and different embodiments of the present disclosure can be combined with each other.

[0164] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto, any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.​

Claims

1. A circuit design verification method, comprising: In response to the completion of the design of the target functional module among the multiple functional modules to be included in the physical module, the target functional module is obtained; Based on the target functional module, the initial layout of the physical module, and the physical module netlist, the module physical constraint information of the target functional module is determined. The target functional module differs from the existing functional modules in the initial layout in terms of circuit logic. The physical module netlist includes the communication relationships between the functional modules in the physical module. Based on the physical constraint information of the module, a timing evaluation is performed on the target functional module to verify the circuit design corresponding to the target functional module; The module physical constraint information includes the target physical boundary range of the target functional module and the pin information of the target functional module; The determination of the module physical constraint information of the target functional module based on the target functional module, the initial layout of the physical module, and the physical module netlist includes: Based on the target functional modules and the initial layout, the target physical boundary range is determined; The pin information is determined based on the target physical boundary range and the physical module netlist.

2. The circuit design verification method as described in claim 1, wherein, Determining the target physical boundary range based on the target functional module and the initial layout includes: Based on the target functional module, the initial physical boundary range of the target functional module is determined in the initial layout using layout tools; Optimize the initial physical boundary range to determine the target physical boundary range.

3. The circuit design verification method as described in claim 2, wherein, The initial layout, including the initial physical boundary range, is divided into multiple panes, and the first pane is the pane among the multiple panes that overlaps with the initial physical boundary range; The optimization of the initial physical boundary range and the determination of the target physical boundary range include: Based on the size of the overlapping portion between each of the first panes and the initial physical boundary range, the corresponding occupancy status of each first pane is determined, wherein the occupancy status includes occupied and unoccupied; Based on the first pane that is occupied and the initial physical boundary range, the correction quantity and correction direction of the second pane are determined, wherein the second pane is the pane among the plurality of panes used to correct the boundary range formed by the occupied first pane; The target physical boundary range is determined based on the second pane and the occupied first pane.

4. The circuit design verification method as described in claim 3, wherein, The total area of ​​the standard units that can be accommodated within the first pane is S. win The total area of ​​the standard cells corresponding to the overlapping portion of the first pane and the initial physical boundary is S. std The preset standard cell occupancy rate Q of the first pane; Determining the target physical boundary range based on the second pane and the occupied first pane includes: In response to S std / S win ≥Q, mark the first pane as occupied, or In response to S std / S win <Q, marks the first pane as unoccupied.

5. The circuit design verification method as described in claim 4, wherein, The occupancy status is marked by an occupancy value F, where F=1 indicates that the space is occupied and F=0 indicates that the space is not occupied. The step of determining the correction quantity and correction direction of the second pane based on the first pane's occupied status and the initial physical boundary range includes: Based on the total area S of the standard units that can be accommodated within the first pane of glass win The sum of the standard cell areas S corresponding to the overlapping portion of the first pane and the initial physical boundary range. std And the occupancy value F, determine the residual area S of each of the n first panes. fix_n where n is a positive integer; Determine the total residual area S based on the residual area of ​​each of the first panes. fix_sum The sum of the residual areas S fix_sum = S fix_1 + S fix_2 + ... + S fix_n ; Based on the sum of the residual areas S fix_sum Determine the amount of correction for the second pane.

6. The circuit design verification method as described in claim 5, wherein, The sum of the residual areas S fix_sum Determine the amount of correction for the second pane, including: Determine the average area S of the standard cells of each pane in the physical module. avg ; Based on the sum of the residual areas S fix_sum Compared with the average area S of the standard unit avg The modulus calculation result is used to determine the correction amount for the second pane.

7. The circuit design verification method as described in claim 6, wherein, The step of determining the correction quantity and correction direction of the second pane based on the first pane's occupied status and the initial physical boundary range includes: Based on the arrangement of the occupied first panes in the first and second directions, the direction with fewer occupied first panes in the first and second directions is determined as the corrected direction for the second panes.

8. The circuit design verification method as described in claim 3, wherein, Determining the target physical boundary range based on the second pane and the occupied first pane includes: In response to the correction quantity instruction, the number of second panes is reduced by a corresponding number based on the number of occupied first panes, and the occupancy status of the second panes is marked as unoccupied; or In response to the correction quantity indication, a corresponding number of second panes are added to the already occupied first pane, and the occupancy status of the second panes is marked as occupied; The panes corresponding to the target functional module that are in an unoccupied state are hidden in order to determine the physical boundary range of the target.

9. The circuit design verification method as described in claim 3, wherein, The size of the multiple panes is determined based on the number of panes divided in the initial layout and the area ratio of the target functional module in the physical module.

10. The circuit design verification method as described in claim 1, wherein, The step of determining the pin information based on the target physical boundary range and the physical module netlist includes: Based on the physical module netlist, the timing path information between the target functional module and other functional modules in the physical module is determined, wherein the timing path information includes the timing path from input to register and / or the timing path from register to output; Based on the target physical boundary range and the timing path information, the pin information of the target functional module is determined.

11. The circuit design verification method as described in claim 10, wherein, The step of determining the pin information of the target functional module based on the target physical boundary range and the timing path information includes: Obtain the target physical edge of the target physical boundary range; The pin information of the target functional module is determined based on the intersection of the timing path from the input to the register and / or the timing path from the register to the output with the target physical edge.

12. The circuit design verification method according to any one of claims 1-11, wherein, Based on the physical constraint information of the module, a timing evaluation is performed on the target functional module to verify the circuit design corresponding to the target functional module, including: Based on the physical constraint information of the module, a netlist of target functional modules is generated through physical logic synthesis. Based on the target functional module netlist and the module physical constraint information, a timing evaluation is performed to obtain the timing evaluation result; The timing evaluation results are used to verify whether the circuit design corresponding to the target functional module meets expectations.

13. A circuit design verification device, comprising: The acquisition unit is configured to acquire the target functional module in response to the completion of the design of the target functional module among the multiple functional modules to be included in the physical module; The determining unit is configured to determine the module physical constraint information of the target functional module based on the target functional module, the initial layout of the physical module, and the physical module netlist. The target functional module differs from the existing functional modules in the initial layout in terms of circuit logic. The physical module netlist includes the communication relationships between the functional modules in the physical module. The verification unit is configured to perform timing evaluation on the target functional module based on the module's physical constraint information in order to verify the circuit design corresponding to the target functional module. The module physical constraint information includes the target physical boundary range of the target functional module and the pin information of the target functional module; The verification unit is further configured as follows: Based on the target functional modules and the initial layout, the target physical boundary range is determined; The pin information is determined based on the target physical boundary range and the physical module netlist.

14. A verification device, comprising: At least one memory is configured to store computer-executable instructions; as well as At least one processor is configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the at least one processor, implement the circuit design verification method according to any one of claims 1-12.

15. A non-transitory storage medium for non-transitory storage of computer-executable instructions, wherein, When the computer-executable instructions are executed by at least one processor, the circuit design verification method as described in any one of claims 1-12 is implemented.

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