Processing method of back heat dissipation structure of power electronic device and power electronic device

Abstract

The invention discloses a processing method of a back heat dissipation structure of a power electronic device and the power electronic device, and relates to the technical field of semiconductor devices. According to the processing method provided by the invention, the steps of substrate surface heat conduction hole structure patterning, transfer substrate surface heat conduction hole structure patterning, substrate thinning, secondary substrate surface heat conduction hole structure patterning, heat conduction hole etching, high heat conduction material filling and the like are sequentially carried out, and a key alignment step is preposed and is permanently marked on a transfer substrate surface; the influence of the process in the traditional process on the alignment precision is avoided; precise alignment is carried out through a double-sided alignment technology, patterning precise etching is carried out on a substrate surface under an active region of a device, and a high-thermal-conductivity material is filled, so that the thermal resistance under the active region of the device is extremely reduced, and different from a traditional substrate whole-surface thinning method, the thermal conductivity limitation caused by the existing whole-surface substrate thinning limit can be broken through.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a processing method for a backside heat dissipation structure of a power electronic device and a power electronic device. Background Art

[0002] Power electronic devices have been widely used in power electronic systems such as fast charging, motors, data centers, and electric vehicles. The technological development trend is to achieve higher power conversion efficiency, smaller size, and higher power density. The power density of power electronic modules in server power supplies has been increased to 100 W / in 3 , resulting in a sharp increase in the device's thermal dissipation power. A large amount of heat generated is concentrated in the active area. Whether the heat can be effectively dissipated becomes the core bottleneck restricting the device's performance and reliability.

[0003] Currently, the industry generally uses the method of adding heat sinks to power modules for heat dissipation, but these heat dissipation devices are large in size, which restricts their application in space-sensitive applications such as electric vehicles and data centers. The traditional external heat sink solution increases the heat dissipation cost and significantly increases the package volume. In order to reduce the module volume, people have invented a method of thinning the substrate to shorten the heat conduction path and reduce the thermal resistance of the device. However, further thinning the substrate will face the following technical challenges: After the substrate is thinned to a critical thickness, under the action of stress, the thinned wafer will curl, which will cause the following problems: (1) affecting the alignment of the subsequent photolithography process and other processes; (2) the increased stress will cause a significant increase in the fragmentation rate during the device processing.

[0004] In order to achieve double-sided photolithography alignment, some people have invented a method of bonding the target wafer with a transparent transfer substrate and a transparent bonding adhesive. However, the difference in thermal expansion characteristics between the transparent transfer substrate and the semiconductor material causes interface stress concentration. The refraction of the multi-layer dielectric material during the photolithography process deteriorates the accuracy of double-sided pattern alignment, making it difficult to achieve double-sided pattern alignment of high-precision heat dissipation structures. The currently used methods are: (1) reducing the bonding stress by stacking multiple layers of bonding materials as a stress buffer layer, but the bonding material design is complex, the process requirements during the debonding process are high, and the cost is high; (2) using a multi-step process for gradual thinning to improve stress distribution, but it significantly prolongs the processing cycle. The above two methods can reduce the substrate thinning stress to a certain extent, but it is difficult to break through the stress limit of the material itself, and the effect of further reducing the substrate thickness is limited.

[0005] Therefore, there is an urgent need to improve the substrate thinning process of power electronic devices to avoid the impact of the thinning process on alignment accuracy, break through the thickness limit of the existing whole-surface substrate thinning technology, and at the same time break through the thermal conductivity limitation brought about by the existing whole-surface substrate thinning limit.

[0006] In view of this, the present invention is proposed. Summary of the Invention

[0007] The purpose of the present invention is to provide a method for processing the back heat dissipation structure of a power electronic device and a power electronic device, aiming to break through the limitation of substrate thinning limit on improving the thermal conductivity of the device and greatly enhance the heat dissipation capacity of the device.

[0008] The implementation method of the present invention is as follows: In a first aspect, the present invention provides a method for processing a backside heat dissipation structure of a power electronic device, comprising: Providing power electronic device wafers: The power electronic device includes a substrate layer and a device layer located on the substrate layer, so that the power electronic device has a device surface and a substrate surface opposite to the device surface; the device layer has multiple periodically arranged devices, and the area between the source and drain of each device is the active area of ​​the device. A cutting street is set between two adjacent devices, i.e., the isolation area between the devices; Patterning of the thermal via structure on the substrate surface: Photolithography exposure is performed on the device surface and the substrate surface using a double-sided alignment technique to form corresponding photolithographic pattern areas on the device surface and the substrate surface, and the photolithographic pattern areas on the substrate surface correspond to the devices on the device surface; the planar distribution pattern of the thermal vias is patterned on the substrate surface, and then the photoresist is removed; Patterning of the thermal via structure on the transfer substrate surface: forming a bonding adhesive layer on the device surface and bonding the transfer substrate to the device surface; performing double-sided alignment photolithography exposure on the transfer substrate surface and the substrate surface so that the formed photolithography pattern area on the transfer substrate surface corresponds to the photolithography pattern area on the substrate surface; photolithography the planar distribution pattern of the thermal vias on the transfer substrate surface, and then removing the photoresist; Substrate thinning: The substrate surface of the wafer is thinned to the target thickness by grinding; Secondary substrate surface thermal via patterning and thermal via etching: Double-sided alignment photolithography exposure is performed on the transfer substrate surface and the substrate surface, so that the planar distribution pattern of the thermal vias on the transfer substrate surface is transferred to the substrate surface again, and the photolithographic pattern area on the substrate surface is kept exactly corresponding to each device on the device surface; the thermal via photolithographic pattern on the substrate surface corresponding to the device surface is etched to form blind holes, and the photoresist is removed after the etching reaches the target depth; Separate the transfer substrate: Debond the bonding adhesive layer to separate the wafer sample from the transfer substrate.

[0009] In an optional embodiment, after the secondary substrate surface thermal via structure patterning and thermal via etching and before the transfer substrate is separated, a high thermal conductivity material is formed in the thermal via of the substrate to fill the thermal via.

[0010] In an optional embodiment, the high thermal conductivity material filling is formed by any one of the following three methods: The first method is to form an entire substrate electroplating, and retain the electroplated high thermal conductivity material on the entire surface; The second method: using photoresist protection, only electroplating filling in the blind hole; The third method is to electroplate the entire substrate and then polish to remove the electroplating material outside the blind holes.

[0011] In an optional embodiment, the high thermal conductivity material is made of at least one of copper, nickel, aluminum, gold, silver and diamond-like carbon.

[0012] In an optional embodiment, the material of the transfer substrate is consistent with the material of the wafer bonding surface or other materials with similar mechanical / thermal properties.

[0013] In an optional embodiment, the bonding adhesive layer is formed by spin coating or pasting bonding adhesive, and the material of the bonding adhesive is selected from at least one of thermoplastic, thermosetting, photosensitive / laser release adhesive and adhesive film.

[0014] In an optional embodiment, the method of separating the transfer substrate is selected from any one of the following: placing the sample in an organic solvent, mechanical separation, heating treatment, and laser debonding.

[0015] In an optional embodiment, dry etching is used in the processes of patterning the thermal hole structure on the substrate surface, patterning the thermal hole structure on the transfer substrate surface, and patterning the thermal hole structure on the secondary substrate surface. The thermal hole etching is performed by dry etching, wet etching, or laser drilling.

[0016] In a second aspect, the present invention provides a power electronic device prepared by the processing method of any one of the aforementioned embodiments.

[0017] The present invention has the following beneficial effects: the processing method provided by the present invention sequentially performs steps such as patterning the thermal conductive hole structure on the substrate surface, patterning the thermal conductive hole structure on the transfer substrate surface, substrate thinning, patterning the thermal conductive hole structure on the secondary substrate surface, etching the thermal conductive hole, and filling with high thermal conductivity materials. The key alignment step is pre-placed and permanently marked on the transfer substrate surface, thereby avoiding the influence of the process in the traditional process on the alignment accuracy; through the double-sided alignment technology, precise alignment is performed, and the substrate surface directly below the device active area is patterned and precisely etched and filled with high thermal conductivity materials, thereby achieving the ultimate reduction in thermal resistance under the device active area. Different from the traditional method of thinning the entire substrate surface, it can break through the thermal conductivity limitation brought by the existing entire substrate thinning limit.

[0018] In a preferred embodiment of the present invention, patterned precision etching is performed on the substrate surface directly below the device active area and filled with high thermal conductivity material, thereby achieving an extreme reduction in thermal resistance under the device active area. This is different from the traditional method of thinning the entire substrate surface and can break through the thermal conductivity limitation brought about by the existing limit of thinning the entire substrate surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 Prepare a complete device diagram for step (1); Figure 2 Schematic diagram of the thermal hole pattern photolithography on the substrate surface in step (2); Figure 3 Schematic diagram of adding bonding glue to the device surface in step (3); Figure 4 This is a schematic diagram of step (4) after the device surface is bonded to the transferred substrate; Figure 5 Schematic diagram of transferring the thermal hole pattern to the transfer substrate surface after double-sided alignment photolithography in step (5); Figure 6 Schematic diagram of the substrate after thinning in step (6); Figure 7 Schematic diagram of etching the thermal via structure on the substrate after double-sided alignment photolithography in step (7); Figure 8 Schematic diagram after electroplating high thermal conductivity material in step (8); Figure 9 Schematic diagram after removing the transfer substrate in step (9).

[0021] Icons: 01-isolation area; 02-device active area; 03-device layer; 04-substrate layer; 05-bonding adhesive layer; 06-transfer substrate; 07-high thermal conductivity material. DETAILED DESCRIPTION

[0022] To make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are described clearly and completely below. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer are used. Where the manufacturer of the reagents or instruments is not specified, all are conventional products that can be purchased commercially.

[0023] The embodiment of the present invention provides a method for processing the back heat dissipation structure of a power electronic device, please refer to Figures 1-9 , step (1) provides a power electronic device, step (2) performs patterning of thermal conductive holes on the substrate surface, step (5) performs patterning of thermal conductive hole structure on the transfer substrate surface, step (6) performs preliminary thinning of the substrate, step (7) performs etching of the thermal conductive hole structure, step (8) electroplates a high thermal conductivity material, and step (9) separates the transfer substrate. The steps are as follows: (1) Provide power electronic devices like Figure 1 As shown, a power electronic device is fabricated using conventional methods. The power electronic device includes a substrate layer 04 and a device layer 03 located on the substrate layer 04, so that the power electronic device has a device surface and a substrate surface opposite the device surface. Device layer 03 includes multiple periodically arranged devices. The region between the source and drain of each device is the device active region 02. A scribe line is provided between adjacent devices, i.e., an ion-implanted isolation region or an etched isolation region 01 is provided between adjacent devices. The devices are isolated from each other and do not interfere with each other.

[0024] It's important to note that the active region (AR) in power electronic devices is the core functional area and the primary source of heat generation. The active region is the core area of ​​the device that enables and blocks current flow. It includes structures such as contact electrodes and conductive channels, responsible for carrier injection, transport, and control (e.g., the source, drain, and gate electrodes of a GaN HEMT, and the 2DEG conductive channel). The isolation region primarily provides electrical isolation, preventing leakage or crosstalk between the two device active regions. The device active region 02 and isolation region 01 are fabricated using conventional fabrication techniques, and the specific steps are not detailed here.

[0025] (2) Double-sided alignment lithography forms a planar distribution pattern of thermal holes on the substrate surface like Figure 2 As shown, double-sided alignment technology is used for photolithographic exposure on both the device and substrate surfaces to form a planar distribution pattern of corresponding thermal vias on the device and substrate surfaces. The etching depth is 400-600 nanometers, and the planar distribution pattern of thermal vias on the substrate surface corresponds to the components on the device surface. High-precision alignment marks are pre-placed on both sides of the wafer to be processed to facilitate subsequent high-precision alignment and are transferred to the transfer substrate surface to form a transitional positioning reference.

[0026] Specifically, double-sided alignment technology is used to ensure that the lithographic patterns on the front and back sides of the wafer are strictly aligned. The double-sided alignment lithography step can be performed using a double-sided alignment mask aligner or a double-sided lithography machine.

[0027] (3) Add bonding glue on the device surface like Figure 3 As shown, a bonding adhesive layer 05 is formed on the device surface. The material of the bonding adhesive is selected from at least one of thermoplastics, thermosetting adhesives, photosensitive / laser release adhesives (if the transfer substrate is transparent) and adhesive films. The material of the bonding adhesive can be any one or more of the above.

[0028] In some embodiments, the bonding adhesive layer 05 is formed by spin coating or pasting bonding adhesive. A suitable method is selected to prepare the bonding adhesive layer 05 according to different materials.

[0029] (4) Bonding the device surface to the transfer substrate like Figure 4 As shown, the transfer substrate 06 is bonded to the device surface, and the transfer substrate 06 is adhered by the adhesive force of the bonding adhesive layer 05. The length and width of the transfer substrate 06 correspond to the device surface, and the device surface is completely covered.

[0030] In some embodiments, the transfer substrate 06 is made of the same material as the wafer substrate or another material with similar mechanical / thermal properties. This means that there is minimal or no interfacial stress between the transfer substrate 06 and the device. This embodiment of the present invention breaks through the conventional wisdom of using transparent transfer substrates by utilizing homogeneous materials for bonding, fundamentally eliminating interfacial stress in heterogeneous bonding.

[0031] In another embodiment, the material of the transfer substrate 06 has low interface stress with the device. For example, when the device is a silicon wafer, the transfer substrate may be made of silicon nitride (Si3N4), hexagonal boron nitride (h-BN), or transparent quartz glass (SiO2).

[0032] (5) Double-sided alignment lithography forms a planar distribution pattern of thermal holes on the transfer substrate surface like Figure 5 As shown, double-sided alignment photolithography exposure is performed on both the transfer substrate and substrate surfaces, so that the resulting photolithographic pattern area on the transfer substrate corresponds to the photolithographic pattern area on the substrate surface. This embodiment of the present invention pre-positions the critical alignment step and permanently marks it on the transfer substrate surface, thus avoiding the impact of traditional processes on the accuracy of the double-sided alignment process.

[0033] (6) Substrate thinning like Figure 6 As shown, the wafer substrate surface is ground down to the target thickness. The thermal via patterning pattern formed by photolithography in the previous step, "Patterning the Thermal Via Structure on the Substrate Surface," is removed. Substrate thinning is performed on the substrate surface. This step can reduce the substrate to within the required thickness, typically 100 to 200 microns.

[0034] Specifically, the means of thinning the substrate is not limited, and mechanical grinding is generally used, which is not limited here.

[0035] (7) Double-sided alignment lithography forms a planar distribution pattern of thermal holes on the substrate surface and accurately etches the thermal holes like Figure 7As shown, double-sided alignment photolithography exposure is performed on the transfer substrate and substrate surfaces, transferring the thermal via planar distribution pattern on the transfer substrate surface to the substrate surface. The substrate surface photolithographic pattern area precisely aligns with the components on the device surface. The thermal vias are primarily distributed directly below the active area and below the inactive area. Depending on heat dissipation requirements, sparser thermal vias can be arranged to further enhance heat dissipation. The thermal via photolithographic pattern on the device substrate surface is etched to form blind vias. After etching to the target depth, the photoresist is removed. (8) Electroplating of high thermal conductivity materials The thermal holes of the substrate are filled with high thermal conductivity material 07. The embodiment of the present invention has achieved a breakthrough in integrating the heat dissipation structure preparation process into the wafer-level manufacturing process. By eliminating the increase in volume and cost caused by external heat sinks, the device miniaturization and heat dissipation performance are simultaneously improved, solving the technical contradiction between traditional discrete heat dissipation solutions and ultra-thin processes.

[0036] In some embodiments, electroplating is used to form a high thermal conductivity material filling. The electroplating method is easy to operate and suitable for forming a high thermal conductivity material filling in the thermal conductive hole. The material of the high thermal conductivity material 07 is at least one of copper, nickel, aluminum, gold, silver and diamond-like carbon. After electroplating, the surface is flattened as required. Specifically, any of the following three methods are used to form the high thermal conductivity material filling: The first method is to form an entire substrate electroplating, and retain the electroplated high thermal conductivity material on the entire surface; The second method: using photoresist protection, only electroplating filling in the blind hole; The third method is to electroplate the entire substrate and then polish to remove the electroplating material outside the blind holes.

[0037] (9) Removal of carrier The bonding adhesive layer 05 is debonded to separate the wafer sample from the transfer substrate 06. After the bonding adhesive layer 05 fails, the sample and the transfer substrate 06 lose their adhesive force, making it easier to separate.

[0038] In some embodiments, the method of separating the transfer substrate is selected from any one of the following: placing the sample in an organic solvent, mechanical separation, heating treatment, and laser debonding. The specific separation method can be any one of the above.

[0039] Exemplarily, the step of separating the transfer substrate 06 includes placing the sample in an organic solvent or heating it to 180°C-250°C to separate the sample from the transfer substrate 06. Organic solvents can dissolve the bonding adhesive, while heating can weaken the adhesive. Both treatments can separate the transfer substrate 06. Specifically, the type of organic solvent is not limited, and examples include NMP (1-methyl-2-pyrrolidone), DMSO (dimethyl sulfoxide), benzyl alcohol, acetone, and specialized adhesive removers.

[0040] An embodiment of the present invention provides a power electronic device, which is prepared by the processing method provided by the embodiment of the present invention. The thickness of the substrate under the active area of ​​the device can be significantly reduced compared with traditional processes, for example, it can reach less than 20 microns, which means that the thermal conductivity is greatly improved; and double-sided pattern alignment of high-precision heat dissipation structure can be easily achieved.

[0041] The features and performance of the present invention are further described in detail below with reference to the embodiments.

[0042] Example 1 This embodiment provides a method for processing a backside heat dissipation structure of a GaN HEMT power electronic device, comprising the following steps: (1) If Figure 1 As shown, the device is prepared using a general process, and the preparation process is as follows: First, an AlGaN / GaN heterojunction epitaxial structure is grown on a Si substrate by MOCVD to form a high-mobility two-dimensional electron gas (2DEG) channel. Ion implantation or etching is then performed to achieve device isolation. Next, low-impedance source and drain ohmic contacts are prepared by pretreatment, metal evaporation, and rapid annealing, and then electron beam evaporation is used to prepare the gate Schottky contact. Finally, a SiNx passivation layer is deposited. The device is in the shape of a rectangular parallelepiped, with a substrate layer 04 having a thickness of 650 microns and made of Si; the device layer is 6 microns thick, and the device active area 02 is spaced apart. Figure 1 The gate length of each device active area 02 is 2 microns, the gate-source spacing is 2 microns, the gate-drain spacing is 10 microns, the gate width is 2 mm, and the width of the isolation region is 30 microns.

[0043] (2) If Figure 2 As shown, photolithography exposure is performed on both the device and substrate surfaces using double-sided alignment technology to form a planar distribution pattern of thermal vias on the substrate surface, with the photolithographic pattern corresponding to the device. Dry etching of the thermal vias to a depth of 400 nanometers is performed on the substrate surface. The dry etching process is as follows: 400 nanometers of inductively coupled plasma (ICP) etching is performed with an ICP RF source power of 500W, a bias RF voltage of 100W, a table temperature of -10°C, and a chamber pressure of 5 mTorr. The photoresist is then removed. (3) If Figure 3 As shown, the device surface is spin-coated with bonding glue (cyclic olefin copolymer (COC)) with a thickness of 20 μm.

[0044] (4) If Figure 4 As shown, a transfer substrate made of Si and 500 microns thick is bonded to the device surface.

[0045] (5) If Figure 5As shown, double-sided alignment photolithography exposure is performed on the transfer substrate surface and the substrate surface, so that the photolithography pattern area formed on the transfer substrate surface corresponds to the pattern area on the substrate surface.

[0046] (6) If Figure 6 As shown, mechanical grinding is used to thin the substrate to 100 microns. (7) If Figure 7 As shown, the transfer substrate surface and the substrate surface are subjected to double-sided alignment photolithography exposure, so that the formed substrate surface photolithography pattern area corresponds to the transfer substrate surface photolithography pattern area, and the device substrate surface is etched and thinned by dry etching to form a thermal hole with a hole depth of 80 microns, that is, only 20 microns of substrate is left, so that the substrate thickness corresponding to the device thermal hole position reaches the target thickness. (8) If Figure 8 As shown, the thermal vias are electroplated with copper, a highly thermally conductive material. The specific process is as follows: First, magnetron sputtering is used to deposit a 300nm SiO2 insulating layer, a 20nm tantalum diffusion barrier layer, and a 100nm copper seed layer on the inner walls of the vias. A strike copper layer is then applied at a current density of 5-10 A / dm² to deposit a thin film (1-2 microns) to ensure adhesion. The main copper plating is performed at a current density of 2-4A / dm², controlling the temperature and pH, to the target thickness. Post-board cleaning involves rinsing with pure water to remove residual surface chemicals. A light acid rinse may be added before rinsing. Drying is performed in an oven at 60-80°C for 10-15 minutes to prevent oxidation. After electroplating, the surface is smoothed using chemical mechanical polishing.

[0047] (9) Figure 9 As shown, the processed sample was heated to 200°C to separate the sample from the temporary transfer substrate.

[0048] The results show that by using the processing method of Example 1, the thickness of the substrate below the device heat source-active region can be reduced to 20 microns and filled with high thermal conductivity material, and the thermal resistance of the device can be reduced by more than one third.

[0049] In summary, the present invention provides a processing method for the back heat dissipation structure of a power electronic device and a power electronic device, which solves the technical problem of double-sided alignment substrate thinning through the collaborative innovation of material system and process route, adopts a homogeneous transfer substrate material that is compatible with the thermal expansion characteristics of the device, pre-sets a high-precision alignment mark system on both sides of the wafer to be processed, and transfers the side mark of the wafer substrate to the surface of the transfer substrate through bonding the transfer substrate and the double-sided alignment photolithography process to form a transitional positioning reference. The processing method provided by the present invention can not only implement a precision etching and thinning process to obtain an ultra-thin substrate thickness, but also perform cross-layer alignment based on the transfer substrate reference mark and the wafer device surface, and can break through the thermal conductivity limitation brought about by the existing whole-surface substrate thinning limit. Specifically, the present invention has the following advantages: (1) The introduction of a homogeneous material transfer substrate effectively suppresses the lattice distortion caused by thermal stress mismatch, significantly reducing the risk of edge curling and cracking during substrate thinning; (2) Based on mark transfer, it breaks through the physical limitations of traditional double-sided alignment and achieves high-precision spatial matching between the pattern on the back of the ultra-thin substrate and the active area on the device surface; (3) Through precise alignment, etching and thinning are performed in specific areas, significantly reducing the risk of cracking during etching and thinning of the substrate area; (4) Ultimately, the thermal conductivity efficiency and stability of the heat dissipation structure are improved to ensure the reliability and life of power devices under high power density conditions.

[0050] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A method for processing a backside heat dissipation structure of a power electronic device, characterized in that: include: Providing a power electronic device wafer: the power electronic device includes a substrate layer and a device layer located on the substrate layer, so that the power electronic device has a device surface and a substrate surface opposite to the device surface; the device layer has a plurality of periodically arranged devices, the area between the source and drain of each device being the active area of ​​the device, and a dicing street is provided between two adjacent devices, i.e., an isolation area between the devices; Patterning of the thermal via structure on the substrate surface: performing photolithographic exposure on the device surface and the substrate surface using a double-sided alignment technique to form photolithographic pattern areas corresponding in position to each other on the device surface and the substrate surface, and the photolithographic pattern areas on the substrate surface correspond to each device on the device surface; photolithographically forming a planar distribution pattern of the thermal vias on the substrate surface, and then removing the photoresist; Patterning the thermal conductive hole structure on the transfer substrate surface: forming a bonding adhesive layer on the device surface and bonding the transfer substrate to the device surface; Performing double-sided aligned photolithography exposure on the transfer substrate surface and the substrate surface so that the formed photolithography pattern area on the transfer substrate surface corresponds to the photolithography pattern area on the substrate surface; photolithography a planar distribution pattern of the thermal conductive holes on the transfer substrate surface, and then removing the photoresist; Substrate thinning: The substrate surface of the wafer is thinned to the target thickness by grinding; Secondary substrate surface thermal via patterning and thermal via etching: performing double-sided alignment photolithography exposure on the transfer substrate surface and the substrate surface, so that the planar distribution pattern of the thermal vias on the transfer substrate surface is transferred to the substrate surface again, and the substrate surface photolithography pattern area is kept exactly corresponding to the devices on the device surface; the thermal via photolithography pattern on the substrate surface corresponding to the active area of ​​the device surface is etched to form blind holes, and the photoresist is removed after the etching reaches the target depth; Separating the transfer substrate: performing a debonding process on the bonding adhesive layer to separate the wafer sample from the transfer substrate.

2. The processing method according to claim 1, characterized in that: After the thermal conductive hole structure of the secondary substrate surface is patterned and the thermal conductive hole is etched and before the transfer substrate is separated, a high thermal conductive material is formed in the thermal conductive hole of the substrate to fill it.

3. The processing method according to claim 2, characterized in that: Use any of the following three methods to form high thermal conductivity material filling: The first method is to form an entire substrate electroplating, and retain the electroplated high thermal conductivity material on the entire surface; The second method: using photoresist protection, only electroplating filling in the blind hole; The third method is to electroplate the entire substrate and then polish to remove the electroplating material outside the blind holes.

4. The processing method according to claim 3, characterized in that: The material of the high thermal conductivity material is at least one of copper, nickel, aluminum, gold, silver and diamond-like carbon.

5. The processing method according to claim 1, characterized in that: The material of the transfer substrate is consistent with the material of the wafer bonding surface or other materials with similar mechanical / thermal properties.

6. The processing method according to any one of claims 1 to 5, characterized in that: The bonding adhesive layer is formed by spin coating or pasting bonding adhesive, and the material of the bonding adhesive is selected from at least one of thermoplastic, thermosetting, photosensitive / laser release adhesive and adhesive film.

7. The processing method according to claim 6, characterized in that: The method of separating the transferred substrate is selected from any one of the following: placing the sample in an organic solvent, mechanical separation, heating treatment, and laser debonding.

8. The processing method according to claim 1, characterized in that: In the processes of patterning the thermal conductive hole structure on the substrate surface, patterning the thermal conductive hole structure on the transfer substrate surface and patterning the thermal conductive hole structure on the secondary substrate surface, dry etching is used for etching, and the thermal conductive hole etching adopts dry etching, wet etching or laser drilling method.

9. A power electronic device, characterized in that: It is prepared by the processing method according to any one of claims 1 to 8.

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