Semiconductor device

Abstract

A semiconductor device includes: lower conductive lines on a substrate and spaced apart from each other in a first direction parallel to an upper surface of the substrate; and a via structure on the lower conductive lines and electrically connected to at least two corresponding lower conductive lines among the lower conductive lines. The via structure includes a via contact extending in a first direction and electrically connected to the at least two corresponding lower conductive lines, and a blocking pattern on a side surface of the via contact and on a bottom surface of the via contact between the at least two corresponding lower conductive lines. A via contact extends through the blocking pattern and contacts the lower conductive line.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices, and more particularly, to a semiconductor device including a via structure connecting a plurality of conductive lines to each other. Background Art

[0002] Semiconductor devices include integrated circuits composed of metal oxide semiconductor field effect transistors (MOSFETs). As the size and design rules of semiconductor devices gradually decrease, the metal oxide semiconductor field effect transistors can be scaled down. When the metal oxide semiconductor field effect transistors (MOSFETs) are scaled down, the operating characteristics of the semiconductor device may be degraded. Therefore, various methods are being studied to overcome the limitations caused by the high integration of semiconductor devices and form semiconductor devices with desired performance. Summary of the Invention

[0003] The present disclosure provides a semiconductor device having improved electrical characteristics.

[0004] An embodiment of the present inventive concept provides a semiconductor device, comprising: lower conductive lines spaced apart from each other on a substrate and in a first direction parallel to an upper surface of the substrate; and a via structure on the lower conductive lines and electrically connected to at least two corresponding lower conductive lines among the lower conductive lines, wherein the via structure comprises via contacts extending in the first direction and electrically connected to the at least two corresponding lower conductive lines, and blocking patterns on side surfaces of the via contacts and on a bottom surface of the via contacts between the at least two corresponding lower conductive lines, wherein the via contacts extend through the blocking patterns and contact the lower conductive lines.

[0005] In one embodiment of the present inventive concept, a semiconductor device includes: a lower insulating film on a substrate; lower conductive lines in the lower insulating film and spaced apart from each other in a first direction parallel to an upper surface of the substrate; an etch stop film on the lower insulating film; an upper insulating film on the etch stop film; a via contact extending through at least a portion of the upper insulating film and the etch stop film and electrically connected to at least two corresponding lower conductive lines among the lower conductive lines; and a blocking pattern interposed between a side surface of the via contact and the upper insulating film and extending between the side surface of the via contact and the etch stop film, wherein the via contact extends in the first direction and is electrically connected to the at least two corresponding lower conductive lines, wherein the blocking pattern is interposed between the lower insulating film between the at least two corresponding lower conductive lines and a bottom surface of the via contact, and wherein the via contact extends through the blocking pattern and contacts the at least two corresponding lower conductive lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated into and constitute a part of this specification. The accompanying drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. In the drawings:

[0007] Figure 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept;

[0008] Figures 2 to 4 is a cross-sectional view of a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept;

[0009] Figure 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept;

[0010] Figure 6 and Figure 7 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept;

[0011] Figure 8 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept;

[0012] Figure 9 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept;

[0013] Figure 10 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept;

[0014] Figure 11 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept;

[0015] Figures 12 to 18 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept;

[0016] Figures 19 to 22 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept;

[0017] Figure 23 and Figure 24 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept;

[0018] Figure 25 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept;

[0019] Figures 26 to 31 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept;

[0020] Figure 32 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to some embodiments of the present inventive concept;

[0021] Figure 33 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept;

[0022] Figure 34 is a plan view of a semiconductor device according to some embodiments of the present inventive concept;

[0023] Figures 35 to 37 Along the Figure 34 sectional views taken along lines AA', BB' and CC';

[0024] Figure 38 and Figure 39 is a plan view of a semiconductor device according to some embodiments of the present inventive concept; and

[0025] Figure 40 It is along Figure 38 and Figure 39 A cross-sectional view taken along line D-D'. DETAILED DESCRIPTION

[0026] Hereinafter, the present invention will be described in detail by describing the example embodiments of the present invention with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used for the same constituent elements, and repeated description thereof is omitted. As used herein, the term "and / or" includes any and all combinations of one or more related listed items. It will be understood that although the terms "first", "second", "upper", "lower" etc. can be used to describe various elements or components here, these elements or components should not be limited by these terms. These terms are only used to distinguish an element or component from another element or component. Therefore, the first element or component discussed below can be referred to as the second element or component. Note that the aspects described in relation to an embodiment can be incorporated into different embodiments, although not specifically described with respect to it. That is, the features of all embodiments and / or any embodiment can be combined in any way and / or combination.

[0027] Figure 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept.

[0028] Reference Figure 1, a lower insulating film 142 may be provided on the substrate 100. The substrate 100 may include a semiconductor substrate. As an example, the substrate 100 may include a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. The lower insulating film 142 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric constant film.

[0029] The lower conductive lines CL1 may be disposed in the lower insulating film 142 and may be spaced apart from each other in a first direction D1 parallel to the upper surface 100U of the substrate 100. Each lower conductive line CL1 may include a lower metal line MP1, a lower barrier pattern 145 between the lower metal line MP1 and the lower insulating film 142, and a lower pad pattern 147 between the lower metal line MP1 and the lower barrier pattern 145. The lower barrier pattern 145 may extend along the side and bottom surfaces of the lower metal line MP1. The lower pad pattern 147 may be interposed between the side surfaces of the lower metal line MP1 and the lower barrier pattern 145, and may extend between the bottom surface of the lower metal line MP1 and the lower barrier pattern 145. The lower metal line MP1 may be spaced apart from the lower insulating film 142 with the lower barrier pattern 145 and the lower pad pattern 147 therebetween. The lower metal line MP1 may include a metal (e.g., copper). The lower barrier pattern 145 may include Ta, Ti, tantalum nitride (TaN), titanium nitride (TiN), manganese oxide (MnO) and / or manganese nitride (MnN), and the lower liner pattern 147 may include Ru, Co, Mo, Ta, Ti, Ga or alloys thereof.

[0030] The etch stopper film 150 may be disposed on the lower insulating film 142 and may extend onto an upper surface of the lower conductive line CL1 .

[0031] According to some embodiments, the etch stop film 150 may have a double-layer structure (or a two-layer structure) including a first sub-film 151 and a second sub-film 153 sequentially stacked on the lower insulating film 142 along a second direction D2 perpendicular to the upper surface 100U of the substrate 100. The first sub-film 151 may be interposed between the lower insulating film 142 and the second sub-film 153 and may extend between the upper surface of the lower conductive line CL1 and the second sub-film 153. The first sub-film 151 and the second sub-film 153 may include different materials. The first sub-film 151 may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN. The second sub-film 153 may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN, but may include a material different from that of the first sub-film 151. As an example, the first sub-film 151 may include aluminum oxide (AlO) or aluminum nitride (AlN), and the second sub-film 153 may include SiOC.

[0032] According to some embodiments, the second sub-film 153 may be omitted, and in this case, the etch stop film 150 may have a single-layer structure consisting of the first sub-film 151. The etch stop film 150 may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN, and may include aluminum oxide (AlO) in some embodiments.

[0033] An upper insulating film 160 may be disposed on the etch stop film 150. The upper insulating film 160 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric constant film.

[0034] A via structure VS and upper conductive lines CL2 may be provided in the upper insulating film 160. The via structure VS may penetrate or extend through a lower portion of the upper insulating film 160 and the etch stop film 150, and may extend in a first direction D1 to electrically connect to at least two corresponding lower conductive lines CL1 among the lower conductive lines CL1. The upper conductive lines CL2 may penetrate or extend through an upper portion of the upper insulating film 160 and may be electrically connected to the via structure VS. The upper conductive lines CL2 may be electrically connected to the at least two corresponding lower conductive lines CL1 through the via structure VS.

[0035] The via structure VS may include a via contact VC that penetrates or extends through a lower portion of the upper insulating film 160 and the etch stop film 150, a barrier pattern 165 disposed on a side surface VC_S and a bottom surface VC_B of the via contact VC, and a pad pattern 167 interposed between the side surface VC_S of the via contact VC and the barrier pattern 165, and between the bottom surface VC_B of the via contact VC and the barrier pattern 165. The barrier pattern 165 and the pad pattern 167 may be interposed between the side surface VC_S of the via contact VC and the upper insulating film 160 and may extend between the side surface VC_S of the via contact VC and the etch stop film 150. The barrier pattern 165 and the pad pattern 167 may be interposed between the lower insulating film 142 and the bottom surface VC_B of the via contact VC between the corresponding lower conductive lines CL1. The via contact VC may penetrate or extend through the barrier pattern 165 and the pad pattern 167 to contact the corresponding lower conductive line CL1 and may contact the lower metal line MP1 of each lower conductive line CL1. The barrier pattern 165 on the bottom surface VC_B of the via contact VC may contact the lower insulating film 142 between the corresponding lower conductive lines CL1 and may contact the uppermost surface of the lower barrier pattern 145 of each corresponding lower conductive line CL1 and the uppermost surface of the lower pad pattern 147. The barrier pattern 165 may be spaced apart from the bottom surface VC_B of the via contact VC with the pad pattern 167 therebetween.

[0036] The via contact VC may include a metal (e.g., copper), and may be, for example, a metal pattern composed of a single metal. That is, in some embodiments, the via contact VC may include a monolithic structure composed of a single metal. The barrier pattern 165 may include Ta, Ti, tantalum nitride (TaN), titanium nitride (TiN), manganese oxide (MnO), and / or manganese nitride (MnN), and the liner pattern 167 may include at least one of Ru, Co, Mo, Ta, Ti, Ga, and alloys thereof.

[0037] The upper conductive line CL2 may include an upper metal line MP2 on the via contact VC. According to some embodiments, the upper metal line MP2 may penetrate or extend through an upper portion of the upper insulating film 160 to contact the via contact VC. The upper metal line MP2 may extend onto the upper insulating film 160 along the first direction D1, across the side surface VC_S of the via contact VC. A barrier pattern 165 and a pad pattern 167 may extend between the upper metal line MP2 and the upper insulating film 160 and may extend along the bottom surface MP2_B and side surface MP2_S of the upper metal line MP2. Therefore, the upper conductive line CL2 may further include a barrier pattern 165 extending along the bottom surface MP2_B and side surface MP2_S of the upper metal line MP2, and a pad pattern 167 extending between the bottom surface MP2_B of the upper metal line MP2 and the barrier pattern 165 and between the side surface MP2_S of the upper metal line MP2 and the barrier pattern 165.

[0038] The upper metal line MP2 may include a metal (e.g., copper). According to some embodiments, the via contact VC and the upper metal line MP2 may include the same material (e.g., copper). In this case, the via contact VC and the upper metal line MP2 may contact each other without a boundary surface and may form a monolithic structure. According to other embodiments, the via contact VC and the upper metal line MP2 may include different materials (e.g., different metals), which may result in a defined boundary between the via contact VC and the upper metal line MP2.

[0039] According to embodiments of the present inventive concept, the etch stop film 150 can have a double-layer structure or a single-layer structure, thereby reducing the parasitic capacitance of a semiconductor device including lower conductive lines CL1, via structures VS, and upper conductive lines CL2. Furthermore, via contacts VC can directly contact the lower metal line MP1 of each corresponding lower conductive line CL1, and the upper metal line MP2 of each upper conductive line CL2 can directly contact via contacts VC. Consequently, the resistance of via structures VS electrically connecting upper conductive lines CL2 and corresponding lower conductive lines CL1 can be reduced. Consequently, the electrical characteristics of the semiconductor device can be improved.

[0040] Figures 2 to 4 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figure 1 Repeated description of semiconductor devices.

[0041] Reference Figure 2 , a lower insulating film 142 may be formed on the substrate 100, and lower trenches TR1 may be formed in the lower insulating film 142. The lower trenches TR1 may be spaced apart from each other in the first direction D1.

[0042] Lower conductive lines CL1 may be formed in the lower trenches TR1, respectively. For example, forming the lower conductive lines CL1 may include: forming a lower barrier film on the lower insulating film 142 to at least partially fill each lower trench TR1; forming a lower liner film on the lower barrier film to partially fill each lower trench TR1; forming a lower conductive film on the lower liner film to at least partially fill the remaining portion of each lower trench TR1; and planarizing the lower conductive film, the lower liner film, and the lower barrier film until the upper surface of the lower insulating film 142 is at least partially exposed. Each lower conductive line CL1 may include a lower metal line MP1, a lower barrier pattern 145, and a lower liner pattern 147 partially formed in each lower trench TR1 by a planarization process.

[0043] Reference Figure 3 , the etching stopper film 150 and the upper insulating film 160 may be sequentially stacked on the lower insulating film 142. According to some embodiments, the etching stopper film 150 may have a double-layer structure including a first sub-film 151 and a second sub-film 153. According to other embodiments, the second sub-film 153 may be omitted, and in this case, the etching stopper film 150 may have a single-layer structure consisting of the first sub-film 151.

[0044] The second trench TR2 may be formed to penetrate or extend through the upper portion of the upper insulating film 160, and the via hole VH may be formed to penetrate or extend from the bottom surface TR2_B of the second trench TR2 through the lower portion of the upper insulating film 160. The via hole VH may penetrate or extend through the etch stop film 150 and may extend in the first direction D1 to expose at least two corresponding lower conductive lines CL1 among the lower conductive lines CL1. The via hole VH may at least partially expose the lower metal line MP1 of each corresponding lower conductive line CL1.

[0045] Reference Figure 4 , the deposition inhibitor 200 may be formed on the lower metal line MP1 exposed by the via hole VH. The deposition inhibitor 200 may include silicon (Si) and / or carbon (C).

[0046] The barrier pattern 165 may be formed to conformally at least partially cover the inner surface of the second trench TR2 and the inner surface of the via hole VH, and may be formed on the lower insulating film 142 between the corresponding lower conductive lines CL1. The barrier pattern 165 may not be formed on the lower metal line MP1 on which the deposition inhibitor 200 is formed. The barrier pattern 165 may be formed using a deposition process such as atomic layer deposition, chemical vapor deposition, and physical vapor deposition. Due to the deposition inhibitor 200, the barrier pattern 165 may be selectively deposited on the side surface TR2_S and bottom surface TR2_B of the second trench TR2, the side surface VH_S of the via hole VH, and the lower insulating film 142 between the corresponding lower conductive lines CL1.

[0047] A pad pattern 167 may be formed on the barrier pattern 165. The pad pattern 167 may not be formed on the lower metal line MP1 on which the deposition inhibitor 200 is formed. The pad pattern 167 may be formed using a deposition process such as atomic layer deposition, chemical vapor deposition, and physical vapor deposition. Due to the deposition inhibitor 200, the pad pattern 167 may be selectively deposited on the side surface TR2_S and bottom surface TR2_B of the second trench TR2, the side surface VH_S of the via hole VH, and the lower insulating film 142 between the corresponding lower conductive line CL1.

[0048] After forming the barrier pattern 165 and the liner pattern 167 , the deposition inhibitor 200 may be removed.

[0049] Refer again Figure 1 , an upper metal line MP2 at least partially filling the remaining portion of the second trench TR2 and a via contact VC at least partially filling the remaining portion of the via hole VH may be formed. For example, forming the upper metal line MP2 and the via contact VC may include: forming an upper conductive film on the upper insulating film 160 to at least partially fill the remaining portion of the second trench TR2 and the remaining portion of the via hole VH; and planarizing the upper conductive film until the upper surface of the upper insulating film 160 is exposed. For example, the upper conductive film may be formed using chemical vapor deposition, physical vapor deposition, electroplating deposition processes, etc.

[0050] The via contact VC may penetrate or extend through the barrier pattern 165 and the pad pattern 167 to make contact with the lower metal line MP1 of each corresponding lower conductive line CL1 .

[0051] Figure 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 1 Describe the differences in semiconductor devices.

[0052] Reference Figure 5 The etch stop film 150 may have a single-layer structure and may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN. For example, the etch stop film 150 may include aluminum oxide (AlO).

[0053] The via contact VC may have a protrusion VCP extending into the lower insulating film 142 between the corresponding lower conductive lines CL1. The protrusion VCP of the via contact VC may be interposed between the corresponding lower conductive lines CL1. A barrier pattern 165 may be interposed between the protrusion VCP and the lower insulating film 142, and a pad pattern 167 may be interposed between the protrusion VCP and the barrier pattern 165. The protrusion VCP of the via contact VC may be spaced apart from the lower insulating film 142 with the barrier pattern 165 and the pad pattern 167 therebetween.

[0054] The barrier pattern 165 and the pad pattern 167 may extend onto and make contact with the uppermost surfaces of the lower barrier pattern 145 and the lower pad pattern 147 of each corresponding lower conductive line CL1 .

[0055] Figure 6 and Figure 7 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 2 to 4 Differences in methods for manufacturing semiconductor devices are described.

[0056] Reference Figure 6 , the etch stop film 150 and the upper insulating film 160 may be sequentially stacked on the lower insulating film 142. According to some embodiments, the etch stop film 150 may have a single-layer structure.

[0057] The second trench TR2 may be formed to penetrate or extend through the upper portion of the upper insulating film 160, and the via hole VH may be formed to penetrate or extend through the lower portion of the upper insulating film 160 from the bottom surface TR2_B of the second trench TR2. The via hole VH may penetrate or extend through the etch stop film 150 and may at least partially expose at least two corresponding lower conductive lines CL1 among the lower conductive lines CL1. The via hole VH may at least partially expose the lower metal line MP1 of each corresponding lower conductive line CL1. According to some embodiments, a recessed region RR may be formed in the lower insulating film 142 between the corresponding lower conductive lines CL1. The recessed region RR may extend from the bottom surface VH_B of the via hole VH into the lower insulating film 142 between the corresponding lower conductive lines CL1.

[0058] Reference Figure 7 , the deposition inhibitor 200 may be formed on the lower metal line MP1 exposed by the via hole VH.

[0059] The barrier pattern 165 may be formed to conformally at least partially cover the inner surface of the second trench TR2, the inner surface of the via hole VH, and the inner surface of the recessed region RR. The barrier pattern 165 may not be formed on the lower metal line MP1 on which the deposition inhibitor 200 is formed. Due to the deposition inhibitor 200, the barrier pattern 165 may be selectively deposited on the side surface TR2_S and bottom surface TR2_B of the second trench TR2, the side surface VH_S of the via hole VH, and the inner surface of the recessed region RR.

[0060] The liner pattern 167 may be formed on the barrier pattern 165. The liner pattern 167 may not be formed on the lower metal line MP1 on which the deposition inhibitor 200 is formed. Due to the deposition inhibitor 200, the liner pattern 167 may be selectively deposited on the side surface TR2_S and the bottom surface TR2_B of the second trench TR2, the side surface VH_S of the via hole VH, and the inner surface of the recess region RR.

[0061] After forming the barrier pattern 165 and the liner pattern 167 , the deposition inhibitor 200 may be removed.

[0062] Return to reference Figure 5 , an upper metal line MP2 at least partially filling the remaining portion of the second trench TR2 and a via contact VC at least partially filling the remaining portion of the via hole VH and the remaining portion of the recessed region RR may be formed. The via contact VC may include a protrusion VCP at least partially filling the remaining portion of the recessed region RR. For example, forming the upper metal line MP2 and the via contact VC may include: forming an upper conductive film on the upper insulating film 160 that at least partially fills the remaining portion of the second trench TR2, the remaining portion of the via hole VH, and the remaining portion of the recessed region RR; and planarizing the upper conductive film until the upper surface of the upper insulating film 160 is exposed.

[0063] The via contact VC may penetrate or extend through the barrier pattern 165 and the pad pattern 167 to make contact with the lower metal line MP1 of each corresponding lower conductive line CL1 .

[0064] Figure 8 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 1 Describe the differences in semiconductor devices.

[0065] Reference Figure 8The via structure VS may include a via contact VC that penetrates a lower portion of the upper insulating film 160 and the etch stop film 150, and a single barrier pattern 168 disposed on a side surface VC_S and a bottom surface VC_B of the via contact VC. The single barrier pattern 168 may be interposed between the side surface VC_S of the via contact VC and the upper insulating film 160, and may extend between the side surface VC_S of the via contact VC and the etch stop film 150. The single barrier pattern 168 may be interposed between the lower insulating film 142 and the bottom surface VC_B of the via contact VC between the corresponding lower conductive lines CL1. The via contact VC may penetrate or extend through the single barrier pattern 168 to contact the corresponding lower conductive lines CL1, and may contact the lower metal line MP1 of each corresponding lower conductive line CL1. A single barrier pattern 168 on the bottom surface VC_B of the via contact VC may contact the lower insulating film 142 between the corresponding lower conductive lines CL1 and may contact the uppermost surface of the lower barrier pattern 145 of each corresponding lower conductive line CL1 and the uppermost surface of the lower pad pattern 147. The single barrier pattern 168 may contact the side surface VC_S and the bottom surface VC_B of the via contact VC.

[0066] The single barrier pattern 168 may include Ru-doped TaN, Ta, Ru, Mo, MoN, MoMnO, TaS, MoS, a Mn—TaN stack material, a MnO—TaN stack material, and / or a carbon-based material (eg, graphene or carbon nanotube).

[0067] Upper conductive line CL2 may include an upper metal line MP2 on via contact VC. According to some embodiments, upper metal line MP2 may penetrate or extend through an upper portion of upper insulating film 160 to contact via contact VC. Upper metal line MP2 may extend onto upper insulating film 160 along first direction D1, across side surface VC_S of via contact VC. A single barrier pattern 168 may extend between upper metal line MP2 and upper insulating film 160 and may extend along bottom surface MP2_B and side surface MP2_S of upper metal line MP2. Therefore, upper conductive line CL2 may also include a single barrier pattern 168 extending along bottom surface MP2_B and side surface MP2_S of upper metal line MP2.

[0068] Figure 9 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 2 to 4 Differences in methods for manufacturing semiconductor devices are described.

[0069] Reference Figure 9 , the deposition inhibitor 200 may be formed on the lower metal line MP1 exposed by the via hole VH.

[0070] A single barrier pattern 168 may be formed to conformally at least partially cover the inner surface of the second trench TR2 and the inner surface of the via hole VH, and may be formed on the lower insulating film 142 between the corresponding lower conductive lines CL1. The single barrier pattern 168 may not be formed on the lower metal line MP1 on which the deposition inhibitor 200 is formed. The single barrier pattern 168 may be formed using a deposition process such as atomic layer deposition, chemical vapor deposition, and physical vapor deposition. Due to the deposition inhibitor 200, the single barrier pattern 168 may be selectively deposited on the side surface TR2_S and bottom surface TR2_B of the second trench TR2, the side surface VH_S of the via hole VH, and the lower insulating film 142 between the corresponding lower conductive lines CL1. After forming the single barrier pattern 168, the deposition inhibitor 200 may be removed.

[0071] Return to reference Figure 8 , an upper metal line MP2 at least partially filling the remaining portion of the second trench TR2 and a via contact VC at least partially filling the remaining portion of the via hole VH may be formed. The upper metal line MP2 and the via contact VC may be formed in the same manner as the reference Figures 2 to 4 The via contact VC may penetrate or extend through the single barrier pattern 168 to contact the lower metal line MP1 of each corresponding lower conductive line CL1 .

[0072] Figure 10 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 8 Describe the differences in semiconductor devices.

[0073] Reference Figure 10 The via contact VC may have a protrusion VCP extending into the lower insulating film 142 between the corresponding lower conductive lines CL1. The protrusion VCP of the via contact VC may be interposed between the corresponding lower conductive lines CL1. A single barrier pattern 168 may be interposed between the protrusion VCP and the lower insulating film 142. The protrusion VCP of the via contact VC may be spaced apart from the lower insulating film 142 so that the single barrier pattern 168 is interposed therebetween. The single barrier pattern 168 may extend onto the uppermost surface of the lower barrier pattern 145 and the uppermost surface of the lower pad pattern 147 of each corresponding lower conductive line CL1 and may contact the uppermost surface of the lower barrier pattern 145 and the uppermost surface of the lower pad pattern 147.

[0074] Figure 11 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 2 to 4 Differences in methods for manufacturing semiconductor devices are described.

[0075] Reference Figure 11 , the etch stop film 150 and the upper insulating film 160 may be sequentially stacked on the lower insulating film 142. According to some embodiments, the etch stop film 150 may have a single-layer structure.

[0076] The second trench TR2 may be formed to penetrate or extend through the upper portion of the upper insulating film 160, and the via hole VH may be formed to penetrate or extend from the bottom surface TR2_B of the second trench TR2 through the lower portion of the upper insulating film 160. The via hole VH may penetrate or extend through the etch stop film 150 and may at least partially expose at least two corresponding lower conductive lines CL1 among the lower conductive lines CL1. The via hole VH may at least partially expose the lower metal line MP1 of each corresponding lower conductive line CL1. According to some embodiments, a recessed region RR may be formed in the lower insulating film 142 between the corresponding lower conductive lines CL1. The recessed region RR may extend from the bottom surface of the via hole VH into the lower insulating film 142 between the corresponding lower conductive lines CL1.

[0077] The deposition inhibitor 200 may be formed on the lower metal line MP1 at least partially exposed by the via hole VH.

[0078] A single barrier pattern 168 may be formed to conformally at least partially cover the inner surface of the second trench TR2, the inner surface of the via hole VH, and the inner surface of the recessed region RR. The single barrier pattern 168 may not be formed on the lower metal line MP1 on which the deposition inhibitor 200 is formed. The single barrier pattern 168 may be formed using a deposition process such as atomic layer deposition, chemical vapor deposition, and physical vapor deposition. Due to the deposition inhibitor 200, the single barrier pattern 168 may be selectively deposited on the side surface TR2_S and bottom surface TR2_B of the second trench TR2, the side surface VH_S of the via hole VH, and the inner surface of the recessed region RR. After forming the single barrier pattern 168, the deposition inhibitor 200 may be removed.

[0079] Return to reference Figure 10 An upper metal line MP2 may be formed to at least partially fill the remaining portion of the second trench TR2, and a via contact VC may be formed to at least partially fill the remaining portion of the via hole VH and the remaining portion of the recessed region RR. The via contact VC may include a protrusion VCP that at least partially fills the remaining portion of the recessed region RR. For example, forming the upper metal line MP2 and the via contact VC may include forming an upper conductive film on the upper insulating film 160 that at least partially fills the remaining portion of the second trench TR2, the remaining portion of the via hole VH, and the remaining portion of the recessed region RR; and planarizing the upper conductive film until the upper surface of the upper insulating film 160 is exposed.

[0080] The via contact VC may penetrate or extend through the single barrier pattern 168 to contact the lower metal line MP1 of each corresponding lower conductive line CL1 .

[0081] Figure 12 and Figure 13 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept.

[0082] Reference Figure 12 and Figure 13 , the side surface VC_S of the via contact VC may be substantially perpendicular to the upper surface 100U of the substrate 100. In addition to the above differences, Figure 12 Semiconductor devices and reference Figure 1 The semiconductor devices described are essentially the same, Figure 13 Semiconductor devices and reference Figure 5 The semiconductor devices described are essentially the same.

[0083] Figure 14 and Figure 15 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept.

[0084] Reference Figure 14 and Figure 15 The upper metal line MP2 may extend on the via contact VC in the first direction D1, and a side surface MP2_S of the upper metal line MP2 may be aligned with a side surface VC_S of the via contact VC along the second direction D2. The upper metal line MP2 may have side surfaces MP2_S opposite to each other in the first direction D1, and the via contact VC may have side surfaces VC_S opposite to each other in the first direction D1. The side surfaces MP2_S of the upper metal line MP2 may be aligned with the side surfaces VC_S of the via contact VC along the second direction D2.

[0085] In addition to the above differences, Figure 14 Semiconductor devices and reference Figure 1 The semiconductor devices described are essentially the same, Figure 15 Semiconductor devices and reference Figure 5 The semiconductor devices described are essentially the same.

[0086] Figure 16 and Figure 17 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept.

[0087] Reference Figure 16 and Figure 17, the upper metal line MP2 may extend on the via contact VC in the first direction D1. The upper metal line MP2 may extend along the first direction D1 across the first side surface VC_S1 of the via contact VC onto the upper insulating film 160. Therefore, the first side surface MP2_S1 of the upper metal line MP2 may be offset from the first side surface VC_S1 of the via contact VC along the first direction D1, and the bottom surface MP2_B of the upper metal line MP2 may extend between the first side surface VC_S1 of the via contact VC and the first side surface MP2_S1 of the upper metal line MP2 in the first direction D1.

[0088] According to some embodiments, the second side surface MP2_S2 of the upper metal line MP2 may be aligned with the second side surface VC_S2 of the via contact VC along the second direction D2. The first side surface MP2_S1 and the second side surface MP2_S2 of the upper metal line MP2 may be opposite to each other in the first direction D1, and the first side surface VC_S1 and the second side surface VC_S2 of the via contact VC may be opposite to each other in the first direction D1.

[0089] In addition to the above differences, Figure 16 Semiconductor devices and reference Figure 1 The semiconductor devices described are essentially the same, Figure 17 Semiconductor devices and reference Figure 5 The semiconductor devices described are essentially the same.

[0090] Figure 18 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 1 Describe the differences in semiconductor devices.

[0091] Reference Figure 18 , the first etch stopper film 150 may be disposed on the lower insulating film 142 and may extend onto the upper surface of the lower conductive line CL1. Figure 1 The described etch stop film 150 is substantially the same.

[0092] The first upper insulating film 160 may be disposed on the first etch stopper film 150. Figure 1 The upper insulating film 160 described is substantially the same.

[0093] The second etch stopper film 170 may be disposed on the first upper insulating film 160 .

[0094] According to some embodiments, the second etch stop film 170 may have a double-layer structure (or a two-layer structure) including a third sub-film 171 and a fourth sub-film 173 sequentially stacked on the first upper insulating film 160 along the second direction D2. The third sub-film 171 may be interposed between the first upper insulating film 160 and the fourth sub-film 173. The third sub-film 171 and the fourth sub-film 173 may include different materials. The third sub-film 171 may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN. The fourth sub-film 173 may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN, but may include a material different from that of the third sub-film 171. For example, the third sub-film 171 may include aluminum oxide (AlO) and / or aluminum nitride (AlN), and the fourth sub-film 173 may include SiOC.

[0095] According to some embodiments, the fourth sub-film 173 may be omitted, and in this case, the second etch stopper film 170 may have a single-layer structure consisting of the third sub-film 171. The second etch stopper film 170 may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN, and may include, for example, aluminum oxide (AlO).

[0096] The second upper insulating film 180 may be disposed on the second etch stopper film 170. The second upper insulating film 180 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride film, and / or a low dielectric constant film.

[0097] The via structure VS may be provided in the first upper insulating film 160. The via structure VS may penetrate or extend through the first upper insulating film 160 and the first etch stopper film 150 and may extend in the first direction D1 to connect to at least two corresponding lower conductive lines CL1 among the lower conductive lines CL1.

[0098] The upper conductive line CL2 may be disposed in the second upper insulating film 180. The upper conductive line CL2 may penetrate or extend through the second upper insulating film 180 and the second etch stop film 170 and may be connected to the via structure VS. The upper conductive line CL2 may be electrically connected to the at least two corresponding lower conductive lines CL1 through the via structure VS.

[0099] The via structure VS may include a via contact VC penetrating or extending through the first upper insulating film 160 and the first etch stopper film 150, a barrier pattern 165 disposed on a side surface VC_S and a bottom surface VC_B of the via contact VC, and a pad pattern 167 interposed between the side surface VC_S of the via contact VC and the barrier pattern 165, and between the bottom surface VC_B of the via contact VC and the barrier pattern 165. The barrier pattern 165 and the pad pattern 167 may be interposed between the side surface VC_S of the via contact VC and the first upper insulating film 160, and may extend between the side surface VC_S of the via contact VC and the first etch stopper film 150. The barrier pattern 165 and the pad pattern 167 may be interposed between the lower insulating film 142 between the corresponding lower conductive lines CL1 and the bottom surface VC_B of the via contact VC. The via contact VC may penetrate or extend through the barrier pattern 165 and the pad pattern 167 to make contact with the corresponding lower conductive line CL1 , and may make contact with the lower metal line MP1 of each corresponding lower conductive line CL1 .

[0100] The upper conductive line CL2 may include an upper metal line MP2 penetrating or extending through the second upper insulating film 180 and the second etch stopper film 170, an upper barrier pattern 185 extending along a side surface MP2_S and a bottom surface MP2_B of the upper metal line MP2, and an upper liner pattern 187 interposed between the side surface MP2_S of the upper metal line MP2 and the upper barrier pattern 185 and between the bottom surface MP2_B of the upper metal line MP2 and the upper barrier pattern 185. The upper barrier pattern 185 and the upper pad pattern 187 may be interposed between the side surface MP2_S of the upper metal line MP2 and the second upper insulating film 180 and may extend between the side surface MP2_S of the upper metal line MP2 and the second etch stopper film 170. The upper barrier pattern 185 and the upper pad pattern 187 may further extend between the bottom surface MP2_B of the upper metal line MP2 and the first upper insulating film 160. The upper metal line MP2 may penetrate or extend through the upper barrier pattern 185 and the upper pad pattern 187 to make contact with the via contact VC.

[0101] The upper barrier pattern 185 may include Ta, Ti, TaN, TiN, manganese oxide (MnO), and / or manganese nitride (MnN), and the upper liner pattern 187 may include Ru, Co, Mo, Ta, Ti, Ga, and / or alloys thereof.

[0102] Figures 19 to 22 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 2 to 4 Differences in methods for manufacturing semiconductor devices are described.

[0103] Reference Figure 19, the first etch stopper film 150 and the first upper insulating film 160 may be sequentially stacked on the lower insulating film 142. According to some embodiments, the first etch stopper film 150 may have a double-layer structure including a first sub-film 151 and a second sub-film 153. According to other embodiments, the second sub-film 153 may be omitted, and in this case, the first etch stopper film 150 may have a single-layer structure consisting of the first sub-film 151.

[0104] The via hole VH may be formed to penetrate or extend through the first upper insulating film 160 and the first etch stopper film 150. The via hole VH may extend in the first direction D1 to expose at least two corresponding lower conductive lines CL1 among the lower conductive lines CL1. The via hole VH may expose the lower metal line MP1 of each corresponding lower conductive line CL1.

[0105] Reference Figure 20 , the deposition inhibitor 200 may be formed on the lower metal line MP1 exposed by the via hole VH.

[0106] The barrier pattern 165 may be formed to conformally at least partially cover the inner surface of the via hole VH and may be formed on the lower insulating film 142 between the corresponding lower conductive lines CL1. The barrier pattern 165 may not be formed on the lower metal line MP1 on which the deposition inhibitor 200 is formed. Due to the deposition inhibitor 200, the barrier pattern 165 may be selectively deposited on the side surface VH_S of the via hole VH and the lower insulating film 142 between the corresponding lower conductive lines CL1.

[0107] The liner pattern 167 may be formed on the barrier pattern 165. The liner pattern 167 may not be formed on the lower metal line MP1 on which the deposition inhibitor 200 is formed. Due to the deposition inhibitor 200, the liner pattern 167 may be selectively deposited on the side surface VH_S of the via hole VH and the lower insulating film 142 between the corresponding lower conductive line CL1.

[0108] After forming the barrier pattern 165 and the liner pattern 167 , the deposition inhibitor 200 may be removed.

[0109] Reference Figure 21A via contact VC may be formed to at least partially fill the remaining portion of the via hole VH. For example, forming the via contact VC may include: forming a via conductive film on the first upper insulating film 160 to at least partially fill the remaining portion of the via hole VH; and planarizing the via conductive film until the upper surface of the first upper insulating film 160 is exposed. For example, the via conductive film may be formed using chemical vapor deposition, physical vapor deposition, or electroplating deposition processes. The via contact VC may penetrate or extend through the barrier pattern 165 and the pad pattern 167 to contact the lower metal line MP1 of each corresponding lower conductive line CL1. The via contact VC, the barrier pattern 165, and the pad pattern 167 may be referred to as a via structure VS.

[0110] The second etch stopper film 170 may be formed on the first upper insulating film 160 and may at least partially cover the via structure VS. According to some embodiments, the second etch stopper film 170 may have a double-layer structure including a third sub-film 171 and a fourth sub-film 173. According to other embodiments, the fourth sub-film 173 may be omitted, and in this case, the second etch stopper film 170 may have a single-layer structure consisting of the third sub-film 171.

[0111] The second upper insulating film 180 may be formed on the second etch stopper film 170. The second etch stopper film 170 may be interposed between the first upper insulating film 160 and the second upper insulating film 180.

[0112] The second trench TR2 may be formed to penetrate or extend through the second upper insulating film 180 and the second etch stopper film 170. The second trench TR2 may at least partially expose the via structure VS. The second trench TR2 may at least partially expose the upper surface of the via contact VC and the uppermost surface of the barrier pattern 165 and the uppermost surface of the pad pattern 167.

[0113] Reference Figure 22 , an additional deposition inhibitor 202 may be formed on the via contact VC exposed by the second trench TR2. The additional deposition inhibitor 202 may include at least one of silicon (Si) and carbon (C).

[0114] The upper barrier pattern 185 may be formed to conformally at least partially cover the inner surface of the second trench TR2. The upper barrier pattern 185 may not be formed on the via contact VC on which the additional deposition inhibitor 202 is formed. The upper barrier pattern 185 may be formed using a deposition process such as atomic layer deposition, chemical vapor deposition, and physical vapor deposition. Due to the additional deposition inhibitor 202, the upper barrier pattern 185 may be selectively deposited on the side surface TR2_S of the second trench TR2 and on a portion of the bottom surface TR2_B of the second trench TR2.

[0115] An upper liner pattern 187 may be formed on the upper barrier pattern 185. The upper liner pattern 187 may not be formed on the via contact VC on which the additional deposition inhibitor 202 is formed. The upper liner pattern 187 may be formed using a deposition process such as atomic layer deposition, chemical vapor deposition, and physical vapor deposition. Due to the additional deposition inhibitor 202, the upper liner pattern 187 may be selectively deposited on the side surface TR2_S of the second trench TR2 and on a portion of the bottom surface TR2_B of the second trench TR2.

[0116] After forming the upper barrier pattern 185 and the upper liner pattern 187 , the additional deposition inhibitor 202 may be removed.

[0117] Return to reference Figure 18 , an upper metal line MP2 may be formed to at least partially fill the remaining portion of the second trench TR2. For example, forming the upper metal line MP2 may include: forming an upper conductive film on the second upper insulating film 180 to at least partially fill the remaining portion of the second trench TR2; and planarizing the upper conductive film until the upper surface of the second upper insulating film 180 is exposed. The upper metal line MP2 may penetrate or extend through the upper barrier pattern 185 and the upper liner pattern 187 to contact the via contact VC.

[0118] Figure 23 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 18 Describe the differences in semiconductor devices.

[0119] Reference Figure 23 Each of the first etch stopper film 150 and the second etch stopper film 170 may have a single-layer structure and may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN. For example, each of the first etch stopper film 150 and the second etch stopper film 170 may include aluminum oxide (AlO).

[0120] The via contact VC may have a protrusion VCP extending into the lower insulating film 142 between the corresponding lower conductive lines CL1. The protrusion VCP of the via contact VC may be interposed between the corresponding lower conductive lines CL1. A barrier pattern 165 may be interposed between the protrusion VCP and the lower insulating film 142, and a pad pattern 167 may be interposed between the protrusion VCP and the barrier pattern 165. The protrusion VCP of the via contact VC may be spaced apart from the lower insulating film 142 with the barrier pattern 165 and the pad pattern 167 therebetween.

[0121] The barrier pattern 165 and the pad pattern 167 may extend onto and make contact with the uppermost surfaces of the lower barrier pattern 145 and the lower pad pattern 147 of each corresponding lower conductive line CL1 .

[0122] Figure 24 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 18 Describe the differences in semiconductor devices.

[0123] Reference Figure 24 , the upper conductive line CL2 may be disposed in the second upper insulating film 180. The upper conductive line CL2 may penetrate or extend through the second upper insulating film 180 and the second etch stop film 170 and may be electrically connected to the via structure VS. The upper conductive line CL2 may be electrically connected to the at least two corresponding lower conductive lines CL1 through the via structure VS.

[0124] The upper conductive line CL2 may include an upper metal line MP2 that penetrates or extends through the second etch stopper film 170 and the second upper insulating film 180, an upper barrier pattern 185 that extends along a side surface MP2_S and a bottom surface MP2_B of the upper metal line MP2, and an upper liner pattern 187 interposed between the side surface MP2_S of the upper metal line MP2 and the upper barrier pattern 185, and between the bottom surface MP2_B of the upper metal line MP2 and the upper barrier pattern 185. The upper barrier pattern 185 and the upper pad pattern 187 may be interposed between the side surface MP2_S of the upper metal line MP2 and the second upper insulating film 180, and may extend between the side surface MP2_S of the upper metal line MP2 and the second etch stopper film 170. The upper barrier pattern 185 and the upper pad pattern 187 may also extend between the bottom surface MP2_B of the upper metal line MP2 and the first upper insulating film 160, and between the bottom surface MP2_B of the upper metal line MP2 and the via structure VS. The upper metal line MP2 may be spaced apart from the via contact VC with the upper barrier pattern 185 and the upper liner pattern 187 therebetween.

[0125] The via contact VC may penetrate or extend through the barrier pattern 165 and the pad pattern 167 to contact the corresponding lower conductive line CL1 and may contact the lower metal line MP1 of each corresponding lower conductive line CL1. According to the present embodiment, the via contact VC may directly contact the lower metal line MP1 of each corresponding lower conductive line CL1, thereby reducing the resistance of the via structure VS electrically connecting the upper conductive line CL2 and the corresponding lower conductive line CL1.

[0126] Figure 25is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 19 to 22 Differences in methods for manufacturing semiconductor devices are described.

[0127] Reference Figure 25 The second trench TR2 may be formed to penetrate or extend through the second etch stopper film 170 and the second upper insulating film 180. The second trench TR2 may expose the via structure VS. The second trench TR2 may expose the upper surface of the via contact VC and the uppermost surface of the barrier pattern 165 and the uppermost surface of the pad pattern 167.

[0128] The upper barrier pattern 185 may be formed to conformally at least partially cover the inner surface of the second trench TR2 .The upper barrier pattern 185 may extend along the side surface TR2_S and the bottom surface TR2_B of the second trench TR2 and may at least partially cover the via structure VS exposed by the second trench TR2 .

[0129] An upper liner pattern 187 may be formed on the upper barrier pattern 185. The upper liner pattern 187 may extend along the side surface TR2_S and the bottom surface TR2_B of the second trench TR2 and may extend onto the via structure VS.

[0130] Return to reference Figure 24 , an upper metal line MP2 may be formed to at least partially fill the remaining portion of the second trench TR2. Figures 19 to 22 The upper metal line MP2 is formed in substantially the same manner as described for the method of manufacturing the semiconductor device. An upper barrier pattern 185 and an upper liner pattern 187 may be interposed between the upper metal line MP2 and the via structure VS.

[0131] Figure 26 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 24 Describe the differences in semiconductor devices.

[0132] Reference Figure 26 Each of the first etch stopper film 150 and the second etch stopper film 170 may have a single-layer structure and may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN. For example, each of the first etch stopper film 150 and the second etch stopper film 170 may include aluminum oxide (AlO).

[0133] The via contact VC may have a protrusion VCP extending into the lower insulating film 142 between the corresponding lower conductive lines CL1. The protrusion VCP of the via contact VC may be interposed between the corresponding lower conductive lines CL1. A barrier pattern 165 may be interposed between the protrusion VCP and the lower insulating film 142, and a pad pattern 167 may be interposed between the protrusion VCP and the barrier pattern 165. The protrusion VCP of the via contact VC may be spaced apart from the lower insulating film 142 with the barrier pattern 165 and the pad pattern 167 therebetween.

[0134] The barrier pattern 165 and the pad pattern 167 may extend onto and make contact with the uppermost surfaces of the lower barrier pattern 145 and the lower pad pattern 147 of each corresponding lower conductive line CL1 .

[0135] Figures 27 to 30 is a cross-sectional view of a semiconductor device according to some embodiments of the present inventive concept.

[0136] Reference Figure 27 and Figure 28 , the upper metal line MP2 may extend in the first direction D1 on the via contact VC. The upper metal line MP2 may extend along the first direction D1 across the first side surface VC_S1 of the via contact VC onto the first upper insulating film 160. Therefore, the first side surface MP2_S1 of the upper metal line MP2 may be offset from the first side surface VC_S1 of the via contact VC along the first direction D1, and the bottom surface MP2_B of the upper metal line MP2 may extend in the first direction D1 between the first side surface VC_S1 of the via contact VC and the first side surface MP2_S1 of the upper metal line MP2.

[0137] According to some embodiments, the second side surface MP2_S2 of the upper metal line MP2 may be aligned with the second side surface VC_S2 of the via contact VC along the second direction D2. The first side surface MP2_S1 and the second side surface MP2_S2 of the upper metal line MP2 may be opposite to each other in the first direction D1, and the first side surface VC_S1 and the second side surface VC_S2 of the via contact VC may be opposite to each other in the first direction D1.

[0138] In addition to the above differences, Figure 27 Semiconductor devices and reference Figure 18 The semiconductor devices described are essentially the same, Figure 28 Semiconductor devices and reference Figure 24 The semiconductor devices described are essentially the same.

[0139] Reference Figure 29 and Figure 30, the upper metal line MP2 may extend in the first direction D1 on the via contact VC. The upper metal line MP2 may extend along the first direction D1 across the first side surface VC_S1 of the via contact VC onto the first upper insulating film 160. Therefore, the first side surface MP2_S1 of the upper metal line MP2 may be offset from the first side surface VC_S1 of the via contact VC along the first direction D1, and the bottom surface MP2_B of the upper metal line MP2 may extend in the first direction D1 between the first side surface VC_S1 of the via contact VC and the first side surface MP2_S1 of the upper metal line MP2.

[0140] According to some embodiments, the second side surface MP2_S2 of the upper metal line MP2 may be offset from the second side surface VC_S2 of the via contact VC along the first direction D1. The second etch stopper film 170 may extend to the uppermost surface of the barrier pattern 165 and the uppermost surface of the pad pattern 167 on the second side surface VC_S2 of the via contact VC, and may extend across the second side surface VC_S2 of the via contact VC to the upper surface of the via contact VC.

[0141] In addition to the above differences, Figure 29 Semiconductor devices and reference Figure 18 The semiconductor devices described are essentially the same, Figure 30 Semiconductor devices and reference Figure 24 The semiconductor devices described are essentially the same.

[0142] Figure 31 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 1 Describe the differences in semiconductor devices.

[0143] Reference Figure 31 , the via structure VS may be provided in the upper insulating film 160. The via structure VS may penetrate or extend through the etch stop film 150 and the upper insulating film 160 and may extend in the first direction D1 to be connected to at least two corresponding lower conductive lines CL1 among the lower conductive lines CL1.

[0144] The via structure VS may include a via contact VC penetrating or extending through the etch stop film 150 and the upper insulating film 160, a barrier pattern 165 disposed on a side surface VC_S and a bottom surface VC_B of the via contact VC, and a pad pattern 167 interposed between the side surface VC_S of the via contact VC and the barrier pattern 165 and between the bottom surface VC_B of the via contact VC and the barrier pattern 165. The via contact VC may penetrate or extend through the barrier pattern 165 and the pad pattern 167 to contact the corresponding lower conductive line CL1 and may contact the lower metal line MP1 of each corresponding lower conductive line CL1.

[0145] The upper conductive line CL2 may be disposed on the upper insulating film 160. The upper conductive line CL2 may extend along the first direction D1 across the side surface VC_S of the via contact VC onto the upper insulating film 160. The upper conductive line CL2 may contact the via contact VC and may contact the uppermost surface of the barrier pattern 165 and the uppermost surface of the pad pattern 167.

[0146] The side surface VC_S of the via contact VC may be inclined to have a first angle θ1 relative to the bottom surface VC_B of the via contact VC. The first angle θ1 may be equal to or greater than approximately 90°. For example, the first angle θ1 may be greater than approximately 90°. The via structure VS may have a first width W1 along the first direction D1. The first width W1 of the via structure VS may increase along a direction away from the substrate 100 (e.g., the second direction D2).

[0147] The side surface CL2_S of the upper conductive line CL2 may be inclined to have a second angle θ2 relative to the bottom surface CL2_B of the upper conductive line CL2. The second angle θ2 may be equal to or less than approximately 90°. For example, the second angle θ2 may be less than approximately 90°. The upper conductive line CL2 may have a second width W2 along the first direction D1. The second width W2 of the upper conductive line CL2 may decrease along a direction away from the substrate 100 (e.g., the second direction D2).

[0148] Figure 32 is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 2 to 4 Differences in methods for manufacturing semiconductor devices are described.

[0149] Reference Figure 32 , a via structure VS may be formed to penetrate or extend through the etch stop film 150 and the upper insulating film 160. The via structure VS may be formed in a manner similar to that of the reference Figures 19 to 21 The method for manufacturing the via structure VS is formed substantially the same as described above. An upper conductive film 300 may be formed on the upper insulating film 160 and may at least partially cover the via structure VS.

[0150] Return to reference Figure 31 , the upper conductive line CL2 may be formed by patterning the upper conductive film 300. For example, forming the upper conductive line CL2 may include forming a mask pattern on the upper conductive film 300 and etching the upper conductive film 300 using the mask pattern as an etching mask.

[0151] Figure 33 is a cross-sectional view of a semiconductor device according to some embodiments of the present invention. Figure 31Describe the differences in semiconductor devices.

[0152] Reference Figure 33 The etch stop film 150 may have a single-layer structure and may include aluminum oxide (AlO), aluminum nitride (AlN), aluminum oxynitride (AlON), SiCN, SiOC, MoN, manganese nitride (MnN), GaN, and / or AlGaN. For example, the etch stop film 150 may include aluminum oxide (AlO).

[0153] The via contact VC may have a protrusion VCP extending into the lower insulating film 142 between the corresponding lower conductive lines CL1. The protrusion VCP of the via contact VC may be interposed between the corresponding lower conductive lines CL1. A barrier pattern 165 may be interposed between the protrusion VCP and the lower insulating film 142, and a pad pattern 167 may be interposed between the protrusion VCP and the barrier pattern 165. The protrusion VCP of the via contact VC may be spaced apart from the lower insulating film 142 with the barrier pattern 165 and the pad pattern 167 therebetween.

[0154] The barrier pattern 165 and the pad pattern 167 may extend onto and make contact with the uppermost surfaces of the lower barrier pattern 145 and the lower pad pattern 147 of each corresponding lower conductive line CL1 .

[0155] Figure 34 is a plan view of a semiconductor device according to some embodiments of the present inventive concept. Figure 35 、 Figure 36 and Figure 37 Along the Figure 34 Cross-sectional views taken along lines AA', BB' and CC'.

[0156] Reference Figures 34 to 37 , the active pattern AP may be provided on the substrate 100. The substrate 100 may include a semiconductor substrate. For example, the substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. The active patterns AP may extend in the X direction and may be spaced apart from each other in the Y direction. The X direction and the Y direction may be parallel to the lower surface 100L of the substrate 100 and may intersect each other. The active pattern AP may protrude from the substrate 100 along the Z direction perpendicular to the lower surface 100L of the substrate 100.

[0157] The device isolation film ST may be disposed on the substrate 100 and may at least partially cover side surfaces of the active pattern AP. The device isolation film ST may include an insulating material such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0158] The channel structures CH may be disposed on each active pattern AP and may be spaced apart from each other in the X direction on each active pattern AP. Each channel structure CH may include a plurality of semiconductor patterns SP spaced apart from each other in the Z direction. The plurality of semiconductor patterns SP may vertically overlap each other in the Z direction. The plurality of semiconductor patterns SP may include a semiconductor material, such as silicon.

[0159] The source / drain patterns SD may be disposed on each active pattern AP and may be spaced apart from each other in the X-direction on each active pattern AP. The channel structure CH and the source / drain patterns SD may be alternately arranged in the X-direction on each active pattern AP. Each channel structure CH may be interposed between a pair of source / drain patterns SD adjacent to each other in the X-direction. The plurality of semiconductor patterns SP of each channel structure CH may be connected (e.g., electrically connected) to the pair of source / drain patterns SD. The source / drain patterns SD may include a semiconductor material such as silicon (Si), silicon germanium (SiGe), and / or germanium (Ge). The source / drain patterns SD may be P-type or N-type conductive. The source / drain patterns SD may include P-type impurities or N-type impurities.

[0160] The gate electrode GE may be disposed on the active pattern AP. The gate electrodes GE may be spaced apart from each other on the active pattern AP in the X direction and may extend in the Y direction to cross the active pattern AP and the device isolation film ST. The gate electrode GE may be disposed on the channel structure CH and may vertically overlap the channel structure CH along the Z direction. Each gate electrode GE may extend between the plurality of semiconductor patterns SP of the corresponding channel structure CH and between the lowermost semiconductor pattern of the plurality of semiconductor patterns SP and the corresponding active pattern AP. Source / drain patterns SD may be disposed on both sides of each gate electrode GE. Each gate electrode GE, the corresponding channel structure CH, and a pair of source / drain patterns SD connected to the corresponding channel structure CH may constitute a three-dimensional field effect transistor (e.g., an MBCFET or a GAAFET). According to some embodiments, each channel structure CH may include a semiconductor pattern (e.g., an active fin) protruding from the corresponding active pattern AP in the Z direction. In this case, each gate electrode GE, the corresponding channel structure CH, and the pair of source / drain patterns SD connected to the corresponding channel structure CH may constitute a fin field effect transistor.

[0161] Gate spacers GS may be disposed on both side surfaces of each gate electrode GE. The gate spacers GS may extend along both side surfaces of each gate electrode GE in the Y direction. The upper surface of the gate spacers GS may be positioned higher in the Z direction than the upper surface of each gate electrode GE. A gate cap pattern GP may be disposed on the upper surface of each gate electrode GE. The gate cap pattern GP may extend along the upper surface of each gate electrode GE in the Y direction. For example, the gate spacers GS and the gate cap pattern GP may comprise silicon nitride.

[0162] A gate insulating film GI may be interposed between each gate electrode GE and the corresponding channel structure CH. The gate insulating film GI may extend between each of the plurality of semiconductor patterns SP and the corresponding gate electrode GE, between each active pattern AP and the corresponding gate electrode GE, and between each source / drain pattern SD and the corresponding gate electrode GE. The gate insulating film GI may also extend between each gate spacer GS and the corresponding gate electrode GE. For example, the gate insulating film GI may include a high dielectric constant film (such as hafnium oxide) and / or silicon oxide.

[0163] A first insulating film 110 may be provided to cover the source / drain pattern SD and the gate spacer GS. The upper surface of the first insulating film 110 may be coplanar with the upper surface of the gate cap pattern GP and the upper surface of the gate spacer GS. A second insulating film 120 may be provided on the first insulating film 110 and may at least partially cover the upper surface of the gate cap pattern GP and the upper surface of the gate spacer GS. For example, the first insulating film 110 and the second insulating film 120 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low dielectric constant film.

[0164] Active contacts AC may be provided in the first insulating film 110 and the second insulating film 120 and between the gate electrodes GE. Each active contact AC may penetrate or extend through the first insulating film 110 and the second insulating film 120 to electrically connect to a corresponding source / drain pattern SD among the source / drain patterns SD. Each active contact AC may have a stripe shape extending in the Y direction. Gate contacts GC may be provided in the second insulating film 120 and on the gate electrodes GE. Each gate contact GC may penetrate or extend through the second insulating film 120 and the gate capping pattern GP to electrically connect to a corresponding gate electrode GE among the gate electrodes GE. The upper surfaces of the active contacts AC and the upper surfaces of the gate contacts GC may be coplanar with the upper surface of the second insulating film 120. The active contact AC and the gate contact GC may include a metal and / or a conductive metal nitride, such as aluminum, copper, tungsten, molybdenum, cobalt, titanium, tantalum, titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and / or platinum nitride (PtN). The active contact AC and the gate contact GC may include the same material.

[0165] A third insulating film 130 may be disposed on the second insulating film 120 and may at least partially cover the upper surfaces of the active contact AC and the gate contact GC. Conductive contacts 131 may be disposed in the third insulating film 130. Each conductive contact 131 may be electrically connected to a corresponding one of the active contact AC and the gate contact GC. The conductive contacts 131 may include a metal and / or a conductive metal nitride. A protective film 140 may be disposed on the third insulating film 130. For example, the third insulating film 130 may include silicon oxide, silicon nitride, silicon oxynitride, and / or a low-k film, and the protective film 140 may include, for example, silicon nitride.

[0166] The lower insulating film 142 may be disposed on the protective film 140, and the lower conductive line CL1 may be disposed in the lower insulating film 142. The lower insulating film 142 and the lower conductive line CL1 may be disposed in the lower insulating film 142. Figure 1 The lower insulating film 142 and the lower conductive lines CL1 are substantially the same. Each lower conductive line CL1 may penetrate or extend through the lower insulating film 142 and the protective film 140 to be electrically connected to a corresponding conductive contact 131 among the conductive contacts 131. According to some embodiments, one of the lower conductive lines CL1 may be electrically connected to a corresponding active contact AC through the corresponding conductive contact 131, and another of the lower conductive lines CL1 may be electrically connected to a corresponding gate contact GC through the corresponding conductive contact 131.

[0167] The etch stop film 150 may be disposed on the lower insulating film 142 and may extend onto the upper surface of the lower conductive line CL1. Figure 1The upper insulating film 160 may be provided on the etching stopper film 150. The upper insulating film 160 may be provided on the etching stopper film 150. Figure 1 The upper insulating film 160 is substantially the same.

[0168] The via structure VS and the upper conductive line CL2 may be provided in the upper insulating film 160. The via structure VS may penetrate or extend through the lower portion of the upper insulating film 160 and the etch stop film 150, and may extend in the Y direction to be connected to the one of the lower conductive lines CL1 and the other of the lower conductive lines CL1. The upper conductive line CL2 may penetrate or extend through the upper portion of the upper insulating film 160, and may be connected to the via structure VS. The upper conductive line CL2 may be electrically connected to the one of the lower conductive lines CL1 and the other of the lower conductive lines CL1 through the via structure VS. The via structure VS and the upper conductive line CL2 and Figure 1 The via structure VS and the upper conductive line CL2 are substantially the same.

[0169] According to an embodiment of the inventive concept, the lower insulating film 142, the lower conductive line CL1, the etch stop film 150, the upper insulating film 160, the via structure VS, and the upper conductive line CL2 may be formed as shown in FIG. Figures 1 to 33 Various transformations are performed.

[0170] Figure 38 and Figure 39 is a plan view of a semiconductor device according to some embodiments of the present inventive concept. Figure 40 It is along Figure 38 and Figure 39 In order to simplify the description, the main description and reference Figures 34 to 37 Describe the differences in semiconductor devices.

[0171] Reference Figures 38 to 40 According to some embodiments, one of the lower conductive lines CL1 may be electrically connected to one of the gate contacts GC through the corresponding conductive contact 131, and the other of the lower conductive lines CL1 may be electrically connected to the other of the gate contacts GC through the corresponding conductive contact 131. The via structure VS may penetrate or extend through the lower portion of the upper insulating film 160 and the etch stop film 150, and may extend in a direction parallel to the lower surface 100L of the substrate 100 to connect to the one of the lower conductive lines CL1 and the other of the lower conductive lines CL1.

[0172] According to some embodiments, Figure 38 As shown, the via structure VS may have a strip shape extending in a direction parallel to the lower surface 100L of the substrate 100 and crossing the X direction and the Y direction. Figure 39As shown, the via structure VS may have a curved shape including a main body portion BP extending in the Y direction, a first extension portion EP1 extending from one end of the main body portion BP in the X direction, and a second extension portion EP2 extending from the other end of the main body portion BP in a direction opposite to the X direction. In this case, the first extension portion EP1 of the via structure VS may be connected to the one of the lower conductive lines CL1, and the second extension portion EP2 of the via structure VS may be connected to the other of the lower conductive lines CL1.

[0173] The upper conductive line CL2 may be electrically connected to the one of the lower conductive lines CL1 and the other one of the lower conductive lines CL1 through the via structure VS.

[0174] According to an embodiment of the present inventive concept, a lower conductive line may be disposed in a lower insulating film, and an etch stop film and an upper insulating film may be sequentially stacked on the lower insulating film. A via structure may penetrate or extend through at least a portion of the upper insulating film and the etch stop film, and may extend in a first direction to connect to at least two lower conductive lines. The etch stop film may have a single-layer structure or a double-layer structure, thereby reducing parasitic capacitance of a semiconductor device including the lower conductive line, the via structure, and the upper conductive line.

[0175] Furthermore, the via structure may include a via contact that penetrates or extends through at least a portion of the upper insulating film and the etch stop film to connect to the at least two lower conductive lines, and a barrier pattern provided on the side and bottom surfaces of the via contact. The via contact may penetrate or extend through the barrier pattern to directly contact the lower conductive lines. Thus, the resistance of the via structure may be reduced.

[0176] Therefore, a semiconductor device having improved electrical characteristics can be provided.

[0177] The above description of the embodiments of the present invention provides examples for the description of the present invention. Therefore, the present invention is not limited to the above embodiments, and it is obvious that those skilled in the art can make various modifications and changes within the technical spirit of the present invention, such as combining the above embodiments.

[0178] This application claims priority from Korean Patent Application No. 10-2024-0031596, filed on Mar. 5, 2024, which is hereby incorporated by reference in its entirety.

Claims

1. A semiconductor device comprising: lower conductive lines on the substrate and spaced apart from each other in a first direction parallel to the upper surface of the substrate; and a via structure on the lower conductive lines and electrically connected to at least two corresponding lower conductive lines among the lower conductive lines, The passage structure comprises: a via contact extending in the first direction and electrically connected to the at least two corresponding lower conductive lines; and a barrier pattern on a side surface of the via contact and on a bottom surface of the via contact between the at least two corresponding lower conductive lines, and The via contact extends through the barrier pattern and contacts the at least two corresponding lower conductive lines.

2. The semiconductor device according to claim 1 , wherein the via structure further comprises a liner pattern interposed between the side surface of the via contact and the barrier pattern and between the bottom surface of the via contact and the barrier pattern, and wherein the via contact extends through the pad pattern and the barrier pattern and contacts the at least two corresponding lower conductive lines.

3. The semiconductor device according to claim 2, further comprising: a lower insulating film on the substrate; an upper insulating film on the lower insulating film; as well as an etching stopper film between the lower insulating film and the upper insulating film, wherein the lower conductive line is in the lower insulating film, wherein the via structure extends through the upper insulating film and the etch stop film and contacts the at least two corresponding lower conductive lines, and The etching stopper film has a single-layer structure or a double-layer structure.

4. The semiconductor device according to claim 3 , wherein the etching stopper film has a single-layer structure, wherein the via contact comprises a protrusion extending into the lower insulating film between the at least two corresponding lower conductive lines, and wherein the barrier pattern and the pad pattern are interposed between the protrusion and the lower insulating film.

5. The semiconductor device according to claim 1 , wherein each of the lower conductive lines comprises: Lower metal wire; a lower barrier pattern extending along side surfaces and a bottom surface of the lower metal line; as well as a lower pad pattern interposed between the side surface of the lower metal line and the lower barrier pattern and between the bottom surface of the lower metal line and the lower barrier pattern, and The via contact is a metal pattern composed of a single metal and extends through the barrier pattern to contact the lower metal line of each of the at least two corresponding lower conductive lines. 6 . The semiconductor device according to claim 5 , wherein the barrier pattern contacts the side surface and the bottom surface of the via contact.

7. The semiconductor device according to claim 6, further comprising: a lower insulating film on the substrate; an upper insulating film on the lower insulating film; as well as an etching stopper film between the lower insulating film and the upper insulating film, wherein the lower conductive line is in the lower insulating film, wherein the via structure extends through the upper insulating film and the etch stop film to be electrically connected to the at least two corresponding lower conductive lines, and The etching stopper film has a single-layer structure or a double-layer structure.

8. The semiconductor device according to claim 7, wherein the etching stopper film has a single-layer structure, wherein the via contact comprises a protrusion extending into the lower insulating film between the at least two corresponding lower conductive lines, and wherein the barrier pattern is interposed between the protrusion and the lower insulating film.

9. The semiconductor device according to claim 1 , further comprising an upper conductive line extending in the first direction on the via structure, wherein the upper conductive line is electrically connected to the at least two corresponding lower conductive lines through the via structure, and wherein the via contacts the upper conductive line.

10. The semiconductor device according to claim 9, wherein the upper conductive line comprises: an upper metal line contacting the via contact and extending in the first direction; and The barrier pattern extends from the side surface of the via contact to the side surface of the upper metal line.

11. The semiconductor device according to claim 9, wherein the upper conductive line comprises: an upper metal line extending in the first direction; and an upper barrier pattern interposed between the upper metal line and the via contact and extending onto a side surface of the upper metal line, and wherein the via contacts the upper barrier pattern.

12. The semiconductor device according to claim 9, wherein an angle between the side surface of the via contact and the bottom surface of the via contact is greater than 90°, and The angle between the side surface of the upper conductive line and the bottom surface of the upper conductive line is less than 90°.

13. A semiconductor device comprising: a lower insulating film on the substrate; lower conductive lines spaced apart from each other in the lower insulating film in a first direction parallel to the upper surface of the substrate; an etching stopper film on the lower insulating film; an upper insulating film on the etching stopper film; a via contact extending through at least a portion of the upper insulating film and the etch stop film and electrically connected to at least two corresponding lower conductive lines among the lower conductive lines; as well as a barrier pattern interposed between a side surface of the via contact and the upper insulating film and extending between the side surface of the via contact and the etch stop film, wherein the via contact extends in the first direction and is electrically connected to the at least two corresponding lower conductive lines, wherein the barrier pattern is interposed between the lower insulating film between the at least two corresponding lower conductive lines and a bottom surface of the via contact, and The via contact extends through the barrier pattern and contacts the at least two corresponding lower conductive lines. 14 . The semiconductor device according to claim 13 , wherein the etching stopper film has a single-layer structure or a double-layer structure.

15. The semiconductor device according to claim 13, wherein each of the lower conductive lines comprises: Lower metal wire; and a lower barrier pattern extending along side surfaces and a bottom surface of the lower metal line, and The via contact is a metal pattern composed of a single metal and extends through the barrier pattern to contact the lower metal line of each of the at least two corresponding lower conductive lines.

16. The semiconductor device according to claim 13 , further comprising a pad pattern interposed between the side surface of the via contact and the barrier pattern and between the bottom surface of the via contact and the barrier pattern, wherein the via contact extends through the pad pattern and the barrier pattern to contact the at least two corresponding lower conductive lines.

17. The semiconductor device according to claim 13, wherein the etching stopper film has a single-layer structure, wherein the via contact comprises a protrusion extending into the lower insulating film between the at least two corresponding lower conductive lines, and wherein the barrier pattern is interposed between the protrusion and the lower insulating film.

18. The semiconductor device according to claim 13, further comprising an upper metal line extending in the first direction on the via contact in the upper insulating film, wherein the via contacts the upper metal line, and The barrier pattern extends between the upper metal line and the upper insulating film.

19. The semiconductor device according to claim 13, when the etching stopper film is a first etching stopper film and the upper insulating film is a first upper insulating film, the semiconductor device further comprises: a second etching stopper film on the first upper insulating film; a second upper insulating film on the second etch stopper film; as well as an upper conductive line extending through the second upper insulating film and the second etch stopper film and electrically connected to the via contact, The upper conductive line comprises: an upper metal line extending in the first direction; and The upper barrier pattern extends along side surfaces and a bottom surface of the upper metal line. 20 . The semiconductor device of claim 19 , wherein the upper metal line extends through the upper barrier pattern to contact the via contact.

Images