Anti-reflux control device

Abstract

The invention belongs to the technical field of anti-reflux control, and particularly relates to an anti-reflux control device. The invention provides a hardware foundation of an anti-reflux control device with high response speed. The system comprises an A-phase control circuit, a B-phase control circuit, a C-phase control circuit, a three-phase current acquisition circuit, a three-phase voltage direction acquisition circuit, a man-machine interaction circuit, a power supply circuit, a single-chip microcomputer circuit and an AD acquisition circuit. The device is characterized in that a detection signal input port of the single-chip microcomputer circuit is respectively connected with a detection signal output port of the A-phase control circuit, a detection signal output port of the B-phase control circuit and a detection signal output port of the C-phase control circuit; and a control signal output port of the singlechip circuit is respectively connected with a control signal input port of the A-phase control circuit, a control signal input port of the B-phase control circuit and a control signal input port of the C-phase control circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of anti-backflow control, and in particular relates to an anti-backflow control device. Background Art

[0002] To reduce electricity costs, businesses, projects, and individuals can install photovoltaic or wind power systems. This allows them to generate electricity during peak electricity prices and use it immediately. Because photovoltaic or wind power generation is significantly affected by weather conditions, to ensure a stable power supply, these systems must be used in conjunction with the grid. However, during periods such as holidays, large power-consuming equipment may suddenly stop operating, causing unexpected grid connection issues (i.e., the power generated by the photovoltaic or wind power plant is not fully consumed and is sent to the grid). For example, if a photovoltaic or wind power plant generates 500 kW of power, and a user has two devices—one with 300 kW and the other with 200 kW—then one device may need to be shut down. The excess power generated by the photovoltaic or wind power plant may cause unexpected grid connection issues. Furthermore, because photovoltaic or wind power generation is significantly affected by weather conditions, the power generated by the photovoltaic or wind plant may fluctuate suddenly, and the user's equipment load may also fluctuate, which can also lead to reverse grid connection issues.

[0003] In some places, due to policy and other factors, electricity generated by photovoltaic and wind power is not allowed to be connected to the power grid. The power supply bureau will monitor the grid-connected power generation situation and impose corresponding penalties for grid-connected power generation without grid-connected procedures; therefore, it is necessary to install an anti-backflow control device.

[0004] Existing backflow prevention systems typically detect the direction and magnitude of current at the incoming grid and transmit this information to the grid-connected inverter via communication. The inverter then adjusts the generated power. This control strategy requires communication with the grid-connected inverter, and the backflow prevention device must use the same backflow prevention equipment as the grid-connected inverter manufacturer. This requires high system configuration and coordination with controllers, energy management systems, and other equipment. The system is complex, the equipment is expensive, and power-based pricing is applied. Furthermore, the response time is slow: once a current change is detected, the inverter takes several to ten seconds to initiate operation, often resulting in a slow response. Rapid shutdown of large equipment can easily lead to short-term backflow, which can be detected by high-speed instrumentation and identified as a power violation. This can also disrupt the power grid. Summary of the Invention

[0005] The present invention aims to solve the above problems and provides a hardware foundation for a backflow prevention control device with a fast response speed.

[0006] To achieve the above-mentioned object, the present invention adopts the following technical solution, which includes an A-phase control circuit, a B-phase control circuit, a C-phase control circuit, a three-phase current acquisition circuit, a three-phase voltage direction acquisition circuit, a human-computer interaction circuit, a power supply circuit, a single-chip microcomputer circuit, and an AD acquisition circuit. It is characterized in that the detection signal input port of the single-chip microcomputer circuit is respectively connected to the detection signal output port of the A-phase control circuit, the detection signal output port of the B-phase control circuit, and the detection signal output port of the C-phase control circuit, and the control signal output port of the single-chip microcomputer circuit is respectively connected to the control signal input port of the A-phase control circuit, the control signal input port of the B-phase control circuit, and the control signal input port of the C-phase control circuit;

[0007] The acquisition signal input port of the AD acquisition circuit is respectively connected to the acquisition signal output port of the A-phase control circuit, the acquisition signal output port of the B-phase control circuit, the acquisition signal output port of the C-phase control circuit, and the acquisition signal output port of the three-phase current acquisition circuit; the acquisition signal output port of the AD acquisition circuit is connected to the acquisition signal input port of the single-chip microcomputer circuit;

[0008] The acquisition signal output port of the three-phase voltage direction acquisition circuit is connected to the acquisition signal input port of the single chip microcomputer circuit;

[0009] The signal transmission port of the human-computer interaction circuit is connected to the signal transmission port of the single-chip computer circuit;

[0010] The power input port of the power supply circuit is connected to the mains, and the power output port of the power supply circuit is respectively connected to the power port of the A phase control circuit, the power port of the B phase control circuit, the power port of the C phase control circuit, and the power port of the single chip microcomputer circuit.

[0011] As a preferred solution, the A-phase control circuit of the present invention includes an IXFN48N50 transistor Q1, the gate of Q1 is connected to Q1B through a resistor R54, the drain of Q1 is connected to VCCA, the source of Q1 is connected to pin 1 of the ACS758LCB chip T101, the 5th pin of T101 is connected to pin 3 of the LM258 chip U19 through an inductor L2 and a resistor R57, and the 1st pin of U19 is connected to ADC1; the 2nd pin of the HT18B20ATZ chip U2 is connected to PA2;

[0012] IXFN48N50 tube Q2, Q2's gate is connected to Q2B through resistor R38, Q2's drain is connected to VCCA, Q2's source is connected to pin 1 of ACS758LCB chip T102, T102's pin 5 is connected to pin 3 of LM258 chip U6 through inductor L9 and resistor R78, U6's pin 1 is connected to ADC2; HT18B20ATZ chip U5's pin 2 is connected to PA3;

[0013] Pin 1 of FOD817C chip OP2~OP16 is connected to PH0~PH15 respectively, and pin 4 of OP2~OP16 is connected to +24VA through inductor L19;

[0014] Pin 1 of FOD817C chip OP17~OP32 is connected to PB0~PB15 respectively, and pin 4 of OP17~OP32 is connected to +24VA through inductor L3;

[0015] Pins 1, 2, and 3 of the OPA549 chip U3 are connected to Q1B, and pin 4 of U3 is connected to Q1-DRIVE;

[0016] Pins 1, 2, and 3 of the OPA549 chip U4 are connected to Q2B, and pin 4 of U4 is connected to Q2-DRIVE.

[0017] As another preferred solution, the B-phase control circuit of the present invention includes an IXFN48N50 tube Q3, the gate of Q3 is connected to Q3B through a resistor R83, the drain of Q3 is connected to VCCA, the source of Q3 is connected to pin 1 of the ACS758LCB chip T103, the 5th pin of T103 is connected to pin 3 of the LM258 chip U9 through an inductor L12 and a resistor R120, and the 1st pin of U9 is connected to ADC3; the 2nd pin of the HT18B20ATZ chip U8 is connected to PA4;

[0018] IXFN48N50 tube Q4, Q4's gate is connected to Q4B through resistor R121, Q4's drain is connected to VCCA, Q4's source is connected to pin 1 of ACS758LCB chip T104, T104's pin 5 is connected to pin 3 of LM258 chip U12 through inductor L14 and resistor R159, U12's pin 1 is connected to ADC4; HT18B20ATZ chip U11's pin 2 is connected to PA5;

[0019] Pin 1 of FOD817C chip OP35~OP50 is connected to PC0~PC15 respectively, and pin 4 of OP35~OP50 is connected to +24VB through inductor L10;

[0020] Pin 1 of FOD817C chip OP52~OP67 is connected to PD0~PD15 respectively, and pin 4 of OP52~OP67 is connected to +24VB through inductor L13;

[0021] Connect pins 1, 2, and 3 of the OPA549 chip U7 to Q3B, and pin 4 of U7 to Q3-DRIVE;

[0022] Pins 1, 2, and 3 of the OPA549 chip U10 are connected to Q4B, and pin 4 of U10 is connected to Q4-DRIVE.

[0023] As another preferred solution, the C-phase control circuit of the present invention includes an IXFN48N50 tube Q5, the gate of Q5 is connected to Q5B through a resistor R162, the drain of Q5 is connected to VCCA, the source of Q5 is connected to pin 1 of the ACS758LCB chip T105, the 5th pin of T105 is connected to pin 3 of the LM258 chip U15 through an inductor L16 and a resistor R197 in sequence, and the 1st pin of U15 is connected to ADC5; the 2nd pin of the HT18B20ATZ chip U14 is connected to PA6;

[0024] IXFN48N50 tube Q6, Q6's gate is connected to Q6B through resistor R200, Q6's drain is connected to VCCA, Q6's source is connected to pin 1 of ACS758LCB chip T106, T106's pin 5 is connected to pin 3 of LM258 chip U18 through inductor L18 and resistor R236, U18's pin 1 is connected to ADC6; HT18B20ATZ chip U17's pin 2 is connected to PA7;

[0025] Pin 1 of FOD817C chip OP68~OP83 is connected to PG0~PG15 respectively, and pin 4 of OP68~OP83 is connected to +24VC through inductor L15;

[0026] Pin 1 of FOD817C chip OP84~OP99 is connected to PF0~PF15 respectively, and pin 4 of OP84~OP99 is connected to +24VC through inductor L17;

[0027] Connect pins 1, 2, and 3 of the OPA549 chip U13 to Q5B, and pin 4 of U13 to Q5-DRIVE;

[0028] Pins 1, 2, and 3 of the OPA549 chip U16 are connected to Q6B, and pin 4 of U16 is connected to Q6-DRIVE.

[0029] As another preferred solution, the three-phase current acquisition circuit of the present invention includes Hall current transformers T107, T108, and T109, and the three pins of T107, T108, and T109 are respectively connected to ADC7, ADC8, and ADC9.

[0030] As another preferred solution, the three-phase voltage direction acquisition circuit of the present invention includes FOD817C chips OP33, OP34, and OP51. Pins 3 of OP33, OP34, and OP51 are respectively connected to PA11, PA12, and PA15. Pin 1 of OP33 is connected to A-LINE through resistor R36, pin 1 of OP34 is connected to B-LINE through resistor R79, and pin 1 of OP51 is connected to C-LINE through resistor R81.

[0031] As another preferred solution, the human-computer interaction circuit of the present invention adopts the DC32480S035 module CH1, and the 2nd and 3rd pins of CH1 are connected to PA9 and PA10 respectively.

[0032] As another preferred embodiment, the power supply circuit of the present invention includes S-60W-24 switching power supplies POW1, POW2, and POW3, the input ends of POW1, POW2, and POW3 are connected to A-LINE, and the output ends of POW1, POW2, and POW3 are connected to +24VA, +24VB, and +24VC respectively.

[0033] Secondly, the single chip microcomputer circuit of the present invention includes an STM32H743IIT6 chip U20, and the 40, 41, 42, 47, 50, 51, 52, 53, 119-123, and 138 pins of U20 are respectively connected to PA0-PA12 and PA15, the 56, 57, 58, 161-168, 79, 80, and 92-95 pins of U20 are respectively connected to PB0-PB15, the 32-35, 54, 55, 115-118, 139-141, and 8-10 pins of U20 are respectively connected to PC0-PC15, and the 142-147, 150, 151, 96-101, 104, and 105 pins of U20 are respectively connected to PD 0 to PD15 are connected accordingly, U20's 169, 170, 1 to 5, 68 to 70, 73 to 78 pins are connected to PE0 to PE15 respectively, U20's 16 to 21, 24 to 28, 59, 60, 63 to 65 pins are connected to PF0 to PF15 respectively, U20's 66, 67, 106 to 112, 152 to 157, 160 pins are connected to PG0 to PG15 respectively, U20's 29, 30, 43 to 46, 83 to 89, 128 to 130 pins are connected to PH0 to PH15 respectively, U20's 131 to 134, 173 to 176, 7, 11, 12, 13 pins are connected to PI0 to PI11 respectively;

[0034] Pin 2 of the URB2405 module U1 is connected to +24VA through inductor L5, the first winding of common-mode inductor L8, diode D29, fuse F1, and ferrite bead L1. Pin 3 of U1 is connected to +5V through inductor L11.

[0035] Connect pin 3 of U22 of the AMS1117-3.3 module to +5V, and pins 2 and 4 of U22 to +3.3V;

[0036] The anode of the EL357 chip OP100 input terminal is connected to PA8, and the emitter of the OP100 output terminal is connected to the base of the NPN transistor Q7 through the resistor R242. The collector of Q7 is connected to the 4th pin of the G5NB-1A-E-24VDC relay K1, and the 2nd and 3rd pins of K1 are connected to NO and COM respectively.

[0037] In addition, the AD acquisition circuit of the present invention includes SC1467 chips U101 and U21, and pins 9 to 22, 24, 25, and 27 to 32 of U101 are respectively connected to PI0 to PI6 and PE-0 to PE-14, and pins 33, 49, 51, 53, 55, 57, 59, 61, and 63 of U101 are respectively connected to PE-15 and ADC1 to ADC8;

[0038] Pins 9 to 22, 24, 25, 27 to 32 of U21 are connected to PI7 to PI11, PA0, PA1, PE0 to PE14 respectively, and pins 33, 49, 51, 53, 55, 57, 59, 61, and 63 of U21 are connected to PE15 and ADC9 to ADC16 respectively.

[0039] The present invention has beneficial effects.

[0040] The present invention uses multiple optocouplers (OP2-OP16, OP17-OP32) combined with resistors of varying resistance values ​​for voltage division. This allows for rapid output of the required regulated voltages Q1-DRIVE and Q2-DRIVE (0V-15V), with a frequency of up to 100kHz (response speed, the number of times per second). This allows for extremely fast feedback regulation. Once reverse flow is detected, Q1 and Q2 are quickly controlled to open and discharge excess energy generated by photovoltaic or wind power. Therefore, if a sudden reverse flow occurs, the present invention can instantly (in milliseconds) consume the excess reverse flow energy, preventing reverse flow from occurring and enabling rapid anti-reverse flow control.

[0041] The present invention uses the A-phase control circuit, the B-phase control circuit, and the C-phase control circuit (six power tubes Q1-Q6) and the single-chip computer circuit control (for example, Q1B) to control Q1-Q6 to operate in the amplification area (i.e., the variable resistance area). The three-phase electricity is rectified (the voltage after rectification is VCCA, VCCB, and VCCC) and discharged to the ground through Q1-Q6. Q1-Q6 are similar to resistors and convert the excess electricity into heat energy, which is energy-saving and environmentally friendly and does not interfere with the power grid.

[0042] The heat energy generated by Q1 to Q6 can be exchanged out through a heat exchange device (for example, connecting a water-cooled plate radiator to power tubes Q1 to Q6 for heat exchange, and using the heat sink temperature for water heating. The connection structure of the water-cooled plate radiator and the power tube is an existing conventional technology, such as a water-cooled computer host structure).

[0043] The water-cooled plate radiator can use the "all-aluminum one-piece electronic chip high-power and high-computing power board water-cooled plate liquid-cooled conversion radiator" from the following website.

[0044] https: / / item.taobao.com / item.htm? from=cart&id=607412074492&pisk=gZkKA5weYFYhbLDLjDRGrlE lhhxiwCmEX2ofEz4hNV3tP4ElE0aue43-yyVW8JD-W4g8qTmSEuM8LAchEyYUe0g0eEYDnKmEY7yWoEVqQI4YhuSCda V51Rwu2D25DPoEY8z5jaOm1DS8v2YMduaWXRZ82kw7O9ZsfPrRFkg7R5__Doy7F4NSf1ZYD_Z7N8_6XoE5RTNQNc__0 osQV4wWXRZu5zw7O4ispe1_z9z5ej0Ld1UA7v65FAEL1CmQ5MwqCkE7kDMdDiCzvWUjAPLBZr5Y10P-UgW8RDGqzogC REVEVf3Tv8pGO-itNqEZdKbLbXmsmPiA4To3pjHYdXLN_J0KCRMIMg6SXJUUNY3dJFUjLcM4C5vXDcMZ-Dktqg97jq4 sYvwJhnyLdywTbYYNdzhsNvVUUwT0T0GtWkef4cDmH5slo3FOOhKOa_PQbNHPSwndfSj8XrxiY_5zsdZTohKOa_PQbl UDjr1Pa5v1.&skuId=4429960978128&spm=a1z0d.6639537%2F202410.item.d607412074492.5c857484UEZw8H.

[0045] The present invention detects trace grid-connected signals, provides immediate and rapid feedback, and controls power generation. T107-T109 detects the three-phase current entering the home, and determines the direction of the three-phase current by comparing it with OP33, OP34, and OP35 to determine the phase of the incoming electricity. The signal is then fed back directly to U20, a 480MHz high-speed processor with an embedded RT-Thread operating system. Using time-division multiple access technology, U20 maintains high-speed current direction acquisition, enabling rapid acquisition of current magnitude and direction data.

[0046] When the detected inflow current is less than the set reverse current protection threshold, the reverse current protection will act quickly. U20 controls the conduction relationship of the optocoupler array (OP2~OP16, OP17~OP32, OP35~OP50, OP52~OP67, OP68~OP83, OP84~OP99) to gradually increase the level of its output terminals Q1-DRIVE~Q6-DRIVE. After the level is increased, the positive input terminals of U3, U4, U7, U10, U13, and U16 are connected. It forms a voltage follower and functions as a power amplifier. The output voltage (pins 1 and 2) is the same as the input voltage, and its maximum output current exceeds 5A. This drive power is connected to the control gates of Q1-Q6, causing them to operate in the variable resistance range and convert excess power into electrothermal energy. The entire circuit is executed entirely by the microprocessor's high-speed GPIO. Registers are used in the program to control the program, ensuring the high speed of the microprocessor program. Switch-type control methods and optocoupler arrays are used to control the voltage at the control gates of Q1-Q6, ensuring high speed. When the local load increases, the current flowing into the local area from the national grid increases. When the detected inflow current exceeds the set reverse current protection threshold, U20 detects the increase in inflow current and controls the OP array to reduce the voltage at the control gates of Q1-Q6. This increases the equivalent resistance of Q1-Q6 and reduces the thermoelectric conversion current.

[0047] The three-phase current acquisition circuit of the present invention is used to detect incoming household current. Hall effect current transformers T107, T108, and T109 not only detect the magnitude of the current but also its direction. Alternating current has positive and negative half-cycles. Determining grid connection (i.e., current flowing from the user's power supply port to the national grid) requires determining the positive and negative half-cycles of the AC current, combined with the current direction, to determine grid connection.

[0048] The three-phase voltage direction acquisition circuit of the present invention detects the direction of the incoming voltage. Taking phase A as an example, in the positive half cycle of A-LINE, PA11 is at a high level; in the negative half cycle of A-LINE, PA11 is at a low level. This is used to determine the voltage direction (i.e., to determine the positive and negative half cycles of the AC power). In the positive half cycle of A-LINE, current flows in, indicating no grid connection; in the negative half cycle of A-LINE, current flows out, indicating no grid connection; in the positive half cycle of A-LINE, current flows out, indicating grid connection; in the negative half cycle of A-LINE, current flows in, indicating grid connection;

[0049] The voltage direction is used to assist in determining the grid power supply status, while the current direction and magnitude are the basis for reverse flow control. For example, if the current is negative (reverse direction) during the positive half-cycle of the voltage, this is considered reverse flow, which should be avoided. Therefore, it is important to always determine the current direction and magnitude, as well as the voltage phase. Maintaining inflow during the positive half-cycle and outflow during the negative half-cycle is crucial, with lower values ​​being more economical.

[0050] The anti-backflow control device of the present invention can ensure that the excess electric energy generated by the photovoltaic or wind power generation system does not flow back into the power grid, and can convert the excess electric energy generated by the photovoltaic or wind power generation system (in the event that large power-consuming equipment suddenly stops working, the photovoltaic or wind power generation system cannot be stopped immediately; or the photovoltaic or wind power generation system can be kept running continuously) into heat energy that can be utilized (for example, for heating, etc.).

[0051] The three-phase current entering the house is detected through T107~T109, and the phase of the electricity entering the house is judged by OP33, OP34, and OP35 to determine the direction of the three-phase current. The signal is directly fed back to U20. U20 is a 480MHZ high-speed processor with an internal embedded operating system RT-Thread. It uses time division multiple access technology to maintain high-speed acquisition of current direction, realize rapid acquisition of current direction, and obtain current magnitude and current direction data.

[0052] When the detected inflow current falls below the set reverse current protection threshold, the reverse current protection system activates immediately. U20 controls the conduction relationship of the optocoupler array, raising the voltage level at its output terminals, Q1-DRIVE through Q6-DRIVE. This voltage increase connects to the positive input terminals of U3, U4, U7, U10, U13, and U16, forming a voltage follower and acting as a power amplifier. This results in a drive power supply (pins 1 and 2) that is the same as the input voltage, with a maximum output current exceeding 5A. This drive power is connected to the control gates of Q1 through Q6, causing them to operate in the variable resistance range and converting excess current into heat. The circuit is entirely executed by the microprocessor's high-speed GPIOs. Registers are used in the program to ensure high speed. Switching control of the voltage at the control gates of Q1 through Q6 is achieved through the optocoupler array, ensuring high speed. When the local load increases and the current flowing into the local area from the power grid increases, when the detected inflow current is greater than the set reverse current protection threshold, U20 detects the increase in inflow current. U20 reduces the voltage of the control electrode of Q1~Q6 by controlling the OP array, and the equivalent resistance value of Q1~Q6 increases, thereby reducing the thermoelectric conversion current.

[0053] The present invention can always keep the current flowing from the power grid to the user. At the same time, in order to ensure that the electricity generated by the photovoltaic or wind power generation system is used as much as possible (reducing electricity usage costs), a smaller reverse current protection threshold can be set (for example, 5A to 10A).

[0054] The anti-backflow device starts to work, starting or increasing the power of thermoelectric conversion to maintain the inflow current within the range of 5A to 10A.

[0055] By detecting the current through T107, T108, and T109, it is possible to determine whether the current electric energy is flowing in or out, as well as the current size, to control the conduction group of the OP optocoupler array.

[0056] Taking the phase A control circuit as an example, PH0~PH15 and PB0~PB15 control the OP optocoupler array (OP2~OP16, OP17~OP32), and then control the voltage of Q1-DRIVER and Q2-DRIVER to control the conduction of Q1 and Q2 to generate heat and control the degree of electrothermal conversion.

[0057] T101 and T102 detect the currents in Q1 and Q2, and the microcontroller circuit controls the currents flowing through Q1 and Q2 to be essentially the same, preventing damage. Furthermore, the use of two power transistors facilitates power increase and maintenance and replacement. Using two smaller power transistors significantly reduces costs compared to using larger power transistors.

[0058] For example: If the current flowing through Q1 is greater than the current flowing through Q2, and the current difference exceeds the set value, the microcontroller circuit controls Q1B and Q2B through the OP optocoupler array (OP2~OP16, OP17~OP32), Q1-DRIVER, and Q2-DRIVER. The voltage of Q1B decreases and the voltage of Q2B increases, which increases the current flowing through Q1 and reduces the current flowing through Q2.

[0059] U2 is used to detect the temperature of Q1, and U5 is used to detect the temperature of Q2. When the temperature reaches the set value, the heat exchange equipment can be controlled. For example, the water-cooled plate radiator mentioned above can be connected to the water tank to heat the water. The inlet and outlet of the water tank are connected to related equipment through a water pump. When the temperature reaches the set value, the microcontroller circuit can control the water pump to transfer heat.

[0060] U3 is an operational amplifier that amplifies the drive signal power and outputs a high-current signal to drive high-power MOS transistors Q1 and Q2. The optocoupler output is a mA-level signal, while the op amp output is a signal of 5A or above.

[0061] The human-computer interaction circuit can set the reverse current protection threshold and display the direction and magnitude of the current entering the house. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The present invention is further described below with reference to the accompanying drawings and specific embodiments. The scope of protection of the present invention is not limited to the following description.

[0063] Figures 1 to 4 It is the principle diagram of the A-phase control circuit of the present invention.

[0064] Figures 5 to 8 It is a schematic diagram of the B-phase control circuit of the present invention.

[0065] Figures 9-12 This is a schematic diagram of the C-phase control circuit of the present invention.

[0066] Figure 13 It is a schematic diagram of the three-phase current acquisition circuit of the present invention.

[0067] Figure 14 It is a schematic diagram of the three-phase voltage direction acquisition circuit of the present invention.

[0068] Figure 15 It is a schematic diagram of the human-computer interaction circuit of the present invention.

[0069] Figure 16 It is a schematic diagram of the power supply circuit of the present invention.

[0070] Figures 17-19 It is a schematic diagram of the single chip microcomputer circuit of the present invention.

[0071] Figure 20 It is the principle diagram of the AD acquisition circuit of the present invention.

[0072] Figure 21 It is a wiring block diagram of the anti-backflow control device of the present invention.

[0073] Since the circuit diagram of the present invention is quite long, in order to clearly display and see the mutual relationship, the whole diagram is cut out and the overlapping parts are retained. Figure 2 、 3 , Figure 2 、 3 It is the left and right parts of a whole picture. Figure 2 The upper part "PH8, PB8" and Figure 3 The lower end "PH8, PB8" are the same node. DETAILED DESCRIPTION

[0074] As shown in the figure, the present invention includes an A-phase control circuit, a B-phase control circuit, a C-phase control circuit, a three-phase current acquisition circuit, a three-phase voltage direction acquisition circuit, a human-computer interaction circuit, a power supply circuit, a single-chip microcomputer circuit, and an AD acquisition circuit. The detection signal input port of the single-chip microcomputer circuit is respectively connected to the detection signal output port of the A-phase control circuit, the detection signal output port of the B-phase control circuit, and the detection signal output port of the C-phase control circuit. The control signal output port of the single-chip microcomputer circuit is respectively connected to the control signal input port of the A-phase control circuit, the control signal input port of the B-phase control circuit, and the control signal input port of the C-phase control circuit;

[0075] The acquisition signal input port of the AD acquisition circuit is respectively connected to the acquisition signal output port of the A-phase control circuit, the acquisition signal output port of the B-phase control circuit, the acquisition signal output port of the C-phase control circuit, and the acquisition signal output port of the three-phase current acquisition circuit; the acquisition signal output port of the AD acquisition circuit is connected to the acquisition signal input port of the single-chip microcomputer circuit;

[0076] The acquisition signal output port of the three-phase voltage direction acquisition circuit is connected to the acquisition signal input port of the single chip microcomputer circuit;

[0077] The signal transmission port of the human-computer interaction circuit is connected to the signal transmission port of the single-chip computer circuit;

[0078] The power input port of the power supply circuit is connected to the mains, and the power output port of the power supply circuit is respectively connected to the power port of the A phase control circuit, the power port of the B phase control circuit, the power port of the C phase control circuit, and the power port of the single chip microcomputer circuit.

[0079] The A-phase control circuit includes an IXFN48N50 transistor Q1, the gate of Q1 is connected to Q1B via a resistor R54, the drain of Q1 is connected to VCCA, the source of Q1 is connected to pin 1 of the ACS758LCB chip T101, pin 5 of T101 is connected to pin 3 of the LM258 chip U19 via an inductor L2 and a resistor R57, and pin 1 of U19 is connected to ADC1; pin 2 of the HT18B20ATZ chip U2 is connected to PA2;

[0080] IXFN48N50 tube Q2, Q2's gate is connected to Q2B through resistor R38, Q2's drain is connected to VCCA, Q2's source is connected to pin 1 of ACS758LCB chip T102, T102's pin 5 is connected to pin 3 of LM258 chip U6 through inductor L9 and resistor R78, U6's pin 1 is connected to ADC2; HT18B20ATZ chip U5's pin 2 is connected to PA3;

[0081] Pin 1 of FOD817C chip OP2~OP16 is connected to PH0~PH15 respectively, and pin 4 of OP2~OP16 is connected to +24VA through inductor L19;

[0082] Pin 1 of FOD817C chip OP17~OP32 is connected to PB0~PB15 respectively, and pin 4 of OP17~OP32 is connected to +24VA through inductor L3;

[0083] Pins 1, 2, and 3 of the OPA549 chip U3 (pins 1 and 2 of U3 are outputs, and pin 3 of U3 is input, connected together to act as a voltage follower) are connected to Q1B, and pin 4 of U3 is connected to Q1-DRIVE;

[0084] Pins 1, 2, and 3 of the OPA549 chip U4 are connected to Q2B, and pin 4 of U4 is connected to Q2-DRIVE.

[0085] The B-phase control circuit includes an IXFN48N50 transistor Q3, the gate of Q3 is connected to Q3B via a resistor R83, the drain of Q3 is connected to VCCA, the source of Q3 is connected to pin 1 of the ACS758LCB chip T103, the pin 5 of T103 is connected to pin 3 of the LM258 chip U9 via an inductor L12 and a resistor R120, the pin 1 of U9 is connected to ADC3; the pin 2 of the HT18B20ATZ chip U8 is connected to PA4;

[0086] IXFN48N50 tube Q4, Q4's gate is connected to Q4B through resistor R121, Q4's drain is connected to VCCA, Q4's source is connected to pin 1 of ACS758LCB chip T104, T104's pin 5 is connected to pin 3 of LM258 chip U12 through inductor L14 and resistor R159, U12's pin 1 is connected to ADC4; HT18B20ATZ chip U11's pin 2 is connected to PA5;

[0087] Pin 1 of FOD817C chip OP35~OP50 is connected to PC0~PC15 respectively, and pin 4 of OP35~OP50 is connected to +24VB through inductor L10;

[0088] Pin 1 of FOD817C chip OP52~OP67 is connected to PD0~PD15 respectively, and pin 4 of OP52~OP67 is connected to +24VB through inductor L13;

[0089] Connect pins 1, 2, and 3 of the OPA549 chip U7 to Q3B, and pin 4 of U7 to Q3-DRIVE;

[0090] Pins 1, 2, and 3 of the OPA549 chip U10 are connected to Q4B, and pin 4 of U10 is connected to Q4-DRIVE.

[0091] The C-phase control circuit includes an IXFN48N50 transistor Q5, the gate of Q5 is connected to Q5B via a resistor R162, the drain of Q5 is connected to VCCA, the source of Q5 is connected to pin 1 of the ACS758LCB chip T105, the pin 5 of T105 is connected to pin 3 of the LM258 chip U15 via an inductor L16 and a resistor R197, and the pin 1 of U15 is connected to ADC5; the pin 2 of the HT18B20ATZ chip U14 is connected to PA6;

[0092] IXFN48N50 tube Q6, Q6's gate is connected to Q6B through resistor R200, Q6's drain is connected to VCCA, Q6's source is connected to pin 1 of ACS758LCB chip T106, T106's pin 5 is connected to pin 3 of LM258 chip U18 through inductor L18 and resistor R236, U18's pin 1 is connected to ADC6; HT18B20ATZ chip U17's pin 2 is connected to PA7;

[0093] Pin 1 of FOD817C chip OP68~OP83 is connected to PG0~PG15 respectively, and pin 4 of OP68~OP83 is connected to +24VC through inductor L15;

[0094] Pin 1 of FOD817C chip OP84~OP99 is connected to PF0~PF15 respectively, and pin 4 of OP84~OP99 is connected to +24VC through inductor L17;

[0095] Connect pins 1, 2, and 3 of the OPA549 chip U13 to Q5B, and pin 4 of U13 to Q5-DRIVE;

[0096] Pins 1, 2, and 3 of the OPA549 chip U16 are connected to Q6B, and pin 4 of U16 is connected to Q6-DRIVE.

[0097] The direction and magnitude of the household current are detected through the three-phase current acquisition circuit and the three-phase voltage direction acquisition circuit, and the current is guaranteed to flow into the user in real time (there is no grid-connected current from the user to the grid). When the local load becomes smaller or the power generation of the photovoltaic and wind power generation systems fluctuates (for example, dark clouds, sunlight intensity, sunlight angle, wind force, etc. cause fluctuations in the power generation of the photovoltaic and wind power generation systems), the current input to the user by the grid is less than the set threshold. The single-chip microcomputer circuit controls Q1 to Q6 at high speed through the optocoupler FOD817C (OP2~OP16, OP17~OP32, OP35~OP50, OP52~OP67, OP68~OP83, OP84~OP99) and the operational amplifier OPA549 (U3, U4, U7, U10, U13, U16) to discharge the current, converting the excess electrical energy into heat energy, with a reaction speed of about 30us.

[0098] The wiring diagram of the anti-backflow control device of the present invention is as follows: Figure 20 shown.

[0099] The State Grid connects to the user's power supply port via an electric meter and switch. A photovoltaic or wind power generation system connects to the user's power supply port via an inverter and switch. The user's power supply port then supplies power to the user's devices. The current direction and magnitude detection method of the present invention detects the current direction and magnitude at the electric meter (i.e., it only detects the direction and magnitude of the current flowing from the State Grid into the user's power supply port). The user's power supply port first determines the positive and negative half-cycles, then determines the current direction based on the positive and negative half-cycles, and then determines whether the current is reversed.

[0100] Since three-phase control is a separate control mode, each phase can be controlled separately. Local load has single-phase load conditions, and each load is different.

[0101] By detecting the current through T107~T109, the current conditions of each line are judged, and the size of the electric-heat conversion of each phase is controlled by Q1, Q2\Q3, Q4\Q5, and Q6. The inflow current of phases A, B, and C is modulated to be almost the same, achieving the effect of three-phase input balance and adjusting the imbalance of the three-phase power consumption.

[0102] OPA549 pin introduction:

[0103] Pins 1 and 2: Output pins (V0), output pins.

[0104] Pins 3 and 4: Inverting input (-In) and non-inverting input (+In).

[0105] Pins 5 and 7: Negative power supply pin (V-), must be connected to the negative power supply (dual supply mode) or ground (single supply mode).

[0106] Pin 6: Reference voltage pin (Ref), provides reference for ILIM and E / S pins, usually connected to V- or ground.

[0107] Pin 8: Current limit setting pin (ILIM), which sets the output current upper limit (0A~10A) through an external resistor (such as RCL) or DAC.

[0108] Pin 9: Enable / status pin (E / S), high level (≥Ref+2.4V) enables the output, low level (≤Ref+0.8V) disables the output, and can monitor the thermal shutdown state.

[0109] Pins 10 and 11: Positive power supply pin (V+). Connect to +8V to +60V in single-supply mode and ±4V to ±30V in dual-supply mode. Decoupling requires parallel connection of a 10μF tantalum capacitor and a 100nF ceramic capacitor.

[0110] As an operational amplifier, OPA549 has an advantage in speed. Its frequency is above 100KHZ, which is much faster than conventional DA chips. It can respond to control signals more quickly and control the working state of MOS tubes more accurately, thereby achieving more efficient anti-backflow control.

[0111] By turning on one optocoupler FOD817C (OP2~OP16, OP17~OP32, OP35~OP50, OP52~OP67, OP68~OP83, OP84~OP99) each time, the output voltage changes from 0 to 15, thereby controlling the size of the thermoelectric conversion.

[0112] Series voltage division principle:

[0113] For example, when OP2 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 1V.

[0114] For example, when OP3 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 2V.

[0115] For example, when OP4 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 3V.

[0116] For example, when OP5 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 4V.

[0117] For example, when OP6 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 5V.

[0118] For example, when OP7 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 6V.

[0119] For example, when OP8 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 7V.

[0120] For example, when OP9 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 8V.

[0121] For example, when OP10 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 9V.

[0122] For example, when OP11 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 10V.

[0123] For example, when OP12 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 11V.

[0124] For example, when OP13 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 12V.

[0125] For example, when OP14 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 13V.

[0126] For example, when OP15 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 14V.

[0127] For example, when OP16 is turned on and other optocouplers are turned off, the output voltage Q1-DRIVE is 15V.

[0128] Input voltage +24VA, pull-down resistor 1kΩ (e.g. Figure 2 R2), adjustable pull-up resistor R (for example Figure 2(R17 in the figure) Set the value of the adjustable pull-up resistor R so that the output voltage range is any integer from 0V to 15V. The corresponding relationship between the resistance value of R and the output voltage is as follows.

[0129]

[0130]

[0131] The three-phase current acquisition circuit includes FX-BY-D (300A) Hall current transformers T107, T108, and T109, and the three pins of T107, T108, and T109 are respectively connected to ADC7, ADC8, and ADC9.

[0132] The website of FX-BY-D (300A) Hall effect current transformer is:

[0133] https: / / item.taobao.com / item.htm? from=cart&id=650736383733&pisk=gOwiAHaBn5l63d_K9JM1a4o ZTRfdfAMjurpxkx3VT2uQBGGxkWm4kysffAEqor4KRRIsMqFHmua3ojsskqu0koPOvTB8flMj3qbReTC4Pyr8SdRZ7i lE40IKb5U4M4Hj3aQD9Kl1Exaw0mLM7BoERmmqbczqLeo-bxoq3CSn8mmWgFz4uM0EmmiqbKJ2Tvoq8IRZ3dueTmowQ FuZ7MqERm0q3xzqTMmjLFSnWoZLLwnnZQ0ti9onjf0zbVrTXJSs_CZt-d9TKW0tzT3H3KynjocKMKvlM4PSWbh389pi nko0W2UPUpDEZ7ZxmPXMQAFUORMTpaxSsr0taJGhLem3KuFrAkflxk2mSbyZtnp84km4ujVCrLniBWcuI5sX8lz-S7k _D3bTxbVnNDlemCkTwuejaRWMP2hSmP3LzTJnLjSyHBRPlXpf764XGIGZAD08-A7y793rcFShxQl-_Di1ZMjHGIGZAD 0RxMAzxfoIf_f..&skuId=4683642000925&spm=a1z0d.6639537%2F202410.item.d650736383733.5c857484h ouer0

[0134] The three-phase voltage direction acquisition circuit includes FOD817C chips OP33, OP34, and OP51. Pin 3 of OP33, OP34, and OP51 are respectively connected to PA11, PA12, and PA15. Pin 1 of OP33 is connected to A-LINE through resistor R36, pin 1 of OP34 is connected to B-LINE through resistor R79, and pin 1 of OP51 is connected to C-LINE through resistor R81.

[0135] The human-computer interaction circuit adopts the DC32480S035 module CH1, and the 2nd and 3rd pins of CH1 are connected to PA9 and PA10 respectively.

[0136] The power supply circuit includes S-60W-24 switching power supplies POW1, POW2, and POW3. The input terminals of POW1, POW2, and POW3 are connected to A-LINE, and the output terminals of POW1, POW2, and POW3 are connected to +24VA, +24VB, and +24VC, respectively. The three voltage groups of +24VA, +24VB, and +24VC are converted and used to isolate each group.

[0137] The single chip microcomputer circuit includes an STM32H743IIT6 chip U20, wherein the 40, 41, 42, 47, 50, 51, 52, 53, 119-123 and 138 pins of U20 are connected to PA0-PA12 and PA15 respectively, the 56, 57, 58, 161-168, 79, 80 and 92-95 pins of U20 are connected to PB0-PB15 respectively, the 32-35, 54, 55, 115-118, 139-141 and 8-10 pins of U20 are connected to PC0-PC15 respectively, the 142-147, 150, 151, 96-101, 104 and 105 pins of U20 are connected to PD0-P15 respectively. D15 is connected to the corresponding pins, U20's 169, 170, 1-5, 68-70, 73-78 pins are connected to PE0-PE15 respectively, U20's 16-21, 24-28, 59, 60, 63-65 pins are connected to PF0-PF15 respectively, U20's 66, 67, 106-112, 152-157, 160 pins are connected to PG0-PG15 respectively, U20's 29, 30, 43-46, 83-89, 128-130 pins are connected to PH0-PH15 respectively, U20's 131-134, 173-176, 7, 11, 12, 13 pins are connected to PI0-PI11 respectively;

[0138] Pin 2 of the URB2405 module U1 is connected to +24VA through inductor L5, the first winding of common-mode inductor L8, diode D29, fuse F1, and ferrite bead L1. Pin 3 of U1 is connected to +5V through inductor L11.

[0139] Connect pin 3 of U22 of the AMS1117-3.3 module to +5V, and pins 2 and 4 of U22 to +3.3V;

[0140] like Figure 19 As shown, the anode of the EL357 chip OP100 input terminal is connected to PA8, the emitter of the OP100 output terminal is connected to the base of the NPN transistor Q7 through the resistor R242, the collector of Q7 is connected to the 4th pin of the G5NB-1A-E-24VDC relay K1, and the 2nd and 3rd pins of K1 are connected to NO and COM respectively.

[0141] K1 is used to control the operation of the water pump and transfer heat.

[0142] The STM32H743IIT6 chip has a low price and fast processing speed.

[0143] The AD acquisition circuit includes SC1467 chips U101 and U21, and pins 9 to 22, 24, 25, and 27 to 32 of U101 are respectively connected to PI0 to PI6 and PE-0 to PE-14, and pins 33, 49, 51, 53, 55, 57, 59, 61, and 63 of U101 are respectively connected to PE-15 and ADC1 to ADC8;

[0144] Pins 9 to 22, 24, 25, 27 to 32 of U21 are connected to PI7 to PI11, PA0, PA1, PE0 to PE14 respectively, and pins 33, 49, 51, 53, 55, 57, 59, 61, and 63 of U21 are connected to PE15 and ADC9 to ADC16 respectively.

[0145] The SC1467 chip converts the collected analog signals ADC1 to ADC8 into digital signals that can be recognized by the microcontroller. The pin functions of the SC1467 chip are as follows:

[0146] AVCC: Power supply for internal analog circuits.

[0147] REFIN / REFOUT: On-chip reference input / output, which can be connected to an external reference or use the internal 2.5V.

[0148] GND: digital ground.

[0149] CS: Chip select signal (enable chip, low active).

[0150] RD: Set low when reading data.

[0151] BUSY: The chip outputs high when sampling / converting, and outputs low when the conversion is completed.

[0152] RESET: Hardware reset, low valid.

[0153] CONVST_A, B: Start sampling trigger (A / B samples two groups of channels simultaneously, parallel mode is optional).

[0154] PAR / SER: Select parallel (high level) or serial SPI (low level) mode.

[0155] DB0~DB15: Parallel data output bus.

[0156] DOUTA / B: SPI output in serial mode.

[0157] SCLK: SPI clock in serial mode.

[0158] STBY: low power standby.

[0159] The pins of the SC1467 chip used in this invention are as follows:

[0160] OS0~OS2: The settings adopt speed and accuracy control. The faster the speed, the lower the accuracy.

[0161] PAR / SER: Parallel (low) / serial (high) mode selection, byte selection function.

[0162] DB0~DB15: Parallel port data output.

[0163] CS: Chip select pin.

[0164] RD: Read data when low.

[0165] BUSY: Used to determine whether the result is ready and the data can be read.

[0166] RESET: Reset.

[0167] CONVST_A / B: pull high to start sampling;

[0168] AGND / GND: analog ground / digital ground.

[0169] REFIN / REFOUT: Floating, use the internal reference of the chip.

[0170] STBY: High for normal measurement, low for low power consumption.

[0171] RANGE: Measurement range setting, connected to GND 0~3V.

[0172] REF SELECT: Connect high to enable the internal reference.

[0173] FRSTDATA: This is the actual framing signal for data transmission. After sampling is triggered, the parallel ports (DB0 to DB15) sequentially output the sampling results of each channel (multiple channels can be output simultaneously using the internal multi-channel output function). When data from the first channel (such as AIN1) is output through the parallel port, FRSTDATA outputs a high level. When data from other channels is subsequently output, FRSTDATA is low until the next new data is output from the first channel, when it goes high again.

[0174] like Figure 20 As shown in the figure, nine capacitors (C28 to C36) with different capacities are used for filtering, covering the entire frequency band: seamless connection from DC to UHF, giving full play to the best filtering performance.

[0175] C28 uses 1pF to filter out interference near 5GHz. The capacitor model is CC0402BRNPO9BN1R0.

[0176] C29 uses 10pF to filter out interference near 1.6GHz. The capacitor model is CC0603FRNPO9BN100.

[0177] C30 uses 100pF, which can filter out interference near 500MHz. The capacitor model is CC0603KRX7R9BB101.

[0178] C31 uses 1nF to filter out interference near 50MHz. The capacitor model is CC0603KRX7R9BB102.

[0179] C32 uses 10nF, which can filter out interference near 16MHz. The capacitor model is CC0805KRX7R9BB103.

[0180] C33 uses 100nF (0.1μF), which can filter out interference near 5MHz. The capacitor model is CC0603KRX7R9BB104.

[0181] C36 uses a 1μF capacitor to filter out interference around 1MHz, and the capacitor model is CC0603KRX7R9BB105. C34 uses a 10μF capacitor to filter out interference around 100kHz, and the capacitor model is CGA0603X5R106K100JT. C35 uses a 100μF capacitor to filter out interference around 30kHz, and the capacitor model is 16TQC100MYF.

Claims

1. A backflow prevention control device, comprising an A-phase control circuit, a B-phase control circuit, a C-phase control circuit, a three-phase current acquisition circuit, a three-phase voltage direction acquisition circuit, a human-computer interaction circuit, a power supply circuit, a single-chip microcomputer circuit, and an AD acquisition circuit, characterized in that The detection signal input port of the single-chip microcomputer circuit is respectively connected to the detection signal output port of the A-phase control circuit, the detection signal output port of the B-phase control circuit, and the detection signal output port of the C-phase control circuit; the control signal output port of the single-chip microcomputer circuit is respectively connected to the control signal input port of the A-phase control circuit, the control signal input port of the B-phase control circuit, and the control signal input port of the C-phase control circuit; The acquisition signal input port of the AD acquisition circuit is respectively connected to the acquisition signal output port of the A-phase control circuit, the acquisition signal output port of the B-phase control circuit, the acquisition signal output port of the C-phase control circuit, and the acquisition signal output port of the three-phase current acquisition circuit; the acquisition signal output port of the AD acquisition circuit is connected to the acquisition signal input port of the single-chip microcomputer circuit; The acquisition signal output port of the three-phase voltage direction acquisition circuit is connected to the acquisition signal input port of the single chip microcomputer circuit; The signal transmission port of the human-computer interaction circuit is connected to the signal transmission port of the single-chip computer circuit; The power input port of the power supply circuit is connected to the mains, and the power output port of the power supply circuit is respectively connected to the power port of the A phase control circuit, the power port of the B phase control circuit, the power port of the C phase control circuit, and the power port of the single chip microcomputer circuit.

2. A backflow prevention control device according to claim 1, characterized in that The A-phase control circuit includes an IXFN48N50 transistor Q1, the gate of Q1 is connected to Q1B via a resistor R54, the drain of Q1 is connected to VCCA, the source of Q1 is connected to pin 1 of the ACS758LCB chip T101, pin 5 of T101 is connected to pin 3 of the LM258 chip U19 via an inductor L2 and a resistor R57, and pin 1 of U19 is connected to ADC1; pin 2 of the HT18B20ATZ chip U2 is connected to PA2; IXFN48N50 tube Q2, Q2's gate is connected to Q2B through resistor R38, Q2's drain is connected to VCCA, Q2's source is connected to pin 1 of ACS758LCB chip T102, T102's pin 5 is connected to pin 3 of LM258 chip U6 through inductor L9 and resistor R78, U6's pin 1 is connected to ADC2; HT18B20ATZ chip U5's pin 2 is connected to PA3; Pin 1 of FOD817C chip OP2~OP16 is connected to PH0~PH15 respectively, and pin 4 of OP2~OP16 is connected to +24VA through inductor L19; Pin 1 of FOD817C chip OP17~OP32 is connected to PB0~PB15 respectively, and pin 4 of OP17~OP32 is connected to +24VA through inductor L3; Pins 1, 2, and 3 of the OPA549 chip U3 are connected to Q1B, and pin 4 of U3 is connected to Q1-DRIVE; Pins 1, 2, and 3 of the OPA549 chip U4 are connected to Q2B, and pin 4 of U4 is connected to Q2-DRIVE.

3. The anti-backflow control device according to claim 1, characterized in that The B-phase control circuit includes an IXFN48N50 transistor Q3, the gate of Q3 is connected to Q3B via a resistor R83, the drain of Q3 is connected to VCCA, the source of Q3 is connected to pin 1 of the ACS758LCB chip T103, the pin 5 of T103 is connected to pin 3 of the LM258 chip U9 via an inductor L12 and a resistor R120, the pin 1 of U9 is connected to ADC3; the pin 2 of the HT18B20ATZ chip U8 is connected to PA4; IXFN48N50 tube Q4, Q4's gate is connected to Q4B through resistor R121, Q4's drain is connected to VCCA, Q4's source is connected to pin 1 of ACS758LCB chip T104, T104's pin 5 is connected to pin 3 of LM258 chip U12 through inductor L14 and resistor R159, U12's pin 1 is connected to ADC4; HT18B20ATZ chip U11's pin 2 is connected to PA5; Pin 1 of FOD817C chip OP35~OP50 is connected to PC0~PC15 respectively, and pin 4 of OP35~OP50 is connected to +24VB through inductor L10; Pin 1 of FOD817C chip OP52~OP67 is connected to PD0~PD15 respectively, and pin 4 of OP52~OP67 is connected to +24VB through inductor L13; Connect pins 1, 2, and 3 of the OPA549 chip U7 to Q3B, and pin 4 of U7 to Q3-DRIVE; Pins 1, 2, and 3 of the OPA549 chip U10 are connected to Q4B, and pin 4 of U10 is connected to Q4-DRIVE.

4. The anti-backflow control device according to claim 1, characterized in that The C-phase control circuit includes an IXFN48N50 transistor Q5, the gate of Q5 is connected to Q5B via a resistor R162, the drain of Q5 is connected to VCCA, the source of Q5 is connected to pin 1 of the ACS758LCB chip T105, the pin 5 of T105 is connected to pin 3 of the LM258 chip U15 via an inductor L16 and a resistor R197, and the pin 1 of U15 is connected to ADC5; the pin 2 of the HT18B20ATZ chip U14 is connected to PA6; IXFN48N50 tube Q6, Q6's gate is connected to Q6B through resistor R200, Q6's drain is connected to VCCA, Q6's source is connected to pin 1 of ACS758LCB chip T106, T106's pin 5 is connected to pin 3 of LM258 chip U18 through inductor L18 and resistor R236, U18's pin 1 is connected to ADC6; HT18B20ATZ chip U17's pin 2 is connected to PA7; Pin 1 of FOD817C chip OP68~OP83 is connected to PG0~PG15 respectively, and pin 4 of OP68~OP83 is connected to +24VC through inductor L15; Pin 1 of FOD817C chip OP84~OP99 is connected to PF0~PF15 respectively, and pin 4 of OP84~OP99 is connected to +24VC through inductor L17; Connect pins 1, 2, and 3 of the OPA549 chip U13 to Q5B, and pin 4 of U13 to Q5-DRIVE; Pins 1, 2, and 3 of the OPA549 chip U16 are connected to Q6B, and pin 4 of U16 is connected to Q6-DRIVE.

5. The anti-backflow control device according to claim 1, characterized in that The three-phase current acquisition circuit includes Hall current transformers T107, T108, and T109, and the three pins of T107, T108, and T109 are respectively connected to ADC7, ADC8, and ADC9.

6. The anti-backflow control device according to claim 1, characterized in that The three-phase voltage direction acquisition circuit includes FOD817C chips OP33, OP34, and OP51. Pin 3 of OP33, OP34, and OP51 are respectively connected to PA11, PA12, and PA15. Pin 1 of OP33 is connected to A-LINE through resistor R36, pin 1 of OP34 is connected to B-LINE through resistor R79, and pin 1 of OP51 is connected to C-LINE through resistor R81.

7. The anti-backflow control device according to claim 1, characterized in that The human-computer interaction circuit adopts the DC32480S035 module CH1, and the 2nd and 3rd pins of CH1 are connected to PA9 and PA10 respectively.

8. The anti-backflow control device according to claim 1, characterized in that The power supply circuit includes S-60W-24 switching power supplies POW1, POW2, and POW3. The input terminals of POW1, POW2, and POW3 are connected to A-LINE, and the output terminals of POW1, POW2, and POW3 are connected to +24VA, +24VB, and +24VC respectively.

9. The anti-backflow control device according to claim 1, characterized in that The single chip microcomputer circuit includes an STM32H743IIT6 chip U20, wherein the 40, 41, 42, 47, 50, 51, 52, 53, 119-123 and 138 pins of U20 are connected to PA0-PA12 and PA15 respectively, the 56, 57, 58, 161-168, 79, 80 and 92-95 pins of U20 are connected to PB0-PB15 respectively, the 32-35, 54, 55, 115-118, 139-141 and 8-10 pins of U20 are connected to PC0-PC15 respectively, the 142-147, 150, 151, 96-101, 104 and 105 pins of U20 are connected to PD0-P15 respectively. D15 is connected to the corresponding pins, U20's 169, 170, 1-5, 68-70, 73-78 pins are connected to PE0-PE15 respectively, U20's 16-21, 24-28, 59, 60, 63-65 pins are connected to PF0-PF15 respectively, U20's 66, 67, 106-112, 152-157, 160 pins are connected to PG0-PG15 respectively, U20's 29, 30, 43-46, 83-89, 128-130 pins are connected to PH0-PH15 respectively, U20's 131-134, 173-176, 7, 11, 12, 13 pins are connected to PI0-PI11 respectively; Pin 2 of the URB2405 module U1 is connected to +24VA through inductor L5, the first winding of common-mode inductor L8, diode D29, fuse F1, and ferrite bead L1. Pin 3 of U1 is connected to +5V through inductor L11. Connect pin 3 of U22 of the AMS1117-3.3 module to +5V, and pins 2 and 4 of U22 to +3.3V; The anode of the EL357 chip OP100 input terminal is connected to PA8, and the emitter of the OP100 output terminal is connected to the base of the NPN transistor Q7 through the resistor R242. The collector of Q7 is connected to the 4th pin of the G5NB-1A-E-24VDC relay K1, and the 2nd and 3rd pins of K1 are connected to NO and COM respectively.

10. The anti-backflow control device according to claim 1, characterized in that The AD acquisition circuit includes SC1467 chips U101 and U21, and pins 9 to 22, 24, 25, and 27 to 32 of U101 are respectively connected to PI0 to PI6 and PE-0 to PE-14, and pins 33, 49, 51, 53, 55, 57, 59, 61, and 63 of U101 are respectively connected to PE-15 and ADC1 to ADC8; Pins 9 to 22, 24, 25, 27 to 32 of U21 are connected to PI7 to PI11, PA0, PA1, PE0 to PE14 respectively, and pins 33, 49, 51, 53, 55, 57, 59, 61, and 63 of U21 are connected to PE15 and ADC9 to ADC16 respectively.

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