Negative pressure turn-off circuit, PCB and chip
By designing a negative voltage shutdown circuit and using a combination of PMOS and NMOS tubes to control the on and off of the IGBT, the overvoltage spike and gate oscillation problems when the IGBT is turned off are solved, the safety and reliability of the circuit are improved, and the miniaturization and integration of the circuit are achieved.
Patent Information
- Application Number
- CN202510555768.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-29
- Publication Date
- 2025-09-05
AI Technical Summary
When IGBT is turned off, it is easy to generate overvoltage spikes and gate oscillations due to stray inductance, resulting in false turn-on and even direct conduction of the upper and lower bridges of the circuit, posing a safety hazard.
A negative voltage shutdown circuit is designed. The control signal is output through the signal input terminal. The switching unit and buffer unit are used to control the conduction and negative voltage shutdown of the power switch, suppressing overvoltage spikes and gate oscillation. The combination of PMOS and NMOS tubes is used to achieve precise control of the IGBT.
It effectively suppresses overvoltage spikes and gate oscillations, reduces the probability of IGBT mis-conduction, improves circuit safety and reliability, avoids circuit failures, and miniaturizes and integrates the circuit.
Smart Images
Figure CN120601875A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technology, and in particular to a negative pressure shutdown circuit, a PCB board and a chip. Background Art
[0002] In the field of power electronics, insulated gate bipolar transistors, as an important power semiconductor device, are widely used in various power conversion and control circuits, such as inverters and frequency converters. The on- and off-control of IGBTs plays a vital role in the performance and stability of the entire circuit.
[0003] IGBT driver circuits often face challenges when controlling IGBT shutdown. Due to the presence of stray inductance in the circuit, when the IGBT rapidly turns off, this stray inductance generates high overvoltage spikes and gate oscillations. These overvoltage spikes and gate oscillations can cause the IGBT to mis-turn on. In severe cases, they can even cause the upper and lower bridges to conduct through the circuit, potentially damaging the IGBT and posing a serious safety hazard to the entire power system. Therefore, designing a reliable IGBT shutdown circuit has become a pressing issue for those skilled in the art. Summary of the Invention
[0004] The present invention aims to improve at least one technical problem in the background technology.
[0005] An embodiment of the first aspect of the present invention provides a negative voltage shutdown circuit, comprising: a signal input end, a switching unit and a power switch; the signal input end is connected to the switching unit, and the switching unit is connected to the power switch; the signal input end is used to output a control signal to the switching unit, and the switching unit is used to adjust the voltage between the control end and the reference end of the power switch according to the control signal, thereby controlling the power switch to be turned on or negatively shut down.
[0006] The beneficial effects of the embodiments of the first aspect of the present invention include: a control signal is output to a switching unit via a signal input terminal, and the switching unit changes the voltage between the control terminal and the reference terminal of the power switch according to the control signal, thereby controlling the conduction and negative voltage shutdown of the power switch. During the negative voltage shutdown process, overvoltage spikes and gate oscillations caused by stray inductance are effectively suppressed, the probability of mis-conduction of the power switch is reduced, and the occurrence of direct conduction of the upper and lower bridges of the circuit is avoided, thereby improving the safety and reliability of the entire circuit.
[0007] As some sub-solutions of the above technical solution, it also includes a buffer unit, which is connected between the switching unit and the power switch; the buffer unit is used to provide working current and working voltage for the conduction or negative pressure shutdown of the power switch.
[0008] As some sub-solutions of the above technical solution, the switching unit includes a first MOS transistor MP1, a second MOS transistor MP2, a third MOS transistor MN3, a fourth MOS transistor MN4, and a power supply voltage terminal; the power switch includes a transistor IGBT; the gate of the first MOS transistor MP1 is connected to the gate of the third MOS transistor MN3 and the signal input terminal, the source of the first MOS transistor MP1 is connected to the power supply voltage terminal, the drain of the first MOS transistor MP1 is connected to the drain of the third MOS transistor MN3, the gate of the second MOS transistor MP2, the gate of the fourth MOS transistor MN4, and the buffer unit; the source of the third MOS transistor MN3 is grounded, the source of the second MOS transistor MP2 is connected to the power supply voltage terminal, the drain of the second MOS transistor MP2 is connected to the drain of the fourth MOS transistor MN4 and the emitter of the transistor IGBT, the source of the fourth MOS transistor MN4 is grounded; and the gate of the transistor IGBT is connected to the buffer unit.
[0009] As some sub-solutions of the above technical solution, the buffer unit includes a first diode D1 and a first resistor R1; the anode of the first diode D1 is connected to the drain of the first MOS transistor MP1, the cathode of the first diode D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the gate of the transistor IGBT.
[0010] As some sub-solutions of the above technical solution, the buffer unit also includes a second diode D2 and a second resistor R2; the cathode of the second diode D2 is connected to the drain of the first MOS tube MP1, the anode of the second diode D2 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the gate of the transistor IGBT.
[0011] As some sub-solutions of the above technical solution, the first MOS transistor MP1 and the second MOS transistor MP2 are PMOS transistors, and the third MOS transistor MN3 and the fourth MOS transistor MN4 are NMOS transistors.
[0012] As some sub-solutions of the above technical solution, the control signal output by the signal input end is a square wave signal.
[0013] As some sub-solutions of the above technical solution, the square wave signal includes a high-level signal and a low-level signal, the low-level signal is used to control the power switch to be turned on, and the high-level signal is used to control the power switch to be turned off at a negative voltage.
[0014] A second aspect of the present invention provides a PCB board, comprising the negative pressure shutdown circuit as described in any one of the above items.
[0015] The PCB board according to the embodiment of the second aspect of the present invention also has corresponding beneficial effects because it includes the negative pressure shutdown circuit of the above technical solution.
[0016] A third aspect of the present invention provides a chip comprising the negative voltage shutdown circuit as described in any one of the above items.
[0017] The chip according to the embodiment of the third aspect of the present invention also has corresponding beneficial effects because it includes the negative voltage shutdown circuit of the above technical solution. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:
[0019] Figure 1 A circuit block diagram of the negative pressure shutdown circuit provided by the present invention;
[0020] Figure 2 A circuit diagram of the negative pressure shutdown circuit provided by the present invention;
[0021] Figure 3 A circuit diagram of the negative pressure shutdown circuit provided by the present invention when it is turned on;
[0022] Figure 4 This is a circuit diagram of the negative pressure shutdown circuit provided by the present invention when it is shut down.
[0023] In the accompanying drawings: 1- signal input terminal; 2- switching unit; 3- power switch; 4- buffer unit. DETAILED DESCRIPTION
[0024] The following describes embodiments of the present invention in detail. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended only to explain the present invention and are not to be construed as limiting the present invention.
[0025] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present invention.
[0026] In the description of the present invention, "several" means an indefinite quantity, "multiple" means more than two, "greater than," "less than," and "exceed" are understood to exclude the number itself, and "above," "below," and "within" are understood to include the number itself. The use of "first" and "second" is solely for the purpose of distinguishing technical features and should not be understood to indicate or imply relative importance, or to implicitly indicate the number or order of the technical features indicated. "And / or" throughout the text represents three parallel solutions. For example, "A and / or B" means a solution where A satisfies, a solution where B satisfies, or a solution where both A and B satisfy.
[0027] In the description of the present invention, if there is a short sentence containing multiple parallel features, the attributive defines the closest feature. For example, "B, C, and E are arranged on A, and are connected to D" means that B is arranged on A and E is connected to D, and does not constitute a limitation on C. However, attributives that express the relationship between features, such as "spaced arrangement" or "circular arrangement", do not fall into this category. If the word "all" is preceded by an attributive, it means that all features in the short sentence are limited. For example, "B, C, and D are all arranged on A" means that B, C, and D are all arranged on A. In a sentence with an omitted subject, the omitted subject is the subject of the previous sentence, that is, "B is arranged on A, including C" means that B is arranged on A and A includes C.
[0028] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, and connecting should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.
[0029] The following combination Figures 1 to 2 Embodiments of the present invention are described.
[0030] A negative voltage shutdown circuit in this embodiment includes: a signal input terminal 1, a switching unit 2 and a power switch 3; the signal input terminal 1 is connected to the switching unit 2, and the switching unit 2 is connected to the power switch 3; the signal input terminal 1 is used to output a control signal to the switching unit 2, and the switching unit 2 is used to adjust the voltage between the control terminal and the reference terminal of the power switch 3 according to the control signal, thereby controlling the power switch 3 to be turned on or negatively shut down.
[0031] In this embodiment, the core function of the signal input terminal 1 is to generate and output a control signal. In practical applications, the control signal is specifically a square wave signal. The square wave signal has clear high and low levels and rapid level conversion, which can provide clear and accurate control instructions for the circuit. The signal input terminal 1 can be implemented by a dedicated signal generator circuit. The circuit can generate a square wave signal that meets the requirements based on a digital circuit such as a microcontroller or a programmable logic device. The frequency and duty cycle of the square wave signal can be adjusted according to the specific application scenario to meet the operating requirements of different power switches 3.
[0032] Switching unit 2 is a logic control circuit built based on semiconductor switching devices. It receives the square wave control signal output by signal input terminal 1. This signal contains two states: high level and low level. Each state corresponds to a different control instruction. Based on these instructions, switching unit 2 adjusts the current path and voltage distribution between the supply voltage and power switch 3 by turning on and off the internal switching devices. This accurately changes the voltage between the control terminal and the reference terminal of the power switch 3, achieving effective control of the conduction and negative voltage shutdown of the power switch 3.
[0033] Specifically, when signal input terminal 1 outputs a low-level signal, switching unit 2 causes the gate potential of the transistor IGBT to rise, while the emitter potential is relatively low. When the gate-emitter voltage reaches the transistor IGBT's conduction threshold voltage, the transistor IGBT turns on. At this point, the transistor IGBT can allow a large current to pass through, achieving power output from the circuit. When signal input terminal 1 outputs a high-level signal, switching unit 2 causes the emitter voltage of the transistor IGBT to be pulled down to -VCC, rapidly releasing the gate charge, causing the gate-emitter voltage to become negative, and the transistor IGBT quickly turns off.
[0034] By precisely controlling the turn-on and negative voltage shutdown of the IGBT, the overvoltage spikes and gate oscillations caused by stray inductance in the circuit are effectively suppressed. In traditional circuits, these overvoltage spikes and gate oscillations can cause the IGBT to mis-turn on, triggering a direct conduction of the upper and lower bridges, and thus burning out the IGBT. This circuit uses negative voltage shutdown technology, which greatly reduces this risk and improves the reliability and stability of the entire circuit system. Furthermore, this circuit uses only a single supply voltage and does not require additional capacitors, which facilitates circuit miniaturization and integration.
[0035] Specifically, it further includes a buffer unit 4, which is connected between the switching unit 2 and the power switch 3; the buffer unit 4 is used to provide working current and working voltage for the conduction or negative pressure shutdown of the power switch 3.
[0036] In this embodiment, the buffer unit 4 is a signal conditioning and protection circuit; through the coordinated action of internal components, it performs current limiting and voltage stabilization operations on the signal output by the switching unit 2, so that the current and voltage ultimately applied between the gate and emitter of the transistor IGBT can meet the requirements for normal operation of the transistor IGBT, thereby avoiding damage to the transistor IGBT due to poor signal quality.
[0037] Specifically, the switching unit 2 includes a first MOS transistor MP1, a second MOS transistor MP2, a third MOS transistor MN3, a fourth MOS transistor MN4, and a power supply voltage terminal; the power switch 3 includes a transistor IGBT; the gate of the first MOS transistor MP1 is connected to the gate of the third MOS transistor MN3 and the signal input terminal 1, the source of the first MOS transistor MP1 is connected to the power supply voltage terminal, the drain of the first MOS transistor MP1 is connected to the drain of the third MOS transistor MN3, the gate of the second MOS transistor MP2, the gate of the fourth MOS transistor MN4, and the buffer unit 4; the source of the third MOS transistor MN3 is grounded, the source of the second MOS transistor MP2 is connected to the power supply voltage terminal, the drain of the second MOS transistor MP2 is connected to the drain of the fourth MOS transistor MN4 and the emitter of the transistor IGBT, and the source of the fourth MOS transistor MN4 is grounded; and the gate of the transistor IGBT is connected to the buffer unit 4.
[0038] See Figure 3 In this embodiment, when the signal input terminal 1 outputs a low-level signal, since the first MOS transistor MP1 is a PMOS transistor, when its gate voltage is lower than the source voltage, the first MOS transistor MP1 is turned on according to the conduction characteristics of the PMOS transistor; and the third MOS transistor MN3 is an NMOS transistor, when its gate voltage is lower than the source voltage, the third MOS transistor MN3 is turned off according to the conduction characteristics of the NMOS transistor; and because the first MOS transistor MP1 is turned on, its drain potential is pulled up to close to the power supply voltage VCC, that is, it is in a high-level state; the second MOS transistor MP2 is a PMOS transistor. , its gate voltage is higher than the source voltage, so the second MOS transistor MP2 is turned off; the fourth MOS transistor MN4 is an NMOS transistor, and its gate voltage is higher than the source voltage, so the fourth MOS transistor MN4 is turned on; at this time, the current of the power supply voltage terminal VCC can flow to the buffer unit 4 through the turned-on first MOS transistor MP1, and then flow into the transistor IGBT through the buffer unit 4. At this time, the gate of the transistor IGBT is at a positive potential and the emitter is at a negative potential. The transistor IGBT is turned on, and the current is output from the negative electrode of the transistor IGBT to the fourth MOS transistor MN4, which is turned on and grounded, completing the current loop.
[0039] See Figure 4When the signal input terminal 1 outputs a high-level signal, the first MOS transistor MP1 functions as a PMOS transistor, and its gate voltage is higher than the source voltage. Due to the conduction characteristics of the PMOS transistor, the first MOS transistor MP1 is turned off. The third MOS transistor MN3 functions as an NMOS transistor, and its gate voltage is higher than the source voltage. Due to the conduction characteristics of the NMOS transistor, the third MOS transistor MN3 is turned on. Since the first MOS transistor MP1 is turned off, its drain potential is pulled down to near the ground potential, that is, in a low-level state. At this time, the second MOS transistor MP2 functions as a PMOS transistor, and its gate voltage is lower than the source voltage. Therefore, the second MOS transistor MP2 is turned on. The fourth MOS transistor MN4 functions as an NMOS transistor, and its gate voltage is lower than the source voltage. Therefore, the fourth MOS transistor MN4 is turned off. At this time, the current at the power supply voltage terminal VCC can flow to the emitter of the transistor IGBT through the turned-on second MOS transistor MP2. Because the second MOS transistor MP2 is turned on, the emitter voltage is pulled up, and the original charge on the gate of the transistor IGBT begins to flow back through the buffer unit 4, from the emitter of the transistor IGBT through the buffer unit 4 to the drain of the first MOS transistor MP1, and finally flows back to ground through the turned-on third MOS transistor MN3, completing the current loop. At this time, the gate of the transistor IGBT is at a negative potential, the emitter is at a positive potential, the IGBT emitter-gate voltage VGE = -VCC, and the transistor IGBT is turned off by a negative voltage. This negative voltage turn-off method can effectively suppress overvoltage spikes and gate oscillations caused by stray inductance during the turn-off process of the transistor IGBT, thereby preventing the transistor IGBT from being turned on incorrectly.
[0040] Specifically, the buffer unit 4 includes a first diode D1 and a first resistor R1; the anode of the first diode D1 is connected to the drain of the first MOS transistor MP1, the cathode of the first diode D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the gate of the transistor IGBT.
[0041] Specifically, the buffer unit 4 also includes a second diode D2 and a second resistor R2; the cathode of the second diode D2 is connected to the drain of the first MOS transistor MP1, the anode of the second diode D2 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the gate of the transistor IGBT.
[0042] In this embodiment, the buffer unit 4 is connected between the switching unit 2 and the transistor IGBT. During the on- and off-processes of the transistor IGBT, the diode and resistor in the buffer unit 4 work together. When on, the power current provides the appropriate current and voltage to the gate of the transistor IGBT through the first diode D1 and the first resistor R1, causing the IGBT gate voltage to rise slowly, preventing voltage surges from damaging the transistor IGBT. This reduces the rate of change of current and voltage at the instant of switching, thereby reducing switching losses and improving the energy conversion efficiency of the circuit. When off, the charge on the gate of the transistor IGBT is quickly released through the second resistor R2 and the first diode D1. At the same time, the second diode D2 prevents the influence of reverse voltage on the circuit, ensuring that the IGBT can be turned off smoothly, suppressing voltage spikes and current shocks, and extending the service life of the transistor IGBT.
[0043] Specifically, during the on-phase of the transistor IGBT, the current at the power supply voltage terminal VCC passes through the turned-on first MOS transistor MP1, and then through the first diode D1 and the first resistor R1 to reach the gate of the transistor IGBT. The first diode D1 acts as a unidirectional conductor, preventing reverse current flow and ensuring that current can only flow from the first MOS transistor MP1 to the gate of the transistor IGBT. The first resistor R1 acts as a current limiter, limiting the current flowing into the gate of the transistor IGBT to prevent damage to the transistor IGBT caused by excessive current. At the same time, the first resistor R1 can also adjust the rising rate of the gate voltage of the transistor IGBT, so that the transistor IGBT can be turned on smoothly.
[0044] During the negative voltage shutdown phase of the IGBT, when the second MOS transistor MP2 and the fourth MOS transistor MN4 are turned on, the emitter voltage of the IGBT is pulled down to -VCC. At this point, the charge on the gate of the IGBT is rapidly released through the second resistor R2, the second diode D2, and the turned-on third MOS transistor MN3, achieving negative voltage shutdown of the IGBT. The second resistor R2 limits the discharge current, preventing damage to the IGBT caused by excessive discharge current. The second diode D2 also provides protection during this process, preventing reverse voltage from affecting the circuit.
[0045] Specifically, the first MOS transistor MP1 and the second MOS transistor MP2 are PMOS transistors, and the third MOS transistor MN3 and the fourth MOS transistor MN4 are NMOS transistors.
[0046] In this embodiment, the reasonable combination of PMOS and NMOS transistors is the key to realizing the negative voltage shutdown function of the IGBT. By combining the different conduction states of the PMOS and NMOS transistors, the emitter voltage of the IGBT can be pulled down to -VCC when the IGBT is turned off, realizing negative voltage shutdown, effectively suppressing overvoltage spikes and gate oscillation, and improving the shutdown performance of the IGBT and the reliability of the circuit. According to the conduction characteristics of the PMOS and NMOS transistors, combined with the control signal of the signal input terminal 1, the normal operation of the switching unit 2 is realized. At the same time, the PMOS and NMOS transistors have fast switching speeds and low on-resistances, can quickly respond to control signals, reduce power loss in the circuit, improve the energy conversion efficiency of the circuit, and further enhance the performance of the entire circuit.
[0047] Specifically, the control signal output by the signal input terminal 1 is a square wave signal.
[0048] Specifically, the square wave signal includes a high level signal and a low level signal. The low level signal is used to control the power switch 3 to be turned on, and the high level signal is used to control the power switch 3 to be turned off under negative pressure.
[0049] In this embodiment, the square wave signal has clear high and low levels and is easy to generate and control. By adjusting the frequency and duty cycle of the square wave signal, the on and off time of the IGBT can be easily changed to adapt to different application scenarios and working requirements.
[0050] A second aspect of the present invention provides a PCB board, comprising the negative pressure shutdown circuit as described in any one of the above items.
[0051] A third aspect of the present invention provides a chip comprising the negative voltage shutdown circuit as described in any one of the above items.
[0052] The above specifically describes the preferred embodiments of the present invention, but the present disclosure is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present disclosure.
Claims
1. A negative pressure shutdown circuit, characterized in that: include: A signal input terminal, a switching unit and a power switch; the signal input terminal is connected to the switching unit, and the switching unit is connected to the power switch; the signal input terminal is used to output a control signal to the switching unit, and the switching unit is used to adjust the voltage between the control terminal and the reference terminal of the power switch according to the control signal, thereby controlling the power switch to be turned on or turned off by negative pressure.
2. The negative pressure shutdown circuit according to claim 1, characterized in that: It also includes a buffer unit, which is connected between the switching unit and the power switch; the buffer unit is used to provide an operating current and an operating voltage for the conduction or negative voltage shutdown of the power switch.
3. The negative pressure shutdown circuit according to claim 2, characterized in that: The switching unit includes a first MOS transistor MP1, a second MOS transistor MP2, a third MOS transistor MN3, a fourth MOS transistor MN4, and a power supply voltage terminal; the power switch includes a transistor IGBT; the gate of the first MOS transistor MP1 is connected to the gate of the third MOS transistor MN3 and the signal input terminal, the source of the first MOS transistor MP1 is connected to the power supply voltage terminal, the drain of the first MOS transistor MP1 is connected to the drain of the third MOS transistor MN3, the gate of the second MOS transistor MP2, the gate of the fourth MOS transistor MN4, and the buffer unit; the source of the third MOS transistor MN3 is grounded, the source of the second MOS transistor MP2 is connected to the power supply voltage terminal, the drain of the second MOS transistor MP2 is connected to the drain of the fourth MOS transistor MN4 and the emitter of the transistor IGBT, the source of the fourth MOS transistor MN4 is grounded; and the gate of the transistor IGBT is connected to the buffer unit.
4. The negative pressure shutdown circuit according to claim 3, characterized in that: The buffer unit includes a first diode D1 and a first resistor R1; the anode of the first diode D1 is connected to the drain of the first MOS transistor MP1, the cathode of the first diode D1 is connected to one end of the first resistor R1, and the other end of the first resistor R1 is connected to the gate of the transistor IGBT.
5. The negative pressure shutdown circuit according to claim 4, characterized in that: The buffer unit further includes a second diode D2 and a second resistor R2; the cathode of the second diode D2 is connected to the drain of the first MOS transistor MP1, the anode of the second diode D2 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is connected to the gate of the transistor IGBT.
6. The negative pressure shutdown circuit according to claim 3, characterized in that: The first MOS transistor MP1 and the second MOS transistor MP2 are PMOS transistors, and the third MOS transistor MN3 and the fourth MOS transistor MN4 are NMOS transistors.
7. The negative pressure shutdown circuit according to claim 1, characterized in that: The control signal output by the signal input end is a square wave signal.
8. The negative pressure shutdown circuit according to claim 7, characterized in that: The square wave signal includes a high-level signal and a low-level signal. The low-level signal is used to control the power switch to be turned on, and the high-level signal is used to control the power switch to be turned off under negative voltage.
9. A PCB board, characterized in that: Comprising the negative pressure shutdown circuit according to any one of claims 1 to 8.
10. A chip, characterized in that: Comprising the negative pressure shutdown circuit according to any one of claims 1 to 8.