A digital phased array antenna automated test system, method, and product

Abstract

The application discloses a digital phased array antenna automatic test system, method and product for the field of antenna test, wherein in the system, an upper computer is connected with a real-time controller, and sends a preprogrammed test instruction sequence to the real-time controller; the real-time controller is connected with a vector network analyzer, sends an analog signal code to the vector network analyzer, is connected with a wave control computer, sends a wave position code to the wave control computer, is connected with a switch matrix, and sends a switch code to the switch matrix; the vector network analyzer is connected with a to-be-tested antenna through a digital-analog conversion card, and is connected with a test transceiving module, the vector network analyzer sends a source signal and receives a echo signal; the wave control computer is connected with the to-be-tested antenna, and controls the beam state of the to-be-tested antenna; the switch matrix is provided with a switch corresponding to each to-be-tested channel of the to-be-tested antenna, and the switch controls the opening or closing of the to-be-tested channel. The application can significantly improve the test efficiency of the digital phased array antenna.

Description

Technical Field

[0001] This application relates to the field of antenna testing, specifically to an automated testing system, method, and product for digital phased array antennas. Background Technology

[0002] Phased array antennas, with their advantages of flexible and controllable beamforming and strong anti-interference capabilities, are widely used in satellite communications, 5G base stations, and military radar. With recent developments, digital phased array antennas have gradually become the main development direction due to their performance advantages. Based on the principle of phase superposition, digital phased array antennas use electronic methods to control the phase and amplitude of each antenna element in the array via digital signals, thereby achieving rapid beam scanning, shaping, control, and multi-target tracking.

[0003] Testing digital phased array antennas is challenging because they consist of an array of channels designed for individual channel control and combined applications. This results in a large number of channels requiring testing. Furthermore, the tests cover various parameters for each channel, including amplitude and phase consistency, multiple frequencies, multiple beam states, and multiple wave positions, all designed to ensure antenna performance. This leads to an exponential increase in the number of combinations requiring testing, significantly extending testing time and reducing efficiency. For digital phased array antennas with thousands of channels, testing can take tens of hours. This severely slows down the design, production, and maintenance of digital phased array antennas, impacting their usability. Summary of the Invention

[0004] The purpose of this application is to overcome the shortcomings of the prior art and provide an automated testing system, method and product for digital phased array antennas, which can significantly improve the testing efficiency of digital phased array antennas.

[0005] Firstly, this application provides an automated testing system for digital phased array antennas, used for testing antennas under test, employing the following technical solution:

[0006] The testing system includes a host computer, a real-time controller, a vector network analyzer, a digital-to-analog converter card, a wave controller computer, a switch matrix, and a test transceiver module;

[0007] The host computer is connected to the real-time controller and sends a pre-programmed sequence of test instructions to the real-time controller;

[0008] The real-time controller is connected to the vector network analyzer and sends analog signal codes to the vector network analyzer; it is also connected to the wave control computer and sends wave position codes to the wave control computer; and it is connected to the switch matrix and sends switch codes to the switch matrix.

[0009] The vector network analyzer is connected to the antenna under test via the digital-to-analog converter card, and is also connected to the test transceiver module deployed in the test space. The vector network analyzer sends source signals to the antenna under test or the test transceiver module and receives echo signals.

[0010] The beam control computer is connected to the antenna under test and controls the beam state of the antenna under test.

[0011] The switch matrix has a switch for each channel under test of the antenna under test, and the switch controls the opening or closing of the channel under test.

[0012] By adopting the above technical solution, a real-time controller is used to call control commands from the host computer, and the real-time controller actually executes the hardware-level control of the vector network analyzer, wave controller computer, and switch matrix. This fully utilizes the performance of each module, increases response speed, and avoids the test progress being constrained by the delay of the host computer system. The vector network analyzer connects to the antenna under test through an external digital-to-analog converter card, which can adapt to the digital interface of the antenna under test's input and output, stably realize the closed-loop connection between the analog signal side of the vector network analyzer and the digital signal side of the antenna under test, and improve the digital-to-analog conversion accuracy. The switch matrix enables controllable multi-channel parallel testing of the antenna under test, further improving test efficiency.

[0013] Preferably, the real-time controller includes a logic control area and a buffer area. The logic control area contains a pre-programmed test instruction sequence sent by the host computer to the real-time controller. The buffer area stores the source signal and echo signal data emitted by the vector network analyzer. The host computer periodically retrieves the source signal and echo signal data from the buffer area.

[0014] Through the above technical solution, by partitioning the real-time controller according to its functions, the logic control and data storage of the real-time controller are isolated from each other and do not affect each other. The source signal and echo signal data of the vector network analyzer are stored in the buffer area, so that the data does not need to be transmitted and stored to the host computer in real time. This avoids the time wasted waiting for data to interact with the host computer, which slows down the test progress and reduces the test efficiency. The host computer periodically retrieves data in batches from the buffer area of ​​the real-time controller. This retrieval process is unrelated to the test process of the antenna under test and will not affect the test progress.

[0015] Preferably, the switching matrix time-division multiplexing controller is connected to the vector network analyzer.

[0016] Through the above technical solution, the time-division multiplexing controller can realize time-division switching and high-precision synchronization of multiple channels under test of the antenna under test in a single test path, enabling multi-channel parallel testing of the channels under test and improving testing efficiency.

[0017] Preferably, the test transceiver module includes a test probe and a horn antenna.

[0018] The above technical solution enables closed-loop testing of both the signal transmission and reception pathways of the antenna under test (AUT). During transmission testing, the vector network analyzer emits an analog source signal, which is converted to a digital signal by a digital-to-analog converter (DAC) and input to the digital terminal of the AUT. The AUT then analyzes this signal to generate a radio frequency (RF) signal, which is emitted and received by the test probe, forming an echo signal that is input to the vector network analyzer. During reception testing, the vector network analyzer emits an analog source signal, which is input to a horn antenna to generate an RF signal. This signal is received by the AUT and converted back to a digital signal. The digital signal is then converted back to an analog signal by the DAC, forming an echo signal that is input to the vector network analyzer.

[0019] Secondly, this application provides an automated testing method for digital phased array antennas, which employs the aforementioned testing system and includes the following steps:

[0020] The host computer sends a pre-programmed sequence of test instructions to the real-time controller;

[0021] According to the test command sequence, the real-time controller sends control codes to the wave control computer, the switch matrix, and the vector network analyzer unit by unit, based on the test set of the test command sequence. The control codes include wave position codes sent to the wave control computer, switch codes sent to the switch matrix, and analog signal codes sent to the vector network analyzer.

[0022] The wave-controlled computer adjusts the parameters of the channel under test according to the wave position code;

[0023] The switch matrix turns on the switch according to the switch code, thus activating the corresponding channel under test; the vector network analyzer sends the source signal to the antenna under test or the test transceiver module according to the analog signal code, and then receives the echo signal.

[0024] The vector network analyzer imports the echo signal and the corresponding source signal into the buffer of the real-time controller, and then sends a test set completion signal to the real-time controller.

[0025] After the real-time controller receives the test set completion signal, it sends control codes to the next test set as the object; until the entire test instruction sequence is completed.

[0026] The host computer periodically retrieves source and echo signal data from the buffer.

[0027] Through the above technical solution, the test command sequence consists of the sequence of each test set. The real-time controller sends control commands to the wave control computer, switch matrix and vector network analyzer in units of test sets, realizing the automatic and orderly advancement of the entire test process of the antenna under test, and saving the time of each test process cycle.

[0028] Preferably, for any one of the test sets, it is divided into several time slices by the time division multiplexing controller of the switching matrix. The number of time slices corresponds to the number of channels under test corresponding to the synthesized beam in the test set, or corresponds to the number of channels under test corresponding to the received beam.

[0029] Preferably, a time-division multiplexing controller is used to control the switching matrix and vector network analyzer, specifically including:

[0030] The switch matrix selects the range of the channel to be tested based on the switch code;

[0031] The vector network analyzer sends source signals to the antenna under test or the transceiver module under test based on the analog signal code.

[0032] The switch matrix sequentially turns on the switch of the corresponding channel under test in the current time slice through the time division multiplexing controller, and turns off the switches of other channels under test; until the opening and closing of the channels under test corresponding to all time slices of the current test set are completed;

[0033] The vector network analyzer uses the timestamps of each time slice of the time-division multiplexing controller as tags to receive the echo signals corresponding to each channel under test one by one.

[0034] The above technical solution divides the test set into several time slices using a time-division multiplexing controller, with each time slice corresponding to a channel under test. On the same test path, the parameters and source signals of the channels under test are the same. Multiple channels under test share the test path, and time-division multiplexing switching and high-precision synchronization are performed, thereby realizing multi-channel parallel testing of the antenna under test and improving testing efficiency.

[0035] Preferably, for any channel under test in any test set, the vector network analyzer sequentially sends source signals with different source frequencies and source powers according to the analog signal code, then receives the corresponding echo signals, and imports the echo signals and the corresponding source signals into the buffer of the real-time controller; after completing the transmission of all source signals and the reception of echo signals in the current test set, the vector network analyzer sends a test set completion signal to the real-time controller.

[0036] Through the above technical solution, for any test set, the parameters of the source signals are switched using a vector network analyzer, and multiple source signals are tested. This realizes the reuse of the test channel with predetermined parameters, optimizes the test process, makes the test process compact, and improves test efficiency.

[0037] Preferably, when the vector network analyzer sends source signals of different frequencies and powers, a delay protection time is provided for the antenna under test to respond when switching between any source signals.

[0038] Through the above technical solution, a delay protection time is reserved when the source signal is switched. This delay protection time is used to ensure that the beam re-established for different source signals reaches stability, to reserve time for transmission path and interface response, and to establish clock synchronization between various modules of the system, thereby avoiding data overwriting or loss, reduced test accuracy, and reduced system stability.

[0039] Thirdly, this application provides a computer program product, which includes a computer program or instructions that enable the computer program or instructions to implement the steps in the above-described automated testing method for digital phased array antennas.

[0040] In summary, this application includes at least one of the following beneficial technical effects:

[0041] 1. This application uses a real-time controller to call the test instruction sequence of the host computer to control the vector network analyzer, wave control computer and switch matrix. The control signal is based on hardware excitation. Compared with the host computer controlling through the operating system, it can avoid the scheduling delay of the operating system, significantly improve the instruction time accuracy, and control the jitter of the operation instruction to the order of hundreds of nanoseconds, thereby achieving microsecond-level time synchronization between modules, high control accuracy, and high-speed switching of test parameters, thus improving test efficiency.

[0042] 2. This application uses a real-time controller to buffer the source signal and echo signal, avoiding the time wasted waiting for data and interaction with the host computer, which slows down the test progress and reduces test efficiency.

[0043] 3. The vector network analyzer of this application uses an external, independent digital-to-analog converter (DAC) card to convert analog signals to digital signals, establishing a signal path from the analog signal side of the vector network analyzer to the digital signal side of the digital phased array antenna. Furthermore, compared to input signals that rely on the built-in DAC module of the antenna element for conversion, the independent DAC card has no space or power consumption limitations, can use a high-precision ADC / DAC to achieve digital-to-analog signal conversion, and can reduce quantization errors; it uses an FPGA to generate a low-jitter clock, ensuring strict matching between the sampling frequency and the signal; and it can achieve noise suppression, improving anti-interference capabilities.

[0044] 4. This application achieves time-division multiplexing switching and high-precision synchronization of each channel under test during testing under a specific test set by using a switching matrix and a time-division multiplexing controller of the switching matrix, thereby realizing multi-channel parallel testing of the antenna under test; at the same time, this application optimizes the test process by testing multiple source signals with different parameters for the channel under test under the current test set, realizing multiplexing of the target channel under test, making the test process compact and improving test efficiency. Attached Figure Description

[0045] Figure 1 This is a schematic diagram of the architecture of an automated testing system for a digital phased array antenna according to an embodiment of this application;

[0046] Figure 2 This is a flowchart illustrating an automated testing method for a digital phased array antenna according to an embodiment of this application.

[0047] Figure 3 This is a schematic diagram of the test instruction sequence for an automated testing method for a digital phased array antenna according to an embodiment of this application;

[0048] Figure 4 This is a schematic diagram of the specific process of S4 in an automated testing method for a digital phased array antenna according to an embodiment of this application;

[0049] Figure 5 This is a schematic diagram for testing loop logic. Detailed Implementation

[0050] This specific embodiment is merely an explanation of this application and is not intended to limit it. After reading this specification, those skilled in the art can make modifications to this embodiment without contributing any inventive step, but such modifications are protected by patent law as long as they are within the scope of this application.

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. It should be noted that in the optional embodiments of this application, the object information and other related data involved require the permission or consent of the object when the embodiments of this application are applied to specific products or technologies, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. That is to say, if the embodiments of this application involve data related to the object, it needs to be obtained with the authorization and consent of the object, the authorization and consent of the relevant departments, and in compliance with the relevant laws, regulations, and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information requires the consent of the individual. If sensitive information is involved, the separate consent of the information subject is required, and the embodiments also need to be implemented with the authorization and consent of the object.

[0052] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0053] Example 1:

[0054] Please see Figure 1 An automated testing system for digital phased array antennas according to an embodiment of this application is used to test the antenna 8 under test. It includes a host computer 1, a real-time controller 2, a vector network analyzer 3, a digital-to-analog converter card 4, a wave control computer 5, a switch matrix 6, and a test transceiver module 7.

[0055] The real-time controller 2 includes a logic control area 21 and a buffer area 22. The logic control area 21 is used to import pre-programmed test instruction sequences sent from the host computer 1 to the real-time controller 2, and the buffer area 22 is used to store data of the source signals emitted by the vector network analyzer 3 and the acquired echo signals. The real-time controller 2 is connected to the host computer 1 via Ethernet, relying on high bandwidth for efficient access and retrieval of large amounts of data. In another embodiment, the buffer area can also be a separate buffer area set up independently of the real-time controller, thereby achieving complete isolation between the host computer 1 reading data from the buffer area and the test process.

[0056] The logic control area 21 of the real-time controller 2 is connected to the vector network analyzer 3 via a GPIB interface, sending analog signal codes to the analyzer; it is also connected to the wave control computer 5, sending wave position codes to the computer; and it is connected to the switch matrix 6, sending switch codes to the matrix. The GPIB interface achieves microsecond-level latency through a hardware-level handshake protocol, ensuring high-precision timing control even with high-frequency test command switching. The buffer area 22 of the real-time controller 2 is connected to the vector network analyzer 3 via Ethernet to efficiently acquire and store the source signals and echo signals emitted by the analyzer 3, for periodic reading by the host computer 1.

[0057] The vector network analyzer 3 is connected to the antenna under test 8 via a digital-to-analog converter (DAC) card 4. The DAC card 4 includes an ADC module, a DAC module, and an FPGA module, used for converting analog signals to digital signals. The DAC card 4 connects to the antenna under test via an RS422 interface, enabling long-distance, high-speed signal transmission. This allows for high-speed bidirectional signal transmission between the vector network analyzer 3 and the DAC card 4 located on the control side, and the antenna under test 8 located in the test space (such as an anechoic chamber).

[0058] It should be noted that a digital phased array antenna in normal working condition has the capability to convert analog signals into digital signals, perform multi-beam control in the digital domain, and then convert them back into analog signals for power amplification and radio frequency transmission. However, due to space and power consumption limitations, the resolution and phase control accuracy of the ADC and DAC modules integrated into the antenna are weaker than those of the independent peripheral digital-to-analog converter card 4, and the timing control accuracy cannot meet the testing requirements. For channel testing of the antenna under test, especially for antennas in the design or maintenance phases, the testing itself does not focus on the antenna's digital-to-analog conversion performance. Therefore, in the embodiments of this application, to focus on the transceiver performance testing of the antenna under test, the signal input and output interfaces of the antenna under test 8 uniformly adopt the digital domain signal ports of the antenna under test 8, while the independent peripheral digital-to-analog converter card 4 is used as a relay point for converting digital signals to analog signals, thereby eliminating signal interference at the digital-to-analog conversion layer and achieving high-resolution, high-precision timing control signal conversion. The digital-to-analog converter card 4 can be adapted to complex testing scenarios through programming and reconfiguration of the FPGA module. In addition, the independent peripheral digital-to-analog converter card 4 can be hot-swapped, enabling multiplexing of tests for different antennas under test.

[0059] The vector network analyzer 3 is also connected to the test transceiver module 7, which is installed in the test space (such as an anechoic chamber). The test transceiver module 7 includes a test probe and a horn antenna. The test of the antenna under test 8 includes transmission and reception tests. For the transmission test, the signal path is as follows: the vector network analyzer 3 emits an analog signal, which is converted into a digital signal by the digital-to-analog converter card 4, and then input to the antenna under test 8 for radio frequency transmission. The radio frequency signal is collected by the test probe and then transmitted back to the vector network analyzer 3 for echo signal collection. For the reception test, the signal path is as follows: the vector network analyzer 3 emits an analog signal, which is transmitted to the horn antenna for radio frequency transmission. The antenna under test 8 receives the signal, converts it into a digital signal, converts it into an analog signal by the digital-to-analog converter card 4, and then transmits it back to the vector network analyzer 3 for echo signal collection.

[0060] The beam control computer 5 is connected to the antenna under test 8. It adjusts the parameters of the channel under test according to the beam position code, including the phase difference, amplitude weight, amplitude and phase calibration compensation value of each antenna element, so as to control the beam state and control the transmission / reception switching of the T / R component of the antenna under test.

[0061] The switch matrix 6 includes a time division multiplexing controller 61 and switches. Each channel under test of the antenna under test 8 is provided with a switch in the switch matrix 6, and the time division multiplexing controller 61 controls the opening or closing of the channel under test.

[0062] For digital phased array antennas, transmitting or receiving any radio frequency (RF) beam is achieved through a subarray composed of several channels. Traditional testing methods for antennas under test involve sequentially testing each channel, switching to the next channel, and then combining the channels for testing. This is inefficient and significantly slows down the antenna testing process. For example, if testing any channel takes 5 minutes, testing a thousand-channel antenna could take tens of hours. Furthermore, lengthy testing consumes substantial resources and manpower, such as the time spent in an anechoic chamber.

[0063] In the embodiments of this application, for any test item with a predetermined beam state, a time-division multiplexing controller 61 is used to switch the corresponding switches of each channel under test in a time-division multiplexing manner. This allows multiple channels under test to be tested in parallel through the same signal path, and a shared signal bus is used for signal transmission. This avoids configuring a separate test environment and signal path for each channel under test, enabling high-speed switching of the channel under test. Furthermore, single-clock source control ensures high timing control accuracy and stability. The time-division multiplexing controller 61 is also connected to a vector network analyzer 3. When the vector network analyzer 3 receives echo signals, it uses the timestamp of the time-division multiplexing controller 61 to map each received echo signal to the channel under test corresponding to the switch, ensuring data correspondence and independence.

[0064] More specifically, in another embodiment, the vector network analyzer 3 has several parallel echo signal buffers. When the time-division multiplexing controller 61 performs high-speed switching of the channel under test to form a high-frequency data stream of echo signals, the echo signals are sequentially stored in the echo signal buffers. This achieves time-division isolation of echo signal data with different adjacent timestamps, avoiding the data processing bottleneck of the vector network analyzer from limiting the testing efficiency of the antenna under test, or causing data loss, overwriting, or other problems. After all echo signal data has been collected, it is transmitted to the buffer 22 and stored.

[0065] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is used as an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0066] Example 2:

[0067] Please see Figure 2 This application discloses an automated testing method for a digital phased array antenna, including transmission testing and reception testing. The testing logic and intermediate processes for both types of tests are essentially the same, differing only in the direction of their respective signal paths. For transmission testing, a vector network analyzer transmits a signal, which is then transmitted via a digital-to-analog converter to the antenna under test. After RF transmission, the signal is converted into an echo signal by the test transceiver module and received by the vector network analyzer. For reception testing, the vector network analyzer transmits a signal to the test transceiver module. After RF transmission, the signal is received by the antenna under test and converted into an echo signal by the digital-to-analog converter and received by the vector network analyzer. Therefore, in this embodiment, for simplicity, the transmission test is used as an example for detailed explanation; the steps for reception testing can be compared to those for transmission testing.

[0068] The launch test includes the following steps:

[0069] S1, the host computer sends a pre-programmed test command sequence to the real-time controller. This test command sequence is edited and initiated by the antenna test software within the host computer system. After initiation, the antenna test software sends the test command sequence to the real-time controller, which then takes over the control of the subsequent specific test process.

[0070] S2, the real-time controller, based on the test command sequence, sends control codes unit by unit to the wave controller computer, switch matrix, and vector network analyzer according to the test set of the test command sequence. The control codes include wave position codes sent to the wave controller computer, switch codes sent to the switch matrix, and analog signal codes sent to the vector network analyzer. It should be noted that the test command sequence is a set arranged in test sets, each test set containing different specific test loops. The control codes are the control signals generated for each module when executing different test loops, such as... Figure 3 As shown. The principle for setting the test loop of the test set is to maximize test efficiency. Test loops with high test efficiency and switching efficiency are set as inner smaller loops, and test loops with low test efficiency and switching efficiency are set as outer larger loops.

[0071] S3, the wave control computer adjusts the parameters of the channel under test according to the wave position code.

[0072] More specifically, the control parameters include the phase difference, amplitude weight, and amplitude-phase calibration compensation values ​​of each antenna element. The beam control computer controls the parameters of each antenna element of the target antenna under test, thereby performing performance tests on the specific beamform and beam pointing of the antenna under test. During this test, the azimuth angle of the antenna under test is controlled by the mechanical rotation of the turntable, and the position signal of the turntable controller is input to the beam control computer.

[0073] It should be noted that when adjusting the parameters of the antenna element, the circuit of the antenna element has a certain response time, and the mechanical rotation of the turntable also takes a certain amount of time. Therefore, the adjustment of the beam shape and beam direction is the control link with the lowest switching efficiency and is set as the outermost large loop.

[0074] S4. After the beam control computer completes the parameter adjustment of the channel under test, the beam shape and direction are determined, and the range of the channel under test is also determined accordingly. At this time, the switch matrix opens the switch according to the switch code, turning on the corresponding channel under test; the vector network analyzer sends the source signal to the antenna under test according to the analog signal code, and then receives the echo signal. Among them, the source signal switching efficiency of the vector network analyzer is relatively high, so it is set to medium loop, while the switching efficiency of the channel under test is the highest, so it is set to small loop.

[0075] S5, the vector network analyzer imports the echo signal and the corresponding source signal into the buffer of the real-time controller, and then sends the test set completion signal to the real-time controller.

[0076] S6, after the real-time controller obtains the test set completion signal, it sends control codes for the next test set as the object; until all test instruction sequences are completed.

[0077] S7: The host computer periodically retrieves source and echo signal data from the buffer. The data retrieval process is independent of the testing process, using different channels to avoid interference. The host computer will not affect the testing timing or resource usage. The specific time interval for data retrieval can be set as needed, but data overflow or overwriting in the buffer must be avoided.

[0078] Example 3:

[0079] Based on Example 2, this implementation provides a detailed explanation of the scheme for multi-channel parallel testing using a time-division multiplexer.

[0080] For any one of the test sets, it is divided into several time slices by the time division multiplexing controller of the switching matrix. The number of time slices corresponds to the number of channels under test corresponding to the synthesized beam in the test set, or to the number of channels under test corresponding to the received beam.

[0081] For a specific test set, once the beam control computer has completed the parametric adjustment of the channel under test, the beam shape and direction are determined, and the range of the channel under test is also determined accordingly. To improve antenna testing efficiency, a time-division multiplexing controller is needed to evenly distribute the test path occupancy time of the channel under test, enabling each channel under test to share the current test path. Please refer to [link to relevant documentation]. Figure 4 The specific steps are as follows:

[0082] S4.1 The switch matrix selects the range of the channel to be tested based on the switch code.

[0083] S4.2 The vector network analyzer sets the start frequency, end frequency, and frequency step value of the source signal according to the analog signal code, and then sends the source signal with the start frequency to the antenna under test, thereby generating an radio frequency beam.

[0084] In step S4.3, the switch matrix sequentially opens the switches of the corresponding channels under test in the current time slice within the selected range through the time-division multiplexing controller, and closes the switches of other channels under test. This process effectively realizes single-channel testing of the channel under test in the current time slice. Time-division multiplexing, on the other hand, enables all test channels to share and conduct parallel testing of the current test path, until the opening, closing, and testing of all channels under test corresponding to all time slices of the current test set are completed.

[0085] S4.4, the vector network analyzer uses the timestamp of each time slice of the time-division multiplexing controller as a tag to receive the echo signal corresponding to each channel under test one by one, and associates the echo signal with the channel under test one by one. In order to cope with the high-frequency start-up and shutdown of the channel under test and the high-frequency information of the echo signal, the vector network analyzer can adopt a structure of parallel echo signal buffers. The specific implementation method is as described in the relevant content of Example 1, and will not be repeated here.

[0086] In step S4.5, the vector network analyzer increases the frequency of the source signal according to the frequency step value set by the analog signal code. Then, it returns to step S4.3 and re-executes the control loop of the time-division multiplexing controller of the switching matrix to perform response scanning of the test channel of the antenna under test at different frequencies until the source signal frequency reaches the set termination frequency. After completing the transmission of all source signals and the reception of echo signals for the current test set, the vector network analyzer sends a test set completion signal to the real-time controller.

[0087] It should be noted that when a vector network analyzer sends source signals of different frequencies and powers to switch signals, the internal oscillator (such as a YIG oscillator) needs time to lock the frequency and stabilize the phase noise. The initial stage of the signal source output may contain phase jitter or amplitude fluctuations. At the same time, when the digitally controlled attenuator and amplifier in the circuit adjust the power, the bias voltage of the semiconductor device will also have a response delay. Therefore, a delay protection time is left between any adjacent intervals of source signals for the antenna under test to respond, so as to avoid the antenna under test receiving distorted data and causing test errors.

[0088] The above technical solution realizes the intermediate loop for source signal switching in the vector network analyzer, and the small loop for switching the channel under test using the switching matrix. These two loops are nested within the larger loop of the beamforming and pointing system controlled by the beam control computer, forming a test set and enabling a complete testing process for the antenna under test. This significantly improves the testing efficiency of digital phased array antennas. The specific test loop logic for the antenna under test is as follows: Figure 5 As shown.

[0089] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0090] In another embodiment, a computer program product of this application includes a computer program or instructions that enable the computer program or instructions to perform the steps in the above-described automated testing method for digital phased array antennas.

[0091] As used in the above embodiments, depending on the context, the term "when..." can be interpreted as meaning "if...", "after...", "in response to determining...", or "in response to detecting...". Similarly, depending on the context, the phrase "when determining..." or "if (the stated condition or event) is interpreted as meaning "if determining...", "in response to determining...", "when (the stated condition or event) is detected", or "in response to detecting (the stated condition or event)".

[0092] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive), etc.

[0093] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. An automated testing system for digital phased array antennas, used to test the antenna under test, characterized in that, Includes a host computer, real-time controller, vector network analyzer, digital-to-analog converter card, beam control computer, switch matrix, and test transceiver module; The host computer is connected to the real-time controller and sends a pre-programmed sequence of test instructions to the real-time controller; The real-time controller is connected to the vector network analyzer and sends analog signal codes to the vector network analyzer; it is also connected to the wave control computer and sends wave position codes to the wave control computer; and it is connected to the switch matrix and sends switch codes to the switch matrix. The vector network analyzer is connected to the antenna under test via the digital-to-analog converter card, and is also connected to the test transceiver module deployed in the test space. The vector network analyzer sends source signals to the antenna under test or the test transceiver module and receives echo signals. The beam control computer is connected to the antenna under test and controls the beam state of the antenna under test. The switch matrix has a switch for each channel under test of the antenna under test, and the switch controls the opening or closing of the channel under test. The real-time controller includes a logic control area and a buffer area. The logic control area imports a pre-programmed test instruction sequence sent by the host computer to the real-time controller. The buffer area stores the source signal and echo signal data emitted by the vector network analyzer. The host computer periodically retrieves the source signal and echo signal data from the buffer area. The switching matrix includes a time-division multiplexing controller, which is connected to a vector network analyzer.

2. The automated testing system for digital phased array antennas according to claim 1, characterized in that, The test transceiver module includes a test probe and a horn antenna.

3. An automated testing method for digital phased array antennas, employing the testing system described in any one of claims 1 to 2, characterized in that, Includes the following steps: The host computer sends a pre-programmed sequence of test instructions to the real-time controller; According to the test command sequence, the real-time controller sends control codes to the wave control computer, the switch matrix, and the vector network analyzer unit by unit, based on the test set of the test command sequence. The control codes include wave position codes sent to the wave control computer, switch codes sent to the switch matrix, and analog signal codes sent to the vector network analyzer. The wave-controlled computer adjusts the parameters of the channel under test according to the wave position code; The switch matrix turns on the switch according to the switch code, thus activating the corresponding channel under test. The vector network analyzer sends source signals to the antenna under test or the transceiver module based on analog signal codes, and then receives the echo signals. The vector network analyzer imports the echo signal and the corresponding source signal into the buffer of the real-time controller, and then sends a test set completion signal to the real-time controller. After the real-time controller receives the test set completion signal, it sends control codes to the next test set as the object; until the entire test instruction sequence is completed. The host computer periodically retrieves source and echo signal data from the buffer.

4. The automated testing method for a digital phased array antenna according to claim 3, characterized in that, For any one of the test sets, it is divided into several time slices by the time division multiplexing controller of the switching matrix. The number of time slices corresponds to the number of channels under test corresponding to the synthesized beam in the test set, or to the number of channels under test corresponding to the received beam.

5. The automated testing method for a digital phased array antenna according to claim 4, characterized in that, The control of the switching matrix and vector network analyzer using a time-division multiplexing controller specifically includes: The switch matrix selects the range of the channel to be tested based on the switch code; The vector network analyzer sends source signals to the antenna under test or the transceiver module under test based on the analog signal code. The switch matrix sequentially turns on the corresponding test channel of the current time slice within the selected range through the time division multiplexing controller, and turns off the switches of other test channels until the opening and closing of the test channels corresponding to all time slices of the current test set are completed. The vector network analyzer uses the timestamps of each time slice of the time-division multiplexing controller as tags to receive the echo signals corresponding to each channel under test one by one.

6. The automated testing method for a digital phased array antenna according to claim 3, characterized in that, For any channel under test in any test set, the vector network analyzer sequentially sends source signals with different source frequencies and source powers according to the analog signal code, then receives the corresponding echo signals, and imports the echo signals and corresponding source signals into the buffer of the real-time controller; after completing the transmission of all source signals and the reception of echo signals in the current test set, the vector network analyzer sends a test set completion signal to the real-time controller.

7. The automated testing method for a digital phased array antenna according to claim 6, characterized in that, For the vector network analyzer to send source signals of different frequencies and powers, a delay protection time is provided between the switching of any source signal to allow the antenna under test to respond.

8. A computer program product, characterized in that, The computer program product includes a computer program or instructions that enable the computer program or instructions to perform the steps in the automated testing method for digital phased array antennas according to any one of claims 3 to 7.

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