Tracking voltage reference for single-ended receiver

Abstract

A receiver includes an input node coupled to receive an analog signal, a first switch coupled between the input node and a first node, a second switch coupled between the input node and a second node, a first resistive element coupled between the first node and a reference node, a second resistive element coupled between the second node and the reference node, a first capacitive element coupled to the first node, and a second capacitive element coupled to the second node. The receiver further includes a comparator having a first input coupled to the input node to receive the analog signal, and a second input coupled to the reference node to receive a reference voltage, wherein an output of the comparator controls the first and second switches.

Description

Technical Field

[0001] This disclosure generally relates to integrated circuit devices, and more specifically, to a tracking voltage reference for a single-ended receiver. Background Technology

[0002] In a typical single-ended AC-coupled communication receiver, circuitry is used at the receiver to set the termination voltage, and a DC level is replicated and used as a reference voltage for the comparator. However, if the start or end of data transmission differs from the line's DC balance, the termination voltage, and therefore the reference voltage, will not be centered on the input signal until the line reaches its DC balance point or steady state. In some communication protocols (e.g., common-mode eARC communication channels), the time required for the line to stabilize extends far beyond the specified start-up window.

[0003] Typical circuitry for extracting switching signals from DC components uses RC filters. However, due to switching, there is a direct trade-off between startup time and ripple. The faster the startup time, the higher the ripple that is directly shifted to higher receiver jitter. The filter also requires a representative density of positive and negative pulses to accurately represent the average value. Summary of the Invention

[0004] According to one embodiment, a receiver includes:

[0005] An input node, which is coupled to receive analog signals;

[0006] A first switch is coupled between the input node and the first node;

[0007] A second switch is coupled between the input node and the second node;

[0008] A first resistive element is coupled between the first node and the reference node;

[0009] A second resistive element is coupled between the second node and the reference node;

[0010] A first capacitive element, the first capacitive element being coupled to the first node;

[0011] A second capacitive element, the second capacitive element being coupled to the second node; and

[0012] A comparator having a first input coupled to the input node to receive the analog signal and a second input coupled to the reference node to receive a reference voltage, wherein the output of the comparator controls the first and second switches.

[0013] In one or more embodiments, the receiver further includes a third capacitive element coupled to the reference node.

[0014] In one or more embodiments, the first switch is configured to conduct electricity between the input node and the first node when the output of the comparator has a first logic state, and not conduct electricity between the input node and the first node when the output of the comparator has a second logic state different from the first logic state.

[0015] In one or more embodiments, the second switch is configured to conduct electricity between the input node and the first node when the output of the comparator has the second logic state, and not conduct electricity between the input node and the first node when the output of the comparator has the first logic state.

[0016] In one or more embodiments, the output of the comparator controls the opening and closing of the first switch, and the inversion of the output of the comparator controls the opening and closing of the second switch.

[0017] In one or more embodiments,

[0018] When the output of the comparator has a first logic state, the first switch is closed; and when the output of the comparator has a second logic state opposite to the first logic state, the first switch is opened; and

[0019] When the inverted output of the comparator has the first logic state, the second switch is closed, and when the inverted output of the comparator has the second logic state, the second switch is opened.

[0020] In one or more embodiments, the receiver further includes:

[0021] An inverter having an input configured to receive the output of the comparator, and an output configured to provide the inverted output of the comparator.

[0022] In one or more embodiments, the first resistive element and the second resistive element have matching resistors, and the first capacitive element and the second capacitive element have matching capacitors.

[0023] In one or more embodiments, the first switch includes a first transistor having a first current electrode coupled to the input node, a second current electrode coupled to the first node, and a control electrode coupled to the output of the comparator, and the second switch includes a second transistor having a first current electrode coupled to the input node, a second current electrode coupled to the second node, and a control electrode coupled to receive the inverted output of the comparator.

[0024] In one or more embodiments, the receiver further includes:

[0025] An inverter having an input configured to receive the output of the comparator and an inverted output configured to provide the output of the comparator, wherein the control electrode of the second transistor is coupled to the output of the inverter.

[0026] According to another embodiment, a receiver includes:

[0027] An input node, which is coupled to receive analog signals;

[0028] A first switch, the first switch having a control terminal, a first data terminal coupled to the input node, and a second data terminal coupled to the first node;

[0029] The second switch has a control terminal, a first data terminal coupled to the input node, and a second data terminal coupled to the second node;

[0030] A first resistive element is coupled between the first node and the reference node;

[0031] A second resistive element is coupled between the second node and the reference node;

[0032] A first capacitive element, the first capacitive element being coupled to the first node;

[0033] A second capacitive element, the second capacitive element being coupled to the second node;

[0034] A third capacitive element, the third capacitive element being coupled to the reference node; and

[0035] A comparator having a first input coupled to the input node to receive the analog signal and a second input coupled to the reference node to receive a reference voltage, wherein the output of the comparator is coupled to the control terminal of the first switch, and the output of the comparator is inversely coupled to the control terminal of the second switch.

[0036] In one or more embodiments,

[0037] The first switch includes a first transistor, wherein a first current electrode of the first transistor represents the first data terminal of the first switch, a second current electrode of the first transistor represents the second data terminal of the first switch, and a control electrode of the first transistor represents the control terminal of the first switch; and

[0038] The second switch includes a second transistor, wherein a first current electrode of the second transistor is characterized as the first data terminal of the second switch, a second current electrode of the second transistor is characterized as the second data terminal of the second switch, and a control electrode of the second transistor is characterized as the control terminal of the second switch.

[0039] In one or more embodiments, the first input of the comparator is the inverted input of the comparator, and the second input of the comparator is the non-inverted input of the comparator.

[0040] In one or more embodiments, the receiver further includes:

[0041] An inverter, the inverter having an input coupled to the output of the comparator,

[0042] And the inverted output coupled to provide the output of the comparator.

[0043] In one or more embodiments, the first and second resistive elements each have the same resistance value, and the first and second capacitive elements each have the same capacitance value.

[0044] According to another embodiment, a method in a receiver includes:

[0045] Receive analog input signals;

[0046] The voltage of the analog input signal is compared with the tracking reference voltage generated at the reference node;

[0047] When the voltage of the analog input signal is less than the tracking reference voltage, the input analog signal is provided to the first input of a first resistive-capacitive (RC) circuit, such that the first node of the first RC circuit tracks the analog input signal, wherein the first output of the first RC circuit is coupled to the reference node; and

[0048] When the voltage of the analog input signal is greater than the tracking reference voltage, the analog input signal is provided to the second input node of the second RC circuit, such that the second input tracks the analog input signal, wherein the second output of the second RC circuit is coupled to the reference node.

[0049] In one or more embodiments,

[0050] When the voltage of the analog input signal is less than the tracking reference voltage:

[0051] The first RC circuit includes a first resistor corresponding to a closed first switch coupled to transmit the analog input signal to the first node, and a first capacitive element coupled between the first node and ground.

[0052] The second node is coupled to the third RC circuit; and

[0053] When the voltage of the analog input signal is greater than the tracking reference voltage:

[0054] The second RC circuit includes a second resistor corresponding to a second closed switch coupled to transmit the analog input signal to the second node, and a second capacitive element coupled between the second node and ground.

[0055] The first node is coupled to the fourth RC circuit.

[0056] In one or more embodiments,

[0057] When the voltage of the analog input signal is less than the tracking reference voltage: the first node is in the tracking phase, and the second node is in the relaxation phase;

[0058] When the voltage of the analog input signal is greater than the tracking reference voltage: the first node is in the relaxation phase, and the second node is in the tracking phase; and

[0059] The tracking reference voltage tracks the average value between the voltage at the first node and the voltage at the second node.

[0060] In one or more embodiments,

[0061] The third RC circuit includes a third resistor coupled between the second node and the reference node, and a third capacitive element coupled between the reference node and ground; and

[0062] The fourth RC circuit includes a fourth resistor coupled between the first node and the reference node, and the third capacitive element.

[0063] In one or more embodiments, the first and second capacitive elements have matching capacitances, and the third and fourth resistors have matching resistances. Attached Figure Description

[0064] This disclosure is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. The elements in the drawings are shown for simplicity and clarity, and these elements are not necessarily drawn to scale.

[0065] Figure 1 A schematic diagram of an integrated circuit device for a communication receiver having a fast-start tracking voltage reference, according to a selected embodiment of the present invention, is shown.

[0066] Figure 2 Show Figure 1 Examples of voltage versus time graphs for various signals shown in a communication receiver. Detailed Implementation

[0067] Embodiments of a communication receiver and methods for operating the communication receiver are provided, wherein the embodiments and methods detect peak high and low pulses and average the peak detection values ​​to generate a reference voltage for a comparator. The comparator generates an output that recovers logic levels. Embodiments of the invention disclosed herein thus allow for a reasonable reference value with fewer input data values ​​than other known solutions. The averaging portion of the receiver also acts as a second RC filter controlling the relaxation of the peak detection circuitry, thereby generating lower ripple. The relaxation of the peak detection circuitry allows the reference point to track the DC component when the DC component is stable during operation of the communication receiver.

[0068] Figure 1A schematic diagram of a communication receiver 100 according to an embodiment of the present invention is shown. The communication receiver 100 includes a terminating resistive element 102, switches 104 and 106, average resistive elements 108 and 110, capacitive elements 112, 114, and 116, a comparator 118, and an inverter 120. An analog communication signal is coupled to an input to a first terminal of the terminating resistive element 102, a non-inverting input to the comparator 118, and an input to the first terminals of switches 104 and 106. The terminating resistive element 102 includes a second terminal coupled to ground or another suitable power supply voltage. Switch 104 includes a control terminal coupled to an OUT signal generated at the output of comparator 118. The OUT signal is also provided as an input to inverter 120. In addition to the first terminal coupled to the analog input signal, switch 104 also includes a second terminal coupled to the first terminal of capacitive element 112. The second terminal of capacitive element 112 is coupled to ground or another suitable power supply voltage. Switch 106 includes a control terminal coupled to a complementary signal (shown as OUTB) of the OUT signal, the control terminal being generated at the output of inverter 120. In addition to a first terminal coupled to the analog input signal, switch 106 also includes a second terminal coupled to the first terminal of capacitive element 114. The second terminal of capacitive element 114 is coupled to ground or another suitable power supply voltage. In some embodiments, resistive elements 108, 110 have matching resistors, and capacitive elements 112, 114 have matching capacitors.

[0069] Resistive element 108 includes a first terminal coupled between the second terminal of switch 104 and the first terminal of capacitive element 112. The conductor coupling the second terminal of switch 104, the first terminal of resistive element 108, and the first terminal of capacitive element 112 is referred to as Net A. The second terminal of resistive element 108 is coupled to the first terminal of resistive element 110. The second terminal of resistive element 110 is coupled between the second terminal of switch 106 and the first terminal of capacitive element 114. The second terminal of capacitive element 114 is coupled to ground or another suitable power supply voltage. The conductor coupling the second terminal of switch 106, the second terminal of resistive element 110, and the first terminal of capacitive element 114 is referred to as Net B.

[0070] In addition to the non-inverting input coupled to the analog input signal, comparator 118 also includes an inverting input coupled between the second terminal of resistive element 108 and the first terminal of resistive element 110.

[0071] The capacitive element 116 includes a first terminal coupled between the second terminal of the resistive element 108 and the first terminal of the resistive element 110, and an inverting input of the comparator 118. The second terminal of the capacitive element 116 is coupled to ground or other suitable power supply voltage.

[0072] Switches 104 and 106 are controlled by signals OUT and OUTB generated by comparator 118 and inverter 120, respectively. The analog input signal is a modulated and encoded binary data signal, which is appropriately AC-coupled to receiver 100 to facilitate data transmission and also isolates the DC level of the channel from the DC level of receiver 100. Switches 104 and 106 can be implemented using MOSFET transistors with resistances based on drain-source voltage and drain current. When switches 104 and 106 are implemented with transistors, each transistor has a current electrode coupled to the analog input signal and another current electrode coupled to either NET A or NET B, which provides the data signal to NET A and NET B. During operation, when the analog input signal is positive, the OUT signal is confirmed, switch 104 is closed, and switch 106 is opened. Net A tracks the peak value of the analog input signal, while Net B is in a relaxed phase. The resistors of switch 104 and capacitive element 112 are selected to provide the required response time for the VREF_TRACK signal supplied to the inverting input of comparator 118. Resistive elements 108 and 110, and capacitive elements 112 and 114, set the relaxation phase response characteristics after reaching the peak value. When the analog input signal is negative, the OUTB signal is confirmed, switch 106 is closed, and switch 104 is opened. Net B tracks the low peak value of the analog input signal, while Net A is in the relaxation phase. The resistors of switch 106 and capacitive element 114 are selected to provide the required response time for the VREF_TRACK signal supplied to the inverting input of comparator 118. Resistive elements 108 and 110, and capacitive elements 112 and 114, set the relaxation phase response characteristics after reaching the peak value of the OUTB signal. The VREF_TRACK signal is a weighted average of the positive and negative peak values ​​of the analog input signal, subject to the selected track and relaxation time constant, and allows for the recovery of the transmitted waveform.

[0073] refer to Figure 1 and Figure 2 , Figure 2 Showing the use of Figure 1Example of a voltage versus time graph for various signals of the communication receiver 100. Analog input signal 202 is a binary-coded analog input signal that may have an amplitude / logic level and DC offset that vary over time. For example only, analog input signal 202 has a 200mV swing with a starting voltage of 200mV set by a terminal. However, other suitable voltage levels and swing amplitudes of analog input signal 202 may be used. Analog input signal 202 is encoded such that logic high and logic low are relatively constant relative to the data switching rate, and thus remain at the upper and lower peaks over varying time intervals. At the start of the time series, at time T0, analog input signal 202, NET A signal, NET B signal, and VREF_TRACK signal are at the lower peak voltage for this example only, and do not necessarily start at this voltage. OUT signal 210 is de-acknowledged, and OUTB signal 212 is acknowledged. At time T1, analog input signal 202 changes from the lower peak voltage to the higher peak voltage. The OUT signal 210 is acknowledged, the OUTB signal 210 is deacknowledged, and the NET A signal 204 closely follows the analog input signal 202 to its upper peak, while the NET B signal 206 remains at or near the lower peak voltage. The NET A signal 204 has a very slight delay in reaching the upper peak voltage, as indicated by the small space between the NET A signal 204 and the analog input signal 202 at the upper leading edge of the pulse. The delay is determined by the time constant of the resistance of switch 104 and capacitive element 112. The VREF TRACK signal 208 begins to increase from the lower peak voltage at time T1 toward the midpoint between the upper and lower peak voltages, approximately 300 mV.

[0074] At time T2, the analog input signal 202 changes from an upper peak voltage to a lower peak voltage. The NET A signal 204 follows approximately the midpoint between the upper and lower peak voltages between times T2 and T3, for example, up to 300mV, and decays or relaxes to a slightly lower voltage, for example, up to 290mV. The amount of decay or relaxation is determined by the resistive element 108 and the capacitive element 112, as well as the delay in the non-ideal comparator 118. Before switch 104 is opened, NET A follows the analog input signal and a fast time constant set by the resistance of switch 104. After switch 104 is opened, the decay is subsequently determined by the resistive element 108 and the capacitive element 112. This allows us to understand the ability to adjust the waveform's response and variability based on component availability and selection. Figure 2Here is an example of the spectrum of the selectable response. The NET B signal 206 barely begins to increase between time T1 and time T2, and returns to a low peak voltage between time T2 and time T3. The VREF_TRACK signal 208 continues to increase from time T2 to T3 to a value between the upper and lower peak voltages.

[0075] At time T3, the analog input signal 202 changes from a lower peak voltage to an upper peak voltage. The NET A signal 204 again closely follows the analog input signal 202 to its upper peak, while the NET B signal 206 is at or near its lower peak voltage. The NET A signal 204 has a very slight delay in reaching its upper peak voltage, as indicated by the small space between the NET A signal 204 and the analog input signal 202 at the upper leading edge of the pulse. The VREF_TRACK signal 208 continues to increase from approximately 235mV to 265mV between times T3 and T4. The NET A signal 204 follows the analog input signal 202 between times T3 and T4 to a value less than the midpoint between the upper and lower peak voltages (e.g., 320mV) and slowly decays to a slightly lower voltage (e.g., 310mV). The NET B signal 206 increases slightly from its lower peak voltage between times T3 and T4. For example, during the relaxation phase based on resistive element 110 and capacitive element 114, the NET B signal 206 rises from 210mV to 220mV. The VREF_TRACK signal 208 continues to increase from time T3 to T4 to a value between the upper peak voltage and the lower peak voltage, for example, from approximately 240mV to 265mV.

[0076] Analog input signal 202 transitions from an upper peak voltage to a lower peak voltage at time T4. NET A signal 204 follows analog input signal 202 between times T4 and T5 to a point between the upper and lower peak voltages, for example, to 320mV, and decays or relaxes to a slightly lower voltage, for example, to 310mV. The amount of decay or relaxation is determined by resistive element 108 and capacitive element 112. NET B signal 206 decreases to the lower peak voltage at time T4 and remains at the lower peak voltage between times T4 and T5. VREF_TRACK signal 208 decreases slightly between times T4 and T5.

[0077] Analog input signal 202 transitions from a lower peak voltage to an upper peak voltage at time T5. NETA signal 204 follows analog input signal 202 to the upper peak voltage and slowly decays to a slightly lower voltage (e.g., from 330mV to 325mV) between times T6 and T7. NETB signal 206 increases from a lower peak voltage to an intermediate voltage at time T5, for example, 220mV at time T5. Between times T5 and T6, NETB signal 206 increases slightly during the relaxation phase between times T5 and T6. For example, during the relaxation phase based on resistive element 110 and capacitive element 114, NETB signal 206 rises from 220mV to 230mV. VREF_TRACK signal 208 continues to increase from time T5 to T6 to a value between the upper and lower peak voltages, for example, from approximately 260mV to 280mV.

[0078] For the remainder of the time, the analog input signal 202 continues to vary between the upper and lower peak voltages. As the analog input signal 202 increases toward the upper peak voltage, the NET A signal 204 follows the analog input signal 202 to the upper peak voltage, while the NET B signal 206 increases to above the lower peak voltage but below the midpoint of the VREF_TRACK signal 208. During the relaxation period, while the analog input signal 202 and the NET A signal 204 remain at the upper peak voltage, the NET B signal 206 increases slightly but remains well below the VREF_TRACK signal 208. As the analog input signal 202 transitions from the upper peak voltage to the lower peak voltage, the NET A signal 204 follows the analog input signal 202 to a midpoint below the upper peak voltage but above the VREF_TRACK signal 208, while the NET B signal 206 decreases with the analog input signal to the lower peak voltage. During the relaxation period, while analog input signal 202 and NET A signal 204 remain at the lower peak voltage, NET B signal 206 decreases slightly but remains well above VREF_TRACK signal 208. VREF_TRACK signal 208 increases moderately when analog input signal 202 and NET A signal 204 are at the upper peak voltage, and decreases by a similar amount when analog input signal 202 and NET B signal 206 are at the lower peak voltage. It should be noted that VREF_TRACK signal 208 achieves most of its stability over time T7.

[0079] The VREF_TRACK signal 202 gradually increases to an intermediate average value with a shallow sawtooth or ripple waveform as the receiver begins operation at time T1. After the first few cycles of the analog input signal 202, the VREF_TRACE signal 202 continues with a sawtooth or ripple pattern alternating between slightly above and below the average reference rail voltage. The upper and lower peak values ​​are shown as decreasing over time because the VREF_TRACK signal 202 has not yet been fed to its DC equilibrium point, which is determined by the swing and the initial or termination voltage. As an example, when the line reaches its DC equilibrium, with a termination voltage of 200mV and a swing amplitude of 200mV, the high level will stabilize at 300mV and the low level will stabilize at 100mV. The start-up time can be adjusted to meet specified requirements by adjusting the values ​​of the resistors of switches 104 and 106 and the capacitive elements 112 and 114. Furthermore, the amount of ripple can be controlled, thereby adjusting the values ​​of resistive elements 108, 110 and capacitive elements 112, 114, 116. Therefore, receiver 100 satisfies two competing requirements, possessing the ability to decouple peak tracking and relaxation phase to achieve fast startup time and low ripple. Due to the damping of the amount of ripple in the VREF_TRACK signal 208, receiver 100 can also achieve a greater noise margin for a specified startup time, since both the upper and lower peak voltages are used to generate the VREF_TRACK signal 208.

[0080] It should now be understood that in some embodiments, a receiver has been provided that may include an input node coupled to receive an analog signal, a first switch coupled between the input node and a first node (NET A), a second switch coupled between the input node and a second node (NET B), a first resistive element (108) coupled between the first node and a reference node, a second resistive element (110) coupled between the second node and the reference node, a first capacitive element (112) coupled to the first node, a second capacitive element (114) coupled to the second node, and a comparator having a first input (+) coupled to the input node to receive an analog signal and a second input (-) coupled to the reference node to receive a reference voltage, wherein the output of the comparator (OUT (which is also used to generate OUTB)) controls the first and second switches.

[0081] On the other hand, the receiver may additionally include a third capacitive element (C2) coupled to the reference node.

[0082] On the other hand, the first switch can be configured to conduct electricity between the input node and the first node when the output of the comparator has a first logic state, and not conduct electricity between the input node and the first node when the output of the comparator has a second logic state different from the first logic state.

[0083] On the other hand, the second switch is configured to conduct electricity between the input node and the first node when the output of the comparator has a second logic state, and not conduct electricity between the input node and the first node when the output of the comparator has a first logic state.

[0084] On the other hand, the comparator's output controls the opening and closing of the first switch, and the inverted output of the comparator controls the opening and closing of the second switch.

[0085] On the other hand, when the comparator output has a first logic state, the first switch is closed, and when the comparator output has a second logic state (opposite to the first logic state), the first switch is opened; and when the inverted output of the comparator has a first logic state, the second switch is closed, and when the inverted output of the comparator has a second logic state, the second switch is opened.

[0086] On the other hand, the receiver may additionally include an inverter having an input configured to receive the output of the comparator and an output configured to provide an inverted version of the comparator's output.

[0087] On the other hand, the first resistive element and the second resistive element have matching resistors, and the first capacitive element and the second capacitive element have matching capacitors.

[0088] On the other hand, the first switch may include a first transistor having a first current electrode coupled to an input node, a second current electrode coupled to a first node, and a control electrode coupled to the output of the comparator, and the second switch may include a second transistor having a first current electrode coupled to an input node, a second current electrode coupled to a second node, and a control electrode coupled to receive the inverted output of the comparator.

[0089] On the other hand, the receiver may additionally include an inverter having an input configured to receive the output of the comparator and an output configured to provide an inverted version of the comparator's output, wherein the control electrode of the second transistor is coupled to the output of the inverter.

[0090] In other embodiments, the receiver may include an input node coupled to receive an analog signal, and a first switch including a control terminal, a first data terminal coupled to the input node, and a second data terminal coupled to a first node (NET A). The second switch includes a control terminal, a first data terminal coupled to the input node, and a second data terminal coupled to a second node (NET B). A first resistive element may be coupled between the first node and a reference node. A second resistive element may be coupled between the second node and the reference node. A first capacitive element may be coupled to the first node. A second capacitive element may be coupled to the second node. A third capacitive element may be coupled to the reference node. The comparator includes a first input (+) coupled to the input node to receive an analog signal and a second input (-) coupled to the reference node to receive a reference voltage. The comparator's output (OUT) is coupled to the control terminal of the first switch, and the inverted output (OUTB) of the comparator is coupled to the control terminal of the second switch.

[0091] In another aspect, the first switch may include a first transistor, wherein a first current electrode of the first transistor represents a first data terminal of the first switch, a second current electrode of the first transistor represents a second data terminal of the first switch, and a control electrode of the first transistor represents a control terminal of the first switch. The second switch includes a second transistor, wherein a first current electrode of the second transistor represents a first data terminal of the second switch, a second current electrode of the second transistor represents a second data terminal of the second switch, and a control electrode of the second transistor represents a control terminal of the second switch.

[0092] On the other hand, the first input of the comparator is the inverting input of the comparator, and the second input of the comparator is the non-inverting input of the comparator.

[0093] On the other hand, the receiver may additionally include an inverter having an input coupled to the output of the comparator and an output coupled to provide the inverted output of the comparator.

[0094] On the other hand, the first and second resistive elements each have the same resistance value, and the first and second capacitive elements each have the same capacitance value.

[0095] In another embodiment, the method implemented using a receiver may include receiving an analog input signal and comparing the voltage of the analog input signal with a tracking reference voltage generated at a reference node. When the voltage of the analog input signal is less than the tracking reference voltage, the input analog signal may be provided to a first input of a first resistive-capacitive (RC) circuit (104, 112), such that a first node (NET A) of the first RC circuit tracks the analog input signal, wherein a first output of the first RC circuit is coupled to the reference node. When the voltage of the analog input signal is greater than the tracking reference voltage, the input analog signal may be provided to a second input node of a second RC circuit (106, 114), such that the second input tracks the analog input signal, wherein a second output of the second RC circuit is coupled to the reference node.

[0096] On the other hand, when the voltage of the analog input signal is less than the tracking reference voltage, the first RC circuit includes a first resistor corresponding to a closed first switch (104) coupled to transmit the analog input signal to the first node (NET A), and a first capacitive element (112) coupled between the first node and ground. The second node is coupled to a third RC circuit (110 / 116). When the voltage of the analog input signal is greater than the tracking reference voltage, the second RC circuit includes a second resistor corresponding to a second closed switch (106) coupled to transmit the analog input signal to the second node (NET B), and a second capacitive element (114) coupled between the second node and ground, and the first node is coupled to a fourth RC circuit (108 / 116).

[0097] On the other hand, when the voltage of the analog input signal is less than the tracking reference voltage: the first node (NET A) is in the tracking phase, and the second node is in the relaxation phase. When the voltage of the analog input signal is greater than the tracking reference voltage: the first node (NET A) is in the relaxation phase, and the second node (NET B) is in the tracking phase. The tracking reference voltage tracks the average value between the voltage at the first node and the voltage at the second node.

[0098] On the other hand, the third RC circuit includes a third resistor (110) coupled between the second node (NET B) and the reference node, and a third capacitive element (116) coupled between the reference node and ground. The fourth RC circuit includes a fourth resistor (108) coupled between the first node (NET A) and the reference node, and a third capacitive element (116).

[0099] On the other hand, the first and second capacitive elements have matching capacitance, and the third and fourth resistors have matching resistance.

[0100] Since the devices implementing this disclosure are mostly composed of electronic components and circuits known to those skilled in the art, the circuit details will not be explained to any greater extent than deemed necessary as shown above, in order to understand and comprehend the basic concepts of this disclosure and to avoid confusion or deviation from its teachings.

[0101] Furthermore, the terms “front,” “rear,” “top,” “bottom,” “above,” “under,” and similar terms (if applicable) used in the specification and claims are for descriptive purposes and are not necessarily used to describe permanent relative positions. It should be understood that such terms are interchangeable where appropriate, so that embodiments of this disclosure described herein (e.g.) can operate in orientations other than those shown or otherwise described herein.

[0102] While this disclosure has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of this disclosure as set forth in the appended claims. Therefore, this specification and drawings should be viewed in an illustrative rather than restrictive sense, and all such modifications are contemplated to be included within the scope of this disclosure. It is not intended that any advantage, benefit, or solution to a problem described herein with reference to specific embodiments be construed as a critical, necessary, or essential feature or element of any or all claims.

[0103] As used in this article, the term “coupling” is not intended to be limited to direct coupling or mechanical coupling.

[0104] Furthermore, as used herein, the term "a" is defined as one or more. Moreover, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed as implying that another claim element introduced by the indefinite article "a" limits any particular claim containing this introduced claim element to a disclosure containing only one of that element, even when the same claim includes the introductory phrase "one or more" or "at least one" and indefinite articles such as "a" or "one". The same applies to the use of definite articles.

[0105] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by such terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority of these elements.

Claims

1. A receiver, characterized in that, include: An input node, which is coupled to receive analog signals; A first switch is coupled between the input node and the first node; A second switch is coupled between the input node and the second node; A first resistive element is coupled between the first node and the reference node; A second resistive element is coupled between the second node and the reference node; A first capacitive element, the first capacitive element being coupled to the first node; A second capacitive element, the second capacitive element being coupled to the second node; as well as A comparator having a first input coupled to the input node to receive the analog signal and a second input coupled to the reference node to receive a reference voltage, wherein the output of the comparator controls the first and second switches; The first switch includes a first transistor having a first current electrode coupled to the input node, a second current electrode coupled to the first node, and a control electrode coupled to the output of the comparator. The second switch includes a second transistor having a first current electrode coupled to the input node, a second current electrode coupled to the second node, and a control electrode coupled to receive the inverted output of the comparator.

2. The receiver according to claim 1, characterized in that, Additionally, a third capacitive element is coupled to the reference node.

3. A receiver, characterized in that, include: An input node, which is coupled to receive analog signals; A first switch, the first switch having a control terminal, a first data terminal coupled to the input node, and a second data terminal coupled to the first node; The second switch has a control terminal, a first data terminal coupled to the input node, and a second data terminal coupled to the second node; A first resistive element is coupled between the first node and the reference node; A second resistive element is coupled between the second node and the reference node; A first capacitive element, the first capacitive element being coupled to the first node; A second capacitive element, the second capacitive element being coupled to the second node; A third capacitive element, the third capacitive element being coupled to the reference node; as well as A comparator having a first input coupled to the input node to receive the analog signal and a second input coupled to the reference node to receive a reference voltage, wherein the output of the comparator is coupled to the control terminal of the first switch, and the output of the comparator is inversely coupled to the control terminal of the second switch; The first switch includes a first transistor, wherein a first current electrode of the first transistor is characterized as the first data terminal of the first switch, a second current electrode of the first transistor is characterized as the second data terminal of the first switch, and a control electrode of the first transistor is characterized as the control terminal of the first switch. as well as The second switch includes a second transistor, wherein a first current electrode of the second transistor is characterized as the first data terminal of the second switch, a second current electrode of the second transistor is characterized as the second data terminal of the second switch, and a control electrode of the second transistor is characterized as the control terminal of the second switch.

4. The receiver according to claim 3, characterized in that, The first and second resistive elements each have the same resistance value, and the first and second capacitive elements each have the same capacitance value.

5. A method in a receiver, characterized in that, include: Receive analog input signals; The comparator compares the voltage of the analog input signal with the tracking reference voltage at the input of the comparator's reference node; When the voltage of the analog input signal is less than the tracking reference voltage, the analog input signal is provided to a first node between the first resistor and the first capacitor in a first resistive-capacitive RC circuit including a first resistor and a first capacitive element, such that the first node of the first RC circuit tracks the analog input signal, wherein the first output of the first RC circuit is coupled to the reference node input of the comparator to provide the tracking reference voltage; as well as When the voltage of the analog input signal is greater than the tracking reference voltage, the analog input signal is provided to a second node between the second resistor and the second capacitive element of a second RC circuit, which includes a second resistor and a second capacitive element, such that the second node tracks the analog input signal, wherein the second output of the second RC circuit is coupled to the reference node input of the comparator to provide the tracking reference voltage.

6. The method according to claim 5, characterized in that: When the voltage of the analog input signal is less than the tracking reference voltage: The first RC circuit includes a first resistor corresponding to a closed first switch coupled to transmit the analog input signal to the first node, and a first capacitive element coupled between the first node and ground. The second node is coupled to the third RC circuit; as well as When the voltage of the analog input signal is greater than the tracking reference voltage: The second RC circuit includes a second resistor corresponding to a second closed switch coupled to transmit the analog input signal to the second node, and a second capacitive element coupled between the second node and ground. The first node is coupled to the fourth RC circuit.

7. The method according to claim 6, characterized in that: When the voltage of the analog input signal is less than the tracking reference voltage: the first node is in the tracking phase, and the second node is in the relaxation phase; When the voltage of the analog input signal is greater than the tracking reference voltage: the first node is in the relaxation phase, and the second node is in the tracking phase; as well as The tracking reference voltage tracks the average value between the voltage at the first node and the voltage at the second node.

8. The method according to claim 6, characterized in that: The third RC circuit includes a third resistor coupled between the second node and the reference node input of the comparator, and a third capacitive element coupled between the reference node and ground; as well as The fourth RC circuit includes a fourth resistor coupled between the first node and the reference node input of the comparator, and the third capacitive element.

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