Methods, devices, systems and equipment for synchronizing feature information of power communication signal frames

Abstract

This invention discloses a method, apparatus, system, and device for synchronizing feature information of power communication signal frames, belonging to the field of communication technology. The method includes: responding to a frame synchronization start signal of the current signal frame, triggering the calculation of corresponding feature information, and writing the feature information into a baseband buffer; after frame synchronization is completed, moving the feature information from the baseband buffer to a shadow register for subsequent reading by the processing module; while the data of the current signal frame stored in the memory module has not yet been read by the processing module, if a frame synchronization completion signal of the next signal frame is detected, updating the feature information stored in the shadow register according to a synchronization strategy. This invention effectively improves the accuracy of feature information synchronization and system stability by introducing a shadow register and combining it with a feature information retention mechanism based on a synchronization strategy.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and in particular relates to a method, apparatus, system and device for synchronizing feature information of power communication signal frames. Background Technology

[0002] In high-speed power line communication (HPLC) systems, signal receiving equipment typically needs to calculate and store channel characteristic information corresponding to received frames, such as channel estimation (CE), received signal strength indicator (RSSI), and signal-to-noise ratio (SNR). This characteristic information is usually used to support application development in upper-layer software, such as protocol parsing, link evaluation, and network management. Therefore, ensuring the accurate matching and reliable storage of this type of information is one of the key issues in system design.

[0003] However, there is some uncertainty between the storage of feature information and its retrieval by software, specifically in the following two aspects:

[0004] (1) When the receiving device is receiving a certain signal frame (such as the frame control field FC or physical layer load PL), if the software synchronization mechanism is not rigorous, it may read channel feature information that is not the current frame, causing misalignment between application layer data and channel information;

[0005] (2) Since the calculation and updating of feature information is usually carried out in parallel with data reception, if the write control or latch strategy is not designed properly, it may lead to inconsistency between channel feature information and actual received frames, which may further cause misjudgment of protocol stack or abnormal state management.

[0006] Therefore, there is an urgent need for a reliable latching and access mechanism for feature information to ensure that the channel state information acquired by the processor at any time is consistent with the current processing context, so as to improve system stability and protocol robustness. Summary of the Invention

[0007] This invention aims to at least solve one of the technical problems existing in related technologies. To this end, this invention proposes a method, apparatus, system, and device for synchronizing feature information of power communication signal frames, so as to improve the accuracy of feature information synchronization and system stability.

[0008] In a first aspect, the present invention provides a method for synchronizing feature information of power communication signal frames, the method comprising:

[0009] In response to the frame synchronization start signal of the current signal frame, the corresponding feature information is calculated and written into the baseband buffer;

[0010] After frame synchronization is completed, the feature information is moved from the baseband buffer to the shadow register for subsequent reading by the processing module;

[0011] If the frame synchronization completion signal of the next signal frame is detected while the data stored in the memory module of the current signal frame has not yet been read by the processing module, the feature information stored in the shadow register is updated according to the synchronization strategy.

[0012] The feature information synchronization method for power communication signal frames provided by this invention introduces a shadow register and a synchronization strategy during the frame synchronization stage to achieve stable latching and intelligent updating of feature information, thereby improving the robustness of continuous frame reception and the reliability of feature synchronization in power communication systems.

[0013] In a second aspect, the present invention provides a feature information synchronization device for power communication signal frames, the device comprising:

[0014] The calculation module is used to respond to the frame synchronization start signal of the current signal frame, trigger the calculation of the corresponding feature information, and write the feature information into the baseband buffer;

[0015] The moving module is used to move the feature information from the baseband buffer to the shadow register after frame synchronization is completed, so that the processing module can read it later.

[0016] The synchronization module is used to update the feature information stored in the shadow register according to the synchronization strategy if the frame synchronization completion signal of the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module.

[0017] Thirdly, the present invention provides a power communication system, the system comprising:

[0018] Signal transmitting equipment for transmitting power communication signals containing continuous signal frames;

[0019] A signal receiving device is configured to receive the power communication signal and execute the feature information synchronization method for the power communication signal frame as described in the first aspect.

[0020] Fourthly, the present invention provides a signal receiving device, including a baseband and a central processing unit, wherein the baseband is configured with a shadow register; wherein:

[0021] The baseband is used to respond to the frame synchronization start signal of the current signal frame, trigger the calculation of the corresponding feature information, and write the feature information into the baseband buffer; after frame synchronization is completed, the feature information is moved from the baseband buffer to the shadow register for subsequent reading by the central processing unit.

[0022] The baseband is also used to update the feature information stored in the shadow register according to the synchronization strategy if a frame synchronization completion signal of the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module.

[0023] The central processing unit is used to read feature information from the shadow register for upper-layer application processing.

[0024] Fifthly, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the feature information synchronization method for power communication signal frames as described in the first aspect above.

[0025] In a sixth aspect, the present invention provides a chip including a processor and a communication interface, the communication interface being coupled to the processor, the processor being used to run computer programs or instructions to implement the feature information synchronization method for power communication signal frames as described in the first aspect above.

[0026] In a seventh aspect, the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the method for synchronizing feature information of power communication signal frames as described in the first aspect above.

[0027] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments with reference to the accompanying drawings, in which:

[0029] Figure 1 This is a schematic diagram illustrating an application scenario of the feature information synchronization method for power communication signal frames provided in some embodiments of the present invention;

[0030] Figure 2 This is a schematic diagram of the power line carrier communication signal processing procedure provided in some embodiments of the present invention;

[0031] Figure 3 This is a schematic diagram of the feature information synchronization process provided in some embodiments of the present invention;

[0032] Figure 4This is a signal diagram illustrating the feature information synchronization process provided in some embodiments of the present invention;

[0033] Figure 5 This is a flowchart illustrating a method for synchronizing feature information of power communication signal frames provided in some embodiments of the present invention;

[0034] Figure 6 This is a schematic diagram illustrating the underlying data interaction principle provided in some embodiments of the present invention;

[0035] Figure 7 This is a schematic diagram of the signal under normal conditions provided in some embodiments of the present invention;

[0036] Figure 8 This is a schematic diagram of the signal under delay conditions provided in some embodiments of the present invention;

[0037] Figure 9 This is a signal schematic diagram of a frame collision handling strategy provided in some embodiments of the present invention;

[0038] Figure 10 This is a signal schematic diagram of another frame collision handling strategy provided in some embodiments of the present invention;

[0039] Figure 11 This is a signal diagram illustrating the feature information synchronization process provided in some embodiments of the present invention;

[0040] Figure 12 This is a schematic diagram of the structure of a feature information synchronization device for power communication signal frames provided in some embodiments of the present invention;

[0041] Figure 13 This is a schematic diagram of the structure of a signal receiving device provided in some embodiments of the present invention. Detailed Implementation

[0042] The technical solutions of the embodiments of the present invention will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the scope of protection of the present invention.

[0043] Unless otherwise defined, all technical and scientific terms used in this invention have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains; the terminology used in the specification of this application is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order or hierarchy.

[0044] In this invention, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0045] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "attachment" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0046] In this invention, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, in this invention, the character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0047] In this invention, "multiple" refers to two or more (including two), similarly, "multiple groups" refers to two or more (including two groups), and "multiple pieces" refers to two or more (including two pieces).

[0048] The following description, in conjunction with the accompanying drawings, details the method for synchronizing the feature information of power communication signal frames provided by the present invention through specific embodiments and application scenarios.

[0049] Figure 1 This is a schematic diagram illustrating an application scenario of the feature information synchronization method for power communication signal frames provided in some embodiments of the present invention. The feature information synchronization method for power communication signal frames provided in the embodiments of the present invention can be applied to, for example... Figure 1The diagram illustrates an application environment for a power communication system. This system includes signal transmitting equipment and signal receiving equipment. The signal transmitting equipment transmits power communication signals, which may consist of continuous signal frames. The signal receiving equipment receives these power communication signals and performs subsequent processing, such as channel estimation.

[0050] The signal transmitting and receiving devices can be, for example, computer devices, such as power line communication terminals, concentrator devices, smart meters, communication module embedded devices, or communication test terminals. Alternatively, the computer devices can also be devices with computing capabilities or intelligent robots, used to perform signal reception, processing, and subsequent possible processing tasks in this invention.

[0051] Based on the above application scenarios, this invention can be applied to power line carrier communication signal processing scenarios. Figure 2 This is a schematic diagram of the power line carrier communication signal processing procedure provided in some embodiments of the present invention. For example... Figure 2 As illustrated, exemplarily, the transmitting end (i.e., the signal transmitting device) encodes the frame control data and payload data accordingly, then adds a preamble to the frame signal through Inverse Fast Fourier Transform (IFFT) and cyclic prefix sum windowing, and transmits it to the power line channel through an analog front-end. The receiving end (i.e., the signal receiving device) receives the signal through the analog front-end and completes initial signal alignment through automatic gain control in conjunction with a clock mechanism or frame synchronization mechanism. Subsequently, the receiving end converts the signal to the frequency domain through a Fast Fourier Transform (FFT) module, and then completes symbol restoration through demodulation. The demodulated frame control data and payload data are then decoded accordingly to finally restore the frame control data and data payload. All of the above processes are completed within the baseband of the receiving end. In addition, the receiving end also uses a buffering mechanism to temporarily store relevant frame data of the current signal frame to ensure that data consistency and system stability can be maintained even when multiple frames arrive consecutively.

[0052] Figure 3 This is a schematic diagram illustrating the feature information synchronization process provided in some embodiments of the present invention. For example... Figure 3As shown, after receiving frame data (including preamble, frame control data, and data payload), the baseband module first completes the reception and field parsing of the frame data. During the period from frame synchronization start (sync-begin) to frame synchronization completion (frame-synced), it extracts corresponding feature information, such as channel estimation, received signal strength indication, and signal-to-noise ratio, and writes it into the baseband buffer. Simultaneously, the frame control data and data payload frame data are transferred to the memory module for writing into system memory. For example, the baseband module first performs synchronization detection on the received signal. When three synchronization peaks are detected consecutively, the baseband module generates a sync-begin signal to mark the start of the current frame synchronization process. After the frame synchronization process ends, the baseband module generates a frame-synced signal to indicate the completion of frame synchronization.

[0053] Subsequently, the baseband module sets the receive completion signal (rx-end-flag), transitioning from a low level to a high level, to indicate that the reception and transmission of the current frame data has been completed. Upon detecting this high-level flag, the processing module (i.e., the CPU) begins reading the corresponding frame data from system memory and simultaneously retrieves feature information from the baseband buffer for upper-layer applications to perform network analysis, link evaluation, and other operations. This mechanism ensures the temporal and structural consistency between frame data and feature information, and achieves data synchronization and release control between the baseband and CPU through the receive completion signal, contributing to improved accuracy of upper-layer service processing and overall stability of the communication system.

[0054] During the continuous reception of multiple frames, the baseband module continuously updates the feature information in the baseband buffer, triggered by the frame synchronization start signal. For example, when the baseband module completes feature extraction between sync-begin and frame-synced during the reception of frame 1, the corresponding feature information for frame 1 is written into the buffer. When the baseband module starts receiving frame 2 and detects the sync-begin signal for frame 2, the baseband buffer will begin updating the feature information corresponding to frame 2. Thus, the contents of the baseband buffer are dynamically refreshed as each frame synchronization progresses, achieving real-time maintenance of the feature data of the currently valid frames.

[0055] Figure 4 This is a signal diagram illustrating the feature information synchronization process provided in some embodiments of the present invention. For example... Figure 4As shown, at time t0, the baseband module begins frame synchronization processing for frame 1. Between the sync-begin and frame-synced states of frame 1 (i.e., time t0 to t0'), it calculates the feature information of frame 1 and writes it into the baseband buffer. Subsequently, at time t1, the data for frame 1 is written to system memory, and the baseband module sets the receive completion signal (rx-end-flag) to notify the processing module (such as the CPU) that the current frame data reception is complete. Ideally, the CPU should respond to the receive completion signal promptly at time t2 and complete the synchronous extraction of the frame 1 data from system memory and the frame 1 feature information from the baseband buffer, thus ensuring a one-to-one correspondence between frame data and feature information. However, in some scenarios, due to delays in CPU or upper-layer software processing, the data extraction operation may not be completed until time t2'. Simultaneously, if the baseband module has already started receiving frame 2 and detects the sync-begin signal of frame 2 at time T1, the frame 1 feature information originally stored in the baseband buffer will be overwritten by the new feature information of frame 2.

[0056] At this point, even if the frame data extracted by the CPU is the complete content of frame 1, its corresponding feature information has already been updated to the content of frame 2, resulting in a mismatch between the frame data and the feature information. If the application processing stage relies on this feature information (e.g., for network topology selection based on signal-to-noise ratio), it may lead to subsequent decision-making errors.

[0057] This shows that the relevant technologies cannot guarantee the correct binding of frame data and feature information, and data mismatch is especially likely to occur in high-concurrency scenarios.

[0058] Therefore, this invention provides a method for synchronizing feature information of power communication signal frames. It introduces a shadow register latching mechanism, uses a shadow register to temporarily store the feature information of the signal frame, and determines whether to retain the current frame or update it to the information of the next frame according to the synchronization strategy before receiving the next signal frame. This realizes feature information protection and switching control between multiple frames, thereby further improving the integrity and synchronization reliability of the feature information of the signal frame.

[0059] The feature information synchronization method for power communication signal frames provided in this embodiment of the invention can be executed by a signal receiving device or a functional module or entity in the signal receiving device that can implement the feature information synchronization method for power communication signal frames, such as a baseband module.

[0060] The following describes the method for synchronizing the feature information of power communication signal frames provided in this embodiment of the invention, using a signal receiving device as the execution subject as an example.

[0061] The signal receiving device includes a baseband module, a memory module, and a processing module. The baseband module is responsible for demodulating and performing preliminary processing of the signal frames, while the memory module is used to store the received signal frame data.

[0062] For example, a baseband module refers to a hardware or hardware / software combination unit used to perform low-level communication operations such as wireless signal demodulation, channel estimation, field identification, and physical layer processing. For instance, a baseband module can be a hardware processing unit composed of FPGA (Field Programmable Gate Array), DSP (Digital Signal Processor), or ASIC (Application Specific Integrated Circuit).

[0063] A memory module refers to a system storage resource used to store complete signal frame data transmitted by the baseband module. It can be on-chip RAM (Random Access Memory), DDR (Double Data Rate) memory, or an embedded cache module.

[0064] The processing module can include an embedded processor (such as an ARM (Advanced RISC Machines) core), an MCU (Microcontroller Unit), or a main control CPU (Central Processing Unit) that runs in conjunction with an operating system. It is used to read frame data from the memory module and combine it with feature information to complete further upper-level business processing, conflict decision-making, control signal issuance, and flag signal clearing operations.

[0065] Figure 5 This is a flowchart illustrating a method for synchronizing feature information of power communication signal frames according to some embodiments of the present invention. For example... Figure 5 As shown, the method for synchronizing the feature information of the power communication signal frame includes steps 510 to 530.

[0066] Step 510: In response to the frame synchronization start signal of the current signal frame, trigger the calculation of the corresponding feature information and write the feature information into the baseband buffer.

[0067] The feature information refers to the data extracted from the received signal frame that characterizes the frame’s features, including but not limited to one or more of the following: Channel Estimation (CE), Signal-to-Noise Ratio (SNR), Received Signal Strength Indicator (RSSI).

[0068] Upon detecting the sync-begin signal of the current signal frame, the baseband module enters the feature extraction process. During this process, the baseband module performs frequency domain transformation or matched filtering on the received data of the current signal frame based on the synchronization sequence SYNCP (Synchronization Pattern), pilot symbols, or a predefined set of reference symbols to extract one or more feature information. This information is then written into the baseband module's internal buffer for use in subsequent transfer operations.

[0069] Step 520: After frame synchronization is completed, the feature information is moved from the baseband buffer to the shadow register for subsequent reading by the processing module.

[0070] After the current signal frame completes frame synchronization, the baseband module detects the frame-synced signal of the current signal frame. Then, the baseband module moves the feature information plate corresponding to the current signal frame in the baseband buffer to the shadow register.

[0071] This shadow register, as a dedicated register area for feature reading, has a write protection mechanism to prevent it from being overwritten by subsequent frame information during CPU reading, thereby ensuring the integrity and consistency of the read data.

[0072] In some embodiments, the baseband module determines that the feature information corresponding to the signal frame is complete and available, and thus triggers a transfer operation.

[0073] The relocation operation can trigger the shadow register in the baseband to write the frame feature information of the current signal frame, ensuring that the feature information is locked in the corresponding shadow register for subsequent processing modules (such as the CPU) to read, process or report.

[0074] Step 530: If a frame synchronization completion signal for the next signal frame is detected while the data stored in the memory module for the current signal frame has not yet been read by the processing module, the feature information stored in the shadow register is updated according to the synchronization strategy.

[0075] Assume the baseband module is processing frame 1. At this point, the data of frame 1 has been successfully transmitted to the system memory, and the relevant frame feature information (such as channel estimation SNR, received signal strength RSSI, etc.) has been stored. The baseband module writes this feature information into the shadow register and completes the relevant flag settings, indicating that the frame data is ready for processing.

[0076] If, during this period, the CPU has not yet read the data for frame 1 (for example, the CPU may be processing other tasks), and the baseband module receives the frame synchronization completion signal for the next frame (i.e., frame 2), indicating that the synchronization process for frame 2 has been completed, the baseband module makes a decision based on a preset synchronization strategy, including:

[0077] One synchronization strategy is to retain the feature information of the current frame 1. That is, if the strategy decides to continue to prioritize the processing of frame 1, the shadow register will not update the latched feature information until the CPU finishes reading frame 1 and clears its flag.

[0078] Another synchronization strategy is to update the shadow register. That is, if the strategy decides to discard the feature information of frame 1, the baseband module will trigger an update based on the sync-begin signal. The shadow register will then be written with the feature information of frame 2, overwriting the original feature data of frame 1. At this point, the data in the shadow register corresponds to the feature information of frame 2, while the feature information of frame 1 is discarded.

[0079] The above synchronization strategy ensures that the feature information acquired by the CPU at any given time matches the signal frame being processed, thereby improving the accuracy of feature information synchronization and system stability.

[0080] The feature information synchronization method for power communication signal frames provided in this invention improves the real-time performance and synchronization of feature information extraction by triggering feature information calculation after detecting a frame synchronization signal. After frame synchronization is completed, the feature information is moved from the baseband buffer to the shadow register for subsequent reading by the processing module. The shadow register is introduced as a stable latching structure, and the calculated feature information is moved from the easily overwritten buffer area to the latching unit, effectively improving the accessibility and stability of the feature information. This allows the subsequent processing module to read the information safely at an appropriate time, improving the system's access robustness and anti-interference capability. If the frame synchronization completion signal of the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module, the feature information stored in the shadow register is updated according to the synchronization strategy. By introducing a synchronization strategy judgment mechanism, the system can intelligently judge and filter the feature information that should be retained in scenarios with dense reception of continuous signal frames, effectively alleviating the feature data overlay conflict caused by lagging processing resources or excessively high reception frequency, thereby improving the timeliness of feature information and the stable reception capability of the communication system.

[0081] In related technologies, baseband modules typically only have a general buffer area (such as a frame buffer register) for temporarily storing feature information, lacking a shadow register structure with independent latching and management capabilities. When consecutive signal frames arrive rapidly, if the previous frame is not processed by the CPU in time, the feature information of the subsequent frame often directly overwrites the feature information of the previous frame that has not yet been read by the processing module, causing data to be discarded prematurely, which seriously affects the accuracy of frame processing and the stability of the system.

[0082] Therefore, in some embodiments, the feature information stored in the shadow register is determined to be updated according to the synchronization strategy, including: the shadow register latches the feature information corresponding to the current signal frame; or, the shadow register updates the feature information corresponding to the current signal frame to the feature information corresponding to the next signal frame.

[0083] This embodiment further introduces a judgment mechanism based on synchronization strategy to dynamically determine the target feature information retained in the shadow register in the scenario of continuous signal frame access.

[0084] Specifically, if the baseband module detects that the next signal frame has completed frame synchronization before the current signal frame has been read by the processing module, it determines whether to perform a feature information shifting operation according to a preset synchronization strategy. The synchronization strategy includes: retaining the feature information of the next signal frame in the baseband buffer without shifting it to the shadow register to maintain the validity of the feature information of the current signal frame; or, if the shifting conditions are met, shifting the feature information of the next signal frame from the baseband buffer to the shadow register to overwrite the feature information of the current signal frame. Shifting conditions may include factors such as the overflow flag being set, incomplete reception, or timeout processing triggering.

[0085] It should be noted that the update of the shadow register is not directly controlled by the baseband module, but is achieved automatically through hardware logic such as gate circuits configured within the baseband module. Specifically, the state of the shadow register is automatically triggered by the control logic circuit based on changes in the synchronization signal and the overflow flag signal. Through the state control of the gate circuits, the shadow register can autonomously choose whether to retain the feature information of the current signal frame or update it with the feature information of the next signal frame.

[0086] When the baseband module detects the frame synchronization completion signal for the next signal frame, the shadow register update operation is automatically executed according to the preset synchronization strategy. This update operation relies on the triggering mechanism of the hardware circuit, and uses gate circuits to control the write and read paths of the shadow register to ensure that no information conflicts or loss occur during frame data processing.

[0087] Therefore, the state changes of the shadow register are completely controlled by hardware, without relying on the direct intervention of the baseband module or the intervention of external processing modules, thereby improving the response efficiency of the power communication system and ensuring the efficient storage and updating of feature information.

[0088] In the above embodiments, by introducing a synchronization strategy at the shadow register layer, selective retention and update control of continuous feature information are achieved, avoiding feature loss due to sudden coverage and improving the communication system's ability to cope with high-speed signal frame access scenarios. This synchronization strategy dynamically decides based on feature information quality, which not only improves the accuracy of frame data processing but also enhances the system's robustness to asynchronous frame structures or strong channel interference.

[0089] In some embodiments, the synchronization strategy includes: if a frame synchronization completion signal for the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module, the baseband module sets up an overflow flag signal; when the overflow flag signal is set up, the baseband module performs a reset operation, and the shadow register latches the feature information corresponding to the current signal frame.

[0090] When the baseband module detects the frame synchronization signal of the next signal frame, if the current signal frame has not yet been read by the processing module, it automatically sets the overflow flag signal. The overflow flag signal is a collision indication signal used to indicate an abnormal state where the previous frame has not been processed, but the next frame has already started entering the reception path.

[0091] Under normal circumstances, when the baseband module receives the current signal frame (e.g., frame 1), it calculates the feature information from the preamble symbol and temporarily stores it in the baseband buffer. After completing the frame synchronization of frame 1, the baseband module moves the feature information of frame 1 from the baseband buffer to the shadow register to form a latch. At the same time, the baseband module continues to receive and process the FC field and PL field of frame 1 and writes them into the system memory. After that, the processing module (e.g., the CPU) reads the data of frame 1 from memory and synchronously reads the feature information of frame 1 in the shadow register to achieve a one-to-one correspondence between features and data.

[0092] When the overflow flag is set, it indicates a conflict scenario, such as the processing module failing to read data from frame 1 from system memory in time, while the baseband module detects that the synchronization process for frame 2 has been completed. In this scenario, the baseband module performs a reset operation to abort the reception of the next signal frame. The shadow register latches the feature information of the current signal frame, ensuring it is not overwritten by the feature information of the next signal frame. This prevents the data from being replaced by the next frame before the processing module has read it, ensuring that the data (frame 1) read later by the processing module is consistent with the feature information (frame 1), avoiding data mismatch. This synchronization strategy effectively ensures that the processing module can always obtain valid and consistent feature information.

[0093] In other words, after the current signal frame is received, the baseband module transmits the data of the current signal frame to the memory module. During the period when the current signal frame has been received and transmitted to the memory module by the baseband module, but has not yet been read by the processing module, if a frame synchronization completion signal for the next signal frame is detected, the baseband module sets the overflow flag signal. When the overflow flag signal is set, the baseband module performs a reset operation to stop processing the next signal frame, so as to maintain the data of the current signal frame stored in the memory module. The shadow register latches and retains the feature information corresponding to the current signal frame, so that the processing module can perform subsequent processing based on the data of the current signal frame in the memory and the feature information of the current signal frame in the shadow register.

[0094] In the above embodiments, by setting an overflow flag signal and performing corresponding synchronization operations by the shadow register based on this signal, the problem of the shadow register being prematurely overwritten by the data of the next signal frame before the processing module has finished reading can be effectively prevented. This strategy ensures the consistency of feature information, improves the stability and reliability of frame data processing, and is particularly suitable for communication scenarios with short inter-frame intervals under high-speed receiving links.

[0095] In other embodiments, the synchronization strategy further includes: if a frame synchronization completion signal for the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module, the baseband module sets up an overflow flag signal; under the condition that the overflow flag signal is set up, the shadow register writes the feature information corresponding to the next signal frame to overwrite the feature information corresponding to the current signal frame.

[0096] Under normal circumstances, after receiving frame 1, the baseband module extracts feature information based on the preamble signal between the synchronization start and synchronization completion (i.e., the period between the frame synchronization start signal sync-begin and the frame synchronization completion signal frame-synced), and simultaneously stores this feature information temporarily in the baseband buffer. When the frame synchronization completion signal is detected, the shadow register is triggered to write this feature information for latching, thereby moving the feature information of the current signal frame from the baseband buffer to the shadow register. Subsequently, the baseband module transmits the payload (FC + PL) of frame 1 to the system memory, waiting for the CPU to read it.

[0097] If the current signal frame has not yet been read and the next signal frame has completed frame synchronization, the baseband module detects a potential collision and sets an overflow flag. Subsequently, based on this flag, the baseband module triggers the shadow register to replace the feature information corresponding to the current signal frame with the feature information corresponding to the next signal frame. From a higher-level perspective, this can be seen as the feature information of the next signal frame being moved from the baseband buffer to the shadow register, overwriting the feature information of the current signal frame in the shadow register. This mechanism can be used to adapt to the rapid response requirements of replacing old frames with new ones in certain scenarios, balancing buffer management efficiency and system timeliness.

[0098] For example, if the baseband module detects a frame synchronization completion signal for frame 2 before the CPU has read the data of frame 1 from the system memory, it considers there to be a reading lag. The baseband module will then set an overflow flag to indicate a reception conflict between the current frame and the next frame. In this embodiment, the baseband module triggers the shadow register to no longer retain the feature information of frame 1, but instead writes the feature information of frame 2, overwriting the original data of frame 1. Therefore, the frame data (frame 2) read by the CPU later is consistent with the feature information (frame 2), avoiding data mismatch.

[0099] In other words, after the current signal frame is received, the baseband module transmits the data of the current signal frame to the memory module. During the period when the current signal frame has been received and transmitted to the memory module by the baseband module, but has not yet been read by the processing module, if a frame synchronization completion signal for the next signal frame is detected, the baseband module sets the overflow flag signal. Under the condition that the overflow flag signal is set, the baseband module discards the data of the current signal frame and transmits the data of the next signal frame to the memory module. The shadow register is then written with the feature information of the next signal frame to overwrite the feature information corresponding to the current signal frame, so that it can be read by the subsequent processing module, ensuring that the feature information stored in the shadow register is consistent when the processing module reads the data of the next signal frame in memory.

[0100] In the above embodiments, the ability to replace old frame features with new frame features under conflict conditions can significantly improve the system's response speed to sudden data, avoid unexpected data overwriting, and improve the controllability and robustness of the frame feature synchronization process. It is suitable for application scenarios with high requirements for information real-time priority.

[0101] In some high-speed power communication systems, signal frames are received continuously. Processing modules may be unable to read the current signal frame in time due to response delays, leading to conflicts between the reception and processing of the next signal frame and the current frame. In such conflict situations, simply deciding which frame's feature information to retain based on timing priority or fixed rules may not simultaneously consider channel quality and system performance. For example, retaining frames with poor channel quality may lead to misjudgments in subsequent processing; discarding higher-quality frames affects data reliability. Therefore, it is necessary to introduce a frame feature information selection mechanism based on channel quality to improve overall processing efficiency and system robustness.

[0102] Therefore, in some embodiments, the above synchronization strategy further includes: the baseband module determines the channel quality corresponding to the current signal frame and the next signal frame respectively, and compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame to obtain a comparison result; the shadow register latches the feature information corresponding to the current signal frame based on the comparison result, or writes the feature information corresponding to the next signal frame to cover the feature information corresponding to the current signal frame.

[0103] In this embodiment, the baseband module supports independent evaluation of the channel quality of the current signal frame and the next signal frame, and controls the feature information retained in the shadow register based on the evaluation results.

[0104] During frame synchronization, the baseband module performs channel characteristic estimation on the current signal frame and the next signal frame respectively to obtain channel quality indicators such as signal-to-noise ratio, received signal strength indication or channel estimation amplitude.

[0105] The baseband module compares the channel quality of the current signal frame with that of the next signal frame to obtain a comparison result, which indicates which frame has better channel quality.

[0106] Therefore, based on this result, the shadow register performs one of the following operations: if the channel quality of the current signal frame is better, it does not update and retains the feature information corresponding to the current signal frame unchanged; if the channel quality of the next signal frame is better, it writes the feature information of the next signal frame, thereby moving the feature information of the next signal frame from the baseband buffer to the shadow register to overwrite the original feature information of the current signal frame.

[0107] In the above embodiments, by using a dynamic comparison mechanism based on channel quality, a synchronization strategy can be adaptively selected in the case of signal frame reception conflicts. Compared with the method of fixedly retaining the first or last arriving frame, it has higher robustness and is particularly suitable for power line communication environments with rapidly changing channel conditions and severe electromagnetic interference.

[0108] In the receiving path, after a signal frame is received, its data needs to be written into the memory module for subsequent processing. However, in some high-frequency communication scenarios, the next frame may begin synchronization and reception before the previous frame has been processed.

[0109] Figure 6 This is a schematic diagram illustrating the underlying data interaction principle provided in some embodiments of the present invention. For example... Figure 6 As shown, frame data (including preamble, frame control data, and data payload) is first received by the baseband module, which then demodulates the signal and parses the fields. After processing the frame data, the baseband module writes the frame control data and data payload into the memory module (i.e., system memory) and, through its internal hardware logic, sets the receive completion signal (rx-end-flag) at time t1, switching from the default low level to a high level to indicate that the reception and transmission of the frame data for that signal frame has been completed. Upon detecting the high level of the receive completion signal, the processing module (i.e., the CPU) begins reading the corresponding frame data from the system memory. After reading is complete, the processing module sets the receive completion signal to zero at time t2, returning it from a high level to a low level to indicate the completion status. This establishes a handshake mechanism jointly implemented by the baseband module and the processing module, ensuring reliable setting and release of the receive completion flag and improving the reliability of frame data reading.

[0110] The following further describes the normal timing process of the handshake mechanism under the condition of consecutive frame arrivals. Figure 7 This is a schematic diagram of signals under normal conditions provided in some embodiments of the present invention. For example... Figure 7 As shown, in the context of the system continuously receiving multiple frames of data, after the baseband module completes the reception and processing of frame 1, it writes the frame control data and data payload into the system memory at time t1 and sets the reception completion signal (rx-end-flag) to indicate that the data for frame 1 has been written. Subsequently, the processing module detects that the reception completion signal is in a high-level state, confirming that the current frame data is ready to be read, and initiates the reading operation. After the processing module completes the reading of frame 1 data, at time t2, it uses software control to set the reception completion signal to zero, i.e., it transitions from a high level to a low level, to notify the baseband module that the processing of the current frame data has ended and the reception process for the next frame data can begin.

[0111] exist Figure 7In the normal data flow scenario shown, the timely setting and resetting of the receive completion signal effectively synchronizes the frame data reception status between the baseband module and the processing module, helping to ensure data integrity and read timing when the system continuously receives multiple signal frames. However, in actual operation, the CPU often undertakes multiple parallel tasks simultaneously, posing a risk of response delay. Especially in scenarios with short frame intervals and high processing pressure, the resetting of the receive completion signal may not be completed within the expected time window, thus affecting the normal reception and storage of subsequent frames. To illustrate the potential data conflict problem caused by this type of response delay, the following shows the overwriting and misreading phenomena caused by continuously receiving frame data when the CPU fails to reset the receive completion signal in a timely manner.

[0112] Figure 8 This is a schematic diagram of the signal under delay conditions provided in some embodiments of the present invention. For example... Figure 8 As shown, at time t1, the baseband module transmits frame 1 data to system memory and sets the receive completion signal (rx-end-flag), which should normally be set to zero at time t2. However, because the CPU is currently processing other tasks and cannot respond in time, the receive completion signal is not set to zero at time t2 and remains at a high level. Assuming the receive completion signal is set to zero at time t2', and the baseband module has already started receiving frame 2 data, the data extracted by the CPU between t1 and t2' will contain a mixture of frame 1 and frame 2 data. This will cause errors in the upper-layer application processing, and subsequent frame 2 data will also be missing, leading to errors in subsequent processing as well.

[0113] It should be noted that although system designs typically reserve frame intervals for the CPU to complete read and flag-setting operations, the CPU response process is software-controlled and inevitably involves latency fluctuations. Delayed responses will directly affect the correctness of the cached data, especially in scenarios with dense, continuous frame reception, where overlay conflicts are more likely to occur.

[0114] Therefore, in some embodiments, the above method further includes: after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, it sets up a reception completion signal to indicate the reception completion status; while the reception completion signal is set up, if the baseband module detects a frame synchronization completion signal, it sets up an overflow flag signal; the overflow flag signal is used to indicate that the processing status of the current signal frame conflicts with the reception behavior of the next signal frame; the overflow flag signal is used to indicate that the processing status of the current signal frame conflicts with the reception behavior of the next signal frame; according to the frame conflict handling strategy, a frame conflict handling operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal.

[0115] The receive completion signal is a status indication signal set by the baseband module. It indicates that the reception operation of the current signal frame has been completed and the process can proceed to the next stage. This signal helps coordinate read / write synchronization between the baseband and subsequent processing modules, preventing overlapping inter-frame operations. The overflow flag signal serves as a trigger condition for conflict management, enabling the signal receiving device to switch processing strategies in a timely manner, switching between normal processing and frame conflict handling to avoid data loss or state confusion.

[0116] The baseband module receives the current signal frame (e.g., frame 1) and completes data parsing and demodulation operations. After data processing is complete, the baseband module writes the FC field (Frame Control) and PL field (Payload) of frame 1 into the memory module and sets the receive completion signal rx-end-flag. The default state of this signal is low; setting it indicates that the current frame has been transmitted and the system is ready for subsequent read operations.

[0117] The baseband module receives the current signal frame and transmits it to the memory module. This process includes not only the direct transmission of the FC (Frame Control) and PL (Payload) fields in the signal frame, but also complete support for the preceding reception processing. Specifically, when constructing a power line carrier signal data frame, the signal transmitting device typically first performs general channel coding on the raw byte data to be transmitted (e.g., hexadecimal 0x12) to improve error resilience. Then, the coding result is interleaved to combat sudden interference or narrowband noise. Afterward, the signal transmitting device inserts multiple preamble symbols before the coded data. These preamble symbols typically consist of multiple synchronization training symbols or pilots, used by the receiver to perform frame synchronization and channel estimation. For example, the raw data 0x12, after coding and interleaving, can be mapped to "110011". Then, a preamble sequence "010101" is inserted, ultimately forming the complete transmitted bit string "010101110011" as a complete physical layer signal frame.

[0118] The baseband module of the signal receiving device first receives the bit string (i.e., a composite frame containing a preamble, FC, and PL). Within the synchronization window, it performs frame synchronization by detecting multiple consecutive synchronization peaks or matching the local frame preamble sequence, triggering the generation of corresponding frame synchronization start signals (sync-begin) and frame synchronization completion signals (frame-synced). Furthermore, the baseband module performs channel estimation and equalization, using the preamble symbol to calculate CE and estimate the channel response. The signal receiving device also performs deinterleaving and decoding, deinterleaving, soft-decision decoding, or maximum likelihood decoding of the payload portions of the FC and PL fields in the received bitstream to restore the original data bytes (e.g., recovering 0x12). Additionally, the receiver can perform verification and field parsing, such as performing CRC checks on the frame control field and parsing the length / address field. Finally, when the decoding result is valid, the baseband module writes the decoding result corresponding to the signal frame (i.e., 0x12) into the system memory module and simultaneously sets the receive completion signal Rx-end-flag to notify the processing module (e.g., the CPU) that the data is readable.

[0119] The overflow flag signal is a collision indication signal used to indicate an abnormal state where the previous frame has not been processed but the next frame has already begun entering the reception path. This signal serves as a trigger condition for collision management, enabling the signal receiving device to switch processing strategies in a timely manner, i.e., switching between normal processing and frame collision handling, to avoid data loss or state confusion.

[0120] While the receive completion signal rx-end-flag is still in the enabled state (high level), if the baseband module detects a frame synchronization completion signal, it indicates that the frame synchronization processing of the next signal frame (e.g., frame 2) has been completed. In this case, the communication system faces a conflict scenario, i.e., the previous frame has not yet been released, and the next frame has already begun to be received. At this time, the baseband module generates an overflow flag signal overflow-flag to explicitly indicate that the current signal frame has not been processed but a new reception action has occurred, which is a potential data conflict state.

[0121] The frame collision handling strategy refers to the predefined collision response scheme of the signal receiving device to deal with the overlap of received signal frames. This collision response scheme includes the strategy for retaining and discarding signal frames, as well as corresponding behavior control logic, state initiation / clearing order, and other parameters. A reasonable setting of this strategy helps ensure system processing stability in continuous frame reception scenarios and improves overall communication quality.

[0122] When a collision is detected and an overflow flag signal is generated, the baseband module executes frame collision handling operations according to a preset frame collision handling strategy. This strategy can determine whether to retain the previous frame or the current frame based on factors such as different system loads and processing priorities.

[0123] For example, frame collision handling strategies may include, but are not limited to: interrupting the current reception, discarding the new frame, latching the old frame, enabling double buffering, and clearing the next frame. The baseband module will select to perform differentiated collision clearing actions for the current frame or the next frame based on the state characteristics at the time of the collision, thereby ensuring stable system operation.

[0124] Taking a wireless communication system based on OFDM (Orthogonal Frequency Division Multiplexing) signal structure as an example, after the baseband module completes the reception of all symbols of frame 1 and transfers them to memory via DMA, it sets a reception completion signal. At this time, since the upper-layer CPU has not yet completed data reading, if frame 2 has started reception through synchronization symbol detection, the baseband module will generate an overflow flag signal and then process it according to the preset frame conflict handling strategy. For example, if the system prioritizes retaining frame 1 data, the frame 2 reception process is discarded and its buffer area is cleared; if frame 2 needs to be retained, the frame 1 reception state is cleared and its reading path is released for use by new frames, and so on.

[0125] In the above embodiments, after the baseband module completes the reception of the current signal frame and transmits the data of the current signal frame to the memory module, it sets the reception completion signal, thereby clearly defining the state between frame reception and processing, which facilitates the processing module in determining the timing of data reading. While the reception completion signal is in the set state, if the baseband module detects a frame synchronization completion signal, it sets the overflow flag signal, enabling timely detection of the next frame's access behavior and generating a flag signal for alarm. This achieves rapid and automatic identification of conflict states without waiting for processor intervention or polling, eliminating reliance on interrupt responses or software scheduling mechanisms. Furthermore, according to the frame conflict handling strategy, based on... The overflow flag signal performs frame collision handling operations related to the current or next signal frame. The baseband module automatically triggers the collision strategy, supporting automatic frame collision handling within the hardware without the need for the processor to participate in judgment and control signal initiation. This reduces control path latency, improves robustness and overall processing efficiency in high-speed reception scenarios, and by introducing configurable or dynamically selectable collision handling strategies, it supports flexible handling of collisions between current frame retention and next frame reception according to application requirements, improving system adaptability and processing efficiency. It can effectively reduce the risk of data loss and state disorder caused by frame collisions, and improve the reliability and processing efficiency of the system in high-density reception scenarios.

[0126] In actual communication, frames may arrive consecutively. Signal receiving devices need to accurately determine when to enter the next frame reception process in order to achieve pre-triggering for frame collision identification and control.

[0127] Therefore, in some embodiments, the baseband module detects the frame synchronization completion signal by: monitoring the synchronization sequence in the input signal, and when a synchronization sequence matching the preset frame format is detected, generating a frame synchronization start signal to indicate that frame synchronization detection for the next signal frame has been initiated; after confirming the frame synchronization position, the baseband module generates a frame synchronization completion signal to indicate that the currently received next signal frame has completed the synchronization process.

[0128] Specifically, during signal reception, the baseband module first continuously monitors the synchronization sequence in the input signal. For example, a sliding window can be set to perform matching operations on the preamble region of the received signal to identify whether a sequence pattern matching a preset frame structure exists. If a continuous correlation peak or feature template that meets the conditions is detected, a frame synchronization start signal (sync-begin) can be triggered to indicate that the synchronization detection phase of the next signal frame has started.

[0129] Subsequently, the baseband module continues to perform frame synchronization processing on the input signal, such as locating the boundary point between the synchronization symbols SYNCP (Synchronization Pattern) and SYNCM (Synchronization Channel Midpoint), or determining the frame header position through the maximum correlation value. Once the frame synchronization position is successfully confirmed, the baseband module generates a frame-synced signal to indicate the end of the current synchronization process, and the reception process can proceed to the frame control segment and data payload segment reception processing.

[0130] Taking a typical OFDM frame structure as an example, its frame header usually contains multiple preamble symbols used for frame synchronization, frequency offset estimation, and channel estimation. The communication system pre-configures a preset frame format and decision threshold. At time t0, the baseband module detects more than three similar synchronization peaks in the input signal, thus generating a frame synchronization start signal (sync-begin), indicating that synchronization detection for frame 2 has started. Next, the baseband module confirms the synchronization position based on a sliding window matching mechanism, for example, determining the intersection of SYNCP and SYNCM, and generates a frame synchronization completion signal (frame-synced), indicating that synchronization of frame 2 is complete and its FC and PL fields can be received. If the previous frame, frame 1, has not yet been read, the baseband module will combine the frame synchronization completion signal with the reception completion signal (Rx-end-flag) to trigger subsequent frame collision handling procedures.

[0131] In the above embodiments, by introducing a synchronization sequence matching and frame synchronization signal generation mechanism into the baseband module, the arrival of the next frame signal can be quickly and accurately identified without CPU intervention. This helps improve the boundary detection accuracy during frame reception and ensures that the frame collision handling process has an accurate starting judgment basis. Simultaneously, this mechanism can effectively reduce system response latency, avoid data misreading or overwriting problems caused by hardware and software asynchrony, and enhance the robustness and real-time performance of the overall communication system.

[0132] It should be noted that the feature information synchronization method for power communication signal frames provided by this invention can be applied to communication systems with continuous frame structures. In a communication system, one scenario is that multiple signal frames are arranged sequentially, and the inter-frame interval between adjacent signal frames is less than the minimum reading cycle of the processing module. That is, when the previous frame has not yet completed data extraction, the next frame has already begun to arrive and enter the synchronization stage.

[0133] Such systems are common in high-density, high-speed data communication scenarios, such as power line carrier communication (HPLC), OFDM systems, or point-to-point communication in specific embedded devices. Due to the lack of inter-frame buffer redundancy, the processing cycle of frame 1 easily overlaps with the reception cycle of frame 2, leading to frame collisions. Against this backdrop, the frame collision handling strategy proposed in this invention can significantly improve system stability.

[0134] The following sections will describe the three frame collision handling strategies proposed in this invention to more clearly illustrate the specific response methods under different collision conditions.

[0135] It should be noted that the classification and implementation methods of frame conflict handling strategies are merely illustrative and do not constitute a limitation on the scope of protection of this invention. Without departing from the core ideas of this invention, the processing flow of the relevant strategies can be adapted and extended according to the actual system design.

[0136] In some embodiments, according to the frame conflict handling strategy, a frame conflict handling operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, including: when the overflow flag signal is in the enabled state, the baseband module generates an overflow reset signal for triggering an interrupt; in response to the overflow reset signal, the baseband module performs a reset operation to stop processing the next frame data; the baseband module sets the receive completion signal and the overflow reset signal to zero to end the conflict state between the current signal frame and the next signal frame.

[0137] When the baseband module detects that the data of the current signal frame has been transmitted to the memory module and the reception completion signal is in the enabled state, and then starts receiving the next frame of data, it will enable the overflow flag signal to indicate the occurrence of a frame collision.

[0138] Under the current frame collision handling strategy, if the overflow flag signal is in the enabled state, the baseband module will automatically generate an overflow reset signal (overflow-rst). This signal serves as a trigger mechanism, prompting the baseband module to actively perform a reset operation based on this signal. The reset operation refers to the baseband module actively suspending the currently executing processing of the next frame during a frame collision. For example, it can reset baseband deinterleaving, decoding, and other modules. It should be noted that the reset operation does not mean terminating the processing of the next signal frame; its purpose is to stop the current data writing operation to avoid problems such as frame aliasing, frame header misalignment, or control signal lag caused by writing data for the next frame. After collision handling is completed, the baseband module simultaneously sets the previously enabled receive completion signal and overflow reset signal to zero, clearly indicating the end of the collision state, thereby allowing the system to re-enter the synchronized receiving state.

[0139] Figure 9 This is a signal diagram illustrating a frame collision handling strategy provided in some embodiments of the present invention. For example... Figure 9 As shown, if the baseband module does not set the receive completion signal (rx-end-flag) to zero after processing frame 1, and the baseband module detects the frame synchronization signal (frame-synced) of frame 2 at time t1', then the baseband module generates an overflow flag signal (overflow-flag). Based on this overflow flag signal, under the current frame conflict handling strategy, the baseband module also generates an overflow reset signal (overflow-rst). Furthermore, the baseband module performs a reset operation based on this overflow reset signal. Here, reset refers to the baseband deinterleaving, decoding, and other modules resetting. Therefore, the baseband module will not perform decoding or other parsing processing on frame 2 data after time t1', and thus will not transmit frame 2 data to the memory module for writing into system memory. The current strategy is a frame conflict handling strategy that discards frame 2 data. Therefore, based on this overflow flag and reset mechanism, the baseband module will not write frame data into system memory, thereby ensuring that frame 1 data is not overwritten by frame 2 data and guaranteeing the integrity of frame 1 data.

[0140] It should be noted that when the baseband module performs frame synchronization detection, the frame 2 data consists of the frame preamble, FC field, and PL field. The frame synchronization position is in the preamble position. Therefore, when the baseband module detects the frame synchronization signal, it has not yet started to move the frame 2 data to the system memory, so there will be no data overwriting.

[0141] In the above embodiments, by actively generating an overflow reset signal after a conflict is detected by the baseband module, and performing buffer clearing and reception termination operations based on this signal, and coordinating the synchronous zeroing of the reception completion signal and the overflow reset signal, a fast closed-loop processing of frame conflict states is achieved. This avoids uncontrollable delays caused by relying on CPU response, ensuring timely handling of conflict states. Furthermore, by clearing the next frame of data and terminating reception, overlapping or overwriting of consecutive frames is avoided, ensuring the integrity of each frame of data. In addition, the entire process is completed independently by the baseband module, without CPU participation, resulting in no response delay. It also completely avoids the problem of delayed conflict response caused by software busyness or scheduling delays. This ensures both the real-time performance of the communication process and the continuity and stability of CPU software tasks. Even when consecutive frames arrive in close succession or the CPU is under high load, the system can still operate stably, achieving efficient and reliable data protection in frame conflict scenarios.

[0142] In other embodiments, the signal receiving device further includes a processing module. The following embodiments further propose a frame collision handling strategy that is collaboratively processed by the processing module.

[0143] Accordingly, in accordance with the frame conflict handling strategy, the frame conflict handling operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, and further includes: when the overflow flag signal is detected, the processing module stops reading the current signal frame; the processing module sets the receive completion signal to zero in order to read the next signal frame.

[0144] When the processing module detects an overflow flag signal set by the baseband module, it determines that there is a risk of reading the current signal frame and immediately stops reading the current signal frame to prevent the data being extracted from being mixed with subsequent data. At the same time, the processing module can send a command to the baseband module to set the receive completion signal to zero, thereby releasing the current frame state and entering the read preparation process for the next signal frame.

[0145] For example, in a scenario involving the reception of a series of consecutive OFDM signal frames, when the baseband module detects the start of frame 2 reception, it has not yet set the reception completion signal corresponding to frame 1 to zero, thus setting the overflow flag. At this point, the CPU, as the processing module, reads this overflow flag in the interrupt response and immediately stops retrieving frame 1 data from system memory to avoid reading the data content of frame 2. Afterwards, the CPU sends a zero-setting instruction to the baseband module, instructing it to set the reception completion signal (Rx-end-flag) to zero, allowing the system to quickly enter the frame 2 data processing flow and avoiding communication backlog.

[0146] Figure 10 This is a signal diagram illustrating another frame collision handling strategy provided in some embodiments of the present invention. For example... Figure 10 As shown, if the baseband module does not set the receive completion signal (rx-end-flag) to zero after processing frame 1, and the baseband module detects the frame synchronization signal (frame-synced) of frame 2 at time t1', then the baseband module generates an overflow flag. Based on this overflow flag, under the current frame collision handling strategy, the processing module (such as the CPU) actively terminates the reading operation of frame 1 to avoid extracting invalid data that may have been partially overwritten; subsequently, the processing module sets the receive completion signal to zero to release the read flag of the current frame 1. On this basis, the baseband module continues to complete the receiving processing of frame 2 and writes the data of frame 2 into system memory. After the transmission of frame 2 is completed, the baseband module sets the receive completion signal again at time t3 to indicate that the data of frame 2 is ready. Finally, after the CPU detects that the receive completion signal is high, it switches to reading the data of frame 2 from system memory, completing the data recovery and normal processing flow after the inter-frame collision. In other words, the current strategy is a frame collision handling strategy that discards the data of frame 1.

[0147] Compared to relying entirely on the baseband module to handle conflicts, the mechanism of suspending reading and clearing flags through the processing module effectively solves the problem of misreading conflicting data caused by frame interruption, enhancing the accuracy and scalability of data reception while maintaining the original system architecture.

[0148] In the above embodiments, by interrupting the continued reading of the current frame through the processing module, invalid data is not extracted after the frame data is partially covered, thus improving the effectiveness of the frame data. Furthermore, by actively setting the receiving completion signal to zero, the conflict handling time is shortened, the preparation for processing the next frame data is accelerated, and the overall system processing speed is improved.

[0149] To further improve the reliability of signal reception and data quality in the event of frame collisions, this invention proposes a frame selection mechanism based on channel quality assessment, building upon the aforementioned frame collision handling strategy. This mechanism enables the signal receiving device to automatically determine and retain the frame with better quality between two conflicting frames, avoiding the misselection of low-quality data under channel degradation and improving the overall robustness of the system.

[0150] Therefore, in some other embodiments, according to the frame collision handling strategy, the frame collision handling operation related to the current signal frame or the next signal frame is performed based on the overflow flag signal, and further includes: the baseband module at least completes the reception of the preamble symbol of the next signal frame, so as to evaluate the channel quality corresponding to the next signal frame based on the preamble symbol; the baseband module compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame, and retains the signal frame with higher channel quality based on the comparison result, and discards the other signal frame.

[0151] Specifically, after detecting a next signal frame that conflicts with the current signal frame, the baseband module in the signal receiving device first receives and parses the preamble symbol in the next signal frame. The preamble symbol, as a channel estimation reference field, possesses strong stability and representativeness. The baseband module can use it to calculate the channel characteristic indicators of the corresponding frame, including but not limited to signal-to-noise ratio (SNR), received signal strength indicator (RSSI), or channel estimation (CE).

[0152] After obtaining the channel quality information of the next signal frame, the baseband module compares and analyzes it with the channel quality of the current signal frame. Based on preset criteria, such as prioritizing maximum SNR and RSSI exceeding a threshold, it determines which frame has better reception conditions. Based on this determination, the frame with higher channel quality is automatically retained for subsequent processing, while the frame with degraded channel quality is discarded to avoid invalid data interference or resource waste.

[0153] In the above embodiments, by introducing a channel quality assessment mechanism into the conflict handling strategy, the signal receiving device can effectively distinguish and select frame data with better reception conditions in high frame density or continuous communication scenarios, avoiding data misuse caused by channel condition fluctuations; at the same time, it reduces the resource burden caused by redundant data processing and improves the overall system's communication reliability and robustness.

[0154] In practical communication systems, the operating load of signal receiving devices is often affected by factors such as upper-layer processing tasks, system buffer usage, and external interrupt frequency. If a fixed frame collision handling strategy is still used under high load conditions, it may be impossible to simultaneously ensure system real-time performance and data integrity. This invention further proposes a load-aware adaptive strategy mechanism, enabling signal receiving devices to dynamically adjust their frame collision handling logic, thereby flexibly balancing data retention strategies and feature information extraction strategies under different operating loads.

[0155] Therefore, in some embodiments, the above method further includes: detecting the load state; automatically selecting different frame collision handling strategies based on the load state to retain the current signal frame or the next signal frame; and determining the reading strategy of the feature information of the current signal frame or the next signal frame based on the selected frame collision handling strategy.

[0156] Specifically, the signal receiving device continuously monitors its load status during operation, which may include indicators such as CPU processing utilization, frame buffer queue depth, and task scheduling latency.

[0157] The signal receiving device determines whether the system is currently under light, medium, or heavy load based on these indicators, and selects the most suitable one from several preset frame collision handling strategies accordingly. For example, under low load, a frame collision handling strategy that retains the current signal frame and discards the next signal frame is preferred. Under high load, a frame collision handling strategy that retains the next signal frame and discards the current signal frame is preferred to reduce congestion and improve processing throughput. If the load is critical or medium, a channel quality optimization strategy can be used to selectively retain the current frame from the next frame.

[0158] In the above embodiments, by introducing a load status perception and processing strategy adaptive mechanism, the signal receiving device's ability to respond flexibly to complex operating environments is enhanced. It can improve the overall processing efficiency and stability of the system while ensuring the integrity of frame data, and is particularly suitable for communication scenarios with dense frame arrivals, high-frequency switching, or frequent interference.

[0159] Therefore, in conjunction with the above embodiments, Figure 11 This is a signal diagram illustrating the feature information synchronization process provided in some embodiments of the present invention. For example... Figure 11 As shown, based on the existing baseband cache structure, this invention adds a shadow register (or shadow memory) to specifically store feature information, ensuring the correctness and readability of frame feature data in conflict states or software latency scenarios. Compared to Figure 3 As shown, the shadow register provides a stable copy of feature information for extraction and use by the CPU or upper-level processing modules.

[0160] refer to Figure 4 As shown in the timing diagram, when the baseband module detects the sync-begin signal of frame 1 (at time t0), i.e., when multiple synchronization peaks are detected consecutively, the baseband module begins processing such as channel estimation, calculates the feature information of frame 1, and writes it into the baseband buffer. This process continues until the frame-synced signal of frame 1 is detected, i.e., at time t0'. When the baseband module detects the frame-synced signal of frame 1 at time t0', the baseband module immediately controls the shadow register to read the feature information of the current frame (frame 1) from the baseband buffer and latches it. At this time, the shadow register stores consistent feature information corresponding to the frame 1 data in the system memory.

[0161] When frame 1 data is successfully transmitted to system memory (at time t1), the baseband module sets up the receive completion signal (rx-end-flag) to notify the CPU that the frame data can be read. When the baseband detects the sync-begin signal for frame 2 at time T1, it begins to recalculate and update the feature information of frame 2. If the CPU has not yet completed extracting the frame 1 data at this time, there is a risk that the frame feature data may be overwritten.

[0162] In conjunction with the above embodiments Figure 7 The provided frame conflict handling strategy detects an overflow flag being set at time t1' (i.e., when frame 2 synchronization is complete). In this case, the baseband module disables the shadow register update, preserving the characteristic information of frame 1. Even if the CPU delays data reading at time t2', the characteristic information obtained from the shadow register remains consistent with the data in frame 1.

[0163] In conjunction with the above embodiments Figure 8 The proposed frame conflict handling strategy triggers a feature shift operation if an overflow flag is detected at time t1'. The baseband module then updates the shadow register with the feature information of frame 2 to align with the system's frame conflict handling strategy that preserves frame 2 data. When the CPU subsequently completes the reading of frame 2 data (e.g., at time t3), it can obtain the corresponding frame 2 feature information from the shadow register, ensuring data consistency. This effectively solves the problem of frame data and feature information mismatch caused by software latency in traditional architectures, further improving data consistency and application reliability of signal receiving devices in high-concurrency scenarios.

[0164] Unlike related technologies where the CPU directly accesses the baseband cache, in this invention, the CPU reads feature information from the shadow register to ensure that the extracted frame data and feature information correspond one-to-one, avoiding data mismatch caused by cache overwriting. After reading is complete, the CPU or upper-layer application sets the reception completion signal (rx-end-flag) to zero to end the current processing cycle.

[0165] The above mechanism is particularly suitable for scenarios that require high communication reliability, have complex meter networking, and are subject to significant power line noise interference, such as the networking application of power line carrier communication chips.

[0166] Furthermore, this invention extends the shadow register mechanism by introducing a multi-shadow register structure to achieve parallel caching of multiple signal feature information.

[0167] Therefore, in some embodiments, multiple shadow registers are configured to latch feature information corresponding to multiple signal frames respectively; the above method further includes: allocating unused shadow registers sequentially for each signal frame that has completed frame synchronization, and moving the feature information corresponding to each signal frame to the allocated shadow registers; while the data of the signal frame whose feature information was first written is stored in the memory module and has not yet been read by the processing module, if the frame synchronization completion signal of the next signal frame is detected, then according to the synchronization strategy, one or more shadow registers latch the written feature information, or one or more shadow registers write the feature information corresponding to the new signal frame to overwrite the feature information corresponding to the previous signal frame.

[0168] In actual reception, after each frame synchronization is completed, the baseband module can use a polling mechanism to find an unoccupied shadow register in the shadow register, so as to trigger the corresponding shadow register to perform the corresponding synchronization operation, thereby moving the feature information of the current signal frame to the selected shadow register.

[0169] If all shadow registers are currently occupied, and the earliest written signal frame has not yet been read by the processing module, after detecting the frame synchronization signal of the next signal frame, the signal receiving device can perform one of the following operations based on the synchronization strategy:

[0170] On the one hand, the shadow register where the earliest feature information was written can be released, and the feature information corresponding to the new signal frame can be written into the register;

[0171] On the other hand, based on priority or business needs, the feature information of new signal frames can be discarded while retaining the original register contents.

[0172] During this process, the baseband module can maintain a write order queue for the shadow register, ensuring that the processing module can read the data according to the write order or priority rules during subsequent processing.

[0173] In the above embodiments, by setting multiple shadow registers and introducing a dynamic allocation and update mechanism, the storage capacity of feature information in multi-frame continuous reception scenarios is improved, and the information loss problem caused by limited buffer resources is effectively avoided. This enhances the reception and processing capability of high-frequency signal frames and strengthens the robustness and scalability of the system.

[0174] Based on this, the baseband module or signal receiving device can assign a register identifier to each shadow register and maintain a write order queue to record the order in which each shadow register is written. This queue can be maintained using a first-in, first-out (FIFO) structure to ensure that the earliest written register can be clearly identified when resources are exhausted.

[0175] Accordingly, the synchronization strategy also includes: when all shadow registers are occupied, releasing the shadow register at the head of the writing sequence queue, removing the register identifier of the released shadow register from the head of the queue, and adding it back to the tail of the queue to store the feature information corresponding to the new signal frame moved from the baseband buffer; or, discarding the feature information corresponding to the new signal frame to keep the feature information currently latched in all shadow registers unchanged.

[0176] When the baseband module detects that all shadow registers are occupied and a new signal frame has completed synchronization, the baseband module can choose between the following two operations based on the synchronization strategy:

[0177] First, the shadow register at the head of the write-order queue (i.e., the earliest written register) is released, its corresponding register identifier is removed from the head of the queue, and then reinserted at the tail of the queue. Subsequently, the feature information corresponding to the new signal frame is moved from the baseband buffer to this register, realizing information updating and resource reuse.

[0178] Second, discard the feature information of the new signal frame and keep the data in all shadow registers unchanged to avoid overwriting historical frame information that may not have been read yet.

[0179] The above synchronization strategy not only ensures the availability of the shadow register under resource-constrained conditions, but also provides the possibility of reserving space for specific keyframe data.

[0180] In the above embodiments, by constructing a write order queue for the shadow register, an automatic recycling and update mechanism is implemented when resources are full, significantly improving the reuse rate of feature information storage resources. Simultaneously, the discard option in the strategy can flexibly address the need for priority retention of key frames, thereby enhancing inter-frame data management capabilities and overall controllability, and reducing stability risks caused by processing latency and data conflicts.

[0181] The feature information synchronization method for power communication signal frames provided in this embodiment of the invention can be executed by a feature information synchronization device for power communication signal frames. This embodiment of the invention uses the feature information synchronization device for power communication signal frames executing the feature information synchronization method for power communication signal frames as an example to illustrate the feature information synchronization device for power communication signal frames provided in this embodiment of the invention.

[0182] This invention also provides a feature information synchronization device for power communication signal frames, which is applied to signal receiving equipment.

[0183] Figure 12 This is a schematic diagram of the structure of a power communication signal frame feature information synchronization device provided in some embodiments of the present invention. For example... Figure 12As shown, the feature information synchronization device for the power communication signal frame includes a calculation module 1201, a transfer module 1202, and a synchronization module 1203. Wherein:

[0184] The calculation module 1201 is used to respond to the frame synchronization start signal of the current signal frame, trigger the calculation of the corresponding feature information, and write the feature information into the baseband buffer.

[0185] The transfer module 1202 is used to transfer feature information from the baseband buffer to the shadow register after frame synchronization is completed, so that the processing module can read it later.

[0186] The synchronization module 1203 is used to update the feature information stored in the shadow register according to the synchronization strategy if the frame synchronization completion signal of the next signal frame is detected while the data of the current signal frame stored in the memory module has not been read by the processing module.

[0187] The frame conflict processing apparatus provided in this embodiment of the invention can implement the various processes implemented in each method embodiment and achieve the same technical effect. To avoid repetition, it will not be described again here.

[0188] The frame collision handling device in this embodiment of the invention can be a signal receiving device or a component within the signal receiving device, such as an integrated circuit or a chip. The signal receiving device is a computer device, such as a terminal device.

[0189] Figure 13 This is a schematic diagram of the structure of a signal receiving device provided in some embodiments of the present invention. In some embodiments, such as... Figure 13 As shown, Figure 13 As shown, the signal receiving device 1300 includes a baseband 1301 and a central processing unit 1302. A shadow register is configured in the baseband 1301. Wherein:

[0190] Baseband 1301 is used to respond to the frame synchronization start signal of the current signal frame, trigger the calculation of the corresponding feature information, and write the feature information into the baseband buffer; after frame synchronization is completed, the feature information is moved from the baseband buffer to the shadow register for subsequent reading by the central processing unit.

[0191] The baseband 1301 is also used to update the feature information stored in the shadow register according to the synchronization strategy if the frame synchronization completion signal of the next signal frame is detected while the data stored in the memory module of the current signal frame has not been read by the processing module.

[0192] The central processing unit 1302 is used to read feature information from the shadow register for upper-layer application processing.

[0193] The baseband 1301 corresponds to the baseband module in the aforementioned embodiment, and the central processing unit 1302 corresponds to the processing module in the aforementioned embodiment.

[0194] The signal receiving device 1300 provided in this embodiment of the invention can implement the various processes implemented in the various method embodiments. To avoid repetition, it will not be described again here.

[0195] This invention also provides a non-transitory computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the various processes of the above-described embodiment of the method for synchronizing feature information of power communication signal frames and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0196] The processor is the processor in the computer device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0197] This invention also provides a computer program product, including a computer program that, when executed by a processor, implements the above-described method for synchronizing feature information of power communication signal frames.

[0198] The processor is the processor in the computer device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0199] This invention also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above-described embodiment of the power communication signal frame feature information synchronization method, and can achieve the same technical effect. To avoid repetition, it will not be described again here. It should be understood that the chip mentioned in this invention embodiment can also be called a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0200] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for synchronizing feature information of power communication signal frames, characterized in that, The method includes: In response to the frame synchronization start signal of the current signal frame, the corresponding feature information is calculated and written into the baseband buffer; After frame synchronization is completed, the feature information is moved from the baseband buffer to the shadow register for subsequent reading by the processing module; If, while the data of the current signal frame stored in the memory module has not yet been read by the processing module, a frame synchronization completion signal for the next signal frame is detected, the characteristic information stored in the shadow register is updated according to the synchronization strategy, including: If, while the data of the current signal frame stored in the memory module has not yet been read by the processing module, a frame synchronization completion signal for the next signal frame is detected, the baseband module sets the overflow flag signal. When the overflow flag signal is set, the baseband module performs a reset operation, and the shadow register latches the feature information corresponding to the current signal frame; or If the frame synchronization completion signal of the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module, the baseband module sets the overflow flag signal. Under the condition that the overflow flag signal is set, the shadow register writes the feature information corresponding to the next signal frame to overwrite the feature information corresponding to the current signal frame.

2. The method for synchronizing feature information of power communication signal frames according to claim 1, characterized in that, The synchronization strategy also includes: The baseband module determines the channel quality corresponding to the current signal frame and the next signal frame respectively, and compares the channel quality corresponding to the next signal frame with the channel quality corresponding to the current signal frame to obtain the comparison result. Based on the comparison result, the shadow register latches the feature information corresponding to the current signal frame, or writes the feature information corresponding to the next signal frame to overwrite the feature information corresponding to the current signal frame.

3. The method for synchronizing feature information of power communication signal frames according to claim 1, characterized in that, The shadow register is configured with multiple registers, used to latch feature information corresponding to multiple signal frames respectively; the method further includes: For each signal frame that has completed frame synchronization, an unused shadow register is allocated sequentially, and the feature information corresponding to each signal frame is moved to the allocated shadow register. If the frame synchronization completion signal of the next signal frame is detected before the data of the earliest signal frame containing the feature information is read by the processing module, one or more shadow registers will latch the written feature information according to the synchronization strategy, or one or more shadow registers will write the feature information corresponding to the new signal frame to overwrite the feature information corresponding to the previous signal frame.

4. The method for synchronizing feature information of power communication signal frames according to claim 3, characterized in that, The method further includes: assigning a register identifier to each shadow register and maintaining a write order queue to record the write order of each shadow register; Accordingly, the synchronization strategy also includes: If all shadow registers are occupied, release the shadow register at the head of the write sequence queue, remove the register identifier of the released shadow register from the head of the queue, and add it back to the tail of the queue to store the feature information corresponding to the new signal frame moved from the baseband buffer; or Discard the feature information corresponding to the new signal frame to keep the feature information already latched in all shadow registers unchanged.

5. A device for synchronizing feature information of power communication signal frames, characterized in that, The device includes: The calculation module is used to respond to the frame synchronization start signal of the current signal frame, trigger the calculation of the corresponding feature information, and write the feature information into the baseband buffer; The moving module is used to move the feature information from the baseband buffer to the shadow register after frame synchronization is completed, so that the processing module can read it later. The synchronization module is used to update the feature information stored in the shadow register according to the synchronization strategy if a frame synchronization completion signal for the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module. This includes: if a frame synchronization completion signal for the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module, the baseband module sets up the overflow flag signal; if the overflow flag signal is set, the baseband module performs a reset operation, and the shadow register latches the feature information corresponding to the current signal frame; or, if a frame synchronization completion signal for the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module, the baseband module sets up the overflow flag signal; if the overflow flag signal is set, the shadow register writes the feature information corresponding to the next signal frame to overwrite the feature information corresponding to the current signal frame.

6. A power communication system, characterized in that, The system includes: Signal transmitting equipment for transmitting power communication signals containing continuous signal frames; A signal receiving device is used to receive the power communication signal and execute the feature information synchronization method of the power communication signal frame as described in any one of claims 1-4.

7. A signal receiving device, characterized in that, The signal receiving device includes a baseband and a central processing unit, wherein the baseband is configured with a shadow register; wherein: The baseband is used to respond to the frame synchronization start signal of the current signal frame, trigger the calculation of the corresponding feature information, and write the feature information into the baseband buffer; after frame synchronization is completed, the feature information is moved from the baseband buffer to the shadow register for subsequent reading by the central processing unit. The baseband module is further configured to update the feature information stored in the shadow register according to a synchronization strategy if a frame synchronization completion signal for the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module. This includes: if a frame synchronization completion signal for the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module, the baseband module sets up an overflow flag signal; if the overflow flag signal is set, the baseband module performs a reset operation, and the shadow register latches the feature information corresponding to the current signal frame; or, if a frame synchronization completion signal for the next signal frame is detected while the data of the current signal frame stored in the memory module has not yet been read by the processing module, the baseband module sets up an overflow flag signal; if the overflow flag signal is set, the shadow register writes the feature information corresponding to the next signal frame to overwrite the feature information corresponding to the current signal frame. The central processing unit is used to read feature information from the shadow register for upper-layer application processing.

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