An event-driven fair arbitration readout method for silicon pixel detectors

Abstract

The application provides an event-driven fair arbitration readout method for a silicon pixel detector, which comprises the following steps: an initial single pulse signal is generated by performing asynchronous reset synchronous release processing on a reset signal through a pulse initialization circuit; a round-robin chain is formed by sequentially transmitting the initial single pulse signal bit by bit according to the order of pixels; the address decoding and data encoding of the pixel are triggered under a preset logic, and are transmitted to the next hit pixel; the pixel not hit is directly skipped; after being transmitted to the last pixel, the first pixel is retransmitted after a clock cycle is delayed, so that a closed-loop round-robin mechanism is formed; a Valid signal is generated by performing logical AND operation on the single pulse signal and a FLAG signal, so that the gate only outputs the address and data of the hit pixel, and the output of the last valid pixel is maintained when the pixel is not hit; through the combination of the pulse round-robin, closed-loop feedback and zero compression technologies, the synergy optimization of fairness, efficiency and hardware complexity is realized at the hardware level, and the application lays a foundation for the large-scale application of the silicon pixel detector.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of nuclear electronics pixel detection technology, and particularly relates to an event-driven fair arbitration readout method for a silicon pixel detector. BACKGROUND

[0002] The silicon pixel detector has become a core detection device in modern high-energy physics experiments due to its advantages of high spatial resolution, high counting rate and low power consumption; however, the traditional readout method has significant bottlenecks in fairness, efficiency and hardware complexity in a high current environment.

[0003] The related art usually adopts a rolling shutter readout, a priority readout and a token ring readout mode. Specifically, the rolling shutter readout mode scans all pixels row by row or frame by frame, and data is read regardless of whether it is hit or not. However, this mode has serious data redundancy, takes a long time, and is prone to distortion in a high-speed motion scene, and is more suitable for low-current, low-speed imaging scenes, and has gradually been eliminated. The priority readout mode presets a priority (such as row, column or area priority) according to the pixel position, and the high-priority pixel is read out first. However, when the high-priority pixel is continuously responsive, the low-priority pixel may be blocked for a long time, which cannot meet the full-pixel coverage requirement under a high-current beam, and a complex priority arbitration logic is required, which increases the chip area and power consumption, and is more suitable for medium and low current experiments with low fairness requirements. The token ring readout mode circulates the token among the pixels, and the pixel holding the token can read out data. However, the token transmission path of this mode is fixed, and the delay increases when the pixel array scale is expanded, and is more suitable for medium-scale pixel arrays.

[0004] It can be seen that the existing priority readout mode pursues efficiency at the expense of fairness, and the token ring readout mode takes into account fairness but is limited in efficiency, and cannot simultaneously meet the requirement that all hit pixels need to be read out within a fixed period in a high-current scene. In addition, the rolling shutter and token ring readout do not realize true zero compression, and a large amount of invalid data transmission leads to bandwidth waste and increased dead time. The priority arbitration logic and token transmission circuit increase the chip area and power consumption, and limit the integration of the detector.

[0005] Therefore, there is an urgent need in the art for an event-driven fair arbitration readout method for a silicon pixel detector to solve the above problems. SUMMARY

[0006] The present application aims to provide an event-driven fair arbitration readout method for a silicon pixel detector, which realizes the coordinated optimization of fairness, efficiency and hardware complexity at the hardware level through the technical combination of pulse wheel patrol, closed-loop feedback and zero compression, and lays a foundation for the large-scale application of silicon pixel detectors.

[0007] In one aspect, the application provides an event-driven fair arbitration readout method for a silicon pixel detector, comprising the following steps:

[0008] Step one, asynchronous reset synchronous release processing of the reset signal is performed by a pulse initialization circuit to generate an initial single pulse signal, and the pixel readout process is started;

[0009] Step two, the initial single pulse signal is used as the input signal of the first pixel, and the single pulse signal is sequentially transmitted bit by bit to form a round-robin chain, when the pulse reaches a pixel and the FLAG signal of the pixel is high, the address decoding and data encoding of the pixel are triggered, and the pulse is transmitted to the next hit pixel; the unhit pixel is directly skipped;

[0010] Step three, after the pulse is transmitted to the last pixel, the pulse is retransmitted to the first pixel by delaying one clock cycle through a feedback unit circuit to form a closed-loop round-robin mechanism;

[0011] Step four, a Valid signal is generated by logical AND operation of the single pulse signal and the FLAG signal, and the address and data of the hit pixel are output by the address decoding and data encoding circuit control gate, and the output of the last valid pixel is maintained when it is not hit.

[0012] In another aspect, the application provides a computer device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor executes the computer program to implement the event-driven fair arbitration readout method for a silicon pixel detector.

[0013] In another aspect, the application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the event-driven fair arbitration readout method for a silicon pixel detector.

[0014] Compared with the prior art, the application has the following advantages:

[0015] 1. The application implements event-driven fair arbitration readout, eliminates pixel priority weight through a pulse round-robin transmission mechanism, and enables each hit pixel to be equally accessed in a closed-loop cycle, thereby solving the problem of long waiting time of low-priority pixels when high-priority pixels respond multiple times in the prior art, and being compatible with high and low flux beam applications.

[0016] 2. The application implements data zero compression, only reads out the address and data of the hit pixel, and directly skips the unhit pixel, thereby reducing readout dead time and data volume, and improving data transmission efficiency.

[0017] 3. The hardware structure of the application is relatively simple, through the design of the pulse generation and transmission circuit and the address decoding and data encoding circuit, the circuit complexity and cost are reduced while the function is ensured.

[0018] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art from the description, or can be learned by practice of the application. The objects and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims.

[0019] The technical solutions of the application are further described in detail below with the help of drawings and examples. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings are included to provide a further understanding of the application, and constitute a part of the specification, illustrate the application, and are used to explain the application together with the embodiments of the application, and do not constitute a limitation on the application.

[0021] In the drawings:

[0022] Figure 1 is a flowchart of an event-driven fair arbitration readout method for a silicon pixel detector provided by the application;

[0023] Figure 2 is a timing diagram of the pulse generation and transmission circuit provided by embodiment 1 of the application;

[0024] Figure 3 is a timing diagram of the data encoding and address decoding circuit provided by embodiment 1 of the application;

[0025] Figure 4 is a structural schematic diagram of a computer device provided by embodiment 2 of the application. DETAILED DESCRIPTION

[0026] The preferred embodiments of the application are described below in combination with the drawings, and it should be understood that the preferred embodiments described herein are only used to illustrate and explain the application, and do not limit the application.

[0027] Embodiment 1:

[0028] Please refer to Figures 1-3 The embodiment of the application provides an event-driven fair arbitration readout method for a silicon pixel detector, comprising the following steps:

[0029] Step 1, the reset signal is asynchronously reset and synchronously released by the pulse initialization circuit, an initial single pulse signal Pulse_start is generated, and the pixel readout process is started;

[0030] The pulse initialization circuit includes an asynchronous reset and synchronous release unit composed of two-stage flip-flops. A reset signal Rst_n is generated into a delay reset signal Sync_rst after being synchronously released, and then an initial single pulse signal Pulse_start with a clock cycle width is generated through logical AND operation.

[0031] Specifically, the reset signal Rst_n passes through an asynchronous reset and synchronous release circuit composed of two flip-flops, and outputs a reset signal Sync_rst. The Sync_rst passes through a next-stage flip-flop to output a signal Sync_rst_dly. The Sync_rst_dly signal passes through a NOT gate and is logically ANDed with the signal Sync_rst, thereby generating the initial single pulse signal Pulse_start.

[0032] Step two, the initial single pulse signal Pulse_start is used as the input signal Pulse_in[0] of the first pixel, so that the single pulse signal Pulse_in is sequentially transmitted bit by bit to form a round-robin chain. When the pulse reaches a pixel and the FLAG signal (Hit Flag Signal) of the pixel is high, the address decoding and data encoding of the pixel are triggered, and the pulse is transmitted to the next hit pixel; the un-hit pixel is directly skipped.

[0033] The logic of the pulse transmission is as follows: when the pixel FLAG signal is high and the single pulse signal Pulse_in is low, the output pulse signal Pulse_out is set to high and maintained for one clock cycle, triggering the pixel to read out and then transmit the pulse to the single pulse signal Pulse_in end of the next pixel. The round-robin chain transmission mechanism sequentially reads out the address and data of each hit pixel in the order of pulse transmission when multiple pixels are hit. The readout order is determined by the pulse transmission path and is irrelevant to the priority of the pixel position.

[0034] Specifically, in order to achieve event-driven readout while achieving fair arbitration, the module needs to set the Pulse_out to high when the pixel Flag is high and the Pulse_in is low, and set the Pulse_out to low and maintain it for one clock length when the next clock arrives. In other cases, Pulse_out is equal to Pulse_in.

[0035] Step three, when the pulse is transmitted to the last pixel, the pulse is retransmitted to the first pixel through a feedback unit circuit delayed for one clock cycle, forming a closed-loop round-robin mechanism.

[0036] The feedback unit circuit delays the output pulse signal Pulse_out of the last pixel through two flip-flops, performs a logical AND operation with the initial single pulse signal Pulse_start, and feeds it back to the input signal Pulse_in[0] of the first pixel after a one-clock-cycle delay. The period of the closed-loop polling mechanism is the product of the total number of hit pixels and the processing time of a single pixel, to ensure that each pixel is accessed equally in the loop.

[0037] Specifically, after passing through two flip-flops, the signal Pulse_out[n] is ANDed with the initial single pulse signal and then passed to Pulse_in[0], which realizes the function of passing the single pulse signal to the last pixel n and waiting for one clock cycle before passing the single pulse signal to pixel 0 again.

[0038] In one embodiment, such as Figure 2 As shown, clk is the clock signal, Rst_n is the reset signal, sync_rst is the global reset signal, sync_rst_dly is the delayed reset signal, Pulse_start is the initial single pulse signal, Flag[3:0] is the hit flag signal, and Pulse_in[0] to Pulse_in[3] are single pulse input signals. This embodiment shows the working timing of the pulse generation and transmission circuit of 4 pixels. The reset signal Rst_n is active low. After passing through the asynchronous reset synchronous release circuit, the global reset signal sync_rst is output. After the reset signal is released, sync_rst generates the initial single pulse signal Pulse_start. At the same time, the single pulse signal Pulse_in[0] is initialized. Due to the hit flag signal Flag[3:0] are all low, so the single pulse signal is transmitted from Pulse_in[0] to Pulse_in[3] within one clock cycle, and then transmitted back to Pulse_in[0] after waiting for one clock cycle, and so on; when Flag[0] and Flag[1] of the 0th and 1st pixels are set to high at the same time, the 0th pixel waits for the single pulse signal, Pulse_in[0] is pulled low and Pulse_in[3:1] is pulled high, and after the next rising edge of the clock arrives, Pulse_in[1] is pulled low and lasts for one clock cycle; at this time, Flag[1] is effectively high, so after the next rising edge of the clock arrives, Pulse_in[2] is pulled low and lasts for one clock cycle; this avoids the situation of continuous response of the same pixel;

[0039] Reference Figure 2The signals are synchronized by clock to form a timing chain of "reset→pulse initialization→round transfer→hit trigger→closed-loop feedback", so as to intuitively show how the pulse generation and transfer circuit realizes event-driven and fair arbitration reading out through the interaction of Pulse_in and Flag signals, avoids continuous response of the same pixel, and ensures that each hit pixel is read out in sequence.

[0040] In step four, the Valid signal is generated by logic AND operation of the single pulse signal and the FLAG signal, and the address decoding and data encoding circuit controls the gate to output only the address and data of the hit pixel, and maintains the output of the last valid pixel when not hit.

[0041] In step four, the address decoding and data encoding circuit includes n+1 gates, n+1 AND gates and a flip-flop, which selects the address line and data line of the corresponding pixel through the Valid signal, and realizes zero compression reading out of the information of the pixel not hit. When the Valid signal is invalid, the address decoding and data encoding circuit maintains the address and data output of the last valid pixel.

[0042] Specifically, the main function of the address decoding and data encoding circuit is to realize pixel address decoding and data encoding under the control of the single pulse signal. The data encoding and address encoding circuit are both composed of two n+1 gates, n+1 AND logic gates and a flip-flop. The single pulse signal Pulse_in[n:0] is inverted and ANDed with the Flag[n:0] signal to output Valid[n:0]. This signal is used as the control signal of address decoding and data encoding to control the reading out of the address and data of the corresponding pixel. When any bit of valid[n:0] is high, the address and data information of the corresponding pixel is output at the next clock rising edge. When Valid[n:0] is all low, the address and data information of the last valid pixel is maintained.

[0043] In one embodiment, please refer to Figure 3 Wherein token_in[0] to token_in[3] are single pulse input signals, i.e. Pulse_in[0] to Pulse_in[3], indicating whether the pulse reaches the corresponding pixel. Data is the data bus output, which reflects the data value of the currently selected pixel in real time. Data[0], Data[1] and Data[3] are the specific data values of pixels 0, 1 and 3 when they are hit (in the example, pixel 2 is not hit, and there is no Data[2] output). Addr is the address signal.

[0044] The embodiment is also an example of four-pixel data encoding and address decoding circuit. When no pixel detector is hit, Flag[3:0] are all low, and the single pulse signal is sequentially transmitted from Pulse_in[0] to Pulse_in[3] in one clock cycle, and then returns to Pulse_in[0] after waiting for one clock cycle, and the cycle is executed. When pixels 0, 1, and 3 are hit, Flag[0], Flag[1], and Flag[3] are set to high, and pixel 0 waits for the single pulse signal, and Pulse_in[0] is low. After the next clock rising edge, the address information 00 and the data information Data[0] of pixel 0 are output, and the single pulse signal is transmitted to Pulse_in[1]. After another clock rising edge, the address information 01 and the data information Data[1] of pixel 1 are output, and the single pulse signal is transmitted to Pulse_in[2]. Since pixel 2 is not hit, Flag[2] is low, and the single pulse signal is transmitted to Pulse_in[3], realizing data zero compression. After the next clock rising edge, the address information 11 and the data information Data[3] of pixel 3 are output, and then since no pixel is hit, the address and data information of the last hit pixel 3 are maintained.

[0045] Reference Figure 3 In the no-hit state, Flag[3:0] are all low, and the token_in signal is sequentially pulled low but does not trigger reading out, and Data and Addr maintain the output of the last valid pixel (if never hit, the initial state is maintained). In the hit state (pixels 0, 1, and 3 are hit), Pulse_in[0] is pulled low and Flag[0] is high, and the clock rising edge outputs Addr=00 and Data=Data[0]. Pulse_in[1] is pulled low and Flag[1] is high, and the next clock rising edge outputs Addr=01 and Data=Data[1]. Pulse_in[2] is pulled low but Flag[2] is low, and pixel 2 is skipped, and Pulse_in[0] is transmitted to Pulse_in[3]. Pulse_in[3] is pulled low and Flag[3] is high, and the next clock rising edge outputs Addr=11 and Data=Data[3]. After all hit pixels are read out, Data and Addr maintain the output of pixel 3 until a new hit event occurs.

[0046] The signals are synchronized by the clock, which shows how the data encoding and address decoding circuit generates the Valid control signal using the Pulse_in and Flag signals, realizes the address and data gating output of the hit pixel, and skips the un-hit pixel through the "zero compression" mechanism, while maintaining the last valid data when there is no new hit event, ensuring the efficiency and accuracy of data transmission.

[0047] Embodiment 2

[0048] In an exemplary embodiment, a computer device, which can be a server or a terminal, is provided, and an internal structure diagram of the computer device can be as shown in FIG. 1. Figure 4 The computer device includes a processor, a memory, an input / output interface (I / O) and a communication interface. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The database of the computer device is configured to store vertical observation data. The input / output interface of the computer device is configured to exchange information between the processor and external devices. The communication interface of the computer device is configured to communicate with external terminals through a network connection. The computer program is executed by the processor to implement a greenhouse gas source analysis method.

[0049] Those skilled in the art can understand that Figure 4 The structure shown in FIG. 1 is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0050] In an exemplary embodiment, a computer device is also provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the above-mentioned method embodiments.

[0051] In an exemplary embodiment, a computer readable storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the above-mentioned method embodiments.

[0052] In an exemplary embodiment, a computer program product is provided, which includes a computer program. The computer program is executed by a processor to implement the above-mentioned method embodiments.

[0053] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in the present application are all information and data authorized by the user or authorized by all parties, and the collection, use and processing of the related data need to comply with relevant regulations.

[0054] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium. When the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to a memory, a database, or other medium used in the embodiments provided by the present application can include at least one of a non-volatile memory and a volatile memory. The non-volatile memory can include a read-only memory (ROM), a magnetic tape, a floppy disk, a flash memory, an optical storage, a high-density embedded non-volatile memory, a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FRAM), a phase change memory (PCM), a graphene memory, and the like. The volatile memory can include a random access memory (RAM) or an external cache memory, and the like. As an illustration but not limitation, the RAM can be in various forms, such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), and the like.

[0055] The database involved in the embodiments provided by the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a blockchain, and the like, without being limited thereto. The processor involved in the embodiments provided by the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, and the like, without being limited thereto.

[0056] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An event-driven fair arbitration readout method for silicon pixel detectors, characterized in that, Includes the following steps: Step 1: The reset signal is asynchronously reset and synchronously released through the pulse initialization circuit to generate an initial single pulse signal and start the pixel readout process. Step 2: The initial single pulse signal is used as the input signal for the first pixel, so that the single pulse signal is passed bit by bit in the pixel order to form a round-robin chain. When the pulse reaches a certain pixel and the FLAG signal of that pixel is high, the address decoding and data encoding of that pixel are triggered, and the pulse is passed to the next pixel that is hit; pixels that are not hit are skipped directly. Step 3: After the pulse is transmitted to the last pixel, it is delayed by one clock cycle through the feedback unit circuit and then transmitted back to the first pixel, forming a closed-loop polling mechanism. Step four: Generate a Valid signal by performing a logical AND operation between the single pulse signal and the FLAG signal. Control the selector through the address decoding and data encoding circuit to output only the address and data of the hit pixel. If the pixel is not hit, retain the output of the previous valid pixel.

2. The event-driven fair arbitration readout method for silicon pixel detectors according to claim 1, characterized in that, In step one, the pulse initialization circuit includes an asynchronous reset and synchronous release unit composed of two flip-flops. After the reset signal is synchronously released, a delayed reset signal is generated, and then the initial single pulse signal with a width of one clock cycle is generated through a logical AND operation.

3. The event-driven fair arbitration readout method for silicon pixel detectors according to claim 1, characterized in that, In step two, the logic for pulse transmission is as follows: When the pixel FLAG signal is high and the single pulse signal is low, the output pulse signal is set to high and maintained for one clock cycle. After triggering the readout of the pixel, the pulse is passed to the single pulse signal terminal of the next pixel.

4. The event-driven fair arbitration readout method for silicon pixel detectors according to claim 1, characterized in that, In step three, the feedback unit circuit delays the output pulse signal of the last pixel by two flip-flops, performs a logical AND operation with the initial single pulse signal, and feeds it back to the input signal terminal of the first pixel after a delay of one clock cycle.

5. The event-driven fair arbitration readout method for silicon pixel detectors according to claim 1, characterized in that, In step four, the address decoding and data encoding circuit includes an n+1 selector, n+1 AND gates and flip-flops. The Valid signal selects the address line and data line of the corresponding pixel to achieve zero-compression readout of the information of the unhit pixel.

6. The event-driven fair arbitration readout method for silicon pixel detectors according to claim 3, characterized in that, In step two, when multiple pixels are hit, the polling chain transmission mechanism reads out the address and data of each hit pixel in the order of pulse transmission. The reading order is determined by the pulse transmission path and is not related to the priority of the pixel position.

7. The event-driven fair arbitration readout method for silicon pixel detectors according to claim 5, characterized in that, In step four, when the Valid signal is invalid, the address decoding and data encoding circuit maintains the address and data output of the previous valid pixel.

8. The event-driven fair arbitration readout method for silicon pixel detectors according to claim 1, characterized in that, In step three, the period of the closed-loop polling mechanism is the product of the total number of hit pixels and the processing time of a single pixel, to ensure that each pixel is accessed equally in the loop.

9. A computer device, comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that the processor executes the computer program to implement the event-driven fair arbitration readout method for a silicon pixel detector as described in any one of claims 1-8.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the event-driven fair arbitration readout method for silicon pixel detectors as described in any one of claims 1-8.

Images