Image sensor and control method thereof, pixel arrangement structure and electronic equipment

Abstract

The invention provides an image sensor and a control method thereof, a pixel arrangement structure and electronic equipment, the image sensor comprises a photosensitive unit, a reset unit, a readout unit and a decoupling unit, the reset unit and the photosensitive unit are coupled to a floating diffusion node, the decoupling unit is arranged corresponding to a signal fluctuation node in a pixel block, and the readout unit is arranged corresponding to the signal fluctuation node in the pixel block. Adjusting the to-be-read signal transferred to the floating diffusion node and / or adjusting the output data signal of the pixel block based on the signal fluctuation node; the read-out unit reads out a signal corresponding to the floating diffusion node. According to the image sensor, through the design of the decoupling unit, the influence on a signal fluctuation node can be adjusted, the accuracy of image data is improved, especially in a pixel circuit with an overflow signal, based on the design of the decoupling unit, the accuracy of a finally output data signal can be effectively improved, and then the image quality is optimized; and device performance is improved.

Description

Technical Field

[0001] The present invention belongs to the field of image acquisition technology, and in particular relates to an image sensor and a control method thereof, a pixel arrangement structure, and an electronic device. Background Art

[0002] Image sensors are a crucial component of digital cameras. Depending on the component, they can be categorized into two main types: CCD (charge-coupled device) and CMOS (metal oxide semiconductor). With the continuous advancement of CMOS integrated circuit manufacturing processes, particularly the design and manufacturing of CMOS image sensors, CMOS image sensors have gradually replaced CCD image sensors as the mainstream. CMOS image sensors offer advantages such as low voltage, low power consumption, low cost, and high integration, making them valuable in applications such as machine vision, consumer electronics, high-definition surveillance, and medical imaging.

[0003] During CMOS image sensor operation, pixel circuits often contain nodes with fluctuating signals. These nodes correspond to the final readout signal. Therefore, any impact on the signals at these nodes can ultimately affect the accuracy of the readout data and, consequently, image quality. Furthermore, to increase dynamic range, existing techniques exist for processing overflow signals (LOFIC). However, due to the addition of LOFIC capacitance nodes, this technique increases the number of high-impedance nodes in the pixel, necessitating careful shielding between signals.

[0004] Therefore, it is necessary to provide an image sensor and a control method thereof, a pixel arrangement structure, and an electronic device to solve the problems in the prior art such as signal crosstalk that ultimately affects image quality. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the object of the present invention is to provide an image sensor and its control method, pixel arrangement structure, and electronic device, which are used to solve the problems of existing image sensors, especially pixel designs with overflow nodes, such as signal crosstalk that ultimately affects image quality.

[0006] To achieve the above objectives and other related objectives, the present invention provides an image sensor comprising a plurality of pixel blocks arranged in an array, wherein the pixel blocks include a photosensitive unit, a reset unit, a readout unit, and a decoupling unit, wherein: the reset unit is coupled to a floating diffusion node and resets at least one of the floating diffusion node and the photosensitive unit; the photosensitive unit is coupled to the floating diffusion node and generates a charge signal based on photoelectric conversion, stores the charge signal, and transfers the charge signal to the floating diffusion node;

[0007] The decoupling unit is provided corresponding to the signal fluctuation node in the pixel block to adjust the signal to be read out transferred to the floating diffusion node based on the signal fluctuation node and / or adjust the output data signal of the pixel block based on the signal fluctuation node, wherein the signal to be read out of the floating diffusion node forms a decoupled signal corresponding to the signal to be read out when adjusted by the signal fluctuation node;

[0008] The readout unit is coupled to the floating diffusion node to read out a signal corresponding to the floating diffusion node.

[0009] Optionally, the pixel block also includes an overflow unit, which is coupled to the floating diffusion node, and the photosensitive unit generates a first charge signal and a second charge signal based on photoelectric conversion, the photosensitive unit stores the first charge signal and transfers the first charge signal to the floating diffusion node, and the overflow unit stores the second charge signal and transfers the second charge signal to the floating diffusion node.

[0010] Optionally, the overflow unit includes a shared path, which is coupled to the photosensitive unit and the floating diffusion node to store the second charge signal based on the shared path and transfer the second charge signal to the floating diffusion node for reading based on the shared path.

[0011] Optionally, the overflow unit includes an overflow path and a quantization path, the overflow path is coupled to the photosensitive unit, the quantization path is coupled to the floating diffusion node, the second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node for reading based on the quantization path.

[0012] Optionally, the pixel block includes a gain control unit coupled to the floating diffusion node, cooperating with the floating diffusion node to form a modulation storage area and forming a voltage signal corresponding to the charge signal based on the modulation storage area;

[0013] When the pixel block includes an overflow unit, the overflow unit is coupled to at least one gain node of the gain control unit to perform readout based on the gain node and the floating diffusion node.

[0014] Optionally, the decoupling unit includes at least two decoupling sub-units, each provided to correspond to the same signal fluctuation node. Optionally, the decoupling unit includes a decoupling transistor coupled to the signal fluctuation node, a control terminal receiving a decoupling control signal, and the decoupling transistor regulating the corresponding signal fluctuation node based on the decoupling control signal. Optionally, the decoupling unit includes an additional decoupling structure electrically connected to the signal fluctuation node and / or the control terminal of the decoupling unit to regulate the corresponding signal fluctuation node in a parasitic manner.

[0015] Optionally, the decoupling transistor further includes a first terminal and a second terminal, the first terminal being electrically connected to the signal fluctuation node, and the second terminal being left floating. Optionally, the first terminal and / or the second terminal of the decoupling transistor are shared with adjacent nodes using node multiplexing. Optionally, the decoupling control signal is a variable voltage signal or a constant voltage signal.

[0016] Optionally, the signal fluctuation node includes a high-impedance node of the pixel block, the high-impedance node includes a second charge signal receiving node corresponding to the overflow unit, the decoupling unit is coupled to the receiving node, and / or the high-impedance node includes at least one gain node of the gain control unit, and the decoupling unit is coupled to the gain node.

[0017] Optionally, the signal fluctuation node comprises a signal output node of a pixel block, configured to output at least a data signal of the pixel block, and the decoupling unit is coupled to the signal output node. Optionally, the image sensor comprises a pixel array comprising a plurality of pixel blocks arranged in an array, and a node sharing structure is provided between the gain control units of at least two pixel blocks. Optionally, a shared decoupling unit is provided between adjacent pixel blocks.

[0018] Optionally, the pixel block includes at least one of a first decoupling transistor, a second decoupling transistor and a third decoupling transistor, the first decoupling transistor is set corresponding to the signal output node, the second decoupling transistor is set corresponding to the second charge signal receiving node, and the third decoupling transistor is set corresponding to the gain node.

[0019] Optionally, corresponding decoupling transistors in adjacent pixel blocks are shared to form the shared decoupling unit.

[0020] Optionally, the third decoupling transistor includes a first sub-decoupling transistor and a second sub-decoupling transistor, the first sub-decoupling transistor is arranged on one side of the gain control transistor of the gain control unit, and the second sub-decoupling transistor is arranged on one side of the reset unit electrically connected to the gain control unit, the first sub-decoupling transistor and the second decoupling transistor of the adjacent pixel block are set as a first shared decoupling transistor, and the second sub-decoupling transistor and the first decoupling transistor of the adjacent pixel block are set as a second shared decoupling transistor.

[0021] Optionally, the pixel block group having the node sharing structure includes a common reset unit, and the common reset unit is provided in at least one pixel block of the pixel block group.

[0022] Optionally, the pixel block further includes an intra-pixel isolation structure, which is arranged on a side of the floating diffusion node to at least achieve isolation of the decoupling signal of the floating diffusion node.

[0023] The present application also provides a pixel arrangement structure, which is suitable for an image sensor as described in any one of the above-mentioned schemes, and can also be selected as a transistor for a pixel circuit of other image sensors arranged based on the pixel structure. The pixel arrangement structure includes: a pixel block area, including a photosensitive unit area and a transistor arrangement area; each of the photosensitive unit areas is arranged in an array corresponding to the pixel array, and the transistor arrangement area includes a first area and a second area arranged in an intersecting manner, and the decoupling unit is arranged in the first area and / or the second area.

[0024] Optionally, the decoupling unit is arranged between the transistor arrangement areas of adjacent pixel blocks.

[0025] Optionally, the photosensitive unit includes at least one photosensitive element and a transfer transistor, the transistor arrangement area is at least arranged inside the pixel block area, and the transistor arrangement area extends from the center of the pixel block area to form the first area and the second area, wherein the source follower transistor is located at the center of the pixel block area, and the floating diffusion point includes a first sub-floating diffusion node and a second sub-floating diffusion node located in the first area and arranged on both sides of the source follower transistor.

[0026] Optionally, the overflow unit includes an overflow quantization transistor, the gain control unit includes a gain control transistor, the reset unit includes a reset transistor, and the readout unit also includes a pixel selection transistor. The gain control transistor and the overflow quantization transistor are located in the first region and are respectively located on the side of the two sub-floating diffusion nodes away from the source follower transistor, or are located in the first region and on the side of one of the two sub-floating diffusion nodes away from the source follower transistor. The reset transistor and the pixel selection transistor are located in the second region and on both sides of the source follower transistor.

[0027] Optionally, a first shared decoupling transistor and a second shared decoupling transistor are disposed between transistor arrangement areas of adjacent pixel blocks. Optionally, a decoupling unit is disposed between the floating diffusion node and the transistor arrangement area of ​​the adjacent pixel block. Optionally, the pixel block further includes an intra-pixel isolation structure disposed to the side of the floating diffusion node, the intra-pixel isolation structure being at least one of shallow trench isolation and doping isolation.

[0028] The present application also provides an electronic device, comprising an image sensor as described in any one of the above solutions, and / or comprising a pixel arrangement structure as described in any one of the above solutions.

[0029] The present application also provides a method for controlling the image sensor according to any one of the above solutions, the method comprising the following steps:

[0030] A decoupling control signal is provided to the decoupling unit, and a data signal generated by the photosensitive unit is at least read out based on the floating diffusion node, where the data signal includes a signal adjusted via a signal fluctuation node.

[0031] Optionally, when the decoupling unit includes a decoupling transistor, the corresponding decoupling transistor is controlled to be turned off based on a decoupling control signal during signal transfer at the signal fluctuation node. Optionally, the decoupling transistor is controlled to be turned off during at least one of idle, global reset, exposure and overflow, and readout phases.

[0032] As described above, the image sensor and its control method, pixel arrangement structure, and electronic device of the present invention have the following beneficial effects: the image sensor of the present invention can adjust the influence of the signal fluctuation node through the design of the decoupling unit, thereby adjusting the accuracy of the image data directly or indirectly output from the fluctuation node. In particular, in a pixel circuit with an overflow signal, based on the design of the decoupling unit, the accuracy of the final output data signal can be effectively improved, thereby optimizing image quality and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 Shown is the basic structural block diagram of an image sensor system.

[0034] Figure 2 Shown is a schematic diagram of a pixel circuit of an image sensor.

[0035] Figure 3 A pixel circuit diagram showing a first example of a pixel block provided in an embodiment of the present application is shown.

[0036] Figure 4 A pixel circuit diagram showing a second example of a pixel block provided in an embodiment of the present application is shown.

[0037] Figure 5 A pixel circuit diagram showing a third example of a pixel block provided in an embodiment of the present application is shown.

[0038] Figure 6 A pixel circuit diagram showing a fourth example of a pixel block provided in an embodiment of the present application is shown.

[0039] Figure 7 A pixel circuit diagram showing a fifth example of a pixel block provided in an embodiment of the present application is shown.

[0040] Figure 8 A pixel circuit diagram of a pixel block with a split decoupling unit provided by an embodiment of the present application is shown.

[0041] Figure 9 Shown is a partial schematic diagram of an array with a node sharing structure provided by an embodiment of the present application.

[0042] Figure 10 Shown is a partial schematic diagram of an array with shared decoupling units provided by an embodiment of the present application.

[0043] Figure 11 Shown is a partial schematic diagram of an array with a shared reset unit provided by an embodiment of the present application.

[0044] Figure 12 Shown is another schematic diagram of an array with shared decoupling units provided by an embodiment of the present application.

[0045] Figure 13 Shown is a schematic diagram of a pixel arrangement structure provided by an embodiment of the present application.

[0046] Figure 14 Shown is a schematic diagram of another pixel arrangement structure provided by an embodiment of the present application.

[0047] Figure 15 The display is an operation example of the image sensor control method provided by an embodiment of the present application.

[0048] Component number description

[0049] 110 - photosensitive unit; 120 - reset unit; 130 - readout unit; 140 - decoupling unit; 150 - gain control unit; 160 - overflow unit; 170 - node sharing structure; 180, 190 - intra-pixel isolation structure. DETAILED DESCRIPTION

[0050] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0051] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0052] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments. For example, when describing embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of illustration. These schematic views are merely examples and should not limit the scope of protection of the present invention. In actual production, three-dimensional dimensions, including length, width, and depth, should be included.

[0053] For ease of description, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or one or more intervening layers may exist. A structure described as having a first feature "above" a second feature may include embodiments in which the first and second features are formed in direct contact, or may include embodiments in which another feature is formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, "coupled" means that the connection may be direct or indirect.

[0054] The diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components relevant to the present invention and are not drawn to the exact number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be varied arbitrarily, and the component layout may be more complex. The present invention will be described in detail below with reference to the accompanying drawings.

[0055] Figure 1 The following diagram shows the basic structure of an image sensor system. The image sensor includes a readout circuit and a control circuit connected to a pixel array. Furthermore, a functional logic unit is connected to the readout circuit. The readout circuit and the control circuit are connected to a status register to control the pixel array. The pixel array includes multiple pixels (P1, P2, P3) arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). The pixel signals output by the pixel array are transmitted to the readout circuit via column lines. In some applications, after the pixels acquire image data, they are read out using the readout mode specified by the status register and then transmitted to the functional logic unit. In specific implementations, the readout circuit may include an analog-to-digital converter (ADC) circuit and other circuits.

[0056] In some applications, the status register may include a programmable selection system to determine whether the readout system is exposed and read out using a rolling shutter mode or a global shutter mode. The functional logic unit may store raw image data or image data after image processing. In some implementations, the readout circuit may read out image data one row at a time along the readout column line. Of course, other methods may also be used to read out image data. The operation of the control circuit can be determined by the current setting of the status register. For example, the control circuit generates a shutter signal for controlling image acquisition. In some applications, this shutter signal can be a global exposure signal so that all pixels of the pixel array simultaneously acquire their image data through a single acquisition window. In other applications, this shutter signal can also be a rolling exposure signal so that the pixels of each pixel row of the pixel array are continuously exposed and read out through the acquisition window.

[0057] Figure 2 Shown is a schematic diagram of a pixel unit in an image sensor. Figure 2 As shown in FIG, each pixel unit includes a photoelectric conversion element (e.g., a photodiode PD) and a pixel circuit (as shown in the transistor in the dotted box in the figure). The photodiode can be a buried photodiode (PPD) used in current image sensors. In one embodiment, the pixel circuit includes a reset transistor (RST), a source follower transistor (SF), and a pixel select transistor (RS), which are connected to the transistors shown in FIG. Figure 2 The transfer transistor (TX) and photodiode shown in . In a stacked structure application example, the pixel circuit includes a reset transistor, a source follower transistor, a pixel selection transistor disposed on a first circuit chip, and also includes a transfer transistor disposed on a second circuit chip, and the photodiode in the second circuit chip is connected to other transistors in the first circuit chip based on the transfer transistor. In a further application example, the pixel circuit may further include a gain control transistor (DCG) connected between a floating diffusion region (FD) and the reset transistor. During operation, the photoelectric conversion element generates photocharges in response to incident light during exposure, the transfer transistor is connected to a transfer signal, which controls the transfer transistor to transfer the charge accumulated in the photoelectric conversion element to the floating diffusion region, the reset transistor is connected between a power supply voltage and the floating diffusion region, responds to the reset signal to reset the sensor pixel circuit (for example, discharges or charges the floating diffusion region and the photodiode to the current voltage), the floating diffusion region is connected to the gate of the source follower transistor, the source follower transistor is connected between the power supply voltage and the pixel selection transistor, responds to the potential of the floating diffusion region and outputs it, the pixel selection transistor is connected to the source follower transistor and the bit line, responds to the pixel selection control signal to implement pixel selection readout and outputs it to the readout column.

[0058] However, during the operation of existing image sensors, there are often nodes with signal fluctuations in the pixel circuit. These nodes correspond to the final signal readout. Therefore, the influence on the signals at these nodes will eventually affect the imaging quality. In addition, in order to increase the dynamic range, the prior art designs nodes for storing overflow signals. For pixel circuits with overflow signal storage nodes, due to the addition of LOFIC capacitor nodes (storing overflow charges), there are more high-resistance nodes in the pixel, more adjacent nodes with potential barriers in the pixel circuit, and more signal fluctuation nodes. Therefore, signal shielding needs to be handled with care. In addition, a larger low-gain capacitance can be achieved by merging nodes (combining) to obtain a smaller low-gain value. A larger low-gain capacitance can also be achieved in pixels with overflow signals by merging nodes. In order to achieve a larger LCG capacitance in LOFIC pixels by combining LCG, the corresponding pixel circuit is often designed. In the circuit of this design, there will also be fluctuation nodes and the problem of signal fluctuation nodes being affected. The present invention can effectively improve the above problems through the design of a decoupling unit.

[0059] Example 1:

[0060] See also Figures 3 to 6 As shown, this embodiment provides an image sensor. Figure 3 For example, in this embodiment, the image sensor includes a plurality of pixel blocks 100 arranged in an array. The pixel block 100 includes a photosensitive unit 110, a reset unit 120, a readout unit 130, and decoupling units 140_1 and 140_2, wherein:

[0061] The reset unit 120 is coupled to the floating diffusion node FD, and is used to reset at least one of the floating diffusion node FD and the photosensitive unit 110; the corresponding reset node can be selected according to actual operation requirements; as an example, the reset unit 120 includes a reset transistor M12, which can be an NMOS tube, the control end receives the reset control signal RST, the first end is coupled to the first power supply potential, and the second end is coupled to the floating diffusion node FD.

[0062] The photosensitive unit 110 is coupled to the floating diffusion node FD. The photosensitive unit 110 generates a charge signal based on photoelectric conversion to obtain information representing a scene image. The photosensitive unit 110 can also store the generated charge signal and further transfer the charge signal generated by photoelectric conversion to the floating diffusion node FD.

[0063] As an example, the photosensitive unit 110 includes at least one photosensitive element PD and at least one transfer transistor M11, which may correspond to each other. The transfer transistor M11 may be an NMOS transistor, with a control terminal receiving a transmission control signal TX, a first terminal coupled to a floating diffusion node FD, a second terminal coupled to a first terminal of the photosensitive element PD, and a second terminal coupled to a reference potential, which may be a ground potential or a negative potential.

[0064] The decoupling units 140_1 and 140_2 correspond to the signal fluctuation node settings in the pixel block 110. The decoupling units 140_1 and 140_2 adjust the final pixel output signal based on the signal fluctuation node. The decoupling unit can adjust the output data signal of the pixel block 100 based on the signal fluctuation node. The decoupling unit can also adjust the signal to be read out transferred to the floating diffusion node FD based on the signal fluctuation node. The signal to be read out of the floating diffusion node FD is adjusted via the signal fluctuation node to obtain a decoupled signal corresponding to the signal to be read out.

[0065] The readout unit 130 is coupled to the floating diffusion node FD, and reads out at least the corresponding voltage signal. That is, the readout unit 130 reads out the decoupled signal obtained by adjusting the signal fluctuation node by the decoupling unit from the corresponding position of the floating diffusion node FD, or directly reads out the signal to be read out at the corresponding position of the floating diffusion node FD.

[0066] As an example, the readout unit 130 includes a source follower transistor M13 and a select transistor M14; the control terminal of the source follower transistor M13 is coupled to the floating diffusion node FD, the first terminal is coupled to the second power supply potential, and the second terminal is coupled to the first terminal of the select transistor M14; the control terminal of the select transistor M14 receives a selection signal SEL, and the second terminal is coupled to the column line BIT. In one implementation, the source follower transistor M13 includes an NMOS transistor, and the select transistor M14 includes an NMOS transistor. In this case, the gate of the source follower transistor M13 is connected to the floating diffusion node FD, the drain is connected to the second power supply potential, and the source is connected to the drain of the select transistor M14. The gate of the select transistor M14 receives the selection signal SEL, and the source is connected to the column line BIT. The second power supply potential is generally the same as the first power supply potential, both being operating voltage potentials, and can also be different, such as always being a high potential.

[0067] In one example, the signal fluctuation node can be a signal output node of the pixel block, which is used to output the signal to be read corresponding to the floating diffusion node FD, and the decoupling unit is coupled to the signal output node; the signal fluctuation node can also be a high-resistance node of the pixel block, which can be an overflow signal (the second charge signal below) receiving node corresponding to the overflow unit, and the decoupling unit is coupled to the receiving node, or it can be at least one gain node corresponding to the gain control unit, and the decoupling unit is coupled to the gain node, for example, it can be a high-gain node or a low-gain node formed by the gain control unit to adjust the influence on the corresponding node.

[0068] Specifically, image sensors often have nodes where signals fluctuate during operation. That is, at these nodes, there are changes in signals, generation and resetting of charge and voltage signals, flow of charge signals, and rise and fall of voltage signals. When the signals that are finally read out flow through these nodes, they are inevitably subject to crosstalk from other signals at the corresponding nodes, thereby affecting the final signal readout.

[0069] For example, for a node that outputs a signal to a bit line BIT, the node is in a closed state before the signal is read out and is in a conducting state during the signal read out. If the signal on the node is interfered by other signals, the accuracy of the image data finally outputted will be affected. The node may be the source of a pixel selection transistor. In this embodiment, see Figure 3 As shown, a decoupling unit 140_1 is provided at the bit line output, i.e., the signal output node of the pixel circuit, to adjust the signal of the fluctuating node, reduce the crosstalk of the node signal from other node signals, improve the accuracy of signal reading, and improve the imaging quality of the image sensor.

[0070] Continue reading Figure 3 As shown, in one example, the pixel block 100 further includes an overflow unit 150, which is coupled to the floating diffusion node FD, either directly or through another transistor. The photosensitive unit 110 generates a first charge signal and a second charge signal based on photoelectric conversion. The photosensitive unit 110 stores the first charge signal and transfers it to the floating diffusion node FD, and the overflow unit 150 stores the second charge signal and transfers it to the floating diffusion node FD. In this embodiment, the overflow unit 150 is coupled to the floating diffusion node FD such that the overflow unit 150 is directly connected to the floating diffusion node FD.

[0071] In combination with actual application scenarios, the first charge signal refers to the charge signal corresponding to the potential well portion, and the second charge signal refers to the charge signal corresponding to the overflow portion after the charge exceeds the potential well; when the amount of charge sensed by the photosensitive unit 110 has not reached the overflow state, the charge signal converted therefrom only includes the first charge signal, which is stored in the photosensitive unit 110. At this time, it can be considered that the second charge signal is zero; when the amount of charge sensed by the photosensitive unit 110 reaches the overflow state, the charge signal converted therefrom includes the first charge signal and the second charge signal, wherein the first charge signal is stored in the photosensitive unit 110, and the second charge signal overflows outside the photosensitive unit 110 and is stored in the overflow unit 150 based on the overflow path. In some applications, the first charge signal can also be defined as the potential well charge signal, and the second charge signal can be defined as the overflow charge signal.

[0072] Specifically, this embodiment has an overflow unit 150. During the exposure process, the charge signal is transferred from the photosensitive unit 110 to the storage element of the overflow unit 150. There is a corresponding node where the charge transfer is stored. There are signal fluctuations in the operation of the image sensor. Of course, during the readout process of the charge signal in the storage element, the node changes from closed to open, and there are also potential changes and signal fluctuations. In addition, during the operation of the image sensor, the overflow unit may also have other fluctuations. In this embodiment, see Figure 3 As shown, a decoupling unit 140_2 is provided corresponding to the signal fluctuation node in the overflow unit 150 to adjust the signal of the fluctuation node, reduce the crosstalk suffered by the node signal, and improve the accuracy of signal reading.

[0073] See also Figures 4 to 6 As shown, in one example, pixel blocks 200, 300_1, and 300_2 further include a gain control unit 160. The gain control unit 160 is coupled to the floating diffusion node FD to form a modulation storage region with the floating diffusion node FD and to generate a voltage signal corresponding to the charge signal based on the modulation storage region. In this embodiment, the gain control unit is coupled between the floating diffusion node FD and the reset unit 120. The gain control unit switches between different gain modes based on the modulation storage region, such as switching between a low conversion gain (LCG) mode and a high conversion gain (HCG) mode. Of course, multiple intermediate gain modes may also exist.

[0074] When the pixel block 200 includes the overflow unit 150, the overflow unit 150 is coupled to at least one gain node of the gain control unit 160 to read out the signal based on the selected coupled gain node and the floating diffusion node FD. Figure 4 As shown, the overflow unit 150 is connected to the high gain node of the gain control unit 160. In this example, the gain control unit 160 and the overflow unit 150 are directly connected to the floating diffusion node FD. Figure 5 and Figure 6 As shown, the overflow unit 150 is connected to the low gain node of the gain control unit 160, and the gain control unit 160 is connected to the floating diffusion node FD, that is, the overflow unit 150 is directly connected to the gain control unit 160, and then coupled to the floating diffusion node FD via the gain control unit.

[0075] It should be noted that the gain control unit 160 can form different gains, that is, correspondingly provide quantization nodes with different capacitance values, thereby cooperating with the floating diffusion node FD to form different modulation storage areas, and quantize the signal transferred to the node based on the resulting modulation storage area. It can be considered that there is a quantization node with the smallest capacity, called the high-gain (HCG) quantization node, and a quantization node with the largest capacity, called the low-gain (LCG) quantization node. Of course, there can also be at least one quantization node with an intermediate gain, corresponding to a node storage capacity located between the high-gain and low-gain quantization nodes. For example, multiple gains can be formed by providing at least two gain transistors based on their respective source and drain.

[0076] Specifically, in this embodiment, there is a gain control unit 160. During the signal reading process, quantization can be performed by changing the capacitance to form different modulation storage areas. For example, when the low-gain node is turned from off to on, the charge signal in the photosensitive unit 110 is transferred to the modulation storage area formed based on the low-gain node, so that the potential of the node changes and the signal fluctuates. In this embodiment, see Figure 4 As shown, a decoupling unit 140_3 is provided at the signal fluctuation node in the corresponding gain control unit 160 to adjust the signal of the fluctuation node, reduce the crosstalk suffered by the node signal, and improve the accuracy of signal reading.

[0077] Specifically, a decoupling unit is provided corresponding to at least one gain node of the gain control unit 160, and may be provided at a low gain node of the gain control unit 160, such as Figure 4-6 As shown, decoupling units can also be provided at both the low gain node and the high gain node of the gain control unit 160, such as Figure 6 As shown in the figure, a decoupling unit 140_3 is provided at a low-gain node, and a decoupling unit 140_3s is provided at a high-gain node.

[0078] In one implementation, Figures 3 to 6 As shown, the overflow unit 150 includes a shared path coupled to the photosensitive unit 110 and the floating diffusion node FD to store the second charge signal based on the shared path and transfer the second charge signal to the floating diffusion node FD for reading based on the shared path.

[0079] As an example, the overflow unit 150 includes an overflow quantization transistor M16 and a memory device C. The control terminal of the overflow quantization transistor M16 receives the overflow quantization control signal OF_CTL, and the first terminal can be coupled to the high gain quantization node of the gain control unit, such as the second terminal of the gain control transistor M18, which can also be considered to be coupled to the floating diffusion node FD, such as Figure 3 and Figure 4 As shown, the second end is coupled to the first end of the memory device; the second end of the memory device is coupled to the reference potential Vc, such as the ground potential; in addition, the first end of the overflow quantization transistor M16 can also be coupled to the low gain quantization node of the gain control unit, such as the first end of the gain control transistor M18, such as Figure 5 and Figure 6 In the pixel blocks 100, 200, 300_1, and 300_2, the path where the overflow quantization transistor M16 is located is a common path for receiving and outputting the second charge signal.

[0080] In a specific example, the storage device includes a capacitor device C, the overflow quantization transistor M16 includes an NMOS tube, the gate of the overflow quantization transistor M16 receives the overflow quantization control signal OF_CTL, the drain is connected to the drain of the gain control transistor M18 or the floating diffusion point FD, and the source is connected to the first end of the capacitor device C.

[0081] Specifically, in this example, the node between the overflow quantization transistor M16 and the memory device serves as a signal fluctuation node, and a decoupling unit 140_2 is provided corresponding to the node to adjust the signal of the fluctuation node.

[0082] In another implementation, Figure 7 As shown, for pixel block 400, the overflow unit 150 includes an overflow path and a quantization path, the overflow path is coupled to the photosensitive unit 110, and the quantization path is coupled to the floating diffusion node FD, wherein the second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node FD for reading based on the quantization path;

[0083] As an example, the overflow unit 150 includes an overflow transistor M22, a quantization transistor M16 and a storage device; the control end of the overflow transistor M22 receives an overflow control signal OFG, the first end is coupled to the photosensitive unit 110, such as, coupled to the first end of the photosensitive element PD, and the second end is coupled to the first end of the storage device; the control end of the quantization transistor M16 receives a quantization control signal OF_CTL, the first end is connected to the floating diffusion node FD, and in a further example, it can be connected to the floating diffusion node FD through the gain control unit 150, and the second end is coupled to the first end of the storage device; the second end of the storage device is coupled to the reference potential Vc, such as the ground potential; wherein, the path where the overflow transistor M20 is located is the overflow path, and the path where the quantization transistor M16 is located is the quantization path.

[0084] In a specific example, the storage device is a capacitor C, the overflow transistor M22 is an NMOS transistor, the quantization transistor M16 is an NMOS transistor, the gate of the overflow transistor M22 receives an overflow control signal OFG, the drain is connected to one end of the photosensitive element PD, and the source is connected to the first end of the capacitor C. The gate of the quantization transistor M16 receives a quantization control signal OF_CTL, the drain is connected to the floating diffusion node FD, and the source is connected to the first end of the capacitor C.

[0085] Specifically, in this example, the node between the quantization transistor M16 and the memory device serves as a signal fluctuation node, and a decoupling unit 140_2 is provided corresponding to the node to adjust the signal of the fluctuation node.

[0086] See also Figure 8 As shown, in one example, a decoupling unit may include at least two decoupling sub-units to adjust the corresponding signal fluctuation nodes. That is, the decoupling unit at a signal fluctuation node may be divided into at least two parts to correspond to Figure 4 Taking the pixel circuit shown in the figure as an example, the corresponding decoupling unit 140_3 in the figure is divided into two sub-units, namely a first decoupling sub-unit 140_3_1 and a second decoupling sub-unit 140_3_2. In this example, corresponding to the pixel block 500, the first decoupling sub-unit 140_3_1 can be set at the low-gain node of the corresponding gain control unit 160, and the second decoupling sub-unit 140_3_2 can be set at the end of the corresponding reset unit 120 electrically connected to the low-gain node of the gain control unit 160, so as to split the fluctuation node based on the two decoupling sub-units. The two can be controlled simultaneously based on the same or different control signals, and can also be controlled respectively by different signals to meet different needs.

[0087] See also Figures 3 to 8As shown, in one example, the decoupling unit includes a decoupling transistor coupled to a signal fluctuation node, a control terminal receiving a decoupling control signal, and the decoupling transistor adjusts the signal fluctuation of the corresponding signal fluctuation node based on the decoupling control signal to adjust the signal transferred from the signal fluctuation node to the floating diffusion node to obtain a decoupling signal, or adjusts the pixel output signal read out from the signal fluctuation node. The decoupling unit can shield the interference of other signals on the corresponding signal fluctuation node. For example, the gate of the decoupling transistor can have a signal shielding effect. In addition, applying a low voltage (such as a negative voltage or ground potential) to the control terminal of the decoupling transistor can further facilitate the realization of the above-mentioned shielding effect. In addition, the decoupling transistor can be turned off by low voltage without affecting the operation of adjacent transistors. The decoupling transistor can alleviate the crosstalk of the corresponding signal fluctuation node from adjacent or surrounding signals in the semiconductor substrate.

[0088] In one implementation, the decoupling transistor further includes a first end and a second end, the first end being connected to the signal fluctuation node, the second end being left floating, and the decoupling control signal received by the control end being a variable voltage signal, although a constant voltage signal may also be received. For example, the decoupling transistor is in the form of an NMOS transistor, the gate end receiving the decoupling control signal, an active end being connected to the signal fluctuation node, and the other active end being left floating. Of course, the floating end may also be used for other purposes without affecting the operation of the decoupling transistor. In addition, the first end and / or the second end of the decoupling transistor may be connected to adjacent nodes in a node multiplexing manner, for example, the drain end (an active end) of a decoupling transistor may also be the source or drain of an adjacent transistor on one side of the decoupling transistor (which may be a signal fluctuation node that needs to be adjusted), and the source end (the other active end) of the decoupling transistor may also be the source or drain of an adjacent transistor on the other side of the decoupling transistor.

[0089] Among them, see Figures 3 to 8 As shown, the first decoupling unit 140_1 includes a first decoupling transistor M15, a gate terminal of which receives the decoupling control signal De_coupl_1, and a first terminal shared with the source terminal of the pixel selection transistor M14; the second decoupling unit 140_2 includes a second decoupling transistor M17, a gate terminal of which receives the decoupling control signal De_coupl_2, and a first terminal shared with the source terminal of the overflow quantization transistor M16; see Figures 4 to 7 As shown, the third decoupling unit 140_3 includes a third decoupling transistor M19, a gate terminal of which receives the decoupling control signal De_coupl_3, and a first terminal shared with the drain terminal of the gain control transistor M18; in addition, see Figure 7 As shown, the boundary decoupling unit 140_3s includes a boundary decoupling transistor Ms, which can be independently arranged between the floating diffusion node and the connected pixel block, and the gate terminal receives the decoupling control signal De_coupl_s; see Figure 8 As shown, the third decoupling unit 140_3 includes a first sub-decoupling transistor M21 and a second sub-decoupling transistor M20, whose gate terminals receive decoupling control signals De_coupl_3-1 and De_coupl_3-2, respectively. The first terminal of the first sub-decoupling transistor M21 is shared with the drain terminal of the gain control transistor M18, and the first terminal of the second sub-decoupling transistor M20 is shared with the source terminal of the reset transistor M12. Furthermore, in the above example, the other terminal of the decoupling transistor that shares one terminal can be left floating or used for other purposes.

[0090] In one example, the decoupling unit further includes an additional decoupling structure (not shown), which is electrically connected to the signal fluctuation node and / or the control terminal of the decoupling transistor to decouple the signal fluctuation based on parasitics. In one implementation, the additional decoupling structure is electrically connected to the signal fluctuation node. For example, the additional decoupling structure can be a conductive structure, which adjusts the influence of other signals on the node based on parasitic capacitance between the conductive structure and other electrical structures. In addition, the additional decoupling structure can also be electrically connected to the control terminal of the decoupling transistor. For example, the additional decoupling structure can be a conductive structure, which adjusts the influence of other signals on the node based on parasitic capacitance between the conductive structure and the gate of the decoupling transistor and other electrical structures.

[0091] In a further example, a decoupling control signal can be applied to the decoupling transistor based on an additional decoupling structure connected to the control terminal of the decoupling transistor, that is, the additional decoupling structure simultaneously serves as a gate terminal control signal application and has a parasitic effect, such as the additional decoupling structure can be implemented based on the existing interconnection structure.

[0092] See also Figure 9 As shown, in one example, the image sensor further includes a node sharing structure 170 coupled between gain units of at least two pixel blocks; wherein the figure shows a node sharing pixel block group 600 consisting of two pixel blocks having the node sharing structure 170 in one example.

[0093] Specifically, node sharing structure 170 is coupled between the gain control units of at least two pixel blocks. It is used to increase the storage capacity of floating diffusion node FD based on node sharing when the gain control units are enabled, resulting in a lower conversion gain for the corresponding pixel blocks being read out, thereby adapting to the increasing demand for high-light scenes. The node sharing structure 170 can be coupled between different gain nodes of the gain control units, and can be coupled between high- and low-gain nodes based on actual needs. In embodiments of the present invention, it is preferably coupled between the gain nodes with the lowest gain of each gain control unit to be coupled.

[0094] In one example, node sharing structure 170 is coupled between gain control units in different rows of pixel blocks in the same column; further, it is coupled between gain control units in two adjacent rows of pixel blocks in the same column. Of course, it can also be coupled between two or more rows as required, for example, between rows corresponding to pixels of the same color, thereby preventing signals from interfering with each other between pixels of different colors.

[0095] As an example, the node sharing structure 170 includes a connecting line coupled between the gain units of at least two pixel blocks, such as, coupled between the first ends of the gain control transistors M18 in the corresponding pixel blocks; when the gain unit is turned on, the storage capacity of the floating diffusion node FD is increased based on node sharing. At this time, the shared node storage capacity corresponds to at least 2*Cfd, where Cfd is the storage capacity of the floating diffusion node FD.

[0096] Furthermore, node sharing structure 170 further includes at least one switch transistor coupled in series to the connection line, with a control terminal thereof receiving a switch control signal. The switch transistor comprises an NMOS transistor, although a PMOS transistor is also feasible. After the node sharing structure of this embodiment includes a first switch transistor, if node sharing is desired, in addition to controlling the gain unit to be on, the switch transistor must also be controlled to be on.

[0097] In one example, the pixel block group 800 having the node sharing structure 170 includes a common reset unit (eg, Figure 11 The shared reset unit includes a reset transistor M12, whose gate terminal receives a reset control signal RST.

[0098] See also Figure 10 As shown, in one example, the image sensor includes a pixel array, and a plurality of pixel blocks arranged in an array constitute the pixel array, and a shared decoupling unit is provided between adjacent pixel blocks in the pixel array, wherein the figure shows a pixel block group 700 with a shared decoupling unit.

[0099] Specifically, the design of a shared decoupling unit can save the layout area of ​​the image sensor while improving signal interference based on the decoupling unit, which is conducive to the miniaturization of the device design.

[0100] Please also refer to Figure 12 and Figure 8As shown, in one example, a pixel block includes at least one of a first decoupling transistor M15, a second decoupling transistor M17, and a third decoupling transistor. The first decoupling transistor M15 is configured to correspond to a corresponding signal output node, the second decoupling transistor M17 is configured to correspond to a second charge signal receiving node of an overflow unit, and the third decoupling transistor is configured to correspond to a low-gain node of a gain control unit. The first decoupling transistor M15, the second decoupling transistor M17, and the third decoupling transistor correspond to the first decoupling unit, the second decoupling unit, and the third decoupling unit described above, respectively. Furthermore, in this example, the decoupling transistors between adjacent pixel blocks in the pixel array are multiplexed.

[0101] Among them, the third decoupling transistor includes a first sub-decoupling transistor M21 and a second sub-decoupling transistor M20, the first sub-decoupling transistor M21 is arranged on the gain control transistor side of the gain control unit, and the second sub-decoupling transistor M20 is arranged on the side of the reset unit electrically connected to the gain control unit.

[0102] Specifically, such as Figure 12 As shown in partial array 800, the second sub-decoupling transistor M20 and the first decoupling transistor M15 of the adjacent pixel block are configured as a shared decoupling transistor Msh. In this example, the second sub-decoupling transistor M20 is shared with the first decoupling transistor M15 of the adjacent row in the same column, forming a shared decoupling unit 140_4. The shared decoupling transistor Msh receives a decoupling control signal De_coupl_4 at its gate, and simultaneously adjusts two corresponding signal fluctuation nodes based on the same control signal. Alternatively, other decoupling transistors may also be shared. The first sub-decoupling transistor M21 and the second decoupling transistor M17 of the adjacent pixel block are configured as a shared decoupling transistor Mcom. In this example, the first sub-decoupling transistor M21 is shared with the second decoupling transistor M17 of the adjacent column in the same row, forming a shared decoupling unit 140_5. The decoupling transistor Mcom receives a decoupling control signal De_coupl_5 at its gate, and simultaneously adjusts two corresponding signal fluctuation nodes based on the same control signal.

[0103] Example 2:

[0104] See also Figure 13 and Figure 14 As shown, this embodiment provides a pixel arrangement structure, that is, a layout implementation method of a pixel block, which is applicable to any image sensor as described in Example 1. The pixel arrangement structure includes a pixel block area (as shown by the dotted line in the box in the figure), corresponding to a pixel block in Example 1.

[0105] Furthermore, the pixel block area includes a photosensitive unit area and a transistor arrangement area, and each photosensitive unit area is arranged in an array corresponding to the pixel array. For example, the arrangement rule of the photosensitive units is consistent with the periodic repetition rule of the pixel array; the transistor arrangement area includes a first area and a second area arranged to intersect, and the decoupling unit is arranged in the first area and / or the second area. The photosensitive unit area and the transistor arrangement area can be arranged in the pixel block area according to actual needs. In addition, the arrangement of the transistor arrangement area can be considered to have at least two areas with intersecting axes. For example, the area where the transfer transistor is located can be considered as the first area, and the floating diffusion node and the reset transistor connected thereto or the floating diffusion node and the gain control transistor connected thereto can be considered as the second area, wherein the axis of the first area where the transfer transistor is located intersects with an axis of a sub-area of ​​the second area where the floating diffusion node is located at 45°. In addition, the second area can also have other axes, such as the axis of another sub-area of ​​the second area where the reset transistor is located, which intersects with the axis of the sub-area of ​​the second area where the floating diffusion node is located at 90°. The decoupling unit is arranged in the first area and / or the second area. For example, the decoupling transistor is arranged in the transistor arrangement area, which is beneficial to pixel layout optimization and signal decoupling.

[0106] Continue reading Figure 13 As shown, the photosensitive unit includes at least one photosensitive element and at least one transfer transistor. In this example, the photosensitive unit includes four photosensitive elements and four transfer transistors TX corresponding to the photosensitive elements. In this example, the transistor arrangement area (the dotted-dash area within the dashed box) is at least provided within the pixel block area. Furthermore, the transistor arrangement area extends from the center of the pixel block area to form a first area and a second area. In this example, the horizontal direction is the first area and the vertical direction is the second area. The source follower transistor SF is located at the center of the pixel block area. The floating diffusion point includes a first sub-floating diffusion node FD1 and a second sub-floating diffusion node FD2 located in the first area and arranged on both sides of the source follower transistor SF. In this example, the four photosensitive elements PD are evenly distributed around the source follower transistor SF. Furthermore, the four transfer transistors TX are evenly distributed around the source follower transistor SF. It should be noted that in order to facilitate clear identification of transistors in this embodiment, the corresponding transistors are identified by gate control signals.

[0107] In one example, the overflow unit includes an overflow quantization transistor OF_CTL, and the gain control unit includes a gain control transistor DCG. The gain control transistor DCG and the overflow quantization transistor OF_CTL are located in the first region and are respectively located on one side of the two sub-floating diffusion nodes away from the source follower transistor SF. In another example, the reset unit includes a reset transistor RST, and the readout unit includes a source follower transistor SF and a selection transistor SEL. In this example, the reset transistor RST and the pixel selection transistor SEL are located in the second region and on both sides of the source follower transistor SF. Further, Figure 13 In the example shown, the gain control transistor DCG, the overflow quantization transistor OF_CTL, the reset transistor RST, and the pixel selection transistor SEL are located around the source follower transistor SF, are symmetrically arranged, and are symmetrically distributed between adjacent photosensitive elements PD.

[0108] Continue reading Figure 13 As shown, in one example, a decoupling unit is configured between the transistor arrangement areas of adjacent pixel blocks. The transistor arrangement area has at least one end side facing the adjacent pixel block, and a corresponding decoupling unit is arranged on this end side, which is conducive to the decoupling of signals between pixel blocks. Among them, a decoupling transistor can be set at the end of the transistor arrangement area. For example, a decoupling transistor can be set at the signal output end of the pixel selection transistor SEL, or at one end of the reset transistor RST, or at one end of the gain control transistor DCG, or at one end of the overflow quantization transistor OF_CTL. In this example, a decoupling transistor is set at each end side of the transistor arrangement area.

[0109] In a further example, for two adjacent pixel blocks, there are at least a pair of end sides of transistor arrangement areas arranged opposite to each other. Furthermore, corresponding to the end sides of this pair of transistor arrangement areas arranged opposite to each other, two corresponding decoupling units adopt a shared setting, such as using shared decoupling transistors.

[0110] In one implementation, a common decoupling transistor Msh is provided between the pixel selection transistor SEL and the reset transistor RST. Figure 13As shown, in this shared design, for the adjustment of the signal fluctuation node as the signal output node (the source end of the pixel selection transistor SEL), the source end of the pixel selection transistor SEL serves as the first end of the multiplexing decoupling transistor Msh, which is equivalent to being coupled to the signal fluctuation node in a multiplexing manner. At the same time, the source end of the reset transistor RST of the adjacent pixel block serves as the second end of the multiplexing decoupling transistor Msh, which is equivalent to being suspended and equivalent to other uses for the reset transistor RST; for the adjustment of the signal fluctuation node as a low gain node (the drain end of the gain control transistor DCG), the source end of the reset transistor RST serves as the first end of the multiplexing decoupling transistor Msh, which is equivalent to being coupled to the signal fluctuation node in a multiplexing manner. At the same time, the source end of the pixel selection transistor SEL of the adjacent pixel block serves as the second end of the multiplexing decoupling transistor Msh, which is equivalent to being suspended and equivalent to other uses for the pixel selection transistor SEL.

[0111] In another implementation, a common decoupling transistor Mcom is provided between the gain control transistor DCG and the overflow quantization transistor OF_CTL. Figure 13 As shown, in this shared design, for the adjustment of the signal fluctuation node as the overflow signal receiving node of the overflow unit (the connection terminal of the overflow quantization transistor OF_CTL and the memory device C), the drain terminal of the overflow quantization transistor OF_CTL serves as the first terminal of the multiplexing decoupling transistor Mcom, which is equivalent to being coupled to the signal fluctuation node in a multiplexing manner. At the same time, the drain terminal of the gain control transistor DCG of the adjacent pixel block serves as the second terminal of the multiplexing decoupling transistor Mcom, which is equivalent to being suspended and equivalent to other uses for the gain control transistor DCG; for the adjustment of the corresponding signal fluctuation node as a low gain node (the drain terminal of the gain control transistor DCG), the drain terminal of the gain control transistor DCG serves as the first terminal of the multiplexing decoupling transistor Mcom, which is equivalent to being coupled to the signal fluctuation node in a multiplexing manner. At the same time, the drain terminal of the overflow quantization transistor OF_CTL of the adjacent pixel block serves as the second terminal of the multiplexing decoupling transistor Msh, which is equivalent to being suspended and equivalent to other uses for the overflow quantization transistor OF_CTL.

[0112] It should be noted that Figure 13 In the example shown in , the adjustment of the drain terminal of the gain control transistor DCG is achieved by means of two sub-decoupling transistors, one is arranged at the drain terminal of the gain control transistor DCG, and the other is arranged at the source terminal of the reset transistor RST. In addition, the drain terminal of the gain control transistor DCG and the source terminal of the reset transistor RST can also be electrically connected through the metal wiring in the interconnection layer.

[0113] Continue to see Figure 13As shown, in one example, the pixel block also includes an intra-pixel isolation structure, disposed on the side of the floating diffusion node, to at least isolate the decoupled signal and prevent substrate signal crosstalk. In one implementation, the intra-pixel isolation structure is implemented using a shallow trench isolation (STI) structure. Of course, in other embodiments, other isolation structures, such as doping isolation, can also be used according to actual needs.

[0114] Specifically, in this example, the intra-pixel isolation structure includes a first intra-pixel isolation structure 180 located between the first and second sub-floating diffusion nodes FD1 and FD2 and the source follower transistor SF, and second intra-pixel isolation structures 190-1 and 190-2 located on the other side of the first and second sub-floating diffusion nodes FD1 and FD2. In this example, the second intra-pixel isolation structure 190-1 is located between the first sub-floating diffusion node FD1 and the gain control transistor DCG, for example, extending to the side of the gain control transistor gate; the second intra-pixel isolation structure 190-2 is located between the second sub-floating diffusion node FD2 and the overflow quantization transistor OF_CTL, for example, extending to the side of the overflow quantization transistor gate. Furthermore, the first intra-pixel isolation structure can extend to the gate sides of the select transistor and the reset transistor on both sides.

[0115] In one example, there is a doping isolation structure between the decoupling transistor and the adjacent photosensitive element, for example, it can be a P-type doping isolation N-type photosensitive doping area; further, when the common decoupling transistor Msh and the common decoupling transistor Mcom are set in a multiplexing manner, the doping isolation structure is set in a partial area between the doping area of ​​the photoelectric conversion element and the source and drain ends of the gain control transistor DCG, the overflow quantization transistor OF_CTL, the reset transistor RST and the pixel selection transistor SEL, which is beneficial to improve dark current, etc.

[0116] See also Figure 14 As shown, Figure 13 The example shown is different in that the first and second regions of the transistor arrangement area in this example are not as Figure 13 The symmetrical arrangement shown in the example is that the first area in the horizontal direction is offset for the source follower transistor SF, and the other areas are Figure 13 Similar to the example shown, in this example, the gain control transistor DCG and the overflow quantization transistor OF_CTL are located in the first region and on the side of one of the two sub-floating diffusion nodes (the first sub-floating diffusion node FD1 in the figure) away from the source follower transistor SF. In this example, the second sub-floating node FD forms the end side adjacent to the adjacent pixel block. Furthermore, a decoupling unit is configured in the end side region S shown in the figure, which can correspond to Figure 7The decoupling unit 140_3s in the pixel circuit shown is used to adjust the floating diffusion node on the end side based on the decoupling transistor in the unit. This node serves as a signal fluctuation node, which is beneficial to ultimately improve image quality.

[0117] Example 3:

[0118] The present invention also provides an electronic device comprising an image sensor according to any of the above-described embodiments. The electronic device can be a security monitoring device, an in-vehicle electronic device, a mobile phone camera, a machine vision device, or the like. The image sensor according to the present invention can acquire high-quality image information and can also be used in infrared utilization devices.

[0119] Example 4:

[0120] This embodiment further provides a method for controlling an image sensor. The method provided in this embodiment is applicable to the image sensor described in any of the above solutions. The method includes the following steps:

[0121] A decoupling control signal is provided to the decoupling unit, and a signal generated by the photosensitive unit is read out based on the floating diffusion node, wherein the readout signal includes a signal adjusted via the signal fluctuation node.

[0122] In one example, when the decoupling unit includes a decoupling transistor, during the process of signal transfer at the signal fluctuation node, the corresponding decoupling transistor is controlled to be turned off based on the decoupling control signal. Specifically, the decoupling transistor can be controlled to be turned off during at least one stage of the idle, global reset, exposure and readout processes.

[0123] See also Figure 15 As shown, in one control mode, the decoupling transistor is controlled in the signal readout phase, and further, the decoupling transistor is controlled in the global reset phase and the exposure overflow phase, wherein: Figure 15 The operation timing in the corresponding Figure 8 Take the circuit shown as an example, the details are as follows:

[0124] Global reset stage Precharge: reset operation is performed on the floating diffusion node FD, the photosensitive unit 110 and the overflow unit 150; further, the floating diffusion node FD, the photosensitive unit 110 and the overflow unit 150 are reset by the reset unit 120, and when the pixel selection transistor SEL is turned off, the reset transistor RST, the transfer transistor TX and the overflow quantization transistor OF_CTL are turned on to achieve the above reset, and then the reset transistor RST, the transfer transistor TX and the overflow quantization transistor OF_CTL are controlled to be turned off.

[0125] The first decoupling transistor De_coupl_1 can be controlled to be in a low state. Since the pixel select transistor SEL is in an off state at this time, the first decoupling transistor De_coupl_1 can be set to a low state, thereby preventing the signal output node from being affected by crosstalk from other signals. In addition, since other signal fluctuation nodes are in a high-level conductive state, the corresponding second decoupling transistor De_coupl_2, first sub-decoupling transistor De_coupl_3-1, and second sub-decoupling transistor De_coupl_3-2 can be set to a high state to assist in the global reset of the pixel array. Of course, all three can also be set to a low state.

[0126] Exposure&Overflow:

[0127] Photoelectric conversion is performed through the photosensitive unit 110 to generate a charge signal corresponding to the image; wherein, the first charge signal is stored in the photosensitive unit 110, and the second charge signal is stored in the overflow unit 150. Of course, when the pixel point corresponding to the actual scene does not overflow, only the first charge signal exists.

[0128] Specifically, the common path may be opened (the overflow quantization transistor is opened), and the second charge signal may be stored in the overflow unit 150 through the common path; of course, in other examples, the overflow path may be opened and the quantization path may be closed, and the second charge signal may be stored in the overflow unit 150 through the overflow path.

[0129] Among them, since the gain control transistor OF_CTL is in the on state to store the overflowed second charge signal, the corresponding second decoupling transistor De_coupl_2 is set to a low level state, which can prevent the receiving node of the overflow signal from being crosstalked by other signals and improve the accuracy of the overflow signal.

[0130] In addition, at this time, the pixel selection transistor SEL is still in the off state, and the first decoupling transistor De_coupl_1 can be set to a low level state to prevent the signal output node from being affected by crosstalk from other signals. In addition, since the gain control transistor DCG and the reset transistor RST are both in the off state, there is no signal fluctuation at this node at this stage, so the first sub-decoupling transistor De_coupl_3-1 and the second sub-decoupling transistor De_coupl_3-2 can be in a high level state. Of course, all three can also be set to a low level.

[0131] Readout: The readout phase includes the readout of the reset signal and the image signal to implement true correlated double sampling and / or non-true correlated double sampling. Quantized readout of the first charge signal and the second charge signal can be performed in different gain modes. Furthermore, when gain unit 150 is enabled, node sharing structure 170 can be used to increase the storage capacity of floating diffusion node FD. The floating diffusion node with increased storage capacity is defined as a shared floating node.

[0132] In one embodiment, the quantization stage includes: performing correlated double sampling on the first charge signal in different gain modes, and performing non-true correlated double sampling on the second charge signal.

[0133] Specifically, it includes: controlling the gain unit 160 to be turned on and then turned off, so as to quantize and read out the first reset signal in the first gain mode and the second gain mode based on the floating diffusion node FD, respectively, see time t1 and t2; controlling the gain unit 160 to be turned off and then turned on, so as to quantize and read out the first charge signal in the second gain mode and the first gain mode based on the floating diffusion node FD, respectively, see time t3 and t4; then, controlling the common path in the overflow unit 150 to be turned on, so as to quantize and read out the second charge signal based on the floating diffusion node FD, see time t5; performing a reset operation on the floating diffusion node FD and the overflow unit 150, so as to quantize and read out the second reset signal based on the floating diffusion node FD, see time t6.

[0134] In the readout phase, there is a transfer of signals at different signal fluctuation nodes. Preferably, the first decoupling transistor De_coupl_1, the second decoupling transistor De_coupl_2, the first sub-decoupling transistor De_coupl_3-1, and the second sub-decoupling transistor De_coupl_3-2 are all controlled to be set to a low level. This helps maintain consistency in signal readout while regulating the signal fluctuation nodes from interference from other signals.

[0135] Idle phase: During the non-data operation phase of the image sensor, the decoupling transistors can be turned on to balance the transistors corresponding to the pixel array. Of course, they can also be kept in a low-level off state.

[0136] In a preferred example, in the global reset stage, the exposure overflow stage, and the readout stage, each decoupling transistor is in a low-level off state, which is beneficial to the regulation of each fluctuation node and saves power consumption. Figure 13The configuration of the shared decoupling transistor Msh and the shared decoupling transistor Mcom shown uses a single shared decoupling transistor to simultaneously control both corresponding transistors. Furthermore, both control signals regulate node signals by turning off the transistors at each stage. Furthermore, the variable voltage terminal Vc of the capacitor in the overflow unit can be grounded at all times or high during the exposure overflow phase, facilitating signal overflow. It can also be set high during the overflow signal transfer phase and during the reset phase corresponding to overflow signal readout for rapid resetting.

[0137] In summary, the image sensor of the present invention, through the design of a decoupling unit, can adjust the impact on signal fluctuation nodes, thereby adjusting the accuracy of image data directly or indirectly output from these fluctuation nodes. In particular, in pixel circuits with overflow signals, the decoupling unit design can effectively improve the accuracy of the final output data signal, thereby optimizing image quality and improving device performance. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0138] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Any equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. An image sensor, characterized in that: The system comprises a plurality of pixel blocks arranged in an array, each pixel block comprising a photosensitive unit, a reset unit, a readout unit and a decoupling unit, wherein: The reset unit is coupled to the floating diffusion node and is used to reset at least one of the floating diffusion node and the photosensitive unit; The photosensitive unit is coupled to the floating diffusion node, and is configured to generate a charge signal based on photoelectric conversion, store the charge signal, and transfer the charge signal to the floating diffusion node; The decoupling unit is provided corresponding to the signal fluctuation node in the pixel block to adjust the signal to be read out transferred to the floating diffusion node based on the signal fluctuation node and / or adjust the output data signal of the pixel block based on the signal fluctuation node, wherein the signal to be read out of the floating diffusion node forms a decoupled signal corresponding to the signal to be read out when adjusted by the signal fluctuation node; The readout unit is coupled to the floating diffusion node to read out a signal corresponding to the floating diffusion node.

2. The image sensor according to claim 1, wherein The pixel block also includes an overflow unit, which is coupled to the floating diffusion node, and the photosensitive unit generates a first charge signal and a second charge signal based on photoelectric conversion, wherein the photosensitive unit stores the first charge signal and transfers the first charge signal to the floating diffusion node, and the overflow unit stores the second charge signal and transfers the second charge signal to the floating diffusion node.

3. The image sensor according to claim 2, wherein: The overflow unit includes a shared path coupled to the photosensitive unit and the floating diffusion node to store the second charge signal based on the shared path and transfer the second charge signal to the floating diffusion node for reading out based on the shared path; Alternatively, the overflow unit includes an overflow path and a quantization path, the overflow path is coupled to the photosensitive unit, and the quantization path is coupled to the floating diffusion node, wherein the second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node for reading based on the quantization path.

4. The image sensor according to claim 1, wherein The pixel block further includes a gain control unit, the gain control unit being coupled to the floating diffusion node to cooperate with the floating diffusion node to form a modulation storage area and to form a voltage signal corresponding to the charge signal based on the modulation storage area; When the pixel block includes an overflow unit, the overflow unit is coupled to at least one gain node of the gain control unit to perform readout based on the gain node and the floating diffusion node.

5. The image sensor according to claim 1, wherein The decoupling unit includes at least two decoupling sub-units, which are respectively arranged corresponding to the same signal fluctuation node; and / or the decoupling unit includes a decoupling transistor coupled to the signal fluctuation node, a control end of which receives a decoupling control signal, and the decoupling transistor adjusts the corresponding signal fluctuation node based on the decoupling control signal; And / or, the decoupling unit includes an additional decoupling structure, which is electrically connected to the signal fluctuation node and / or the control end of the decoupling unit to adjust the corresponding signal fluctuation node in a parasitic manner.

6. The image sensor according to claim 5, wherein: The decoupling transistor also includes a first end and a second end, the first end is electrically connected to the signal fluctuation node, and the second end is set to be suspended, or the first end and / or the second end of the decoupling transistor are shared with adjacent nodes in a node multiplexing manner; and / or the decoupling control signal is a variable voltage signal or a constant voltage signal.

7. The image sensor according to claim 1, wherein The signal fluctuation node includes a high-impedance node of the pixel block, wherein the high-impedance node includes a second charge signal receiving node corresponding to the overflow unit, and the decoupling unit is coupled to the receiving node, and / or the high-impedance node includes at least one gain node of a gain control unit, and the decoupling unit is coupled to the gain node; And / or, the signal fluctuation node includes a signal output node of the pixel block, which is used to at least output the data signal of the pixel block, and the decoupling unit is coupled to the signal output node.

8. The image sensor according to any one of claims 1 to 7, wherein: The image sensor includes a pixel array, and a plurality of pixel blocks arranged in an array constitute the pixel array, wherein a node sharing structure is provided between the gain control units of at least two of the pixel blocks in the pixel array; and / or a shared decoupling unit is provided between adjacent pixel blocks in the pixel array.

9. The image sensor according to claim 8, wherein The pixel block includes at least one of a first decoupling transistor, a second decoupling transistor and a third decoupling transistor. The first decoupling transistor is set corresponding to the signal output node, the second decoupling transistor is set corresponding to the second charge signal receiving node of the overflow unit, and the third decoupling transistor is set corresponding to the gain node of the gain control unit. The corresponding decoupling transistors in adjacent pixel blocks are shared to form the shared decoupling unit.

10. The image sensor according to claim 9, wherein The third decoupling transistor includes a first sub-decoupling transistor and a second sub-decoupling transistor, the first sub-decoupling transistor is arranged on one side of the gain control transistor of the gain control unit, and the second sub-decoupling transistor is arranged on one side of the reset unit electrically connected to the gain control unit, wherein the first sub-decoupling transistor and the second decoupling transistor of the adjacent pixel block are set as a first shared decoupling transistor, and the second sub-decoupling transistor and the first decoupling transistor of the adjacent pixel block are set as a second shared decoupling transistor.

11. The image sensor according to claim 8, wherein The pixel block group having the node sharing structure includes a common reset unit, and the common reset unit is provided in at least one pixel block of the pixel block group; And / or, the pixel block further includes an intra-pixel isolation structure, which is disposed on a side of the floating diffusion node to at least isolate the decoupling signal of the floating diffusion node.

12. A pixel arrangement structure, suitable for the image sensor according to any one of claims 1 to 11, characterized in that: The pixel arrangement structure includes: A pixel block area, wherein the pixel block area includes a photosensitive unit area and a transistor arrangement area; each of the photosensitive unit areas is arranged in an array corresponding to the pixel array, and the transistor arrangement area includes a first area and a second area arranged to intersect, wherein the decoupling unit is arranged in the first area and / or the second area; and / or the decoupling unit is configured between the transistor arrangement areas of adjacent pixel blocks.

13. The pixel arrangement structure according to claim 12, wherein: The photosensitive unit includes at least one photosensitive element and a transfer transistor, and the readout unit includes a source follower transistor, wherein: The transistor arrangement area is at least arranged inside the pixel block area, and the transistor arrangement area extends from the center of the pixel block area to form the first area and the second area, wherein the source follower transistor is located in the center of the pixel block area, and the floating diffusion point includes a first sub-floating diffusion node and a second sub-floating diffusion node located in the first area and arranged on both sides of the source follower transistor.

14. The pixel arrangement structure according to claim 13, wherein: The overflow unit includes an overflow quantization transistor, the gain control unit includes a gain control transistor, the reset unit includes a reset transistor, and the readout unit further includes a pixel selection transistor, wherein: The gain control transistor and the overflow quantization transistor are located in the first region and are respectively located on the side of the two sub-floating diffusion nodes away from the source follower transistor or are located in the first region and on the side of one of the two sub-floating diffusion nodes away from the source follower transistor, and the reset transistor and the pixel selection transistor are located in the second region and on both sides of the source follower transistor.

15. The pixel arrangement structure according to any one of claims 12 to 14, wherein: The first shared decoupling transistor and the second shared decoupling transistor are arranged between the transistor arrangement areas of adjacent pixel blocks; and / or, a decoupling unit is set between the floating diffusion node and the transistor arrangement area of ​​the adjacent pixel block; and / or, the pixel block also includes an intra-pixel isolation structure arranged on the side of the floating diffusion node, and the intra-pixel isolation structure is at least one of shallow trench isolation and doped isolation; and / or, a doped isolation structure is provided between the decoupling transistor and the adjacent photosensitive element.

16. An electronic device, characterized in that: The image sensor comprises the image sensor according to any one of claims 1 to 11, and / or the pixel arrangement structure according to any one of claims 12 to 15.

17. A method for controlling an image sensor according to any one of claims 1 to 11, characterized in that: The control method comprises the following steps: A decoupling control signal is provided to the decoupling unit, and a data signal generated by the photosensitive unit is at least read out based on the floating diffusion node, where the data signal includes a signal adjusted via a signal fluctuation node.

18. The method for controlling an image sensor according to claim 17, wherein: When the decoupling unit includes a decoupling transistor, during the process of signal transfer at the signal fluctuation node, the corresponding decoupling transistor is controlled to be turned off based on the decoupling control signal, wherein the decoupling transistor is controlled to be turned off in at least one stage of idle, global reset, exposure and overflow, and readout.

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