Semiconductor device and manufacturing method thereof
By introducing a first gate structure and a field plate structure surrounding the platform area into the semiconductor device and setting a separate source conductive layer, the problems of uneven electric field distribution and low high-frequency switching efficiency of the traditional SGT structure are solved, the device's withstand voltage performance and switching speed are improved, and the on-resistance is reduced.
Patent Information
- Application Number
- CN202510653221.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-20
- Publication Date
- 2025-09-05
AI Technical Summary
The traditional shielded gate trench (SGT) structure has limitations in on-resistance, switching loss and breakdown voltage, uneven electric field distribution leads to insufficient voltage withstandability, and high gate leakage capacitance limits the efficiency of high-frequency switching applications.
Using an improved semiconductor device structure, by forming a first gate structure surrounding the platform region and a central field plate structure in the semiconductor layer, combined with a separate source conductive layer, the electric field distribution and current path are optimized to reduce parasitic capacitance.
It improves the voltage withstand performance, switching speed and stability of the device, reduces on-resistance, enhances current carrying capacity, and optimizes the current distribution and overall performance of the device.
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Figure CN120603310A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor device manufacturing, and more particularly, to a semiconductor device and a method for manufacturing the same. Background Art
[0002] With the continuous advancement of power semiconductor device technology, the shielded gate trench (SGT) structure, as an important device architecture, has been widely adopted in various electronic devices. In the traditional SGT structure, the gate and source are integrated in the same trench and isolated from the active area by an oxide dielectric. The trench and contact holes are parallel and strip-shaped. This structure has certain limitations in terms of on-resistance (Rdson), switching loss, and breakdown voltage (BV). Its uneven electric field distribution leads to insufficient withstand voltage in high-voltage applications, while the high gate-to-drain capacitance (Cgd) limits its efficiency in high-frequency switching applications. Summary of the Invention
[0003] In view of this, the present disclosure provides an improved semiconductor device and a method for manufacturing the same, thereby improving the overall performance of the device.
[0004] According to one aspect of an embodiment of the present disclosure, there is provided a semiconductor device, including:
[0005] A plurality of cells formed based on a semiconductor layer, at least one of the cells comprising:
[0006] a first gate structure extending inward from a surface of the semiconductor layer, wherein the first gate structure surrounds or semi-surrounds a platform region of the semiconductor layer;
[0007] a field plate structure, located at the center of the platform region and extending inward from the surface of the semiconductor layer;
[0008] a well region, located in a platform region between the first gate structure and the field plate structure, extending inward from the surface of the semiconductor layer, wherein the depth of the well region is less than the depth of the first gate structure, and the sidewalls of the well region are in contact with the sidewalls of the first gate structure and the field plate structure;
[0009] a source region, located in the well region, extending inward from the surface of the semiconductor layer, wherein the depth of the source region is less than the depth of the well region, and the sidewalls of the source region are in contact with the sidewalls of the first gate structure and the field plate structure;
[0010] The source conductive layer is located in the platform region between the first gate structure and the field plate structure and is at least partially located on the surface of the semiconductor layer. The source conductive layer includes a plurality of discontinuous portions.
[0011] Optionally, in at least one of the cells, the first gate structure forms a closed regular polygonal structure.
[0012] Optionally, the plurality of discontinuous portions of the source conductive layer are conformal to the first gate structure.
[0013] Optionally, the first gate structure forms a square structure,
[0014] The source conductive layer includes four discontinuous parts, each discontinuous part forms an L-shaped structure corresponding to one corner of the square first gate structure, and two sides of the L-shape correspond to two adjacent sides of the square first gate structure.
[0015] Optionally, the first gate structure forms a square structure,
[0016] The source conductive layer includes eight discontinuous parts, four of which form L-shaped structures corresponding to one corner of the square first gate structure respectively, and two sides of the L-shape correspond to two adjacent sides of the square first gate structure. The other four discontinuous parts form strip structures corresponding to one side of the square first gate structure respectively, and the L-shaped structure is spaced apart from the strip structure.
[0017] Optionally, the first gate structure forms a square structure,
[0018] The source conductive layer includes two discontinuous parts, and the interval between the two discontinuous parts corresponds to the middle of two opposite sides of the square first gate structure.
[0019] Optionally, the first gate structure forms a square structure,
[0020] The source conductive layer includes four discontinuous parts forming a circular ring structure, and each discontinuous part corresponds to a corner of the square first gate structure.
[0021] Optionally, in at least one of the cells, the field plate structure is sandwiched between two rows of the first gate structures, and the two rows of first gate structures are bent toward the field plate structure to semi-enclose the field plate structure.
[0022] Optionally, in at least one of the cells, the field plate structure is sandwiched between two rows of the source conductive layers, and the source conductive layer is conformal to an adjacent row of the first gate structures.
[0023] Optionally, in the plurality of cells, the plurality of field plate structures are arranged in a staggered array, each row of the field plate structures is sandwiched between two rows of the first gate structures, and two adjacent rows of the first gate structures form opposite fold lines to semi-enclose the field plate structures in that row.
[0024] Optionally, each row of the field plate structures is sandwiched between two rows of the source conductive layers, and the source conductive layers are conformal to an adjacent row of the first gate structures.
[0025] Optionally, an extension depth of the field plate structure in the semiconductor layer is greater than an extension depth of the first gate structure in the semiconductor layer.
[0026] Optionally, the semiconductor layer has a gate trench and a field plate trench, each extending from the surface of the semiconductor layer toward the inside.
[0027] The first gate structure includes:
[0028] a first gate dielectric layer, covering an inner surface of the gate trench; and
[0029] a first gate conductor, located in the gate trench and separated from the semiconductor layer by the first gate dielectric layer;
[0030] The field plate structure includes:
[0031] a field plate dielectric layer, covering the inner surface of the field plate trench; and
[0032] A field plate conductor is located in the field plate trench and is separated from the semiconductor layer by the field plate dielectric layer.
[0033] Optionally, the thickness of the first gate dielectric layer is smaller than the thickness of the field plate dielectric layer.
[0034] Optionally, it also includes:
[0035] The second gate conductor is located in the field plate trench, extends in the field plate dielectric layer along the thickness direction of the semiconductor layer, and is separated from the field plate conductor and the semiconductor layer respectively.
[0036] Optionally, the second gate conductor extends deeper than the well region.
[0037] Optionally, the at least one cell further includes:
[0038] a field plate conductive plug, at least partially located above the surface of the semiconductor layer and connected to the field plate conductor; and
[0039] A source wiring layer is located above the semiconductor layer and is respectively connected to the plurality of source conductive layers and the field plate conductive plugs.
[0040] According to another aspect of an embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, including: forming the semiconductor device as described above.
[0041] One of the above technical solutions has the following unexpected technical effects:
[0042] By having the first gate structure surround or semi-surround the platform area and setting a field plate structure extending into the semiconductor layer in the center of the platform area, the electric field concentration between the gate and the source is reduced, the voltage resistance of the device is improved, and the charge distribution in the semiconductor layer can be more effectively utilized, reducing the length and resistance of the current path, thereby reducing the on-resistance.
[0043] Furthermore, a separate source conductive layer is provided in the gap between the field plate trench and the gate trench, reducing parasitic capacitance between the gate and source, thereby lowering gate charge and improving device switching speed. Furthermore, by rationally distributing the source conductive layer, uniform current distribution within the active area is ensured, reducing current crowding and improving device stability and reliability. The separate source conductive layer also improves the device's on-resistance, thereby increasing its current-carrying capacity.
[0044] Therefore, the semiconductor device provided by the present disclosure can improve product performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.
[0046] Figure 1 A schematic diagram showing the three-dimensional structure of a semiconductor device according to a first embodiment of the present disclosure is shown;
[0047] Figure 2 A schematic top view of the semiconductor device according to the first embodiment of the present disclosure is shown;
[0048] Figure 3 Shown Figure 2 A schematic diagram of the enlarged structure in the middle dotted box;
[0049] Figure 4 Shown along Figure 2 Schematic diagram of the cross-section structure taken along line AA;
[0050] Figure 5 Shown along Figure 2 Schematic diagram of the cross-section structure taken along line BB;
[0051] Figures 6 to 12 sectional views showing some stages of a method for manufacturing the semiconductor device according to the first embodiment of the present disclosure;
[0052] Figure 13 A schematic top view of a semiconductor device according to a second embodiment of the present disclosure is shown;
[0053] Figure 14 A schematic top view of a semiconductor device according to a third embodiment of the present disclosure is shown;
[0054] Figure 15 FIG4 is a schematic top view of a semiconductor device according to a fourth embodiment of the present disclosure;
[0055] Figure 16 Shown along Figure 15 Schematic diagram of the cross-section structure taken along the CC line;
[0056] Figure 17 FIG2 is a schematic top view of a semiconductor device according to a fifth embodiment of the present disclosure;
[0057] Figure 18 A schematic top view of the structure of a semiconductor device according to a sixth embodiment of the present disclosure is shown. DETAILED DESCRIPTION
[0058] The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by similar reference numerals throughout the various figures. For clarity, parts in the figures are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a semiconductor structure obtained after several steps may be depicted in a single figure.
[0059] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it may mean that it is directly on the other layer or region, or that other layers or regions are included between it and the other layer or region. Furthermore, if the device is turned over, the layer or region will be "below" or "beneath" the other layer or region.
[0060] If the purpose is to describe the situation of being directly above another layer or another area, this article will use expressions such as "directly above..." or "above and adjacent to...".
[0061] Many specific details of the present disclosure are described below, such as device structures, materials, dimensions, processing techniques, and technologies, to provide a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be implemented without following these specific details.
[0062] The present disclosure may be embodied in various forms, some examples of which are described below.
[0063] Figure 1 FIG2 shows a schematic diagram of the three-dimensional structure of a semiconductor device according to the first embodiment of the present disclosure. Figure 2FIG2 shows a schematic top view of the semiconductor device according to the first embodiment of the present disclosure. Figure 3 Shown Figure 2 The enlarged structural diagram at the dotted line frame 11 is shown in FIG. Figure 4 Shown along Figure 2 Schematic diagram of the cross-section structure cut by line AA, Figure 5 Shown along Figure 2 Schematic diagram of the cross-section structure cut along line BB. In order to more clearly show the positional relationship of each structure in the semiconductor device, Figures 1 to 5 The insulating layer above the semiconductor layer is not shown. Figure 2 and Figure 3 Only the trench and its internal structure as well as the source conductive layer and the conductive plug are shown.
[0064] like Figures 1 to 5 As shown, the semiconductor device of the first embodiment of the present disclosure has multiple cells formed based on the semiconductor layer 10, at least one cell includes: a well region 121, a source region 122, a field plate structure 130, a first gate structure 140, a source conductive layer 150, a field plate conductive plug 160 and a source wiring layer 170.
[0065] In this embodiment, the semiconductor layer 10 includes a substrate 101 and an epitaxial layer 11 located on the substrate 101. A well region 121 extends inward from the surface of the semiconductor layer 10. A source region 122 extends inward from the surface of the semiconductor layer 10 within the well region 121. The depth of the source region 122 is less than that of the well region 121. The well region 121 is either P-type or N-type, while the semiconductor layer 10 and the source region 122 are either P-type or N-type. The substrate 101 can serve as a drain, and its material may be, for example, silicon, silicon carbide, germanium, gallium nitride, or the like.
[0066] The semiconductor device of this embodiment can be used as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT), for example, a drain contact region is formed in the substrate, and the conductivity type of the drain contact region is set to P-type or N-type. However, the embodiments of the present disclosure are not limited to this. Those skilled in the art can make other settings for the conductivity type of each region in the semiconductor layer 10 as needed to use the semiconductor device as a MOSFET or IGBT. Other settings can also be made to the components of the semiconductor layer 10 as needed, for example, the semiconductor layer 10 only includes the substrate 101 but does not include the epitaxial layer 110, and the well region 121 is directly formed in the substrate 101.
[0067] The field plate trench 102 and gate trench 103 extend from the top surface of the semiconductor layer 10 into the semiconductor layer 10. The gate trench 103 surrounds the field plate trench 102 and separates the field plate trench 102. Starting from the top surface of the semiconductor layer 10, the field plate trench 102 and gate trench 103 sequentially pass through the source region 122 and the well region 121, reaching their bottoms into the epitaxial layer 110. The width of the field plate trench 102 is greater than the width of the gate trench 103, and the depth of the field plate trench 102 is greater than the depth of the gate trench 103. This allows the field plate trench 102 to penetrate deeper into the epitaxial layer 110, even reaching the substrate 101, to enhance the auxiliary depletion capability. The deep penetration of the field plate trench 102 into the epitaxial layer 110 can better control the electric field distribution at the bottom of the trench, enhancing the auxiliary depletion effect. This helps improve the device's breakdown voltage (BV) performance, making it more stable and reliable at high voltages.
[0068] The field plate structure 130 includes a field plate dielectric layer 131 and a field plate conductor 132. The field plate dielectric layer 131 covers the inner surface of the field plate trench 102. The field plate conductor 132 fills the field plate trench 102 and is separated from the semiconductor layer 10 by the field plate dielectric layer 131. The first gate structure 140 includes a first gate dielectric layer 141 and a first gate conductor 142.
[0069] The first gate dielectric layer 141 covers the inner surface of the gate trench 103. The first gate conductor 142 is filled in the gate trench 103 and is separated from the semiconductor layer 10 by the first gate dielectric layer 141. The material of the field plate dielectric layer 131 and the first gate dielectric layer 141 is, for example, an oxide layer, and the material of the field plate conductor 132 and the first gate conductor 142 is, for example, polysilicon. The thickness of the first gate dielectric layer 141 is less than the thickness of the field plate dielectric layer 131. The thinner first gate dielectric layer 141 can reduce the capacitance between the gate and the active area, thereby improving the control ability of the gate. This helps to more effectively control the opening and closing of the channel when the device is working, and improve the switching speed and performance of the device. By adjusting the thickness of the first gate dielectric layer 141, the capacitance parameters between the gate and the active area can be optimized, further improving the overall performance of the device. Especially in high-frequency applications, optimizing the capacitance parameters can reduce signal delay and improve signal integrity.
[0070] In this embodiment, the field plate trenches 102 are circular and there are multiple of them, and the gate trenches 103 are in a grid shape, with each grid corresponding to one field plate trench 102. More specifically, each grid of the gate trenches 103 is rectangular. Figure 2 Nine grids of the gate trench 103 are shown, corresponding to the nine cells of the device. Of course, the number and correspondence between grids and cells can be set as needed. In some other embodiments, each grid of the gate trench 103 can also form other polygons surrounding the field plate trench 102, and the field plate trench 102 can also have other shapes.
[0071] In at least one cell of this embodiment, the first gate structure 140 surrounds a terrace region 10a of the semiconductor layer 10. The field plate structure 130 is located at the center of the terrace region 10a. The well region 121 is located in the terrace region 10a between the first gate structure 140 and the field plate structure 130. The depth of the well region 121 is less than the depth of the first gate structure 140, and the sidewalls of the well region 121 are in contact with the sidewalls of the first gate structure 140 and the field plate structure 130. The sidewalls of the source region 122 are in contact with the sidewalls of the first gate structure 140 and the field plate structure 130. The source conductive layer 150 is located in the terrace region 10a between the first gate structure 140 and the field plate structure 130. It is located above the surface of the semiconductor layer 10, passes through the source region 122, and extends its bottom into the well region 121. The source conductive layer 150 includes multiple discontinuous portions.
[0072] In some specific embodiments, the first gate structure 140 in the cell forms a closed regular polygonal structure. Multiple discontinuous portions of the source conductive layer 150 conform to the first gate structure 140, and the source conductive layer 150 is separated from the field plate structure 130, and the source conductive layer 150 is separated from the gate structure 140. For example, the first gate structure 140 forms a square structure, and the source conductive layer 150 includes four discontinuous portions, each of which forms an L-shaped structure corresponding to one corner of the square first gate structure 140, and the two sides of the L-shape correspond to two adjacent sides of the square first gate structure 140. The field plate conductive plug 160 corresponds to the field plate trench 102, and the bottom extends into the field plate conductor 132. The source wiring layer 170 is located above the semiconductor layer 10 and is respectively connected to the multiple source conductive layers 150 and the field plate conductive plug 160.
[0073] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other arrangements for the distribution and shape of the source conductive layer 150 as needed.
[0074] Compared to conventional SGT devices, the semiconductor device of the first embodiment of the present disclosure separates the field plate trench from the gate trench. The field plate trench contains source polysilicon and is separated from the active area by an oxide layer dielectric. The gate trench contains gate polysilicon and is separated from the active area by a relatively thin oxide layer dielectric. Separate contact holes are distributed in the active area. The separate contact holes can be distributed around and on both sides of the field plate trench to achieve potential extraction. The field plate trench penetrates deep into the substrate, which helps enhance the depletion capability. By reasonably adjusting the epitaxial concentration, the Rdson, BV, and output capacitance capabilities can be improved.
[0075] The following will be combined Figures 6 to 12 A method for manufacturing a semiconductor device according to a first embodiment of the present disclosure will be described in detail.
[0076] like Figure 6 As shown, an epitaxial layer 110 is formed on a substrate 101, and a hard mask 104 is formed on the upper surface of the epitaxial layer 110. The epitaxial layer 110 is etched through the opening in the hard mask 104 to form a field plate trench 102 and a gate trench 103. The width of the field plate trench 102 is greater than the width of the gate trench 103. In this step, the etching depths of the field plate trench 102 and the gate trench 103 are substantially the same.
[0077] Furthermore, a sacrificial layer 105 is formed in the field plate trench 102 and the gate trench 103, as shown in FIG. Figure 7 shown.
[0078] In this step, a sacrificial layer 105 is deposited, for example, by chemical vapor deposition (CVD) or other suitable processes. The thickness of the deposited layer should be sufficient to completely fill the gate trench 103. To save costs, it is not necessary to completely fill the large field plate trench 102. The material of the sacrificial layer 105 is, for example, an oxide.
[0079] Furthermore, the depth of the field plate trench 102 is extended, as shown in FIG. Figure 8 shown.
[0080] In this step, for example, the sacrificial layer 105 above the hard mask 104 is first removed by a process such as chemical mechanical polishing (CMP), and then a barrier layer is formed above the gate trench 103. The field plate trench 102 is then etched further, extending the field plate trench 102 further into the substrate 101. The sacrificial layer 105 within the field plate trench 102 is also removed.
[0081] Furthermore, a field plate dielectric layer 131 is formed on the inner surface of the field plate trench 102 and a field plate conductor 132 is filled in the field plate trench 102, as shown in FIG. Figure 9 shown.
[0082] In this step, a field plate dielectric layer 131 is first formed on the inner surface of the field plate trench 102 by thermal oxidation, chemical vapor deposition (CVD), or other suitable processes. The thickness of the field plate dielectric layer 131 can be adjusted according to actual needs to ensure good insulation performance. Subsequently, a field plate conductor 132 is filled in the field plate trench 102 by processes such as low-pressure chemical vapor deposition (LPCVD) or physical vapor deposition (PVD). The field plate conductor 132 is separated from the semiconductor layer 10 by the field plate dielectric layer 131, ensuring reliable isolation between the source and the semiconductor layer. The material of the field plate conductor 132 can be polysilicon, metal, or other conductive materials. The specific selection depends on the design requirements of the device and the compatibility of the manufacturing process.
[0083] Furthermore, a first gate dielectric layer 141 is formed on the inner surface of the gate trench 103, and a first gate conductor 142 is filled in the gate trench 103. Figure 10 shown.
[0084] In this step, for example, etching, CMP, or other processes are first used to remove the hard mask 104 and the barrier layer corresponding to the gate trench 103. A barrier layer is then formed above the field plate trench 102, and the sacrificial layer 105 within the gate trench 103 is removed. A first gate dielectric layer 141 is then formed on the inner surface of the gate trench 103 through thermal oxidation, chemical vapor deposition (CVD), or other suitable processes. The first gate dielectric layer 141 is relatively thin to reduce capacitance between the gate and the semiconductor layer, thereby improving device switching speed and efficiency. Subsequently, a first gate conductor 142 is formed in the gate trench 103 through processes such as low-pressure chemical vapor deposition (LPCVD) or physical vapor deposition (PVD). The first gate conductor 142 is separated from the semiconductor layer 10 by the first gate dielectric layer 141, ensuring reliable isolation between the gate and semiconductor layers. The material of the first gate conductor 142 can also be polysilicon, metal, or other conductive material. The specific material selection should take into account compatibility with the field plate conductor 132 and overall device performance. Finally, the barrier layer above the field plate trench 102 is removed.
[0085] Further, a well region 121 and a source region 122 are formed, as shown in FIG. Figure 11 shown.
[0086] In this step, a well region 121 is first formed in the epitaxial layer 110 through an ion implantation process. Subsequently, a source region 122 is formed within the well region 121. The doping type of the well region 121 is opposite to that of the substrate 101. For example, if the substrate 101 is P-type, the well region 121 is N-type, and vice versa. The doping type of the source region 122 is opposite to that of the well region 121 to form a source contact region. By precisely controlling the energy and dose of the ion implantation, the depth and doping concentration of the well region 121 and source region 122 can be ensured to meet design requirements, thereby optimizing the device's electrical performance.
[0087] Furthermore, an isolation layer 180 is formed on the upper surface of the semiconductor layer 10, and a plurality of source conductive layers 150 and field plate conductive plugs 160 are formed penetrating the isolation layer 180, as shown in FIG. Figure 12 shown.
[0088] The material of the isolation layer 180 can be silicon dioxide (SiO2) or other insulating materials. Its function is to prevent the source conductive layer 150 and the field plate conductive plug 160 from short-circuiting with other parts of the semiconductor layer 10. After the isolation layer 180 is formed, a plurality of through holes are formed in the isolation layer 180 by photolithography and etching processes. The positions of these through holes are the same as those of the semiconductor layer 10. Figures 1 to 5 The source conductive layer 150 and the field plate conductive plug 160 are positioned correspondingly. Subsequently, these through-holes are filled with conductive material through processes such as electroplating, chemical vapor deposition (CVD), or physical vapor deposition (PVD) to form the source conductive layer 150 and the field plate conductive plug 160. The material of the source conductive layer 150 and the field plate conductive plug 160 can be metal (such as aluminum, copper, etc.) or polysilicon, the specific choice depending on the device design requirements and the compatibility of the manufacturing process.
[0089] Furthermore, a source wiring layer 170 is formed on the isolation layer 180, as shown in FIG. Figure 12 shown.
[0090] The source wiring layer 170 electrically connects to the multiple source conductive layers 150 and the field plate conductive plug 160, thereby providing access to the field plate conductor 132 within the field plate trench 102. The source wiring layer 170 can be made of a metal (such as aluminum or copper), and its thickness and width can be adjusted based on actual application requirements to ensure good conductivity and mechanical strength. Furthermore, the design of the source wiring layer 170 can also consider heat dissipation and electromagnetic compatibility (EMC) requirements to further enhance overall device performance. For example, the portion of the source wiring layer 170 connecting the source conductive layer 150 and the field plate conductive plug 160 can be formed as a single piece to increase the heat dissipation area.
[0091] A dielectric layer covering the source wiring layer 170 may also be formed on the isolation layer 180 , and a first gate conductive plug penetrating the dielectric layer and the isolation layer 180 may be formed. The first gate conductive plug contacts the first gate conductor 142 , and a first gate wiring layer is correspondingly formed on the dielectric layer.
[0092] Figure 13 A schematic top view of the semiconductor device according to the second embodiment of the present disclosure is shown.
[0093] like Figure 13 As shown, the semiconductor device of the second embodiment of the present disclosure is substantially the same as that of the first embodiment, and similarities are not repeated here, and reference may be made to the relevant description.
[0094] The difference is that, in this embodiment, the source conductive layer 150 in the cell includes eight discontinuous parts, four of which form L-shaped structures corresponding to one corner of the square first gate structure 140 respectively, and the two sides of the L-shape correspond to two adjacent sides of the square first gate structure 140. The other four discontinuous parts form strip structures corresponding to one side of the square first gate structure 140 respectively, and the L-shaped structure and the strip structure are arranged at intervals.
[0095] Figure 14 A schematic top view of the structure of a semiconductor device according to a third embodiment of the present disclosure is shown.
[0096] like Figure 14 As shown, the semiconductor device of the third embodiment of the present disclosure is substantially the same as that of the first embodiment, and similarities are not repeated here, and reference may be made to the relevant description.
[0097] The difference is that, in this embodiment, the source conductive layer 150 in the cell includes four discontinuous parts forming a circular ring structure, each discontinuous part corresponds to one corner of the square first gate structure 140 , and the source conductive layer 150 is adjacent to the field plate trench 102 .
[0098] Figure 15 FIG2 shows a schematic top view of a semiconductor device according to a fourth embodiment of the present disclosure. Figure 16 Shown along Figure 15 Schematic diagram of the cross-section structure taken along the CC line.
[0099] like Figure 15 and Figure 16 As shown, the semiconductor device of the fourth embodiment of the present disclosure is substantially the same as that of the first embodiment, and similarities are not repeated here, and reference may be made to the relevant description.
[0100] The difference is that in this embodiment, at least one cell further includes a second gate conductor 192, which is located in the field plate trench 102 and extends in the field plate dielectric layer 131 along the thickness direction of the semiconductor layer 10. The second gate conductor 192 is separated from the field plate conductor 132 and the semiconductor layer 10 by the field plate dielectric layer 131. The extension depth of the second gate conductor 192 is greater than the depth of the well region 121. The field plate dielectric layer 131 surrounding the second gate conductor 192 also serves as the second gate dielectric layer 191. The second gate dielectric layer 191 and the second gate conductor 192 form a second gate structure surrounding the field plate conductor 132.
[0101] In this embodiment, the semiconductor device adopts a double-ring gate structure. The second gate conductor 192 and the first gate conductor 142 can be electrically connected to the gate wiring layer through a gate conductive plug, or the second gate conductor 192 and the first gate conductor 142 have different potential lead-out lines so as to be controlled separately.
[0102] In this embodiment, the introduction of the second gate conductor 192 further increases the channel density, improves the gate control capability, and reduces the channel resistance, thereby reducing the conduction loss of the device.
[0103] In addition, the provision of the second gate conductor 192 helps to enhance the depletion capability of the field plate structure 130, so that in high voltage applications, the breakdown voltage (BV) of the device is significantly improved, achieving overall performance optimization without sacrificing other parameters or adding special process steps.
[0104] Figure 17 A schematic top view of the structure of a semiconductor device according to a fifth embodiment of the present disclosure is shown.
[0105] like Figure 17 As shown, the semiconductor device of the fifth embodiment of the present disclosure is substantially the same as that of the fourth embodiment, and similarities are not repeated here, and reference may be made to the relevant description.
[0106] The difference is that, in this embodiment, the source conductive layer 150 in the cell includes two discontinuous portions, and the interval between the two discontinuous portions corresponds to the middle portions of two opposite sides of the square first gate structure 140 .
[0107] Figure 18 A schematic top view of the structure of a semiconductor device according to a sixth embodiment of the present disclosure is shown.
[0108] like Figure 18As shown, in at least one cell, the field plate structure 130 is sandwiched between two rows of first gate structures 140, and the two rows of first gate structures 140 are bent toward the field plate structure 130 to semi-enclose the field plate structure 130. In multiple cells, multiple field plate structures 130 are arranged in a staggered array, with each row of field plate structures 130 sandwiched between two rows of first gate structures 140, and adjacent rows of first gate structures 140 forming opposing fold lines to semi-enclose the row of field plate structures 130. A source conductive layer 150 is disposed between each row of field plate structures 130 and the adjacent row of first gate structures 140, and the source conductive layer 150 is conformal to the adjacent row of first gate structures 140.
[0109] Furthermore, it is also possible to set Figure 15 and Figure 16 The second gate structure is shown.
[0110] The above-mentioned embodiments of the present disclosure can improve the breakdown voltage, reduce the on-resistance, optimize the capacitance parameters without sacrificing other parameters or adding special process steps, and are compatible with existing processes.
[0111] In the above description, the technical details of patterning and etching of each layer are not described in detail. However, those skilled in the art will understand that various technical means can be used to form layers, regions, etc. of desired shapes. In addition, those skilled in the art may also design methods that are not identical to the methods described above to form the same structure. In addition, although each embodiment is described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage.
[0112] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.
Claims
1. A semiconductor device comprising a plurality of cells formed based on a semiconductor layer, at least one of the cells comprising: a first gate structure extending inward from a surface of the semiconductor layer, wherein the first gate structure surrounds or semi-surrounds a platform region of the semiconductor layer; a field plate structure, located at the center of the platform region and extending inward from the surface of the semiconductor layer; a well region, located in a platform region between the first gate structure and the field plate structure, extending inward from the surface of the semiconductor layer, wherein the depth of the well region is less than the depth of the first gate structure, and the sidewalls of the well region are in contact with the sidewalls of the first gate structure and the field plate structure; a source region, located in the well region, extending inward from the surface of the semiconductor layer, wherein the depth of the source region is less than the depth of the well region, and the sidewalls of the source region are in contact with the sidewalls of the first gate structure and the field plate structure; The source conductive layer is located in the platform region between the first gate structure and the field plate structure and is at least partially located on the surface of the semiconductor layer. The source conductive layer includes a plurality of discontinuous portions.
2. The semiconductor device according to claim 1, wherein In at least one of the cells, the first gate structure forms a closed regular polygonal structure.
3. The semiconductor device according to claim 2, wherein: A plurality of discontinuous portions of the source conductive layer are conformal to the first gate structure.
4. The semiconductor device according to claim 3, wherein The first gate structure forms a square structure, The source conductive layer includes four discontinuous parts, each discontinuous part forms an L-shaped structure corresponding to one corner of the square first gate structure, and two sides of the L-shape correspond to two adjacent sides of the square first gate structure.
5. The semiconductor device according to claim 3, wherein The first gate structure forms a square structure, The source conductive layer includes eight discontinuous parts, four of which form L-shaped structures corresponding to one corner of the square first gate structure respectively, and two sides of the L-shape correspond to two adjacent sides of the square first gate structure. The other four discontinuous parts form strip structures corresponding to one side of the square first gate structure respectively, and the L-shaped structure is spaced apart from the strip structure. The semiconductor device according to claim 3 , wherein: The first gate structure forms a square structure, The source conductive layer includes two discontinuous parts, and the interval between the two discontinuous parts corresponds to the middle of two opposite sides of the square first gate structure.
7. The semiconductor device according to claim 2, wherein The first gate structure forms a square structure, The source conductive layer includes four discontinuous parts forming a circular ring structure, and each discontinuous part corresponds to a corner of the square first gate structure.
8. The semiconductor device according to claim 1, wherein In at least one of the cells, the field plate structure is sandwiched between two rows of the first gate structures, and the two rows of the first gate structures are bent toward the field plate structure to semi-enclose the field plate structure.
9. The semiconductor device according to claim 8, wherein In at least one of the cells, the field plate structure is sandwiched between two rows of the source conductive layers, and the source conductive layer is conformal to an adjacent row of the first gate structures.
10. The semiconductor device according to claim 1, wherein An extension depth of the field plate structure in the semiconductor layer is greater than an extension depth of the first gate structure in the semiconductor layer.
11. The semiconductor device according to any one of claims 1 to 10, wherein: The semiconductor layer has a gate trench and a field plate trench, each extending from the surface of the semiconductor layer toward the inside. The first gate structure includes: a first gate dielectric layer, covering an inner surface of the gate trench; and a first gate conductor, located in the gate trench and separated from the semiconductor layer by the first gate dielectric layer; The field plate structure includes: a field plate dielectric layer, covering the inner surface of the field plate trench; and A field plate conductor is located in the field plate trench and is separated from the semiconductor layer by the field plate dielectric layer.
12. The semiconductor device according to claim 11, further comprising: The second gate conductor is located in the field plate trench, extends in the field plate dielectric layer along the thickness direction of the semiconductor layer, and is separated from the field plate conductor and the semiconductor layer respectively.
13. The semiconductor device according to claim 12, wherein The second gate conductor extends deeper than the well region.
14. The semiconductor device according to claim 11, wherein The at least one cell further comprises: a field plate conductive plug, at least partially located above the surface of the semiconductor layer and connected to the field plate conductor; and A source wiring layer is located above the semiconductor layer and is respectively connected to the plurality of source conductive layers and the field plate conductive plugs.
15. A method for manufacturing a semiconductor device, for forming the semiconductor device according to any one of claims 1 to 14.