Semiconductor device

Abstract

The invention relates to a semiconductor device. A protection unit has a first MISFET group composed of a plurality of first MISFETs and a second MISFET group composed of a plurality of second MISFETs. The first MISFET group and the second MISFET group are disposed separately from each other. The first MISFET group is electrically connected to the first power supply wiring group and the first ground wiring group to electrically short them. The second MISFET group is electrically connected to the second power supply wiring group and the first ground wiring group to electrically short them. In plan view, the first MISFET group overlaps a portion of the first power supply wiring group and a portion of the first ground wiring group.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The disclosure of Japanese Patent Application No. 2024-032909 filed on March 5, 2024 including the specification, drawings and abstract is incorporated herein by reference in its entirety. Background Art

[0003] The present invention relates to a semiconductor device, and in particular to a semiconductor device equipped with a protection unit for an ESD protection circuit.

[0004] In order to protect the various circuits formed in the semiconductor device from the damage of electrostatic discharge, a semiconductor device equipped with an electrostatic discharge (ESD) protection circuit is adopted. The ESD protection circuit includes, for example, a trigger circuit and a discharge circuit. The trigger circuit includes a detection circuit and an inverter. When the detection circuit detects the ESD current flowing to the power wiring, the detection circuit outputs a detection signal to the inverter. In response to the detection signal, the inverter outputs a drive signal to the gate electrode of a plurality of metal insulator semiconductor field effect transistors (MISFETs) constituting the discharge circuit. Each MISFET of the discharge circuit is in the on state, and the ESD current is discharged from the power wiring to the ground wiring.

[0005] The disclosed technologies are listed below.

[0006] [Patent Document 1] International Publication No. 2016 / 203648

[0007] For example, Patent Document 1 discloses an ESD protection circuit including an RC timer as a detection circuit, an inverter, and an n-channel transistor as a discharge circuit. Patent Document 1 also discloses a planar layout in which the RC timer, the inverter, and the n-channel transistor are sequentially arranged in one direction as protection units for the ESD protection circuit. Summary of the Invention

[0008] The present invention relates to a semiconductor device, and in particular to a semiconductor device equipped with a protection unit for an ESD protection circuit.

[0009] On the other hand, several types of power supply wiring groups are provided depending on the type of power supply used in the semiconductor device, and therefore, several types of protection cells with different voltage resistances are provided. By laying out the discharge circuits of each of the several types of protection cells so that they overlap with the corresponding power supply wiring group and ground wiring group in plan view, rapid discharge can be achieved. However, providing each of the several types of protection cells independently increases the area occupied by the protection cells in the peripheral region, making it difficult to promote miniaturization of the semiconductor device. Consequently, it is difficult to promote miniaturization of the semiconductor device while simultaneously performing rapid discharge and ensuring the reliability of the semiconductor device.

[0010] Other issues and novel features will become clear from the description of this specification and the accompanying drawings.

[0011] Typical embodiments among the embodiments disclosed in this application will be briefly described below.

[0012] In one embodiment, a semiconductor device is provided, which includes: a core region in which a first circuit and a second circuit are provided, a peripheral region surrounding the core region in a plan view, a protection unit provided in the peripheral region and constituting an ESD protection circuit, a first power wiring group for supplying a first power supply potential to the first circuit, a second power wiring group for supplying a second power supply potential to the second circuit, and a first ground wiring group for supplying a first ground potential to the first circuit and the second circuit, the first power wiring group, the second power wiring group and the first ground wiring group being provided in the peripheral region so as to overlap with the protection unit in a plan view, the protection unit having a first MISFET group consisting of a plurality of first MISFETs and a second MISFET group consisting of a plurality of second MISFETs, the first MISFET group and the second MISFET group being provided separately from each other, the first MISFET group being electrically connected to the first power wiring group and the first ground wiring group so as to electrically short-circuit the first power wiring group and the first ground wiring group, the second MISFET group being electrically connected to the second power wiring group and the first ground wiring group so as to electrically short-circuit the second power wiring group and the first ground wiring group, and the first MISFET group overlapping with a portion of the first power wiring group and a portion of the first ground wiring group in a plan view.

[0013] According to one embodiment, it is possible to promote miniaturization of a semiconductor device and ensure the reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a plan view showing a semiconductor device according to a first embodiment;

[0015] Figure 2 is a plan view showing a semiconductor device according to a first embodiment;

[0016] Figure 3 is an equivalent circuit diagram showing the ESD protection circuit in the first embodiment and the studied example;

[0017] Figure 4 is an equivalent circuit diagram showing the ESD protection circuit in the first embodiment and the studied example;

[0018] Figure 5 is a plan view showing a protection unit in a study example;

[0019] Figure 6 is a plan view showing a power wiring group and a ground wiring group formed above a protection unit in a studied example;

[0020] Figure 7 It is a plan view used to explain the problem of the research example;

[0021] Figure 8 is an equivalent circuit diagram used to explain the problem of the study example;

[0022] Figure 9 It is a plan view used to explain other issues of the research example;

[0023] Figure 10 is a plan view showing a protection unit in the first embodiment;

[0024] Figure 11 is a plan view showing a power wiring group and a ground wiring group formed above the protection unit in the first embodiment;

[0025] Figure 12 is a plan view showing a detailed structure of a protection unit in the first embodiment;

[0026] Figure 13 is a sectional view showing a protection unit in the first embodiment;

[0027] Figure 14 is a plan view showing a MISFET in the first embodiment;

[0028] Figure 15 is a cross-sectional view showing a MISFET in the first embodiment;

[0029] Figure 16 is an equivalent circuit diagram showing the ESD protection circuit in the first embodiment;

[0030] Figure 17 is an equivalent circuit diagram showing an ESD protection circuit in a second embodiment;

[0031] Figure 18 is a plan view showing a protection unit in a second embodiment; and

[0032] Figure 19 is a plan view showing a detailed layout of a protection unit in the second embodiment. DETAILED DESCRIPTION

[0033] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In all the drawings used to explain the embodiments, components having the same function are represented by the same reference numerals, and their repeated descriptions are omitted. In the following embodiments, the description of the same or similar components will not be repeated in principle unless particularly necessary.

[0034] In addition, the X-direction, Y-direction, and Z-direction described in this application intersect and are orthogonal to each other. In this application, the Z-direction is described as the vertical direction, depth direction, or thickness direction of a specific structure. The expression "plan view" or "plan view" used in this application means that the plane formed by the X-direction and the Y-direction is regarded as a "plane", and this "plane" is observed from the Z-direction.

[0035] (First embodiment)

[0036] <Semiconductor Device Planar Layout>

[0037] The following will use Figure 1 and Figure 2 The planar layout of the semiconductor device 100 in the first embodiment is described.

[0038] like Figure 1 As shown, semiconductor device 100 is a semiconductor chip that includes a core region CR and a peripheral region OR surrounding the core region CR in a plan view. The core region CR is equipped with multiple circuits. For example, these multiple circuits include logic circuits constituting a CPU or SRAM, and analog intellectual property (IP). IP refers to a circuit functional block with a specific function. Examples of analog IP include a phase-locked loop (PLL), a true random number generator (TRNG), an oscillator, a temperature sensor, an analog-to-digital converter, and a digital-to-analog converter.

[0039] The logic circuits are composed of low-voltage MISFETs. The analog IP is composed of high-voltage MISFETs with a higher withstand voltage than the low-voltage MISFETs. For example, the gate insulating film thickness of the low-voltage MISFETs is thinner than that of the high-voltage MISFETs, and the gate length of the low-voltage MISFETs is shorter than that of the high-voltage MISFETs. Furthermore, the pitch between the gate electrodes of the multiple low-voltage MISFETs is narrower than that of the multiple high-voltage MISFETs.

[0040] In the peripheral region OR, a plurality of protection cells ESD12, a plurality of protection cells ESD3, and a plurality of I / O (input / output) signal cells 10C are provided. The I / O signal cells 10C are composed of the above-mentioned high-voltage MISFETs.

[0041] Each of the plurality of protection cells ESD12 and the plurality of protection cells ESD3 includes a plurality of MISFETs for constituting an ESD protection circuit. The protection cell ESD12 constitutes an ESD protection circuit for a plurality of circuits provided in the core region CR. The protection cell ESD3 constitutes an ESD protection circuit for the I / O signal cell 10C.

[0042] The semiconductor device 100 has a rectangular planar shape and includes sides 10a and 10b along the X direction and sides 10c and 10d along the Y direction. The sides 10a, 10b, 10c, and 10d constitute the outer edge of the peripheral region OR. The peripheral region OR is a region provided between the core region CR and the sides 10a, 10b, 10c, and 10d.

[0043] like Figure 2 As shown, the peripheral region OR is provided with a group of power wirings LVcc composed of a plurality of power wirings and a group of ground wirings LVss composed of a plurality of ground wirings. The group of power wirings LVcc includes a group of power wirings LVcc1, a group of power wirings LVcc2 for supplying a higher power voltage than the group of power wirings LVcc1, and a group of power wirings LVcc3 for supplying a higher power voltage than the group of power wirings LVcc2. The group of ground wirings LVss includes a group of ground wirings LVss1 and a group of ground wirings LVss2.

[0044] The power wiring group LVcc1, LVcc2, LVcc3, and the ground wiring groups LVss1 and LVss2 surround the core region CR in plan view and extend along sides 10a, 10b, 10c, and 10d so as to overlap with the protection cells ESD12, ESD3 and the I / O signal cell 10C in plan view.

[0045] Power supply wiring group LVcc1 supplies power supply potential to multiple circuits comprised of low-voltage MISFETs in the core region CR. Power supply wiring group LVcc2 supplies power supply potential to multiple circuits comprised of high-voltage MISFETs in the core region CR. Ground wiring group LVss1 supplies ground potential to multiple circuits comprised of low-voltage MISFETs or high-voltage MISFETs in the core region CR. Power supply wiring group LVcc3 supplies power supply potential to the I / O signal cell 10C. Ground wiring group LVss2 supplies ground potential to the I / O signal cell 10C.

[0046] It should be noted that, as will be described in detail later, each of the power supply wiring groups LVcc1, LVcc2, LVcc3 and the ground wiring groups LVss1, LVss2 is composed of a plurality of wirings M13 and M14 formed in the global wiring layer in the multi-layer wiring layer.

[0047] <ESD protection circuit>

[0048] Hereinafter, Figure 3 and Figure 4 will be used to describe the ESD protection circuit 50 provided in the semiconductor device 100 according to the first embodiment.

[0049] As Figure 3 shown, a plurality of circuits in the core region CR and the I / O signal unit IOC are supplied with a power supply potential from a power supply terminal TVcc connected to the power supply wiring group LVcc, and are supplied with a ground potential from a ground terminal TVss connected to the ground wiring group LVss.

[0050] The ESD protection circuit 50 includes a trigger circuit TR and a discharge circuit B-MOS. The trigger circuit TR includes a detection circuit SPC and an inverter INV. The discharge circuit B-MOS includes a group of MISFETs 1QA. The group of MISFETs 1QA is composed of a plurality of n-type MISFETs 1Q connected in parallel. The inverter INV includes multiple groups of MISFETs 2QA and 3QA. The group of MISFETs 2QA is composed of a plurality of p-type MISFETs 2Q connected in parallel. The group of MISFETs 3QA is composed of a plurality of n-type MISFETs 3Q connected in parallel. The detection circuit SPC is a time constant circuit for detecting a positive surge voltage, and is, for example, composed of an integration circuit including a resistance element and a capacitance element.

[0051] The detection circuit SPC, the inverter INV (each group of MISFETs 2QA, 3QA), and the discharge circuit B-MOS (the group of MISFETs 1QA) are electrically connected to the power supply wiring group LVcc and the ground wiring group LVss, respectively, to electrically short-circuit them.

[0052] When the detection circuit SPC detects an ESD current flowing into the power supply wiring group LVcc, the detection circuit SPC outputs a detection signal to the inverter INV. In response to the detection signal, the MISFET group 2QA of the inverter INV outputs a signal to each gate electrode of the plurality of MISFETs 1Q to turn on the plurality of MISFETs 1Q, thereby forming the discharge circuit B-MOS. As a result, as Figure 3 shown by the "discharge path" in, the ESD current is discharged from the power supply wiring group LVcc to the ground wiring group LVss.

[0053] When the detection circuit SPC does not detect the ESD current, the MISFET group 3QA of the inverter INV outputs a signal to each gate electrode of the plurality of MISFETs 1Q to turn off the plurality of MISFETs 1Q.

[0054] For example, when a steep high voltage is applied to the power terminal TVcc, ESD current flows from the power wiring group LVcc to the ground wiring group LVss through the ESD protection circuit 50. This prevents the circuits in the core region CR and protected circuits (such as the I / O signal cell 10C) from being destroyed by the steep high voltage.

[0055] Figure 4 Each ESD protection circuit 50 used in the first embodiment is shown. The ESD protection circuit 50a, which electrically short-circuits the power supply wiring group LVcc1 and the ground wiring group LVss1, includes a trigger circuit TR1 and a discharge circuit B-MOS1. The ESD protection circuit 50b, which electrically short-circuits the power supply wiring group LVcc2 and the ground wiring group LVss1, includes a trigger circuit TR2 and a discharge circuit B-MOS2. The ESD protection circuit 50c, which electrically short-circuits the power supply wiring group LVcc3 and the ground wiring group LVss2, includes a trigger circuit TR3 and a discharge circuit B-MOS3.

[0056] For example, the bidirectional diode BD is composed of two diodes, one of which has an anode electrically connected to the other cathode, and the other has an anode electrically connected to the cathode. The bidirectional diode BD forms a discharge path from the ground wiring group LVss1 to the ground wiring group LVss2 or from the ground wiring group LVss2 to the ground wiring group LVss1.

[0057] Note that each MISFET included in the trigger circuit TR1 and the discharge circuit B-MOS1 is identical to the low-voltage MISFET in the core region CR. Each MISFET included in the trigger circuit TR2 and the discharge circuit B-MOS2 is identical to the high-voltage MISFET in the core region CR. Each MISFET included in the trigger circuit TR3 and the discharge circuit B-MOS3 is identical to the high-voltage MISFET in the I / O signal cell 10C.

[0058] <Research Examples and Questions>

[0059] The following will use Figures 5 to 9 A semiconductor device of a research example that the inventors of the present application have studied is described.

[0060] Figure 5The planar layout of the protection cell ESD1, the protection cell ESD2, and the protection cell ESD3 forming the ESD protection circuit 50a, 50b, and 50c is shown. Here, the protection cells ESD1, ESD2, and ESD3 are arranged side by side with 10a.

[0061] Typically, in the peripheral region OR, the width of each of the protection cells ESD1, ESD2, and ESD3 in the Y direction is set to match the width of the I / O signal cell IOC in the Y direction.

[0062] In addition, if Figure 6 As shown, for rapid discharge, the discharge circuit B-MOS1 is arranged to overlap as much as possible with the power wiring group LVcc1 and the ground wiring group LVss1 in a plan view. For the same reason, the discharge circuit B-MOS2 is arranged to overlap as much as possible with the power wiring group LVcc2 and the ground wiring group LVss1 in a plan view, and the discharge circuit B-MOS3 is arranged to overlap as much as possible with the power wiring group LVcc3 and the ground wiring group LVss2 in a plan view.

[0063] like Figure 7 As shown, for example, in the case of the protection unit ESD1, if the discharge circuit B-MOS1 (MISFET group 1QA) is provided at a position away from the power supply wiring group LVcc1 and the ground wiring group LVss1, wiring is required to connect each MISFET 1Q to the power supply wiring group LVcc1 and the ground wiring group LVss1. Therefore, the farther away from the power supply wiring group LVcc1 and the ground wiring group LVss1, the greater the wiring resistance ( Figure 3 The greater the wiring resistance R1).

[0064] Figure 8 The equivalent circuit diagram shows the wiring resistance R1n between the power supply wiring group LVcc1, the ground wiring group LVss1, and the MISFET 1Q. The longer the distance between the power supply wiring group LVcc1, the ground wiring group LVss1, and the MISFET 1Q, that is, the larger the value of the "natural number n," the greater the wiring resistance R1n. Therefore, the longer the distance between the power supply wiring group LVcc1, the ground wiring group LVss1, and the MISFET 1Q, the slower the discharge. In other words, the clamping performance of the ESD protection circuit 50 deteriorates.

[0065] At the same time, if Figure 5As shown, each of the protection cells ESD1, ESD2, and ESD3 has an open space OS. Semiconductor devices such as MISFETs that contribute to the ESD protection circuit 50 are not formed in the open space OS, but rather dummy gate patterns are formed. The dummy gate patterns contribute to planarizing the top surface of, for example, an interlayer insulating film formed in a multilayer wiring layer. The reasons for providing such open spaces OS are described below in the research example.

[0066] exist Figure 9 In the “Discussion A” of FIG. 5 , in order to effectively utilize the open space OS as a part of the protection circuit 50 , a discharge circuit B-MOS1 (MISFET group 1QA) is further provided in the open space OS.

[0067] In recent years, with the miniaturization of semiconductor devices, the application of MISFETs such as the FIN-FET structure has progressed, and the thinning of the gate insulating film of MISFETs and the increase in the gate width of MISFETs have also been advancing. Considering the impact of these factors on the performance of the ESD protection circuit 50, the problem of thinning the gate insulating film of the MISFET 1Q and increasing the gate width Wg of the MISFET 1Q has arisen, resulting in an excessive increase in the gate capacitance Cg.

[0068] like Figure 9 As shown in "Discussion A" of FIG1 , the greater the number of MISFETs 1Q included in the MISFET group 1QA, the greater the likelihood that the output signal from the trigger circuit TR1 to the MISFET group 1QA will be delayed due to an increase in gate capacitance Cg. Consequently, the gate drive force of the MISFET 1Q decreases, or the speed at which it turns on slows. This leads to difficulties in adequately protecting the multiple circuits provided in the core region CR from the effects of ESD current. In other words, the clamping performance of the ESD protection circuit 50 deteriorates.

[0069] Therefore, if Figure 9 As shown in "Discussion B" of FIGURE 2, in protection cell ESD1, the number of MISFETs 1Q included in MISFET group 1QA is adjusted to optimize gate width Wg and reduce gate capacitance Cg. As a result, it is necessary to provide an open space OS. For the same reason, an open space OS is also provided in protection cells ESD2 and ESD3.

[0070] However, taking such measures increases the occupied area of ​​the protection units ESD1 , ESD2 , and ESD3 in the peripheral region OR, making it difficult to promote miniaturization of the semiconductor device 100 .

[0071] like Figure 9As shown in "Discussion C" of FIG1 , it is conceivable to reduce the width of protection unit ESD1 in the X direction and reduce the area of ​​protection unit ESD1 to reduce the area of ​​open space OS. For the same reason, it is conceivable to reduce the width of protection units ESD2 and ESD3 in the X direction to achieve miniaturization of semiconductor device 100.

[0072] However, such measures reduce the number of wires extending from the power supply wiring group LVcc1 and the ground wiring group LVss1 in the Y direction. Furthermore, the number of MISFETs 1Q formed away from the power supply wiring group LVcc1 and the ground wiring group LVss1 increases, and the length of these wires extending in the Y direction becomes longer. As a result, the wiring resistance R1 increases, and discharge slows down. In other words, the clamping performance of the ESD protection circuit 50 decreases. Therefore, considering the clamping performance of the ESD protection circuit 50, reducing the width of the protection cell ESD1 in the X direction is not highly desirable.

[0073] <Protection Unit of First Embodiment>

[0074] In the following, we will use Figures 10 to 15 The protection unit ESD12 in the first embodiment is described. Figure 1 The protection units ESD12 and ESD3 are shown as an example, wherein the protection units ESD12 and ESD3 are arranged along the side 10a.

[0075] In the first embodiment, by Figure 5 In the example of the study of protection unit ESD1, the trigger circuit TR2 and discharge circuit B-MOS2 of protection unit ESD2 are provided in the open space OS, forming protection unit ESD12. In other words, protection unit ESD12 integrates the functions of both protection unit ESD1 and protection unit ESD2. It should be noted that the protection unit ESD3 and I / O signal unit 10C of the first embodiment are the same as those of the study example.

[0076] like Figure 10 As shown, in the protection cell ESD12 , a discharge circuit B-MOS1 , a trigger circuit TR1 , a discharge circuit B-MOS2 , a trigger circuit TR2 , and a bidirectional diode BD are sequentially provided in the direction from the core region CR toward the side 10 a .

[0077] In other words, the MISFET group 1QA of the discharge circuit B-MOS1 and the MISFET group 1QA of the discharge circuit B-MOS2 are arranged separately from each other. The distance between the core region CR of the discharge circuit B-MOS1 and the MISFET group 1QA is shorter than the distance between the core region CR and the MISFET group 1QA of the discharge circuit B-MOS2. The MISFET group 1QA of the discharge circuit B-MOS1 is arranged between the core region CR and the trigger circuit TR1. The trigger circuit TR1 is arranged between the MISFET group 1QA of the discharge circuit B-MOS1 and the MISFET group 1QA of the discharge circuit B-MOS2. The MISFET group 1QA of the discharge circuit B-MOS2 is arranged between the trigger circuit TR1 and the trigger circuit TR2. The trigger circuit TR2 is arranged between the MISFET group 1QA of the discharge circuit B-MOS2 and the bidirectional diode BD.

[0078] Figure 12 The detailed planar layout of the MISFET groups 1QA, 2QA, 3QA and the detection circuit SPC included in the protection unit ESD12 is shown. Figure 12 Rotating 180 degrees, a detailed planar layout of the MISFET group 1QA, 2QA, 3QA and the detection circuit SPC included in the protection unit ESD3 can be obtained.

[0079] like Figure 12 As shown, the MISFET group 2QA is provided between the MISFET group 1QA and the MISFET group 3QA. The MISFET group 3QA is provided between the MISFET group 2QA and the detection circuit SPC.

[0080] The MISFET 1Q includes a p-type well region PW1 formed in a semiconductor substrate, an n-type gate electrode GEn formed on the well region PW1 via a gate insulating film, and an n-type impurity region NSD formed in the well region PW1. The impurity region NSD constitutes the source region or the drain region of the MISFET 1Q. A p-type impurity region PR1 is formed in the well region PW1. The impurity region PR1 surrounds the multiple MISFETs 1Q in plan view. The MISFET group 1QA consists of multiple MISFETs 1Q connected in parallel.

[0081] The planar layout shape of the MISFET group 1QA forms a rectangular shape. The MISFET groups 2QA and 3QA and the detection circuit SPC are arranged along the short sides of the MISFET group 1QA.

[0082] In other words, the planar shape of the well region PW1 in which the MISFET group 1QA is formed is rectangular. Furthermore, the region surrounded by the impurity region PR1 in a plan view is the region in which the MISFET group 1QA is arranged, and is rectangular. Therefore, the long side of the MISFET group 1QA can be referred to as the long side of the well region PW1 or the long side of the impurity region PR1, and the short side of the MISFET group 1QA can be referred to as the short side of the well region PW1 or the short side of the impurity region PR1.

[0083] The MISFET 2Q includes an n-type well region NW1 formed in a semiconductor substrate, a p-type gate electrode GEp formed on the well region NW1 via a gate insulating film, and a p-type impurity region PSD formed in the well region NW1. The impurity region PSD constitutes the source region or drain region of the MISFET 2Q. An n-type impurity region NR1 is formed in the well region NW1. The impurity region NR1 surrounds the plurality of MISFETs 2Q in plan view. A group of MISFETs 2QA consists of the plurality of MISFETs 2Q connected in parallel.

[0084] The MISFET 3Q includes a p-type well region PW2 formed in a semiconductor substrate, an n-type gate electrode GEn formed on the well region PW2 via a gate insulating film, and an n-type impurity region NSD formed in the well region PW2. The impurity region NSD constitutes the source region or drain region of the MISFET 3Q. A p-type impurity region PR2 is formed in the well region PW2. The impurity region PR2 surrounds the plurality of MISFETs 3Q in plan view. A group of MISFETs 3QA consists of the plurality of MISFETs 3Q connected in parallel.

[0085] In the first embodiment, as an example, the MISFET 1Q is an n-type, the MISFET 2Q is a p-type, and the MISFET 3Q is an n-type. However, if the MISFET 1Q is a p-type, a p-type MISFET 2Q and an n-type MISFET 3Q are used. In this case, for example, the impurity region NSD becomes a p-type impurity region, and the conductivity type of each component included in each group of MISFETs 1QA, 2QA, and 3QA becomes the opposite conductivity type.

[0086] In order to connect the respective groups of MISFETs 1QA, 2QA, 3QA and the detection circuit SPC, a plurality of wirings M1 and a plurality of wirings M2 are used. The wirings M1 are formed in the lowest wiring layer in the multilayer wiring layer, and the wirings M2 are formed in the wiring layer above the wirings M1.

[0087] The detection circuit SPC is electrically connected to each gate electrode GEp of the plurality of MISFETs 2Q and each gate electrode GEn of the plurality of MISFETs 3Q through wirings M1 and M2. Each drain region of the plurality of MISFETs 2Q and the plurality of MISFETs 3Q is electrically connected to each gate electrode GEn of the plurality of MISFETs 1Q through wirings M1 and M2.

[0088] In order to make the drawing clear, only the wirings M1 and M2 are used to connect the respective groups of MISFETs 1QA, 2QA, 3QA, and the detection circuit SPC is shown.

[0089] That is, some of the plurality of wirings M1 and the plurality of wirings M2 are electrically connected to the power supply wiring group LVcc1, LVcc2 or the ground wiring group LVss1 through the wirings M3 to M12. Therefore, each group of MISFETs 1QA, 2QA, 3QA or the detection circuit SPC is electrically connected to the power supply wiring group LVcc1, LVcc2 or the ground wiring group LVss1 through the wirings M1 to M12.

[0090] Figure 11 A planar layout of power wiring groups LVcc1, LVcc2, LVcc3 and ground wiring groups LVss1 and LVss2 disposed above the protection unit ESD12, the protection unit ESD3, and the I / O signal unit 10C is shown.

[0091] For rapid discharge, the MISFET group 1QA of the discharge circuit B-MOS1 is arranged to overlap as much as possible with the power supply wiring group LVcc1 and the ground wiring group LVss1 in a plan view. The MISFET group 1QA of the discharge circuit B-MOS1 overlaps at least a portion of the power supply wiring group LVcc1 and a portion of the ground wiring group LVss1 in a plan view.

[0092] As described above, in the well region PW1, a plurality of impurity regions NSD constituting the source regions or drain regions of the plurality of MISFETs 1Q are formed. Therefore, it is more preferred that the area of ​​the well region PW1 overlapping with the power supply wiring group LVcc1 and the ground wiring group LVss1 in a plan view is larger than the area of ​​the well region PW1 not overlapping with the power supply wiring group LVcc1 and the ground wiring group LVss1. It is further preferred that the area of ​​the plurality of impurity regions NSD overlapping with the power supply wiring group LVcc1 and the ground wiring group LVss1 in a plan view is larger than the area of ​​the plurality of impurity regions NSD not overlapping with the power supply wiring group LVcc1 and the ground wiring group LVss1.

[0093] Furthermore, for rapid discharge, the MISFET group 1QA of the discharge circuit B-MOS2 is arranged to overlap with the power wiring group LVcc2 and the ground wiring group LVss1 as much as possible in a plan view. Figure 11 In the example shown in FIG. 2A , the MISFET group 2QA overlaps at least a portion of the power supply wiring group LVcc2 in a plan view.

[0094] The low-voltage MISFETs electrically connected to the power wiring group LVcc1 and the ground wiring group LVss1 in the core region CR have a lower EDS withstand voltage than the high-voltage MISFETs electrically connected to the power wiring group LVcc2 and the ground wiring group LVss1 in the core region CR. Therefore, the arrangement of the MISFET group 1QA of the discharge circuit B-MOS1 and the MISFET group 1QA of the discharge circuit B-MOS2 is set so that discharge by the MISFET group 1QA of the discharge circuit B-MOS1 takes priority over discharge by the MISFET group 1QA of the discharge circuit B-MOS2.

[0095] While the MISFET group 1QA of the discharge circuit B-MOS2 is optimally arranged so as to overlap with the power supply wiring group LVcc2 and the ground wiring group LVss1 in plan view, the high-voltage MISFETs electrically connected to the power supply wiring group LVcc2 and the ground wiring group LVss1 in the core region CR have a relatively high EDS withstand voltage. Therefore, even if the discharge speed is slightly delayed, the high-voltage MISFETs in the core region CR can be protected. In the first embodiment, in the protection cell ESD12, the discharge speed of the MISFET group 1QA of the discharge circuit B-MOS2 is not optimal. However, if the MISFET group 1QA of the discharge circuit B-MOS2 is arranged so as to overlap with a portion of the power supply wiring group LVcc2 in plan view, the discharge speed is within an acceptable range.

[0096] As described above, by using the protection unit ESD12 of the first embodiment, the occurrence of the open space OS can be suppressed and the occupation area of ​​the protection unit in the peripheral region OR can be reduced, thereby promoting the miniaturization of the semiconductor device 100. At the same time, it can quickly discharge and ensure the reliability of the semiconductor device 100.

[0097] <Cross-sectional structure of protection unit>

[0098] Figure 13 1A and 1B show an example of a cross-sectional structure of the MISFET group 1QA, the MISFET group 2QA, the MISFET group 3QA, and the detection circuit SPC included in the protection unit ESD12 or the protection unit ESD3. Figure 13 Essentially, from relative to Figure 12 The cross-sectional view of the surface formed by the plane view in the Y direction and the Z direction when viewed in the X direction. However, in order to make the structure of each MISFET easier to understand, Figure 13, the arrangement direction of each gate electrode GEn, GEp and each impurity region NSD, PSD is changed and illustrated.

[0099] like Figure 13 As shown, the semiconductor device 100 includes a semiconductor substrate SUB, a plurality of transistors, and a multi-layer wiring layer formed on the semiconductor substrate SUB.

[0100] The semiconductor substrate SUB has an upper surface and a lower surface and is made of, for example, p-type silicon. An element isolation portion (STI) is formed in the semiconductor substrate SUB. The element isolation portion (STI) includes a groove formed in the semiconductor substrate SUB to a predetermined depth from the upper surface of the semiconductor substrate SUB, and an insulating film embedded in the groove. The insulating film is, for example, a silicon oxide film.

[0101] An n-type well region DNW is formed in the semiconductor substrate SUB, and a p-type well region PW1 , an n-type well region NW1 , a p-type well region PW2 , and a p-type well region PW3 are formed in the well region DNW.

[0102] It should be noted that the semiconductor substrate SUB is electrically connected to the ground wiring group LVss1. The well region DNW is used to electrically isolate the semiconductor substrate SUB from the well region PW1, PW2, or PW3. As a region for electrically connecting the semiconductor substrate SUB to the ground wiring group LVss1, for example, when the protection cell ESD12 is used, the protection cell ESD12 does not need to be formed with the well region DNW.

[0103] On the well regions PW1, PW2, and PW3, gate electrodes GEn are formed through a gate insulating film. The gate electrodes GEn are, for example, n-type polysilicon films. On the well region NW1, gate electrodes GEp are formed through a gate insulating film. The gate electrodes GEp are, for example, p-type polysilicon films.

[0104] N-type impurity regions NSD are formed in well regions PW1, PW2, and PW3, respectively. Furthermore, p-type impurity region PR1 is formed in well region PW1, p-type impurity region PR2 is formed in well region PW2, and p-type impurity region PR3 is formed in well region PW3. P-type impurity region PSD is formed in well region NW1. Furthermore, n-type impurity region NR1 is formed in well region NW1.

[0105] The impurity region NSD formed in the well region PW1 functions as a source region or a drain region of the MISFET 1Q. A portion of the well region PW1 located between the source region and the drain region and covered by the gate electrode GEn functions as a channel region of the MISFET 1Q.

[0106] In the case of the protection cell ESD12, the well region PW1 is electrically connected to the ground wiring group LVss1 through the impurity region PR1. In the case of the protection cell ESD3, the well region PW1 is electrically connected to the ground wiring group LVss2 through the impurity region PR1.

[0107] The impurity region PSD formed in the well region NW1 functions as a source region or a drain region of the MISFET 2Q. In the well region NW1, a portion located between the source region and the drain region and covered by the gate electrode GEp functions as a channel region of the MISFET 2Q.

[0108] In the case of the trigger circuit TR1 of the protection cell ESD12, the well region NW1 is electrically connected to the power wiring group LVcc1 through the impurity region NR1. In the case of the trigger circuit TR2 of the protection cell ESD12, the well region NW1 is electrically connected to the power wiring group LVss2 through the impurity region NR1. In the case of the protection cell ESD3, the well region NW1 is electrically connected to the power wiring group LVss3 through the impurity region NR1.

[0109] The impurity region NSD formed in the well region PW2 functions as a source region or a drain region of the MISFET 3Q. In the well region PW2, a region located between the source region and the drain region and covered by the gate electrode GEn functions as a channel region of the MISFET 3Q.

[0110] In the case of the protection cell ESD12, the well region PW2 is electrically connected to the ground wiring group LVss1 through the impurity region PR2. In the case of the protection cell ESD3, the well region PW2 is electrically connected to the ground wiring group LVss2 through the impurity region PR2.

[0111] The integrated circuit of the detection circuit SPC is primarily composed of a capacitor and a resistor. These capacitor and resistor elements can be configured by appropriately combining a well region PW3, a gate insulating film formed over the well region PW3 and the gate electrode GEn, and an impurity region NSD formed in the well region PW3. The resistor element can be composed of a barrier metal film included in wiring having a damascene structure or a dual damascene structure, as described later.

[0112] The multilayer wiring layer is formed on the semiconductor substrate SUB and has a plurality of wiring layers. Figure 13 In the example shown in FIG, the multilayer wiring layer consists of a first wiring layer to a fourteenth wiring layer. Wirings M1 to M14 are formed in each of the first to fourteenth wiring layers, respectively. The first to fifth wiring layers are local wiring layers, the sixth to twelfth wiring layers are semi-global wiring layers, and the thirteenth and fourteenth wiring layers are global wiring layers.

[0113] The thickness of each of the wirings M13 and M14 is thicker than the thickness of each of the wirings M6 to M12, and the line width of each of the wirings M13 and M14 is wider than the line width of each of the wirings M6 to M12. The thickness of each of the wirings M6 to M12 is thicker than the thickness of each of the wirings M1 to M5, and the line width of each of the wirings M6 to M12 is wider than the line width of each of the wirings M1 to M5.

[0114] Each of the wirings M1 to M14 is a wiring having a damascene structure or a dual damascene structure, for example, composed of a barrier metal film including a tantalum film and a tantalum nitride film, and a copper film formed on the barrier metal film and having a thickness greater than that of the barrier metal film.

[0115] In the first embodiment, although the multilayer wiring layer is exemplified as consisting of the first to fourteenth wiring layers, the number of wiring layers in the multilayer wiring layer is not limited to fourteen, but may be more or less than fourteen.

[0116] Note that the power terminals TVcc, TVcc1, TVcc2, TVcc3 and the ground terminals TVss, TVss1, TVss2 are formed by a portion of a wiring formed on an upper layer of the wiring M14 (not shown). The wiring formed on the upper layer of the wiring M14 is mainly formed of a patterned aluminum alloy film.

[0117] <Detailed Structure of Each MISFET>

[0118] Below, reference Figure 14 and Figure 15 , detailed structures of a plurality of MISFETs included in the semiconductor device 100, such as MISFET 1Q, MISFET 2Q, MISFET 3Q, a low voltage MISFET provided in the core region CR, and a high voltage MISFET provided in the core region CR and the I / O signal unit 10C, will be described.

[0119] In the first embodiment, the channel region of each of the plurality of MISFETs included in the semiconductor device 100 is three-dimensionally covered by the gate electrode of each of the plurality of MISFETs. Such MISFETs may adopt a FIN-FET structure or a GAA (Gate All Around) structure using nanowires or nanosheets.

[0120] In this section, a case where a plurality of MISFETs included in the semiconductor device 100 have a FIN-FET structure is described. Figure 14 and Figure 15 , a plurality of MISFETs 1Q included in a MISFET group 1QA are illustrated.

[0121] like Figure 14 and Figure 15 As shown, a plurality of protrusions 20 are provided on the semiconductor substrate SUB, which are part of the semiconductor substrate SUB. The plurality of protrusions 20 extend in the X direction and are spaced apart from each other in the Y direction. Element isolation regions (STI) are formed on the semiconductor substrate SUB between the plurality of protrusions 20. In other words, the spaces between the plurality of protrusions 20 correspond to grooves formed in the semiconductor substrate SUB, and the element isolation regions (STI) are formed within these grooves. The upper surface of the element isolation regions (STI) is lower than the upper surface of the protrusions 20.

[0122] The gate electrode GEn is formed to extend in the Y direction and cover the upper surface and both side surfaces of at least one protrusion among the plurality of protrusions 20. A gate insulating film GI is formed between the gate electrode GEn and the protrusion 20. A well region PW1 is formed in the semiconductor substrate SUB including the protrusion 20. An impurity region NSD is formed in the protrusion 20 exposed from the gate electrode GEn (in the well region PW1).

[0123] In the case of the FIN-FET structure, the well region PW1 located between the two impurity regions NSD that become the source region or the drain region and covered with the gate electrode GEn becomes the channel region of the MISFET 1Q.

[0124] In the three-dimensional MISFET, more MISFETs can be arranged in the same plane area compared to the planar MISFET, and the gate width Wg of each MISFET in the same plane area can be increased. Therefore, in the three-dimensional MISFET, a larger drive current can be ensured compared to the planar MISFET, and miniaturization of the semiconductor device 100 can be promoted.

[0125] To increase the speed of MISFETs, thinning of the gate insulating film GI is being promoted. In the case of low-voltage MISFETs used in the discharge circuit B-MOS1, trigger circuit TR1, and core region CR, the thickness of the gate insulating film GI is, for example, not less than 1 nm and not more than 4 nm. In the case of high-voltage MISFETs used in the discharge circuit B-MOS2, discharge circuit B-MOS3, trigger circuits TR2 and TR3, core region CR, and I / O signal cell 10C, the thickness of the gate insulating film GI is thicker than that of the low-voltage MISFET, for example, not less than 3 nm and not more than 6 nm.

[0126] In addition, the gate insulating film GI may be, for example, a silicon oxide film, or a laminated film of a silicon oxide film and a high dielectric constant film. The high dielectric constant film is an insulating film having a higher dielectric constant than that of a silicon nitride film, and may be, for example, a hafnium oxide film (HfO2 film) or a hafnium silicate film (HfSiO film).

[0127] As the gate insulating film GI becomes thinner and has a higher dielectric constant, and as the gate width Wg increases due to the three-dimensional structure, the gate capacitance Cg tends to further increase. However, even when the gate capacitance Cg increases in this manner, by using the protection unit ESD12 of the first embodiment, the area occupied by the protection unit in the peripheral region OR can be reduced, and the miniaturization of the semiconductor device 100 can be promoted. At the same time, rapid discharge can be achieved and the reliability of the semiconductor device 100 can be ensured.

[0128] As described above, the first embodiment is explained in the case where the plurality of MISFETs included in the semiconductor device 100 have a three-dimensional structure such as a FIN-FET structure. However, even if the plurality of MISFETs have a planar structure, the protection unit ESD12 of the first embodiment can be effectively utilized.

[0129] (Second embodiment)

[0130] In the following, we will use Figure 16 and Figure 19 A semiconductor device 100 in the second embodiment is described. Note that in the following description, differences from the first embodiment will be mainly explained, and overlapping contents with the first embodiment will be omitted.

[0131] In the second embodiment, in order to reduce Figure 3 The wiring resistor R2 shown changes the planar layout of the protection unit ESD12 and the protection unit ESD3.

[0132] As semiconductor devices become smaller, wiring is being thinned and narrowed. In particular, wiring layers near MISFETs, such as wiring M1 and wiring M2, need to be thinned and narrowed to cope with the miniaturization of MISFETs, resulting in increased wiring resistance.

[0133] As described above, during the discharge of the ESD current, the MISFET group 2QA outputs a signal to each gate electrode of the plurality of MISFETs 1Q to turn on the plurality of MISFETs 1Q. However, as the wiring M1 and the wiring M2 become thinner and narrower, the increase in wiring resistance tends to cause a delay in the output signal from the MISFET group 2QA.

[0134] Figure 16 Shown Figure 12 The equivalent circuit diagram of the protection unit ESD12 in the case of a planar layout is shown. Figure 16As shown in the first embodiment, the greater the distance from the MISFET group 2QA, the greater the increase in wiring resistance, resulting in greater signal delay. In other words, the greater the distance from the MISFET group 2QA, the greater the wiring resistance ΣR2n (n is a natural number). As the wiring M1 and wiring M2 become thinner and narrower, the increase in wiring resistance ΣR2n becomes more significant.

[0135] Therefore, among the plurality of MISFETs 1Q, those MISFETs 1Q that are farther from the MISFET group 2QA have reduced gate driving force or slower turn-on speed. In the second embodiment, in order to achieve faster discharge, the increase in the wiring resistance ΣR2n is improved.

[0136] In the following, we will use Figure 18 and Figure 19 The protection unit ESD12 and the protection unit ESD3 in the second embodiment are described.

[0137] Figure 18 1 and 2 show the planar layout of the protection unit ESD12, the protection unit ESD3, and the I / O signal unit 10C in the second embodiment. Figure 19 FIG1 shows a detailed planar layout of the MISFET group 1QA, the MISFET group 2QA, the MISFET group 3QA, and the detection circuit SPC included in the protection unit ESD12. It should be noted that the detailed planar layout of the MISFET group 1QA, the MISFET group 2QA, the MISFET group 3QA, and the detection circuit SPC included in the protection unit ESD3 is obtained by Figure 19 Obtained by rotating 180 degrees.

[0138] like Figure 18 and Figure 19 As shown, in the second embodiment, the position of the MISFET group 2QA is different from that in the first embodiment. In the second embodiment, the protection units ESD12 and ESD3 have a pair of MISFET groups 2QA. The MISFET group 1QA is adjacent to the pair of MISFET groups 2QA and is provided between the pair of MISFET groups 2QA.

[0139] Even in the second embodiment, the planar layout of the MISFET group 1QA forms a rectangular shape. A pair of MISFET groups 2QA are arranged along the long sides of the MISFET group 1QA so as to sandwich the MISFET group 1QA. The MISFET group 3QA is arranged along the short sides of the MISFET group 1QA. The detection circuit SPC is arranged along the short sides of the MISFET group 1QA via the MISFET group 3QA.

[0140] In the first embodiment, as Figure 16As shown, there is a problem that the wiring resistance ΣR2n increases as the distance from the MISFET group 2QA increases, resulting in a greater signal delay. Figure 12 As shown, the wiring path of the MISFET 1Q farthest from the MISFET group 2QA is approximately the sum of the length of the long side of the MISFET group 1QA and half the length of the short side of the MISFET group 1QA.

[0141] In the second embodiment, as Figure 19 As shown, the MISFET group 2QA is arranged along the long side of the MISFET group 1QA. Therefore, the wiring path of the MISFET 1Q farthest from the MISFET group 2QA is approximately half the length of the short side of the MISFET group 1QA.

[0142] By comparison Figure 16 and Figure 17 As can be understood, the distribution of wiring resistance differs between the first embodiment and the second embodiment. In the second embodiment, the wiring resistance between each gate electrode GEn of the plurality of MISFETs 1Q connected in parallel and the MISFET group 2QA is balanced to a relatively low value (wiring resistance R2a). Therefore, in the second embodiment, the signal delay from the MISFET group 2QA to the gate electrode GEn of the MISFET 1Q can be significantly suppressed compared to the first embodiment.

[0143] Therefore, according to the second embodiment, the problem of reduced gate drive force in some MISFETs 1Q of the MISFET group 1QA and the problem of slow transition to the on state can be suppressed. Therefore, the clamping performance of the ESD protection circuit 50 can be improved, and the multiple circuits and I / O signal cells 10C arranged in the core region CR can be fully protected from the influence of ESD current. This means that the ESD withstand voltage of the semiconductor device 100 can be improved.

[0144] In the second embodiment, the wiring resistance R2 between the MISFET group 2QA of the inverter INV and the discharge circuit B-MOS (MISFET group 1QA) is reduced, but the wiring impedance between the detection circuit SPC and the MISFET group 2QA of the inverter INV is slightly increased. However, the number of MISFETs 2Q included in the MISFET group 2QA is very small compared to the number of MISFETs 1Q included in the MISFET group 1QA. In addition, the total gate width of the multiple MISFETs 2Q included in the MISFET group 2QA is approximately several tens of μm to one hundred μm, which is very small compared to the total gate width of the multiple MISFETs 1Q included in the MISFET group 1QA. Therefore, the total gate capacitance of the MISFET group 2QA is small. Therefore, the increase in the wiring resistance between the detection circuit SPC and the MISFET group 2QA does not significantly affect the clamping performance of the ESD protection circuit 50.

[0145] On the other hand, the total gate width of the multiple MISFETs 1Q included in the MISFET group 1QA is approximately several thousand μm, and the total gate capacitance of the MISFET group 1QA is significantly larger than the total gate capacitance of the MISFET group 2QA. Therefore, the reduction in wiring resistance between the MISFET group 2QA and the MISFET group 1QA significantly affects the clamping performance of the ESD protection circuit 50. Therefore, the second embodiment can significantly improve the clamping performance of the ESD protection circuit 50.

[0146] As described above, the present invention has been specifically described based on the embodiments, but the present invention is not limited to the above-described embodiments, but various modifications can be made without departing from the gist of the present invention.

Claims

1. A semiconductor device comprising: The core area is provided with a first circuit and a second circuit; a peripheral region surrounding the core region in plan view; a protection unit disposed in the peripheral region and constituting an ESD protection circuit; a first power wiring group, configured to supply a first power potential to the first circuit; a second power wiring group, configured to supply a second power potential to the second circuit; as well as a first ground wiring group for supplying a first ground potential to the first circuit and the second circuit; wherein the first power wiring group, the second power wiring group, and the first ground wiring group are arranged in the peripheral area so as to overlap with the protection unit in a plan view, wherein the protection unit comprises a first MISFET group consisting of a plurality of first MISFETs and a second MISFET group consisting of a plurality of second MISFETs, wherein the first MISFET group and the second MISFET group are arranged separately from each other, wherein the first MISFET group is electrically connected to the first power wiring group and the first ground wiring group so as to electrically short-circuit the first power wiring group and the first ground wiring group, wherein the second MISFET group is electrically connected to the second power wiring group and the first ground wiring group so as to electrically short-circuit the second power wiring group and the first ground wiring group, and In a plan view, the first MISFET group overlaps with a portion of the first power wiring group and a portion of the first ground wiring group.

2. The semiconductor device according to claim 1, further comprising: semiconductor substrates; a first well region of a first conductivity type formed in the semiconductor substrate; as well as a plurality of first impurity regions of a second conductivity type opposite to the first conductivity type, formed in the first well region and constituting source regions or drain regions of the plurality of first MISFETs, The area of ​​the first well region that overlaps with the first power wiring group and the first ground wiring group in a plan view is larger than the area of ​​the first well region that does not overlap with the first power wiring group and the first ground wiring group.

3. The semiconductor device according to claim 1, In a plan view, the second MISFET group overlaps with a portion of the second power supply wiring group.

4. The semiconductor device according to claim 1, The second power supply potential is higher than the first power supply potential, and the thickness of each first gate insulating film of the plurality of first MISFETs is thinner than the thickness of each second gate insulating film of the plurality of second MISFETs.

5. The semiconductor device according to claim 1, The distance between the first MISFET group and the core region is closer than the distance between the second MISFET group and the core region.

6. The semiconductor device according to claim 5, The protection unit further includes a first trigger circuit, wherein the first trigger circuit detects an ESD current flowing to the first power wiring group and outputs a signal to each first gate electrode of the plurality of first MISFETs to turn on or off the plurality of first MISFETs, and The first trigger circuit is arranged between the first MISFET group and the second MISFET group.

7. The semiconductor device according to claim 6, The protection unit further includes a second trigger circuit, wherein the second trigger circuit detects an ESD current flowing to the second power wiring group and outputs a signal to each second gate electrode of the plurality of second MISFETs to turn on or off the plurality of second MISFETs, and The second MISFET group is arranged between the first trigger circuit and the second trigger circuit.

8. The semiconductor device according to claim 7, wherein the protection unit further includes a bidirectional diode electrically connected to the first MISFET group and the second MISFET group via the first ground wiring group, and The second trigger circuit is arranged between the second MISFET group and the bidirectional diode.

9. The semiconductor device according to claim 7, further comprising: a plurality of first wirings for connecting the first MISFET group and the first trigger circuit, and a plurality of second wirings for connecting the second MISFET group and the second trigger circuit, wherein the first power wiring group, the second power wiring group, and the first ground wiring group are formed in a wiring layer above the plurality of first wirings and the plurality of second wirings, and The thickness of each of the first power wiring group, the second power wiring group, and the first ground wiring group is thicker than the thickness of each of the plurality of first wirings and the plurality of second wirings.

10. The semiconductor device according to claim 5, The protection unit further includes a first trigger circuit, The first trigger circuit includes a first detection circuit, a pair of third MISFET groups consisting of a plurality of third MISFETs, and a fourth MISFET group consisting of a plurality of fourth MISFETs. wherein the first detection circuit is capable of detecting an ESD current flowing to the first power wiring group, Wherein, the pair of third MISFET groups outputs a signal to each of the first gate electrodes of the multiple first MISFETs to turn on the multiple first MISFETs, the fourth MISFET group outputs a signal to each of the first gate electrodes of the multiple first MISFETs to turn off the multiple first MISFETs, the planar arrangement shape of the first MISFET group forms a rectangular shape, the pair of third MISFET groups are arranged along the long side of the first MISFET group to clamp the first MISFET group, the fourth MISFET group is arranged along the short side of the first MISFET group, and the first detection circuit is arranged along the short sides of the first MISFET group to the fourth MISFET group.

11. The semiconductor device according to claim 10, The protection unit further includes a second trigger circuit, wherein the second trigger circuit includes a second detection circuit, a pair of fifth MISFET groups consisting of a plurality of fifth MISFETs, and a sixth MISFET group consisting of a plurality of sixth MISFETs, wherein the second detection circuit is capable of detecting an ESD current flowing to the second power wiring group, wherein the pair of fifth MISFET groups outputs a signal to each of the second gate electrodes of the plurality of second MISFETs to turn on the plurality of second MISFETs, wherein the sixth MISFET group outputs a signal to each of the second gate electrodes of the plurality of second MISFETs to turn off the plurality of second MISFETs, wherein a planar arrangement shape of the second MISFET group forms a rectangular shape, wherein the pair of fifth MISFET groups are arranged along the long sides of the second MISFET group to sandwich the second MISFET group, wherein the sixth MISFET group is arranged along a short side of the second MISFET group, and The second detection circuit is arranged along the short sides of the second MISFET group to the sixth MISFET group.

12. The semiconductor device according to claim 1, wherein each of the first gate electrodes of the plurality of first MISFETs extends along a first direction in a plan view, and wherein each of the channel regions of the plurality of first MISFETs is three-dimensionally covered by each of the first gate electrodes of the plurality of first MISFETs.

13. The semiconductor device according to claim 12, further comprising: semiconductor substrates; as well as a plurality of protrusions that are part of the semiconductor substrate, extend in a second direction intersecting the first direction in a plan view, and are spaced apart from each other in the first direction; as well as an element isolation portion formed on the semiconductor substrate between the plurality of protrusions, wherein the upper surface of the element isolation portion is located lower than the upper surface of the protrusion, and The first gate electrode is formed to cover at least one of the upper surface and both side surfaces of the plurality of protrusions.

14. The semiconductor device according to claim 1, further comprising: a first side along the first direction in a plan view; a second side along a second direction intersecting the first direction in a plan view; as well as Multiple protection units, wherein the first side and the second side constitute the outer edge of the peripheral area, wherein the plurality of protection units include a first protection unit disposed between the first side and the core region and a second protection unit disposed between the second side and the core region, and Each of the first power wiring group, the second power wiring group, and the first ground wiring group loops along the first side and the second side in a plan view so as to overlap with the first protection unit and the second protection unit.

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