Semiconductor device

Abstract

A semiconductor device (100) is provided with a floating region (202) of a second conductivity type, which is disposed below a lower end (43) of a first gate trench portion (40) on the upper surface side of a semiconductor substrate (10), and which does not extend below a lower end (33) of a first dummy trench portion. The first mesa portion has: an emitter region (12) of a first conductivity type, which is provided in contact with the first gate trench portion and has a higher concentration than a drift region (18); and a base region (14) of a second conductivity type, which is provided between the emitter region and the drift region and is provided in contact with the first gate trench portion. The lower end of the first dummy trench portion is in contact with a region of a first conductivity type.

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Background Art

[0002] Conventionally, there is known a semiconductor device provided with a transistor such as an insulated gate bipolar transistor (IGBT) (see, for example, Patent Documents 1 to 4).

[0003] Prior art literature Patent Literature Patent Document 1: Japanese Patent No. 6472714 Patent Document 2: Japanese Patent No. 4456013 Patent Document 3: Japanese Patent Application Laid-Open No. 2020-21941 Patent Document 4: Japanese Patent Application Laid-Open No. 2010-232627 Summary of the Invention

[0004] Technical issues In a semiconductor device, it is preferable to suppress a voltage snapback phenomenon.

[0005] Technical Solution To solve the above-mentioned problems, in one embodiment of the present invention, a semiconductor device including an IGBT is provided. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type. Any of the semiconductor devices may include a first gate trench portion, the first gate trench portion being provided on the upper surface of the semiconductor substrate. Any of the semiconductor devices may include a first dummy trench portion, the first dummy trench portion being provided on the upper surface of the semiconductor substrate and arranged side by side with the first gate trench portion on the upper surface. Any of the semiconductor devices may include a first mesa portion, the first mesa portion being sandwiched within the semiconductor substrate by the first gate trench portion and the first dummy trench portion. Any of the semiconductor devices may include a floating region of a second conductivity type, the second conductive type being arranged below the lower end of the first gate trench portion on the upper surface side of the semiconductor substrate and not extending below the lower end of the first dummy trench portion. The first mesa portion of any of the aforementioned semiconductor devices may include an emitter region of a first conductivity type, the emitter region of the first conductivity type being disposed in contact with the first gate trench portion and having a concentration higher than that of the drift region. The first mesa portion of any of the aforementioned semiconductor devices may include a base region of a second conductivity type, the base region of the second conductivity type being disposed between the emitter region and the drift region and in contact with the first gate trench portion. In any of the aforementioned semiconductor devices, the lower end of the first dummy trench portion may be in contact with a region of the first conductivity type.

[0006] In any of the above semiconductor devices, the floating region may not be in contact with a lower end of the gate trench portion.

[0007] In any of the above semiconductor devices, the floating region may be in contact with a lower end of the gate trench portion.

[0008] In any of the above-mentioned semiconductor devices, the first mesa portion may further include an accumulation region of the first conductivity type, the accumulation region of the first conductivity type being provided between the base region and the drift region and having a concentration higher than that of the drift region.

[0009] In any of the above-described semiconductor devices, the accumulation region may be in contact with the floating region.

[0010] In any of the above-mentioned semiconductor devices, the lower end of the accumulation region may be arranged below the lower end of the floating region.

[0011] In any of the above-mentioned semiconductor devices, a lower end of the accumulation region may be arranged above a lower end of the floating region.

[0012] In any of the above-mentioned semiconductor devices, the first mesa portion may further include a contact region of the second conductivity type, the contact region of the second conductivity type being in contact with the upper surface of the semiconductor substrate and having a concentration higher than that of the base region.

[0013] In any of the above-mentioned semiconductor devices, the first mesa portion may further include a contact portion provided from the upper surface of the semiconductor substrate to the interior of the first mesa portion and filled with a conductive material.

[0014] In any of the above-mentioned semiconductor devices, a lower end of the contact portion may be in contact with the contact region.

[0015] In any of the above semiconductor devices, the first dummy trench portions may be provided on both sides of the first gate trench portion.

[0016] In any of the above semiconductor devices, the floating region may be in contact with a sidewall of the first dummy trench portion.

[0017] In any of the above-mentioned semiconductor devices, the first dummy trench portion may include an electrode made of polysilicon to which impurities of the first conductivity type are added.

[0018] Any of the above-mentioned semiconductor devices may include a lower end region of the first conductivity type, the lower end region of the first conductivity type being provided in contact with a lower end of the first dummy trench portion and having a concentration higher than that of the drift region.

[0019] Any of the above-mentioned semiconductor devices may include two dummy trenches, the two dummy trenches being disposed on the upper surface of the semiconductor substrate and arranged side by side on the upper surface. In any of the above-mentioned semiconductor devices, the spacing between the first gate trench and the first dummy trench may be the same as the spacing between the two dummy trenches.

[0020] Any of the aforementioned semiconductor devices may include diode portions, the diode portions being arranged alternately and side by side with the IGBTs in a first direction. In any of the aforementioned semiconductor devices, the IGBTs sandwiched between the diode portions may include a plurality of trench portions, the plurality of trench portions including the first gate trench portion and the first dummy trench portion, and being arranged side by side in the first direction. In any of the aforementioned semiconductor devices, the spacing between the plurality of trench portions may be the same.

[0021] The above summary of the invention does not list all the necessary features of the present invention. In addition, sub-combinations of these feature groups can also constitute inventions. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 1 is a plan view showing an example of a semiconductor device 100 according to an embodiment of the present invention.

[0023] Figure 2 yes Figure 1 Magnified view of area D in FIG.

[0024] Figure 3 It shows Figure 2 A diagram of an example of the ee cross section in .

[0025] Figure 4 It shows Figure 2 FIG. 1 is a diagram showing an example of an ff cross section.

[0026] Figure 5 Graphs showing collector voltage-collector current characteristics in Examples and Reference Examples.

[0027] Figure 6 Graphs showing collector voltage-collector current characteristics in Examples and Reference Examples.

[0028] Figure 7 Graphs showing measurement examples of voltage and current in the semiconductor device of the embodiment.

[0029] Figure 8 Graphs showing other measurement examples of the voltage and current of the semiconductor device of the reference example.

[0030] Figure 9 This is a diagram showing another measurement example of the voltage and current of the semiconductor device of the embodiment.

[0031] Figure 10 Graphs showing trade-off characteristics between conduction loss and reverse recovery dV / dt in a reference example and an embodiment.

[0032] Figure 11 FIG. 1 is a diagram showing another example of the ff cross section.

[0033] Figure 12 FIG. 1 is a diagram showing another example of the ff cross section.

[0034] Figure 13 FIG. 1 is a diagram showing another example of the ff cross section.

[0035] Figure 14 FIG. 1 is a diagram showing another example of the ff cross section.

[0036] Figure 15 FIG. 1 is a diagram showing another example of the ff cross section.

[0037] Figure 16 FIG. 1 is a diagram showing another example of the ff cross section.

[0038] Figure 17 It is a diagram showing another example of the ee cross section.

[0039] Explanation of symbols 10···Semiconductor substrate, 11···Well region, 12···Emitter region, 14···Base region, 15···Contact region, 16···Accumulator region, 18···Drift region, 19···Contact region, 20···Buffer region, 21···Upper surface, 22···Collector region, 23···Lower surface, 24···Collector electrode, 29···Straight line portion, 30···Dummy trench portion, 30-1···First dummy trench portion, 31···Front end portion, 32···Dummy insulating film, 33···Lower end, 34···Dummy conductive portion, 38···Interlayer insulating film, 39···Straight line portion, 40···Gate trench portion, 40-1···First gate trench portion, 41···Front end portion , 42···Gate insulating film, 43···Lower end, 44···Gate conductive portion, 45···Trench, 52···Emitter electrode, 54···Contact portion, 60, 61···Mesa portion, 60-1···First mesa portion, 60-2···Second mesa portion, 60-3···Third mesa portion, 70···Transistor portion, 80···Diode portion, 81···Extension region, 82···Cathode region, 90···Edge terminal structure portion, 100···Semiconductor device, 130···Peripheral gate wiring, 131···Active side gate wiring, 160···Active portion, 162···End side, 164···Gate pad, 202···Floating region, 204···Lower end region DETAILED DESCRIPTION

[0040] The present invention will be described below by way of embodiments of the invention, but the following embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the technical aspects of the invention.

[0041] In this specification, one side parallel to the depth direction of a semiconductor substrate is referred to as "upper," and the other side is referred to as "lower." One of the two principal surfaces of a substrate, layer, or other component is referred to as the upper surface, and the other is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the orientation when a semiconductor device is mounted.

[0042] In this specification, the X-axis, Y-axis, and Z-axis are sometimes used to describe technical matters. These axes simply determine the relative positions of components and do not define specific directions. For example, the Z-axis is not limited to indicating the height relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is specified without specifying a positive or negative sign, it refers to a direction parallel to the +Z and -Z axes.

[0043] In this specification, the axes perpendicular to the upper and lower surfaces of the semiconductor substrate are referred to as the X-axis and Y-axis. Furthermore, the axis perpendicular to the upper and lower surfaces of the semiconductor substrate is referred to as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Furthermore, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.

[0044] The region from the center in the depth direction of the semiconductor substrate to the upper surface of the semiconductor substrate is sometimes referred to as the upper surface side. Similarly, the region from the center in the depth direction of the semiconductor substrate to the lower surface of the semiconductor substrate is sometimes referred to as the lower surface side.

[0045] In this specification, the term "same" or "equal" may include a case where there is an error due to manufacturing variation, etc. The error is within 10%, for example.

[0046] In this specification, the conductivity type of the impurity-doped region is described as P-type or N-type. In this specification, the term "impurity" sometimes specifically refers to either an N-type donor or a P-type acceptor, and is sometimes referred to as a dopant. In this specification, doping refers to the introduction of donors or acceptors into a semiconductor substrate to produce an N-type or P-type semiconductor.

[0047] In this specification, the doping concentration refers to the concentration of donors or acceptors in thermal equilibrium. In this specification, the net doping concentration refers to the actual concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions in a manner that includes the polarity of the charge. As an example, if the donor concentration is N D And the acceptor concentration is set to N A , then the net doping concentration at any position becomes N D -N A In this specification, the net doping concentration may be described simply as the doping concentration.

[0048] In this specification, the term "P+ type" or "N+ type" refers to a higher doping concentration than that of the P-type or N-type. In the case of "P-type" or "N-type", it means a lower doping concentration than that of the P-type or N-type. In addition, the term "P++ type" or "N++ type" refers to a higher doping concentration than that of the P+ type or N+ type. The units used in this specification are SI units unless otherwise specified. Although cm is sometimes used to represent the unit of length, calculations can be performed after conversion to meters (m).

[0049] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the state of electrical activation. The chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The above-mentioned net doping concentration can be measured by voltage-capacitance measurement (CV method). In addition, the carrier concentration measured by diffusion resistance measurement (SR method) can be used as the net doping concentration. The carrier concentration measured by the CV method or the SR method can be set to a value in thermal equilibrium. In addition, in the N-type region, since the donor concentration is sufficiently greater than the acceptor concentration, the carrier concentration in this region can be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can be used as the acceptor concentration. In this specification, the doping concentration of the N-type region is sometimes referred to as the donor concentration, and the doping concentration of the P-type region is sometimes referred to as the acceptor concentration.

[0050] When the concentration distribution of the donor, acceptor, or net doping has a peak, the peak value can be used as the concentration of the donor, acceptor, or net doping in the region. When the concentration of the donor, acceptor, or net doping is almost uniform, the average value of the concentration of the donor, acceptor, or net doping in the region can be used as the concentration of the donor, acceptor, or net doping. In this specification, the concentration per unit volume is expressed in at ms / cm 3 or / cm 3 This unit is used for the concentration of donors or acceptors, or chemical concentrations, within a semiconductor substrate. The word "atoms" can be omitted.

[0051] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. In the current flow range used to measure diffusion resistance, the carrier mobility of a semiconductor substrate may be lower than that of a crystalline state. This reduction in carrier mobility is caused by carrier scattering due to disorder in the crystal structure caused by lattice defects and other factors.

[0052] The donor or acceptor concentration calculated from carrier concentrations measured by CV or SR methods can be lower than the chemical concentration of the element representing the donor or acceptor. For example, the donor concentration of phosphorus or arsenic, which act as donors, or the acceptor concentration of boron, which acts as an acceptor, in a silicon semiconductor is approximately 99% of their chemical concentrations. Meanwhile, the donor concentration of hydrogen, which acts as a donor in a silicon semiconductor, is approximately 0.1% to 10% of the chemical concentration of hydrogen.

[0053] Figure 1 FIG. 1 is a top view showing an example of a semiconductor device 100 according to an embodiment of the present invention. Figure 1 , the positions of the components projected onto the upper surface of the semiconductor substrate 10 are shown. Figure 1 , only some components of the semiconductor device 100 are shown, and some components are omitted.

[0054] The semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has an edge 162 when viewed from above. In this specification, the term "viewed from above" refers to the state viewed from the upper surface of the semiconductor substrate 10. The semiconductor substrate 10 in this example has two sets of edges 162 that are opposite to each other when viewed from above. Figure 1 In FIG. 1 , the X-axis and the Y-axis are parallel to any one of the end sides 162. In addition, the Z-axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0055] The semiconductor substrate 10 is provided with an active portion 160. The active portion 160 is a region where a main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is in operation. An emitter electrode is provided above the active portion 160. Figure 1 The active portion 160 may refer to a region that overlaps with the emitting electrode in a plan view. In addition, a region sandwiched between the active portions 160 in a plan view may also be included in the active portion 160.

[0056] The active portion 160 includes a transistor portion 70 including transistor elements such as an IGBT (Insulated Gate Bipolar Transistor). The active portion 160 also includes a diode portion 80 including diode elements such as a freewheeling diode (FWD). Figure 1 In this example, transistor portions 70 and diode portions 80 are alternately arranged along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 of this example is a reverse conducting IGBT (RC-IGBT).

[0057] exist Figure 1 In the figure, the region where the transistor portion 70 is arranged is marked with a symbol "I", and the region where the diode portion 80 is arranged is marked with a symbol "F". In this specification, the direction perpendicular to the arrangement direction in a plan view is sometimes referred to as the extension direction (in Figure 1 The Y-axis direction is the Y-axis direction in the figure). The transistor portion 70 and the diode portion 80 may each have a long side in the direction in which they extend. That is, the length of the transistor portion 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode portion 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending direction of the transistor portion 70 and the diode portion 80 may be the same as the long side direction of each trench portion described later.

[0058] The diode portion 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is the area that overlaps with the cathode region when viewed from above. On the lower surface of the semiconductor substrate 10, a P+ type collector region may be provided in an area other than the cathode region. In this specification, an extension region 81 in which the diode portion 80 is extended in the Y-axis direction to the gate wiring described later is sometimes also included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0059] The transistor portion 70 has a P+ type collector region in a region in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor portion 70 has an N-type emitter region, a P-type base region, and a gate structure having a gate conductive portion and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0060] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 164. Semiconductor device 100 may also have pads such as an anode pad, a cathode pad, and a current detection pad. Each pad is positioned near edge 162. The area near edge 162 refers to the area between edge 162 and the emitter electrode when viewed from above. When semiconductor device 100 is mounted, each pad can be connected to an external circuit via wiring such as a wire.

[0061] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes a gate wiring that connects the gate pad 164 to the gate trench portion. Figure 1 In FIG, the gate wiring is marked with oblique hatching.

[0062] The gate wiring of this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is positioned between the active portion 160 and the edge 162 of the semiconductor substrate 10 when viewed from above. The peripheral gate wiring 130 of this example surrounds the active portion 160 when viewed from above. The area surrounded by the peripheral gate wiring 130 when viewed from above can be considered the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the base region, described later, and is formed from the upper surface of the semiconductor substrate 10 to a position deeper than the base region. The area surrounded by the well region when viewed from above can be considered the active portion 160.

[0063] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is arranged above the semiconductor substrate 10. The peripheral gate wiring 130 can be a metal wiring containing aluminum or the like.

[0064] The active-side gate wiring 131 is provided in the active portion 160 . By providing the active-side gate wiring 131 in the active portion 160 , it is possible to reduce variations in wiring length from the gate pad 164 in each region of the semiconductor substrate 10 .

[0065] The peripheral gate wiring 130 and the active-side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active-side gate wiring 131 are arranged above the semiconductor substrate 10. The peripheral gate wiring 130 and the active-side gate wiring 131 can be formed of a semiconductor such as polysilicon doped with impurities.

[0066] The active-side gate wiring 131 can be connected to the peripheral gate wiring 130. In this example, the active-side gate wiring 131 is provided so as to extend along the X-axis direction from the peripheral gate wiring 130 on one side sandwiching the active portion 160 to the peripheral gate wiring 130 on the other side, so as to cross the active portion 160 approximately at the center in the Y-axis direction. When the active portion 160 is divided by the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 can be alternately arranged in the X-axis direction in each divided region.

[0067] The semiconductor device 100 may include a temperature sensing portion (not shown) which is a PN junction diode formed of polysilicon or the like, and a current detecting portion (not shown) which simulates the operation of a transistor portion provided in the active portion 160 .

[0068] The semiconductor device 100 of this embodiment includes an edge termination structure 90 between the active portion 160 and the edge 162 in a plan view. The edge termination structure 90 of this embodiment is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 can include at least one of a guard ring, a field plate, and a surface electric field reducer, disposed in an annular shape surrounding the active portion 160.

[0069] Figure 2 yes Figure 1 is an enlarged view of region D in FIG. Region D includes the transistor portion 70, the diode portion 80, and the active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench portion 40, a dummy trench portion 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15, all disposed within the upper surface of the semiconductor substrate 10. The gate trench portion 40 and the dummy trench portion 30 are each an example of a trench portion. Furthermore, the semiconductor device 100 of this example includes an emitter electrode 52 and an active-side gate wiring 131, both disposed above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are disposed separately from each other.

[0070] An interlayer insulating film is provided between the emitter electrode 52, the active-side gate wiring 131, and the upper surface of the semiconductor substrate 10. Figure 2 In this embodiment, the interlayer insulating film is provided with a contact portion 54 in a manner that penetrates the interlayer insulating film. The contact portion 54 may include a contact hole provided in the interlayer insulating film and a conductive component filled in the contact hole. Figure 2 In FIG. 1 , each contact portion 54 is marked with oblique hatching.

[0071] Emitter electrode 52 is provided above gate trench 40, dummy trench 30, well region 11, emitter region 12, base region 14, and contact region 15. Emitter electrode 52 is connected to emitter region 12, contact region 15, and base region 14 on the upper surface of semiconductor substrate 10 via contact portion 54. Furthermore, emitter electrode 52 is connected to a dummy conductive portion within dummy trench 30 via a contact hole provided in the interlayer insulating film. Emitter electrode 52 can be connected to the dummy conductive portion of dummy trench 30 at the front end of dummy trench 30 in the Y-axis direction.

[0072] The active-side gate wiring 131 is connected to the gate trench 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench 40 at the front end portion 41 of the gate trench 40 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion in the dummy trench 30.

[0073] The emitter electrode 52 is formed of a material containing metal. Figure 2 , the area where emitter electrode 52 is provided is shown. For example, at least a portion of emitter electrode 52 may be formed from aluminum or an aluminum-silicon alloy, such as AlSi or AlSiCu. Emitter electrode 52 may include a barrier metal formed from titanium, a titanium compound, or the like, beneath the aluminum region. Furthermore, a plug formed by embedding tungsten or the like in contact with the barrier metal and the aluminum may be included in the contact hole.

[0074] The well region 11 is provided so as to overlap with the active-side gate wiring 131. Even within the area not overlapping with the active-side gate wiring 131, the well region 11 is provided to extend to a predetermined width. In this example, the well region 11 is provided so as to separate from the end of the contact portion 54 in the Y-axis direction toward the active-side gate wiring 131. The well region 11 is a region of the second conductivity type having a higher doping concentration than the base region 14. In this example, the base region 14 is of the P- type, and the well region 11 is of the P+ type.

[0075] The transistor section 70 and the diode section 80 each have a plurality of trench sections arranged in the arrangement direction. In the transistor section 70 of this example, one or more gate trench sections 40 and one or more dummy trench sections 30 are alternately provided along the arrangement direction. In the diode section 80 of this example, a plurality of dummy trench sections 30 are provided along the arrangement direction. In the diode section 80 of this example, no gate trench section 40 is provided.

[0076] The gate trench portion 40 of this example may include two straight portions 39 extending in an extending direction perpendicular to the arrangement direction (portions forming a straight trench along the extending direction) and a front end portion 41 connecting the two straight portions 39 . Figure 2 The extension direction is the Y-axis direction.

[0077] At least a portion of the tip portion 41 is preferably curved in a plan view. The tip portion 41 connects the ends of the two straight portions 39 in the Y-axis direction, thereby alleviating electric field concentration at the ends of the straight portions 39.

[0078] In transistor portion 70, dummy trench portion 30 is provided between each straight portion 39 of gate trench portion 40. One dummy trench portion 30 may be provided between each straight portion 39, or a plurality of dummy trench portions 30 may be provided. Dummy trench portion 30 may have a straight shape extending in the extension direction, or may have a straight portion 29 and a front end portion 31 similar to gate trench portion 40.

[0079] The diffusion depth of the well region 11 can be deeper than the depth of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are located in the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This can alleviate electric field concentration at the bottom of each trench portion.

[0080] A mesa portion is provided between each groove portion in the arrangement direction. The mesa portion refers to the region within the semiconductor substrate 10 that is sandwiched between the groove portions. As an example, the upper end of the mesa portion is the upper surface of the semiconductor substrate 10. The lower end of the mesa portion is at the same depth as the lower end of the groove portion. The mesa portion in this example is provided so as to extend along the groove extension direction (Y-axis direction) on the upper surface of the semiconductor substrate 10. In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. When referred to simply as a mesa portion in this specification, both mesa portion 60 and mesa portion 61 are referred to.

[0081] A base region 14 is provided in each mesa portion. Of the base region 14 exposed on the upper surface of the semiconductor substrate 10 in the mesa portion, a region closest to the active-side gate wiring 131 is referred to as a base region 14-e. Figure 2 , a base region 14-e is shown as being arranged at one end of each mesa portion in the extension direction, but a base region 14-e is also arranged at the other end of each mesa portion. In each mesa portion, the region sandwiched by the base region 14-e when viewed from above can be provided with at least one of an emitter region 12 of the first conductivity type and a contact region 15 of the second conductivity type. In this example, the emitter region 12 is of the N+ type, and the contact region 15 is of the P+ type with a higher concentration than that of the base region 14. The emitter region 12 and the contact region 15 can be provided in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0082] Mesa portion 60 of transistor portion 70 includes emitter region 12 exposed on the upper surface of semiconductor substrate 10. Emitter region 12 is provided in contact with gate trench portion 40. Mesa portion 60 in contact with gate trench portion 40 may include contact region 15 exposed on the upper surface of semiconductor substrate 10.

[0083] Emitter region 12 in mesa portion 60 is provided in contact with gate trench portion 40. Emitter region 12 may or may not be in contact with dummy trench portion 30. Emitter region 12 is also provided in a region overlapping with contact portion 54.

[0084] Contact region 15 in mesa portion 60 is provided in a region overlapping contact portion 54. Contact region 15 may or may not be in contact with gate trench portion 40. Contact region 15 may or may not be in contact with dummy trench portion 30.

[0085] exist Figure 2 In the example shown in FIG. 1 , the emitter region 12 in the mesa portion 60 extends from the groove portion on one side to the groove portion on the other side in the X-axis direction. Alternatively, the contact region 15 in the mesa portion 60 may extend from the groove portion on one side to the groove portion on the other side in the X-axis direction. Alternatively, the contact region 15 may not contact either of the two groove portions sandwiching the mesa portion 60. In this case, the base region 14 may be provided between the contact region 15 and the groove portion.

[0086] exist Figure 2 In the example, the contact regions 15 and the emitter regions 12 of the mesa portion 60 are alternately arranged along the extension direction of the groove portion (Y-axis direction). In other examples, the contact regions 15 and the emitter regions 12 of the mesa portion 60 can be arranged in a stripe shape along the extension direction of the groove portion (Y-axis direction). For example, the emitter region 12 is provided in the region in contact with the groove portion, and the contact region 15 is provided in the region sandwiched by the emitter region 12. In addition, the emitter region 12 can also be provided in the mesa portion 60 instead of the contact region 15. For example, the emitter region 12 can also be provided in the entire region sandwiched by the base region 14-e in the Y-axis direction.

[0087] Emitter region 12 is not provided in mesa portion 61 of diode portion 80. Base region 14 and contact region 15 may be provided on the upper surface of mesa portion 61. Contact region 15 may be provided in the region sandwiched between base regions 14-e on the upper surface of mesa portion 61, so as to be in contact with each base region 14-e. Base region 14 may be provided in the region sandwiched between contact regions 15 on the upper surface of mesa portion 61. Base region 14 may be arranged throughout the region sandwiched between contact regions 15.

[0088] A contact portion 54 is provided above each mesa portion. Contact portion 54 is located in the region sandwiched between base regions 14-e. In this example, contact portion 54 is provided above each of contact region 15, base region 14, and emitter region 12. Contact portion 54 is not provided in the region corresponding to base region 14-e and well region 11. Contact portion 54 can be located at the center of the mesa portion 60 in the arrangement direction (X-axis direction).

[0089] In the diode portion 80, an N+ type cathode region 82 is provided in a region adjacent to the lower surface of the semiconductor substrate 10. In a region of the lower surface of the semiconductor substrate 10 where the cathode region 82 is not provided, a P+ type collector region 22 may be provided. The cathode region 82 and the collector region 22 are provided between the lower surface 23 of the semiconductor substrate 10 and the buffer region 20. Figure 2 In FIG. 8 , the boundary between the cathode region 82 and the collector region 22 is shown by a dotted line.

[0090] Cathode region 82 is positioned away from well region 11 in the Y-axis direction. This ensures a secure distance between the P-type region (well region 11), which has a high doping concentration and is formed deep, and cathode region 82, thereby improving the breakdown voltage. In this example, the Y-axis end of cathode region 82 is positioned farther from well region 11 than the Y-axis end of contact portion 54. In other examples, the Y-axis end of cathode region 82 may be positioned between well region 11 and contact portion 54.

[0091] Figure 3 It shows Figure 2 . The ee cross section is an XZ plane passing through the emitter region 12 and the cathode region 82. The semiconductor device 100 of this example includes the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, and the collector electrode 24 in this cross section.

[0092] The interlayer insulating film 38 is provided on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film including at least one of an insulating film such as silicate glass to which impurities such as boron or phosphorus are added, a thermal oxide film, and other insulating films. Figure 2 The contact portion 54 described in FIG.

[0093] The contact portion 54 is provided so as to penetrate the interlayer insulating film 38. The contact portion 54 may be formed of a metal different from that of the emitter electrode 52. The contact portion 54 may include tungsten. A barrier metal layer including at least one of a titanium film and a titanium nitride film may also be provided at the bottom of the contact portion 54. The contact portion 54 may be provided on the upper surface 21 of the semiconductor substrate 10 or may be provided inside the semiconductor substrate 10. Figure 3 In the example shown, contact portion 54 is a contact groove extending from upper surface 21 of semiconductor substrate 10 to the interior of each mesa portion. This increases the contact area between contact portion 54 and semiconductor substrate 10. In this cross section, the lower end of contact portion 54 of transistor portion 70 contacts emitter region 12. In this cross section, the lower end of contact portion 54 of diode portion 80 contacts base region 14.

[0094] Emitter electrode 52 is provided above interlayer insulating film 38. Emitter electrode 52 is connected to semiconductor substrate 10 via contact portion 54. Collector electrode 24 is provided on lower surface 23 of semiconductor substrate 10. Emitter electrode 52 and collector electrode 24 are formed of a metal material such as aluminum. In this specification, the direction connecting emitter electrode 52 and collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0095] The semiconductor substrate 10 has an N-type or N-type drift region 18 . The drift region 18 is provided in each of the transistor portion 70 and the diode portion 80 .

[0096] In the mesa portion 60 of the transistor portion 70, an N+ type emitter region 12 and a P- type base region 14 are provided in order from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N+ type accumulation region 16 may be provided in the mesa portion 60. The accumulation region 16 is arranged between the base region 14 and the drift region 18.

[0097] Emitter region 12 is exposed on upper surface 21 of semiconductor substrate 10 and is provided in contact with gate trench 40. Emitter region 12 may be in contact with the trenches on both sides of mesa portion 60. The doping concentration of emitter region 12 is higher than that of drift region 18.

[0098] The base region 14 is provided below the emitter region 12. In this example, the base region 14 is provided so as to be in contact with the emitter region 12. The base region 14 may be in contact with the trench portions on both sides of the mesa portion 60.

[0099] The accumulation region 16 is provided below the base region 14. The accumulation region 16 is an N+ type region with a higher doping concentration than the drift region 18. Specifically, the donor concentration in the accumulation region 16 is higher than that in the drift region 18. Providing the high-concentration accumulation region 16 between the drift region 18 and the base region 14 enhances the carrier injection enhancement effect (IE effect) and reduces the on-state voltage. The accumulation region 16 can be provided to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0100] A P-type base region 14 is provided in contact with the upper surface 21 of the semiconductor substrate 10 in the mesa portion 61 of the diode portion 80. A drift region 18 is provided below the base region 14. An accumulation region 16 may also be provided below the base region 14 in the mesa portion 61.

[0101] In each transistor portion 70 and diode portion 80, an N+ type buffer region 20 may be provided below the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 may have a concentration peak having a higher doping concentration than the doping concentration of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Alternatively, the doping concentration of the drift region 18 may be an average value of the doping concentration in a region where the doping concentration distribution is substantially flat.

[0102] The buffer region 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer region 20 may be located at the same depth as, for example, the chemical concentration peaks of hydrogen (protons) or phosphorus. The buffer region 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base region 14 from reaching the P+ collector region 22 and the N+ cathode region 82.

[0103] In transistor portion 70, a P+ type collector region 22 is provided below buffer region 20. The acceptor concentration in collector region 22 is higher than the acceptor concentration in base region 14. Collector region 22 may contain the same acceptor as base region 14 or a different acceptor. The acceptor in collector region 22 is, for example, boron.

[0104] In the diode portion 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration in the cathode region 82 is higher than the donor concentration in the drift region 18. The donor in the cathode region 82 is, for example, hydrogen or phosphorus. It should be noted that the elements that serve as donors and acceptors in each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metal material such as aluminum.

[0105] One or more gate trenches 40 and one or more dummy trenches 30 are provided on the upper surface 21 of the semiconductor substrate 10. Each trench is provided so as to penetrate the base region 14 from the upper surface 21 of the semiconductor substrate 10 and reach below the base region 14. In the region where at least one of the emitter region 12, the contact region 15, and the reservoir region 16 is provided, each trench also penetrates these doped regions. The formation of the doped regions after the trench is formed is not limited to the formation of the doped regions. The formation of doped regions between the trenches after the trenches are formed is also included in the case where the trench penetrates the doped regions.

[0106] As described above, transistor portion 70 is provided with gate trench portion 40 and dummy trench portion 30. Diode portion 80 is provided with dummy trench portion 30, but no gate trench portion 40 is provided. In this example, the boundary between diode portion 80 and transistor portion 70 in the X-axis direction is the boundary between cathode region 82 and collector region 22.

[0107] The gate trench portion 40 includes a gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is provided so as to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided within the gate trench at a position further inward than the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0108] The gate conductive portion 44 can be arranged to be longer in depth than the base region 14. The gate trench portion 40 at this cross section is covered by the interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed in the surface layer of the interface in the base region 14 that contacts the gate trench portion 40.

[0109] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in this cross section. The dummy trench portion 30 includes a dummy trench provided on the upper surface 21 of the semiconductor substrate 10, a dummy insulating film 32, and a dummy conductive portion 34. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided so as to cover the inner wall of the dummy trench. The dummy conductive portion 34 is provided within the dummy trench and further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 may be formed of a conductive material such as polysilicon. The dummy conductive portion 34 may have the same length as the gate conductive portion 44 in the depth direction.

[0110] In this example, the gate trench 40 and the dummy trench 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that the bottoms of the dummy trench 30 and the gate trench 40 may be curved surfaces that are convex downward (curved in cross section). In this specification, the depth position of the lower end 43 of the gate trench 40 is denoted as Zt.

[0111] The semiconductor device 100 of this embodiment includes a P-type floating region 202 provided below the lower end 43 of the gate trench 40. The lower end 43 of the gate trench 40 is the portion of the gate trench 40 that is closest to the lower surface 23 of the semiconductor substrate 10. Figure 3 In the example, the lower end 43 of the gate trench portion 40 is arranged at the center of the gate trench portion 40 in the X-axis direction. In addition, the lower end 33 of the dummy trench portion 30 refers to the portion of the dummy trench portion 30 that is closest to the lower surface 23 of the semiconductor substrate 10. Figure 3In the example, the lower end 33 of the dummy groove portion 30 is arranged at the center of the dummy groove portion 30 in the X-axis direction.

[0112] At least a portion of the floating region 202 is disposed at a position overlapping with the lower end 43 when viewed from above, and is disposed below the lower end 43 in the Z-axis direction. The floating region 202 may include a portion that does not overlap with the lower end 43 when viewed from above. The floating region 202 may also include a portion disposed above the lower end 43. The floating region 202 may be in contact with the lower end 43 or may be separated from the lower end 43. Figure 3 In the example shown in FIG, the floating region 202 contacts the entire curved surface portion including the lower end 43 in the gate trench portion 40. The floating region 202 can be formed by implanting a P-type dopant near the lower end of the trench structure after forming the trench structure of the gate trench portion 40 and before forming the gate conductive portion 44.

[0113] The floating region 202 is electrically floating relative to an electrode such as metal or polysilicon. At least one of an N-type region and an insulating film is disposed between the floating region 202 and the electrode. In other words, the floating region 202 and the electrode are not connected using a P-type region or a conductive material. The doping concentration of the floating region 202 can be lower than the doping concentration of the base region 14 or higher than the doping concentration of the base region 14. In this example, the doping concentration of the floating region 202 is higher than the doping concentration of the base region 14. The doping concentration can be 1×10 15 cm -3 Above and 1×10 17 cm -3 the following.

[0114] The floating region 202 is disposed so as to be separated from the base region 14. An N-type region (in this example, at least one of the reservoir region 16 and the drift region 18) is provided between the floating region 202 and the base region 14.

[0115] In this specification, the gate trench portion 40 with the floating region 202 disposed thereunder is referred to as the first gate trench portion 40-1. Furthermore, the dummy trench portion 30 disposed side by side with the first gate trench portion 40-1 along the X-axis on the upper surface 21 of the dummy trench portion 30 is referred to as the first dummy trench portion 30-1. The first gate trench portion 40-1 and the first dummy trench portion 30-1 are two adjacent trench portions in the X-axis direction. In this example, the first dummy trench portion 30-1 is disposed on both sides of the first gate trench portion 40-1 in the X-axis direction. Furthermore, the mesa portion 60 sandwiched between the first gate trench portion 40-1 and the first dummy trench portion 30-1 is referred to as the first mesa portion 60-1. The mesa portion 60 sandwiched between two dummy trench portions 30 is referred to as the second mesa portion 60-2. The second deck portion 60 - 2 may have the same structure as the first deck portion 60 - 1 .

[0116] Each transistor unit 70 has at least one first gate trench portion 40-1. Each transistor unit 70 may have multiple first gate trench portions 40-1. In each transistor unit 70, more than 50% of the gate trench portions 40 may be first gate trench portions 40-1, more than 80% of the gate trench portions 40 may be first gate trench portions 40-1, or all of the gate trench portions 40 may be first gate trench portions 40-1.

[0117] The floating region 202 is located below the lower end 43 of the first gate trench 40-1 and does not extend below the lower end 33 of the adjacent first dummy trench 30-1. The lower end 33 contacts the N-type region (in this example, the drift region 18). Furthermore, on the upper surface 21 of the semiconductor substrate 10, an N-type region (in this example, the drift region 18) is provided below the lower end 33, rather than a P-type region.

[0118] By providing the floating region 202, when the transistor portion 70 is turned on, the flow of electrons toward the lower end 43 of the first gate trench portion 40-1 can be blocked, leaving a depletion layer near the lower end 43. This reduces reverse recovery dV / dt. Reverse recovery dV / dt is the slope of the time waveform of the anode-cathode voltage during reverse recovery of the diode portion 80. Furthermore, when the semiconductor device 100 is used in a circuit such as a three-phase inverter, the tail portion of the voltage waveform of the IGBT provided in the opposing arm can be reduced. This improves the trade-off between conduction loss and reverse recovery dV / dt.

[0119] On the other hand, if the floating region 202 extends below the lower end 33 of the first dummy trench portion 30-1, then when a channel is formed in the base region 14 of the first mesa portion 60-1 and an electron current flows, the electron current does not easily flow to the collector region 22. Therefore, voltage foldback sometimes occurs when the transistor portion 70 is turned on. In addition, the turn-on time of the transistor portion 70 sometimes becomes longer. The floating region 202 of the semiconductor device 100 of this example does not extend below the lower end 33 of the first dummy trench portion 30-1. Therefore, when a channel is formed in the base region 14 of the first mesa portion 60-1 and an electron current flows, the electron current easily flows to the collector region 22. As a result, the occurrence of voltage foldback can be suppressed, thereby reducing the delay in conduction.

[0120] In this example, the floating region 202 is configured so as not to overlap with the first dummy groove portion 30-1 when viewed from above. The floating region 202 can be configured so as not to contact the first dummy groove portion 30-1. In this example, an N-type region is configured between the floating region 202 and the first dummy groove portion 30-1. The floating region 202 can be configured so as to overlap with the first terrace portion 60-1 when viewed from above. The first terrace portion 60-1 can have a region that does not overlap with the floating region 202 when viewed from above. In the first terrace portion 60-1 in this example, the region that contacts the first dummy groove portion 30-1 does not overlap with the floating region 202. The floating region 202 can extend to a position that overlaps with the contact portion 54 of the first terrace portion 60-1, or it can be configured so as not to overlap with the contact portion 54.

[0121] The floating region 202 is provided so as to extend along the Y-axis direction when viewed from above. The length of the floating region 202 in the Y-axis direction may be at least 50%, at least 70%, or at least 90% of the length of the straight portion 39 of the first gate trench 40-1 in the Y-axis direction. When the floating region 202 is provided throughout the first gate trench 40-1, the end of the floating region 202 in the Y-axis direction is located below the base region 14-e.

[0122] The spacing between the first gate trench portion 40-1 and the first dummy trench portion 30-1 in the X-axis direction is denoted by X1. The spacing between trench portions is the distance between the centers of the trench portions in the X-axis direction. The spacing between the two dummy trench portions 30 in the transistor portion 70 in the X-axis direction is denoted by X2. In this example, the spacing between the two first dummy trench portions 30-1 is denoted by X2. Spacing X1 and spacing X2 may be the same. The spacing between the two dummy trench portions 30 in the diode portion 80 in the X-axis direction is denoted by X3. Spacing X1, spacing X2, and spacing X3 may be the same.

[0123] The intervals between all the trench portions in at least one transistor portion 70 disposed in the X-axis direction so as to be sandwiched between two diode portions 80 may be the same. In addition, the intervals between all the trench portions in the semiconductor device 100 may also be the same.

[0124] Figure 4 It shows Figure 2 FIG2 is a diagram showing an example of an ff cross section. The ff cross section is an XZ plane passing through contact region 15 and cathode region 82. The structure of semiconductor device 100 in the ff cross section has contact region 15 instead of emitter region 12 in mesa portion 60, as compared to the structure of semiconductor device 100 in the ee cross section. Furthermore, contact region 15 is also provided in mesa portion 61. The remaining structure is the same as that of semiconductor device 100 in the ee cross section.

[0125] The contact region 15 is exposed on the upper surface 21 of the semiconductor substrate 10. The contact region 15 is provided between the upper surface 21 and the base region 14. In this embodiment, the contact region 15 does not contact the groove portions on both sides of each mesa portion. Figure 4 In the example shown in FIG, base region 14 is provided between contact region 15 and each trench portion. In this example, contact region 15 is connected to emitter electrode 52 via contact portion 54. Contact region 15 may be provided with a groove portion for inserting contact portion 54. In this cross section, the lower ends of contact portions 54 of transistor portion 70 and diode portion 80 are in contact with contact region 15.

[0126] Figure 5 Graphs showing collector voltage-collector current characteristics in the embodiment and the reference example. The reference example is an example in which the floating region 202 is extended to below the lower end 33 of the first dummy trench portion 30-1. Figures 1 to 4 The semiconductor device 100 described in .

[0127] In the reference example, the electron current of the first terrace portion 60-1 is not easily transferred to the collector region 22 due to the floating region 202. Therefore, in the reference example, Figure 5 As shown, voltage foldback occurs, in which collector current hardly flows until the collector voltage exceeds a predetermined voltage. In contrast, in the semiconductor device 100 of the embodiment, electron current in the first terrace portion 60-1 easily flows in the collector region 22. Therefore, voltage foldback does not occur.

[0128] Figure 6 Graphs showing a measurement example of voltage and current in a semiconductor device of a reference example. Figure 6 The semiconductor device of the reference example has Figure 5 The semiconductor device of the reference example has the same structure. Figure 6 , time waveforms of the collector voltage Vce, collector current Ic, and gate voltage Vge of the semiconductor device are shown. Figure 6 Here, Vbus represents the voltage of the bus line connected to the collector of the semiconductor device, Ic represents the steady-state value of the collector current, Rg represents the gate resistance, and Tj represents the temperature of the measurement environment.

[0129] exist Figure 6 In the example, the time when a predetermined on-voltage is applied to the gate of the semiconductor device is defined as reference time 0. The time until the collector voltage Vce drops to 10% of the off-state voltage value (600 V) is defined as the on-time of the semiconductor device.

[0130] As the gate capacitance charges, the gate voltage Vge increases. In this example, when the gate voltage Vge is approximately 440V, a channel forms in the base region 14. However, in the reference example, the electron current in the first terrace portion 60-1 is less likely to flow to the collector region 22, resulting in a slow rise in the collector current Ic and a delayed fall in the collector voltage Vce. Consequently, the on-time becomes relatively long, leading to increased losses during conduction.

[0131] Figure 7 Graphs showing measurement examples of voltage and current in the semiconductor device of the embodiment. Figure 7 A semiconductor device of an embodiment is Figures 1 to 4 . In the embodiment, the electron current in the first terrace portion 60-1 easily flows to the collector region 22. Therefore, the delay between the rise of the collector current Ic and the fall of the collector voltage Vce is small. This shortens the on-time and reduces the loss during conduction.

[0132] Figure 8 This is a graph showing another example of measuring the voltage and current of a semiconductor device of a reference example. In this example, the steady-state value of the collector current Ic (150A) is Figure 6 The steady-state value of the collector current Ic (15A) of the reference example is different. Other conditions are the same as Figure 6 The same as the reference example. Figure 8 In the reference example, the collector current Ic rises slowly, and the collector voltage Vce falls slowly. Therefore, the on-time becomes relatively long, resulting in increased loss during conduction.

[0133] Figure 9 This is a graph showing another example of measuring the voltage and current of the semiconductor device of the embodiment. In this example, the steady-state value of the collector current Ic (150A) is Figure 7 The steady-state value (15A) of the collector current Ic of the embodiment is different. Other conditions are the same as Figure 7 The same as the embodiment of Figure 9 In the embodiment of FIG. 1 , the delay in the rise of the collector current Ic and the fall of the collector voltage Vce is also small. As a result, the on-time becomes relatively short, and the loss during conduction can be reduced.

[0134] Figure 10 Graphs showing trade-off characteristics between conduction loss and reverse recovery dV / dt in a reference example and an embodiment. Figure 10 This shows a trade-off relationship in which if the reverse recovery dV / dv is reduced, the conduction loss increases.

[0135] Figure 10 The reference example in FIG. 1 is a semiconductor device that does not have the floating region 202. The semiconductor device of the embodiment is Figures 1 to 4The semiconductor device 100 described in . The semiconductor device 100 of the embodiment improves the trade-off characteristics by including the floating region 202. For example, when the reverse recovery dV / dt is set to the same, the conduction loss of the embodiment is smaller than that of the reference example.

[0136] like Figure 10 As described in , according to the semiconductor device 100, the trade-off characteristics between conduction loss and reverse recovery dV / dt can be improved. Figure 5 As described in , the semiconductor device 100 can suppress voltage foldback. Figures 6 to 9 As described in , according to the semiconductor device 100 , it is possible to reduce a delay in turning on the transistor portion 70 .

[0137] Figure 11 FIG. 1 is a diagram showing another example of the ff cross section. The structure of the accumulation region 16 of the semiconductor device 100 of this embodiment is similar to that of FIG. Figure 3 and Figure 4 The semiconductor device 100 in FIG. 1 is different in structure from that of the accumulation region 16. The other structures are the same as those of the semiconductor device 100 in any embodiment described in this specification.

[0138] In this example, the accumulation region 16 is in contact with the floating region 202. The accumulation region 16 may or may not be in contact with the base region 14. The lower ends of the accumulation regions 16 may be positioned at the same depth in each mesa portion. The lower end of the accumulation region 16 may be positioned closer to the upper surface 21 than the lower end 43 of the first gate trench portion 40-1, closer to the lower surface 23 than the lower end 43, or at the same depth as the lower end 43. In this example, the lower end of the accumulation region 16 is positioned above the lower end of the floating region 202.

[0139] According to this embodiment, since the high-concentration accumulation region 16 is disposed near the floating region 202, excessive diffusion of P-type dopants in the floating region 202 can be suppressed, and the entire first mesa portion 60-1 can be prevented from being covered by the floating region 202. For example, an N-type region is likely to remain near the first dummy trench portion 30-1. This makes it easier to suppress the occurrence of voltage foldback, etc.

[0140] Figure 12 FIG. 1 is a diagram showing another example of the ff cross section. The structure of the accumulation region 16 of the semiconductor device 100 of this embodiment is similar to that of FIG. Figure 11 The semiconductor device 100 in FIG. 1 is different in structure from that of the accumulation region 16. The other structures are the same as those of the semiconductor device 100 in any embodiment described in this specification.

[0141] In this example, the lower end of the reservoir region 16 is positioned below the lower end of the floating region 202. In this example, the floating region 202 is surrounded by the reservoir region 16, except for the portion in contact with the trench. The lower end of the reservoir region 16 can be positioned on the upper surface 21 side of the semiconductor substrate 10. The distance between the lower end of the floating region 202 and the lower end of the reservoir region 16 in the Z-axis direction can be 10 μm or less, 5 μm or less, or 3 μm or less.

[0142] According to this example, the floating region 202 is surrounded by the reservoir region 16. Therefore, it is possible to prevent excessive diffusion of P-type dopants in the floating region 202, which would otherwise cause the entire first mesa portion 60-1 to be covered by the floating region 202. For example, an N-type region is likely to remain near the first dummy trench portion 30-1. This makes it easier to suppress the occurrence of voltage foldback, etc.

[0143] Figure 13 ff is a diagram showing another example of a cross section. The arrangement of the floating region 202 of the semiconductor device 100 of this example is different from that of the semiconductor device 100 of other examples. The remaining structure is the same as that of any semiconductor device 100 described in this specification.

[0144] The floating region 202 of this example does not contact the first gate groove portion 40-1. The floating region 202 is configured below the lower end 43 of the first gate groove portion 40-1 in a manner separated from the lower end 43. In this example, the floating region 202 is also configured on the upper surface 21 side of the semiconductor substrate 10. The distance between the floating region 202 and the lower end 43 in the Z-axis direction can be less than 10 μm, less than 5 μm, or less than 3 μm. According to this example, it is easy to ensure the path for the electron current to flow from the first terrace portion 60-1 to the collector region 22. Therefore, the occurrence of voltage foldback, etc. can be further suppressed.

[0145] Figure 14 ff is a diagram showing another example of a cross section. The arrangement of the floating region 202 of the semiconductor device 100 of this example is different from that of the floating region 202 of the semiconductor device 100 of other examples. The remaining structure is the same as that of any semiconductor device 100 described in this specification.

[0146] In this example, the floating region 202 contacts the first dummy trench 30 - 1 . If first dummy trenches 30 - 1 are disposed on both sides of the first gate trench 40 - 1 in the X-axis direction, the floating region 202 may contact the first dummy trenches 30 - 1 on both sides.

[0147] In this example, the floating region 202 also does not extend below the lower end 33 of the first dummy trench portion 30-1. The floating region 202 may contact the sidewalls of the first dummy trench portion 30-1. The sidewalls are the outer wall portions of the first dummy trench portion 30-1 excluding the lower end 33. The sidewalls of the first dummy trench portion 30-1 may be planar portions of the outer wall of the first dummy trench portion 30-1. This example also improves the aforementioned trade-off characteristics.

[0148] In this example, the dummy conductive portion 34 of the first dummy groove portion 30-1 can be an electrode of polysilicon doped with N-type impurities. When the dummy conductive portion 34 is P-type polysilicon, the sidewalls of the first dummy groove portion 30-1 and the floating region 202 are at the same potential. In this case, the path for the electron current from the channel to flow is cut off by the region of equal potential, making it difficult for the electron current to flow. By making the dummy conductive portion 34 N-type, the sidewalls of the first dummy groove portion 30-1 and the floating region 202 can be at different potentials. In this case, a path for the electron current to flow remains near the sidewalls of the first dummy groove portion 30-1. Therefore, the trade-off characteristics of the semiconductor device 100 can be improved, and the occurrence of voltage foldback can be suppressed.

[0149] The conductive portions of the groove portions other than the first dummy groove portion 30-1 may also be N-type polysilicon. The doping concentration of N-type impurities in the dummy conductive portion 34 of the first dummy groove portion 30-1 may be higher than the doping concentration of N-type impurities in the gate conductive portion 44 of the first gate groove portion 40-1. This makes it easier to ensure a path for electron current to flow near the sidewalls of the first dummy groove portion 30-1. In other examples, the conductive portions of at least a portion of the groove portions other than the first dummy groove portion 30-1 may be P-type polysilicon. For example, the conductive portion of the first gate groove portion 40-1 may be P-type polysilicon.

[0150] Figure 15 1 is a diagram showing another example of a cross section taken along line ff. The arrangement pattern of the trench portions in the transistor portion 70 in the X-axis direction of the semiconductor device 100 of this example differs from the arrangement patterns of the semiconductor devices 100 of the other examples. The structure of the trench portions, other than the arrangement pattern, is the same as that of any semiconductor device 100 described in this specification.

[0151] The transistor portion 70 of this example has two first gate trench portions 40 - 1 arranged adjacent to each other in the X-axis direction. As an example, in the transistor portion 70 , two first gate trench portions 40 - 1 and two first dummy trench portions 30 - 1 are alternately arranged in the X-axis direction.

[0152] A floating region 202 is provided below the lower end 43 of each first gate trench 40-1. The floating regions 202 below two first gate trenches 40-1 adjacent to each other in the X-axis direction may be as follows: Figure 15 Although shown as separated from each other, they can also be connected to each other.

[0153] The mesa portion 60 sandwiched between the two first gate trench portions 40-1 is referred to as a third mesa portion 60-3. The third mesa portion 60-3 may have the same structure as the first mesa portion 60-1. In other examples, the third mesa portion 60-3 may have a different structure from the first mesa portion 60-1. The third mesa portion 60-3 may be sandwiched between the first mesa portion 60-1 in the X-axis direction. In this example, no more than three first gate trench portions 40-1 are arranged continuously in the X-axis direction.

[0154] Figure 16 ff is a diagram showing another example of a cross section. The semiconductor device 100 of this example differs from the semiconductor devices 100 of the other examples in that it includes a lower end region 204. The structure other than the lower end region 204 is the same as that of any semiconductor device 100 described in this specification.

[0155] The lower end region 204 is an N-type region provided below the lower end 33 of the first dummy trench portion 30-1. The doping concentration of the lower end region 204 is higher than the doping concentration of the drift region 18. The doping concentration of the lower end region 204 can be at least twice, at least five times, or even at least ten times the doping concentration of the drift region 18. The doping concentration of the lower end region 204 can be higher or lower than the doping concentration of the floating region 202. By providing the lower end region 204, the vicinity of the lower end 33 of the first dummy trench portion 30-1 can be prevented from becoming P-type, thereby facilitating the securement of a path for electron current.

[0156] The lower end region 204 may be in contact with the lower end 33 of the first dummy trench portion 30-1, or may be separated from the lower end 33. The lower end of the lower end region 204 may be positioned above the lower end of the floating region 202, or may be positioned below the lower end of the floating region 202. The lower end region 204 may be separated from the reservoir region 16, or may be in contact with the reservoir region 16.

[0157] Figure 17 is a diagram showing another example of the ee cross section. Figure 3 In the example shown, the semiconductor device 100 of this example further includes a contact region 19. In addition, the arrangement of the contact portion 54 is different. Figure 3 Same as the example.

[0158] Contact region 19 is provided in contact with the lower end of contact portion 54 and is a P+ type region having a higher concentration than that of base region 14. The doping concentration of contact region 19 may be the same as that of contact region 15. At least a portion of contact region 19 may be provided inside base region 14. Contact portion 54 in transistor portion 70 may be provided so as to penetrate emitter region 12 or so as not to penetrate emitter region 12. In this example, contact region 19 in transistor portion 70 is provided below emitter region 12. In addition, the entire contact region 19 in diode portion 80 is provided inside base region 14.

[0159] The contact region 19 may be provided at the same depth position as the ee cross section in each mesa portion of the ff cross section. In addition, when the emission region 12 is provided instead of the contact region 15, the ff cross section becomes the same as the ee cross section. Figure 17 Same structure.

[0160] While the present invention has been described above using the embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. As can be clearly seen from the description of the claims, embodiments in which such changes or improvements are made are also included in the technical scope of the present invention.

[0161] It should be noted that the order of execution of actions, sequences, steps, stages, and other processes in the apparatus, system, program, or method described in the claims, specifications, and drawings may be implemented in any order, unless otherwise indicated by phrases such as "before," "prior to," and so forth, and unless the output of a previous process is used in a subsequent process. Even if the phrases "first," "next," and so forth are used for convenience in describing the process flow in the claims, specifications, and drawings, this does not necessarily imply that the processes must be performed in that order.

Claims

1. A semiconductor device, characterized in that: A semiconductor device including an IGBT is provided. a semiconductor substrate having an upper surface and a lower surface and provided with a drift region of a first conductivity type; a first gate trench portion, which is disposed on the upper surface of the semiconductor substrate; a first dummy trench portion, which is provided on the upper surface of the semiconductor substrate and arranged side by side with the first gate trench portion on the upper surface; a first mesa portion sandwiched by the first gate trench portion and the first dummy trench portion within the semiconductor substrate; as well as a second conductive type floating region disposed below the lower end of the first gate trench portion on the upper surface side of the semiconductor substrate and not extending below the lower end of the first dummy trench portion; The first surface portion has: an emitter region of a first conductivity type, which is provided in contact with the first gate trench portion and has a concentration higher than that of the drift region; and a base region of a second conductivity type, which is disposed between the emitter region and the drift region and contacts the first gate trench portion; A lower end of the first dummy trench portion contacts a region of the first conductive type.

2. The semiconductor device according to claim 1, wherein The floating region does not contact a lower end of the first gate trench portion.

3. The semiconductor device according to claim 1, wherein The floating region contacts a lower end of the first gate trench portion.

4. The semiconductor device according to any one of claims 1 to 3, wherein The first mesa portion further includes an accumulation region of a first conductivity type, the accumulation region of the first conductivity type being provided between the base region and the drift region and having a concentration higher than that of the drift region.

5. The semiconductor device according to claim 4, wherein The accumulation region is in contact with the floating region.

6. The semiconductor device according to claim 5, wherein The lower end of the accumulation region is arranged below the lower end of the floating region.

7. The semiconductor device according to claim 5, wherein The lower end of the accumulation region is arranged above the lower end of the floating region.

8. The semiconductor device according to claim 1, wherein The first mesa portion further includes a second conductivity type contact region that is in contact with the upper surface of the semiconductor substrate and has a concentration higher than that of the base region.

9. The semiconductor device according to claim 8, wherein The first mesa portion further includes a contact portion that is provided from the upper surface of the semiconductor substrate to the interior of the first mesa portion and is filled with a conductive material.

10. The semiconductor device according to claim 9, wherein A lower end of the contact portion contacts the contact area.

11. The semiconductor device according to any one of claims 1 to 3, wherein: The first dummy trench portions are provided on both sides of the first gate trench portion.

12. The semiconductor device according to any one of claims 1 to 3, wherein: The floating region is in contact with a sidewall of the first dummy trench portion.

13. The semiconductor device according to claim 12, wherein: The first dummy trench portion includes an electrode made of polysilicon to which first conductivity-type impurities are added.

14. The semiconductor device according to any one of claims 1 to 3, wherein: The semiconductor device further includes a lower end region of a first conductivity type, the lower end region of the first conductivity type being provided in contact with a lower end of the first dummy trench portion and having a concentration higher than that of the drift region.

15. The semiconductor device according to any one of claims 1 to 3, wherein The semiconductor device further includes two dummy trench portions, the two dummy trench portions being provided on the upper surface of the semiconductor substrate and arranged side by side on the upper surface. The interval between the first gate trench portion and the first dummy trench portion is the same as the interval between the two dummy trench portions.

16. The semiconductor device according to any one of claims 1 to 3, wherein: The semiconductor device further includes a diode portion, the diode portion being arranged alternately in parallel with the IGBT in a first direction. The IGBT sandwiched between the diode portions has a plurality of trench portions, the plurality of trench portions including the first gate trench portion and the first dummy trench portion, and arranged side by side in the first direction. The intervals between the plurality of grooves are the same.

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