Capacitance test method and device of wafer and electronic equipment
By reading common information before wafer capacitance testing to generate judgment variables and determining whether there is an empty needle capacitance value, the problems of resource waste and shortened probe card life caused by repeated testing in the existing technology are solved, and efficient capacitance testing is achieved.
Patent Information
- Application Number
- CN202510802634.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-02
- Publication Date
- 2025-09-09
AI Technical Summary
In existing wafer capacitance testing methods, the probe needs to be lifted for each test, resulting in waste of test resources, reduced production capacity and shortened probe card life.
Before the test, the test information of the object to be tested is read, and a judgment variable is generated based on the common information to determine whether there is an empty needle capacitance value. If it exists, it is automatically obtained. If it does not exist, an empty needle test is performed and the capacitance value is associated.
By reducing repeated empty probe capacitance tests, capacitance test efficiency is improved, the number of needle lifts/punctures is reduced, the probe card life is extended, and costs are reduced.
Smart Images
Figure CN120610067A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of wafer testing technology, and in particular to a wafer capacitance testing method, device and electronic equipment. Background Art
[0002] Capacitance is a common item in wafer acceptance testing. During testing, it is affected by the parasitic capacitance of the associated test circuit. Therefore, to obtain accurate capacitance test values, it is necessary to minimize the interference of parasitic capacitance.
[0003] In the prior art, deducting the empty probe capacitance is a common method to effectively reduce parasitic capacitance interference. The empty probe capacitance (C0) is obtained by measuring the capacitance value of the corresponding loop when the probe card is not in contact with the wafer to characterize the parasitic capacitance. After obtaining the empty probe capacitance, the probe card contacts the wafer and measures the capacitance value of the corresponding loop, which is C1. The actual capacitance (C = C1-C0) can effectively reduce the influence of parasitic capacitance.
[0004] However, the test methods for C0 and C1 are the same, primarily characterizing the parasitic capacitance of the test system. Existing test methods require a probe lift to test the empty probe capacitance (C0) for each device on the wafer, resulting in a waste of test resources and test capacity. Furthermore, the numerous probe lift / insert operations shorten the life of the probe card. Summary of the Invention
[0005] In view of this, an object of the present invention is to provide a method, device and electronic equipment for testing capacitance of a wafer, so as to quickly and intelligently test capacitance, thereby greatly improving the efficiency of capacitance testing.
[0006] In the first aspect, an embodiment of the present invention provides a capacitance testing method for a wafer, the method comprising: before performing an empty needle capacitance test, reading the test information of the object to be tested; generating a judgment variable based on the common information in the test information; the common information characterizes the same test position and test conditions relative to the same reference dimension; determining whether there is a corresponding empty needle capacitance value based on the judgment variable; if not, performing an empty needle test on the object to be tested according to the test information, and associating the empty needle capacitance value obtained from the test with the judgment variable; if it exists, automatically obtaining the existing empty needle capacitance value.
[0007] In an optional embodiment of the present application, the above-mentioned test information includes test object information and test parameters, and generates judgment variables based on the common information in the test information, including: obtaining the test mode selected by the user, and determining the data dimensions required for the common information according to the test mode; selecting the required test object information according to the data dimensions required for the common information, and together with the common information in the test parameters, forming the judgment variable information.
[0008] In an optional embodiment of the present application, the above-mentioned test mode includes testing one batch once, testing one wafer once, and testing one bare die once. The data dimensions are correspondingly set with batch dimension, wafer dimension, and bare die dimension. According to the data dimension, the required test object information is determined to be composed of at least one of the batch ID, wafer ID, and bare die ID.
[0009] In an optional embodiment of the present application, the above-mentioned determination of the required test object information consisting of at least one of batch ID, wafer ID, and die ID based on the data dimension includes: if the mode selected by the user corresponds to the die dimension, determining that the test object information includes: batch ID, wafer ID, and die ID; if the mode selected by the user corresponds to the wafer dimension, determining that the test object information includes: batch ID and wafer ID; if the mode selected by the user corresponds to the batch dimension, determining that the test object information includes: batch ID.
[0010] In an optional embodiment of the present application, the above-mentioned test parameters include position information of the object to be tested in the bare chip and test conditions of the object to be tested.
[0011] In an optional embodiment of the present application, the above-mentioned determination of whether there is a corresponding empty needle capacitance value based on the judgment variable includes: setting the judgment variable to key, setting the return instruction ($) to obtain the variable output quantity, and the return instruction ($) to obtain the quantitative output is empty; based on the judgment variable, obtain the global variable of $$key; when $$key is an empty value, the global variable is the target value; when $$key is a quantity, the global variable is the value of the variable $key; determine whether to test the empty needle capacitance based on the value of the global variable; when testing the empty needle capacitance, set $key to a variable whose value is equal to the empty needle capacitance value obtained by the current test.
[0012] In an optional embodiment of the present application, the above-mentioned target value is greater than a preset threshold value; whether to test the empty needle capacitance is determined based on the value of the global variable, including: if the value of the global variable is greater than the threshold value, determining to test the empty needle capacitance; if the value of the global variable is less than or equal to the threshold value, determining not to test the empty needle capacitance.
[0013] In the second aspect, an embodiment of the present invention also provides a capacitance testing device for a wafer, the device including: a test information reading module, used to read the test information of the object to be tested before performing an empty needle capacitance test; generating a judgment variable based on the common information in the test information; the common information representation represents the same test position and test conditions relative to the same reference dimension; a test judgment module, used to determine whether there is a corresponding empty needle capacitance value based on the judgment variable; if not, performing an empty needle test on the object to be tested according to the test information, and associating the empty needle capacitance value obtained by the test with the judgment variable; if it exists, automatically obtaining the existing empty needle capacitance value.
[0014] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the above-mentioned wafer capacitance testing method.
[0015] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the above-mentioned wafer capacitance testing method.
[0016] The embodiments of the present invention bring the following beneficial effects:
[0017] The embodiment of the present invention provides a capacitance testing method, device and electronic device for a wafer. Before performing an empty needle capacitance test, the test information of the object to be tested is read; a judgment variable is generated based on the common information in the test information; the common information represents the same test position and test conditions relative to the same reference dimension; based on the judgment variable, it is determined whether there is a corresponding empty needle capacitance value; if not, an empty needle test is performed on the object to be tested according to the test information, and the empty needle capacitance value obtained by the test is associated with the judgment variable; if it exists, the existing empty needle capacitance value is automatically obtained. In this method, by using the test information such as the test object and the test parameters as common information, it is determined based on the judgment of the global variable whether there is an empty needle capacitance, and the empty needle capacitance test can be repeated without increasing production capacity and improving production efficiency; at the same time, the number of needle lifts / needles is greatly reduced, the life of the needle card is increased, and the cost is reduced.
[0018] Other features and advantages of the present disclosure will be set forth in the following description, or some features and advantages may be inferred or unambiguously determined from the description, or may be learned by practicing the above-mentioned technology of the present disclosure.
[0019] In order to make the above-mentioned objectives, features and advantages of the present disclosure more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0021] Figure 1 A flow chart of a wafer capacitance testing method provided by an embodiment of the present invention;
[0022] Figure 2 A flow chart of another wafer capacitance testing method provided by an embodiment of the present invention;
[0023] Figure 3 A schematic diagram of a wafer capacitance testing method provided by an embodiment of the present invention;
[0024] Figure 4 A schematic structural diagram of a wafer capacitance testing device provided by an embodiment of the present invention;
[0025] Figure 5 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0026] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0027] Currently, existing technologies for wafer capacitance testing require a probe lift for each device to test for empty probe capacitance. However, multiple probe lifts waste production capacity and testing resources, and the numerous probe lift and insertion operations shorten the life of the probe card.
[0028] Based on this, the embodiments of the present invention provide a method, device and electronic equipment for testing the capacitance of a wafer, which specifically provides a method for quickly testing capacitance applied in the field of wafer electrical testing. It can intelligently allocate data to the corresponding test object without repeatedly testing the empty needle capacitance, thereby effectively reducing the influence of parasitic capacitance, quickly and intelligently testing capacitance, and greatly improving the efficiency of capacitance testing without the need for manual operation.
[0029] To facilitate understanding of this embodiment, a capacitance testing method for a wafer disclosed in an embodiment of the present invention is first introduced in detail.
[0030] Example 1:
[0031] The embodiment of the present invention provides a method for testing the capacitance of a wafer. Figure 1 The flowchart of a wafer capacitance testing method is shown, and the wafer capacitance testing method includes the following steps:
[0032] Step S102, before performing the empty needle capacitance test, read the test information of the object to be tested; generate a judgment variable based on the common information in the test information; the common information represents the same test position and test conditions relative to the same reference dimension.
[0033] In this embodiment, before performing the electrical test / empty needle capacitance test, the test information of the object to be tested can be read; the test information may include the test object information and test parameters, and the read test information is integrated and assigned to the judgment variable (i.e., the variable key). The variable key can be assigned to a string related to the test information.
[0034] Step S104, based on the judgment variable, determine whether there is a corresponding empty needle capacitance value; if not, perform an empty needle test on the object to be tested according to the test information, and associate the empty needle capacitance value obtained by the test with the judgment variable; if it exists, automatically obtain the existing empty needle capacitance value.
[0035] In this embodiment, commonality information can be determined based on test requirements and / or test hardware and software implementation conditions. For example, for relatively identical test locations and test conditions, the value of the empty needle capacitance can be considered identical or shared, and the commonality information can be composed of parameters related to the test location and test conditions. Relatively identical test locations can refer to relatively identical test coordinates or test objects, such as the same device within the same module on different wafers / dies within the same lot, or the same module on different wafers / dies within the same lot.
[0036] In this embodiment, a global variable can be determined based on the variable key. In this case, a global variable of $$key (a variable that can be used by different test items before the entire software is closed) can be obtained using an instruction. The above $key can refer to a string related to the test information in the above steps.
[0037] If there is no empty pin capacitance value associated with $key, then $key is still a string related to the test information, and the obtained global variable result can be the preset target value. 30 The value X2 is used as the target value.
[0038] If there is an empty pin capacitance value associated with $key, that is, the empty pin capacitance has been measured before on the device under test at the same position on other dies (bare chips), then $key is associated with the empty pin capacitance value, that is, the string information is associated with the empty pin capacitance value. Specifically, by setting $key to a variable with a value equal to the empty pin capacitance value, the global variable result obtained can be the above-mentioned empty pin capacitance value, and the above-mentioned empty pin capacitance value is assigned to the global variable.
[0039] In this embodiment, whether to test the empty needle capacitance can be determined by judging the value of the global variable. If the empty needle capacitance is tested, the test is performed without contacting the pin card, and the empty needle capacitance test value is assigned to the global variable; if the empty needle capacitance is not tested, the empty needle capacitance test result is automatically obtained.
[0040] An embodiment of the present invention provides a capacitance testing method for a wafer. Before performing an empty needle capacitance test, the test information of the object to be tested is read; a judgment variable is generated based on the common information in the test information; the common information represents the same test position and test conditions relative to the same reference dimension; based on the judgment variable, it is determined whether there is a corresponding empty needle capacitance value; if not, an empty needle test is performed on the object to be tested according to the test information, and the empty needle capacitance value obtained by the test is associated with the judgment variable; if it exists, the existing empty needle capacitance value is automatically obtained. In this method, by using the test information such as the test object and the test parameters as common information, it is determined based on the judgment of the global variable whether there is an empty needle capacitance, and the empty needle capacitance test can be repeated without increasing production capacity and improving production efficiency; at the same time, the number of needle lifts / needles is greatly reduced, the life of the needle card is increased, and the cost is reduced.
[0041] Example 2:
[0042] This embodiment provides another method for testing the capacitance of a wafer, which is implemented on the basis of the above embodiment. Figure 2 A flow chart of another wafer capacitance testing method is shown, and the wafer capacitance testing method includes the following steps:
[0043] Step S202, before performing the empty needle capacitance test, read the test information of the object to be tested, the test information includes the test object information and test parameters; obtain the test mode selected by the user, and determine the data dimensions required for the common information according to the test mode; select the required test object information according to the data dimensions required for the common information, and together with the common information in the test parameters, form a judgment variable.
[0044] In some embodiments, the above-mentioned test mode includes testing one batch once, testing one wafer once, and testing one bare die once. The data dimensions are correspondingly set with batch dimension, wafer dimension, and bare die dimension. According to the data dimension, the required test object information is determined to be composed of at least one of the batch ID, wafer ID, and bare die ID.
[0045] Among them, "one die, one test" means that the DUT with the same common information in each die only needs to be tested once. Specifically, it means that the open pin capacitance of each die on a wafer is measured separately. For example, each die has multiple modules, and the DUT is located on the module:
[0046] If the empty pin capacitance of the devices under test on the same module of a single die is set to be the same, then under the same test conditions, multiple devices under test on the entire module only need to measure the empty pin capacitance once, and subsequent devices under test can directly use the same empty pin capacitance.
[0047] If the capacitance empty pin values of the devices under test in a single die are all set to be different, the empty pin capacitances of the devices under test on the single die need to be tested separately.
[0048] Among them, one wafer test once refers to the empty pin capacitance test of multiple bare chips under each wafer. The DUTs with the same common information only need to be tested once. Specifically, it means that only one wafer needs to be tested for empty pin capacitance. For example, each bare chip has multiple modules, and the DUT is located on the module:
[0049] If the empty pin capacitance of the same device under test on the same module of different dies is set to be the same, then under the same test conditions, only the corresponding empty pin capacitance on one die needs to be tested. The devices under test at the same position on other dies can then directly use this empty pin capacitance.
[0050] Among them, one batch test once refers to the empty pin capacitance test of multiple wafers in a batch. The DUTs with the same common information only need to be tested once. Specifically, it means that the empty pin capacitance of multiple wafers in a batch only needs to be tested once. For example, each bare die has multiple modules, and the DUT is located on the module:
[0051] If the empty pin capacitance of the same device under test on the same module of different dies is set to be the same, then under the same test conditions, only the corresponding empty pin capacitance on one die needs to be tested. The devices under test at the same position on other dies can then directly use this empty pin capacitance.
[0052] In some embodiments, if the mode selected by the user corresponds to the die dimension, the test object information is determined to include: batch ID, wafer ID and die ID. According to the difference in die ID, the empty needle capacitor of different dies can be tested separately; if the mode selected by the user corresponds to the wafer dimension, the test object information is determined to include: batch ID and wafer ID; if the mode selected by the user corresponds to the batch dimension, the test object information is determined to include: batch ID.
[0053] In some embodiments, the test parameters include location information of the object to be tested in the die and test conditions of the object to be tested.
[0054] The test object information in this embodiment may include: the name of the batch (lotID), the name of the wafer (waferID) or the name of the die (die ID), and the test parameters include test input information (such as the pad number and voltage value of the device under test).
[0055] In this embodiment, the user can select a die, wafer, or lot as a mode for measuring the primary pin capacitance.
[0056] See also Figure 3 The schematic diagram of a wafer capacitance test method is shown in FIG. 1 , where the user can select the mode. If the user selects the die dimension mode (i.e. Figure 3 If the user selects the mode of wafer dimension (i.e. mode 0 in ), it means that each die needs to be tested. Figure 3 If the user selects the mode 1 in lot dimension, it means that each wafer only needs to be tested once. For example, if there are multiple test objects with the same position, then after completing the empty pin capacitance test of the first test object, the subsequent test objects do not need to be tested again. Figure 3 Mode 3) in the figure means that a batch (which may include 1-25 wafers) only needs to be tested once. For example, after completing the empty pin capacitance test of the test object (DUT) in a certain die of the first wafer, the subsequent test objects with the same position relative to the die do not need to be tested again.
[0057] In this embodiment, the composition of the test object information can be determined based on the selected mode, as follows: if the user selects the die dimension mode, the test object information includes lot ID, wafer ID, and die ID; if the user selects the wafer dimension mode, the test object information includes lot ID and wafer ID; if the user selects the lot dimension mode, the test object information includes lotID.
[0058] like Figure 3 As shown, in this embodiment, a string related to the test information can be assigned to the variable key. For example, the variable key in this embodiment can be key = [lot ID, wafer ID, die XY, test parameters], where die XY can be the coordinates of the die relative to the wafer.
[0059] Step S204, determine whether there is a corresponding empty needle capacitance value based on the judgment variable; if not, perform an empty needle test on the object to be tested according to the test information, and associate the empty needle capacitance value obtained from the test with the judgment variable; if it exists, automatically obtain the existing empty needle capacitance value.
[0060] In some embodiments, the judgment variable can be set as key, and the return instruction ($) can be set to obtain the variable output quantity, and the return instruction ($) obtains that the quantitative output is empty; based on the judgment variable, the global variable of $$key is obtained; when $$key is an empty value, the global variable is the target value; when $$key is a quantity, the global variable is the value of the variable $key; based on the value of the global variable, it is determined whether to test the empty needle capacitance; when testing the empty needle capacitance, $key is set to a variable whose value is equal to the empty needle capacitance value obtained by the current test.
[0061] like Figure 3 As shown, if there is no empty pin capacitance value associated with the variable key, the target value X2 can be assigned to Var1. If there is an empty pin capacitance value C0_tmp associated with the variable key, the obtained global variable result can be C0_tmp, and C0_tmp is assigned to Var1.
[0062] In some embodiments, if the value of the global variable is greater than a threshold, it is determined that the empty needle capacitance is tested; if the value of the global variable is less than or equal to the threshold, it is determined that the empty needle capacitance is not tested.
[0063] The target value is greater than a preset threshold. For example, in this embodiment, the target value can be greater than the preset threshold 1e 30 The value X2 is taken as the target value. Figure 3 As shown, in this embodiment, it is possible to determine whether to test the empty needle capacitance. 30 , you can enter the loop, that is, test the empty pin capacitance.
[0064] Among them, after determining the test empty needle capacitance, the wafer can also be controlled to descend to separate from the probe to test the current empty needle capacitance value; the current empty needle capacitance value is associated with the variable, and the current empty needle capacitance value is placed in the empty needle array as a test result.
[0065] like Figure 3 As shown, the wafer is controlled to descend (separated from the probe), the current empty needle capacitance value is tested, and then $key is set to a variable whose value is equal to the current empty needle capacitance value C0_tmp. At this time, it is equivalent to converting the aforementioned string into a variable whose value is the empty needle capacitance, and putting C0_tmp into the empty needle array C0.
[0066] like Figure 3 As shown, if Var1≤1e 30 , that is, there is already an available empty pin capacitor, so it can be determined not to test the empty pin capacitor.
[0067] After determining not to test the empty pin capacitance, the value of the global variable can be placed into the empty pin array as a test result.
[0068] like Figure 3 As shown, the global variable result obtained is C0_tmp, Var1 is C0_tmp, then the value of Var1 is directly put into the empty needle array C0.
[0069] At the wafer level, a wafer consists of multiple dies (bare chips), each of which contains multiple modules, and each module contains multiple DUTs. If a second device (DUT) in the same module on a die undergoes capacitance testing, the variable keys will differ due to different input conditions for different parameters. Therefore, the first capacitance test of each device will go through the entire process, with a separate test for the bare pin capacitance.
[0070] For the same module and the same device in different dies, wafers, and lots (meaning the relative position relative to the die is the same), by setting different mode values (such as Figure 3 The 0, 1, and 2 in the value correspond to one empty pin test per die, wafer, or lot, respectively. This allows the same device in the same die, wafer, or lot to share a key value. After the first capacitance test of the device, $key will be associated with the empty pin capacitance value C0_tmp. Therefore, the obtained global variable is C0_tmp, that is, Var1 is equal to C0_tmp. At this time, it is determined not to test the empty pin capacitance, and the value of Var1 is directly put into the empty pin array C0. There is no need to perform the wafer_down test again, thereby achieving only one measurement of the empty pin capacitance C0 of the same device in the same module across different lots / wafers / dies.
[0071] For devices under test (test objects) at the same relative position on different dies, the corresponding empty pin capacitance is basically the same. In the prior art, if there are devices under test at the same position on two dies, both need to be tested for empty pin capacitance.
[0072] The method provided by the embodiment of the present invention integrates relevant information about the device under test to form a global variable. Based on the information of the current device under test and the global variable, it is determined whether the current device under test has available free-needle capacitors. If so, the data is directly obtained to avoid repeated testing. Without repeatedly testing free-needle capacitors, data is intelligently allocated to the corresponding test object, effectively reducing the impact of parasitic capacitance, allowing for rapid and intelligent testing of capacitors, significantly improving capacitor testing efficiency, and eliminating the need for manual operation, thereby improving test efficiency.
[0073] Example 3:
[0074] Corresponding to the above method embodiment, the present invention provides a capacitance test device for a wafer, see Figure 4 The structure diagram of a wafer capacitance test device shown in FIG. 1 includes:
[0075] The test information reading module 41 is used to read the test information of the object to be tested before performing the empty needle capacitance test; generate a judgment variable based on the common information in the test information; the common information represents the same test position and test conditions relative to the same reference dimension;
[0076] The test judgment module 42 is used to determine whether there is a corresponding empty needle capacitance value based on the judgment variable; if not, an empty needle test is performed on the object to be tested according to the test information, and the empty needle capacitance value obtained by the test is associated with the judgment variable; if it exists, the existing empty needle capacitance value is automatically obtained.
[0077] An embodiment of the present invention provides a capacitance testing device for a wafer. Before performing an empty needle capacitance test, the test information of the object to be tested is read; a judgment variable is generated based on the common information in the test information; the common information represents the same test position and test conditions relative to the same reference dimension; based on the judgment variable, it is determined whether a corresponding empty needle capacitance value exists; if not, an empty needle test is performed on the object to be tested according to the test information, and the empty needle capacitance value obtained by the test is associated with the judgment variable; if it exists, the existing empty needle capacitance value is automatically obtained. By using the test information such as the test object and the test parameters as common information, and determining whether an empty needle capacitance exists based on the judgment of the global variable, it is possible to avoid repeated testing of the empty needle capacitance, thereby increasing production capacity and improving production efficiency; at the same time, the number of needle lifts / needle insertions is greatly reduced, the life of the needle card is increased, and costs are reduced.
[0078] The above-mentioned test information includes test object information and test parameters. The above-mentioned test information reading module is used to obtain the test mode selected by the user and determine the data dimensions required for the common information based on the test mode; select the required test object information based on the data dimensions required for the common information, and together with the common information in the test parameters, form a judgment variable.
[0079] The above test modes include testing one batch once, testing one wafer once, and testing one bare die once. The data dimensions are correspondingly set with batch dimension, wafer dimension, and bare die dimension. According to the data dimensions, the required test object information is determined to be composed of at least one of the batch ID, wafer ID, and bare die ID.
[0080] The above-mentioned test information reading module is used to determine that the test object information includes: batch ID, wafer ID and bare die ID if the mode selected by the user corresponds to the die dimension; if the mode selected by the user corresponds to the wafer dimension, the test object information includes: batch ID and wafer ID; if the mode selected by the user corresponds to the batch dimension, the test object information includes: batch ID.
[0081] The test parameters include the position information of the object to be tested in the die and the test conditions of the object to be tested.
[0082] The above-mentioned test judgment module is used to set the judgment variable as key, set the return instruction ($) to obtain the variable output quantity, and the return instruction ($) obtains the quantitative output as empty; based on the judgment variable, obtain the global variable of $$key; when $$key is an empty value, the global variable is the target value; when $$key is a quantity, the global variable is the value of the variable $key; based on the value of the global variable, determine whether to test the empty needle capacitance; when testing the empty needle capacitance, set $key to a variable whose value is equal to the empty needle capacitance value obtained by the current test.
[0083] The above-mentioned target value is greater than the preset threshold; the above-mentioned test judgment module is used to determine to test the empty needle capacitance if the value of the global variable is greater than the threshold; if the value of the global variable is less than or equal to the threshold, determine not to test the empty needle capacitance.
[0084] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the wafer capacitance testing device described above can refer to the corresponding process in the aforementioned embodiment of the wafer capacitance testing method, and will not be repeated here.
[0085] Example 4:
[0086] The embodiment of the present invention further provides an electronic device for running the above-mentioned wafer capacitance testing method; see Figure 5 A structural diagram of an electronic device is shown, which includes a memory 100 and a processor 101, wherein the memory 100 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor 101 to implement the above-mentioned wafer capacitance testing method.
[0087] Furthermore, Figure 5 The electronic device shown further includes a bus 102 and a communication interface 103 , and the processor 101 , the communication interface 103 and the memory 100 are connected via the bus 102 .
[0088] The memory 100 may include a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk storage. The communication connection between the system network element and at least one other network element is achieved through at least one communication interface 103 (which may be wired or wireless), and the Internet, wide area network, local area network, metropolitan area network, etc. may be used. The bus 102 may be an ISA bus, a PCI bus, or an EISA bus. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 5 Only one bidirectional arrow is used in the diagram, but this does not mean that there is only one bus or one type of bus.
[0089] The processor 101 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor 101 or software instructions. The above processor 101 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in conjunction with the embodiments of the present invention can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as a random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or register. The storage medium is located in the memory 100, and the processor 101 reads the information in the memory 100 and, in conjunction with its hardware, completes the steps of the method of the aforementioned embodiment.
[0090] An embodiment of the present invention also provides a computer-readable storage medium, which stores computer-executable instructions. When the computer-executable instructions are called and executed by a processor, the computer-executable instructions prompt the processor to implement the above-mentioned wafer capacitance testing method. The specific implementation can be found in the method embodiment and will not be repeated here.
[0091] The computer program product of the wafer capacitance testing method, device and electronic device provided in the embodiments of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method in the previous method embodiment. The specific implementation can be referred to the method embodiment and will not be repeated here.
[0092] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working process of the system and / or device described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.
[0093] In addition, in the description of the embodiments of the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.
[0094] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, and other media that can store program code.
[0095] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0096] Finally, it should be noted that the above embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.
Claims
1. A method for testing the capacitance of a wafer, characterized in that: The method comprises: Before performing the empty needle capacitance test, the test information of the object to be tested is read; a judgment variable is generated based on the common information in the test information; the common information is determined according to the test requirements and / or the test software and hardware implementation conditions; Based on the judgment variable, determine whether there is a corresponding empty needle capacitance value; if not, perform an empty needle test on the object to be tested according to the test information, and associate the empty needle capacitance value obtained by the test with the judgment variable; if it exists, automatically obtain the existing empty needle capacitance value.
2. The method according to claim 1, characterized in that The test information includes test object information and test parameters, and generating a judgment variable based on common information in the test information includes: Obtaining a test mode selected by a user, and determining data dimensions required for the common information according to the test mode; The required test object information is selected according to the data dimensions required by the common information, and is combined with the common information in the test parameters to form a judgment variable.
3. The method according to claim 2, characterized in that The test mode includes testing one batch once, testing one wafer once, and testing one die once. The data dimensions are correspondingly provided with batch dimension, wafer dimension, and die dimension. The required test object information is determined based on the data dimension and is composed of at least one of the batch ID, wafer ID, and die ID.
4. The method according to claim 3, characterized in that The step of determining the required test object information composed of at least one of a batch ID, a wafer ID, and a die ID according to the data dimension includes: If the mode selected by the user corresponds to the die dimension, determining that the test object information includes: batch ID, wafer ID and die ID; If the mode selected by the user corresponds to wafer dimensions, determining that the test object information includes: batch ID and wafer ID; If the mode selected by the user corresponds to the batch dimension, it is determined that the test object information includes: batch ID.
5. The method according to claim 3, characterized in that The test parameters include position information of the object to be tested in the die and test conditions of the object to be tested.
6. The method according to claim 1, characterized in that The common information representation represents the same test position and test conditions relative to the same reference dimension.
7. The method according to claim 1, characterized in that The determining whether there is a corresponding empty needle capacitance value based on the judgment variable includes: Set the judgment variable to key, set the return instruction ($) to obtain the variable output quantity, and the return instruction ($) obtains the quantitative output as empty; Based on the judgment variable, obtain the global variable of $$key; when $$key is empty, the global variable is the target value; when $$key is a fixed value, the global variable is the value of the variable $key; Whether to test the empty pin capacitance is determined based on the value of the global variable; when the empty pin capacitance is tested, $key is set to a variable with a value equal to the empty pin capacitance value obtained by the current test.
8. The method according to claim 7, characterized in that The target value is greater than a preset threshold; and determining whether to test the empty needle capacitance based on the value of the global variable includes: If the value of the global variable is greater than the threshold, determining to test the empty needle capacitance; If the value of the global variable is less than or equal to the threshold, it is determined not to test the empty pin capacitance.
9. A method for testing capacitance of a wafer, characterized in that: The method comprises: Before performing the empty needle capacitance test, reading the test information of the object to be tested; the test information includes test object information and test parameters, and the test object information includes a batch ID and a wafer ID; generating a judgment variable based on the common information in the test information; Based on the judgment variable, determine whether there is a corresponding empty needle capacitance value; if not, perform an empty needle test on the object to be tested according to the test information, and associate the empty needle capacitance value obtained by the test with the judgment variable; if it exists, automatically obtain the existing empty needle capacitance value.
10. The method according to claim 9, characterized in that The test parameters include position information of the object to be tested in the die and test conditions of the object to be tested.
11. The method according to claim 9, characterized in that The common information representation represents the same test position and test conditions relative to the same reference dimension.
12. The method according to claim 9, characterized in that The determining whether there is a corresponding empty needle capacitance value based on the judgment variable includes: Set the judgment variable to key, set the return instruction ($) to obtain the variable output quantity, and the return instruction ($) obtains the quantitative output as empty; Based on the judgment variable, obtain the global variable of $$key; when $$key is empty, the global variable is the target value; when $$key is a fixed value, the global variable is the value of the variable $key; Whether to test the empty pin capacitance is determined based on the value of the global variable; when the empty pin capacitance is tested, $key is set to a variable with a value equal to the empty pin capacitance value obtained by the current test.
13. A method for testing capacitance of a wafer, characterized in that: The method comprises: Before performing the empty needle capacitance test, reading the test information of the object to be tested; the test information includes test object information and test parameters, and the test object information includes a batch ID; generating a judgment variable based on the common information in the test information; Based on the judgment variable, determine whether there is a corresponding empty needle capacitance value; if not, perform an empty needle test on the object to be tested according to the test information, and associate the empty needle capacitance value obtained by the test with the judgment variable; if it exists, automatically obtain the existing empty needle capacitance value.
14. The method according to claim 13, characterized in that The test parameters include position information of the object to be tested in the die and test conditions of the object to be tested.
15. The method according to claim 13, characterized in that The common information representation represents the same test position and test conditions relative to the same reference dimension.
16. The method according to claim 13, characterized in that The determining whether there is a corresponding empty needle capacitance value based on the judgment variable includes: Set the judgment variable to key, set the return instruction ($) to obtain the variable output quantity, and the return instruction ($) obtains the quantitative output as empty; Based on the judgment variable, obtain the global variable of $$key; when $$key is empty, the global variable is the target value; when $$key is a fixed value, the global variable is the value of the variable $key; Whether to test the empty pin capacitance is determined based on the value of the global variable; when the empty pin capacitance is tested, $key is set to a variable with a value equal to the empty pin capacitance value obtained by the current test.
17. A wafer capacitance testing device, characterized in that: The device comprises: A test information reading module is used to read the test information of the object to be tested before performing the empty needle capacitance test; generate a judgment variable based on the common information in the test information; the common information is determined according to the test requirements and / or the test software and hardware implementation conditions; The test judgment module is used to determine whether there is a corresponding empty needle capacitance value based on the judgment variable; if not, an empty needle test is performed on the object to be tested according to the test information, and the empty needle capacitance value obtained by the test is associated with the judgment variable; if it exists, the existing empty needle capacitance value is automatically obtained.
18. An electronic device, characterized in that: The method comprises a processor and a memory, wherein the memory stores computer-executable instructions that can be executed by the processor, and the processor executes the computer-executable instructions to implement the wafer capacitance testing method according to any one of claims 1 to 8.