Design method for SerDes core granulation

Abstract

The invention relates to the technical field of integrated circuit design and communication, in particular to a SerDes core grain design method, which comprises the following steps: designing interfaces of SerDes core grains, including a high-speed serial interface, a parallel interface and a configuration interface; high-speed data transmission with an external device or equipment is realized through the high-speed serial interface; butt joint of the SerDes core particles and chip / system internal core particles is realized through the parallel interface; dynamically adjusting parameters of the SerDes core particles through the configuration interface; a SerDes core particle is designed, and the SerDes core particle comprises a physical medium adaptation layer (PMA), a control unit and a clock module. A configurable parallel interface, clock data synchronous transmission and a modular architecture are adopted, the communication efficiency and flexibility between chips and systems are improved, the development period is shortened, and the cost is reduced.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit design and communication technology, and in particular to a SerDes (Serializer / Deserializer) core granularization design method. Background Art

[0002] As Moore's Law and Dennard scaling gradually become obsolete, the single-chip performance gains achieved through process advancements are gradually diminishing. Chiplet technology, based on core particle assembly technology, has gradually become a research hotspot in the integrated circuit field. Chiplet technology offers many benefits, including the following:

[0003] 1. Improved manufacturing yield: Compared to monolithic chips, chiplets are smaller. Splitting a large chip into multiple smaller cores, each manufactured independently, allows for better control of the manufacturing process, reduces the likelihood of defects during production, and thus improves the overall chip yield. Although this may increase area and cost, multi-chip design can effectively reduce production costs and improve production efficiency by significantly improving yield, reducing single-chip complexity, and increasing design flexibility.

[0004] 2. Reduce chip costs: Different chiplets can use the manufacturing process that best suits their functions. For example, mature IP modules can be manufactured using a mature process, while key performance modules can be manufactured using a more advanced process. This hybrid process can reduce the overall cost of the chip. Furthermore, the chiplet design allows manufacturers to reduce the unit cost of each chiplet through mass production.

[0005] 3. High design flexibility: Chiplet design allows for rapid implementation of diverse functions by combining different modules, significantly improving design flexibility and product scalability. Designers can optimize and iterate specific modules for specific needs without affecting other modules, enabling the chip to better meet diverse market demands. The same chiplet can be used in many different devices, improving the reusability of intellectual property cores, reducing design costs, and minimizing resource waste.

[0006] 4. Accelerate time to market: Since chiplets can be designed and manufactured independently, a more modular IC design approach can be adopted, and work can be carried out in parallel, thereby speeding up the development process and accelerating the time to market for new products.

[0007] 5. Heterogeneous Integration: In traditional chip design, integrating different functional modules often encounters complex manufacturing and technical challenges. However, chiplet technology can make heterogeneous integration easier through standardized interfaces and protocols. Different vendors can provide chiplets with various functions. This diverse selection allows designers to easily integrate multiple technologies according to their needs.

[0008] 6. Improved performance and energy efficiency: The modular design of chiplets allows for more flexible thermal management. Through proper layout and heat dissipation design, power consumption can be effectively reduced at the system level. Furthermore, by assigning functions to different chiplets, higher performance and energy efficiency can be achieved for specific applications. For example, NVIDIA's newly released DGX B200 is a product of chiplet technology. Leveraging the computing advancements of the NVIDIA Blackwell architecture, the DGX B200 boasts three times the training performance of the DGX H100 and 15 times the inference performance.

[0009] 7. Promote industrial cooperation and innovation: Different chip modules can be developed and produced by different manufacturers, which strengthens cooperative relationships, promotes cross-integration of technologies, accelerates the pace of innovation, and brings more diverse product choices to the market.

[0010] Chiplet technology further expands the physical size of chips and innovates in process integration. However, it targets the package-level ecosystem and supports a limited scale of chiplet integration. Therefore, Chinese scientists have proposed the Software-Defined System on Wafer (SDSoW) from a systems engineering perspective. This concept replaces general-purpose computing architectures with domain-specific hardware-software collaborative computing structures, achieving orders of magnitude improvements in performance and efficiency. By assembling dielets through hot-pressed bonding, instead of reusing chip designs based on the same process IP, and then integrating them step-by-step through PCB stacking, it achieves orders of magnitude improvements in bandwidth, latency, energy efficiency, and volume, thereby driving a generational leap in the performance and physical form of high-performance computing systems. The Software-Defined System on Wafer (SDSoW) integrates architectural and integrated process innovations, focusing on the design of the underlying interconnect network architecture and on unified interconnect interfaces for heterogeneous dielets. It is a key development direction for integrated circuits and various cyber-physical systems in the post-Moore era. Both chiplets and SDSoW are based on dielets.

[0011] With the advancement of electronic technology, high-speed serial interfaces have become mainstream. SerDes, as a high-speed serial communication technology, can convert multiple low-speed parallel signals into high-speed serial signals for transmission, meeting the requirements of high-bandwidth, low-latency data transmission between chips. Currently, SerDes is typically integrated into chips / chiplets. After adopting a chiplet-based design, SerDes can be designed, verified, and integrated as an independent chiplet. This allows, when designing complex chip systems, to change or upgrade the functionality of the SerDes portion, only the SerDes chiplet needs to be modified without affecting the design of other components, thus increasing design flexibility. It also facilitates the flexible selection and combination of SerDes chiplets with different performance characteristics according to different application requirements, achieving scalability of chip systems. However, in the face of the rise of heterogeneous integration and multi-chiplet packaging technologies, there is no existing chiplet-based approach for SerDes. Summary of the Invention

[0012] The present invention aims to solve the problem of lack of SerDes core-granularization method in the existing technology, and proposes a SerDes core-granularization design method. By rationally designing interfaces and structures, efficient data transmission and flexible configuration in different communication scenarios are achieved. The method is particularly suitable for multi-core integration applications such as System on Wafer (SoW), and effectively improves the communication efficiency and flexibility between chips / systems (such as SoW).

[0013] In order to achieve the above purpose, the technical solutions adopted are:

[0014] The present invention provides a SerDes core-granular design method, comprising the following steps:

[0015] Designing interfaces for the SerDes coreparticle, including a high-speed serial interface, a parallel interface, and a configuration interface; enabling high-speed data transmission with external devices or equipment through the high-speed serial interface; enabling docking of the SerDes coreparticle with coreparticles within the chip / system through the parallel interface; and dynamically adjusting parameters of the SerDes coreparticle through the configuration interface.

[0016] A SerDes core particle is designed, wherein the SerDes core particle includes a physical medium adaptation layer (PMA), a control unit, and a clock module.

[0017] According to the SerDes core-granular design method of the present invention, further, the high-speed serial interface supports at least one of Ethernet, RapidIO, and PCIe protocols.

[0018] According to the SerDes core-based design method of the present invention, further, the parallel interface is a parallel interface between the PCS and the PMA, and the parallel interface is used to transmit data signals, clock signals and control signals.

[0019] According to the SerDes core-granular design method of the present invention, further, the data signal includes a data signal TxData and a valid indication signal TxData Valid in the sending direction, a data signal RxData, a valid indication signal RxData Valid and an error indication signal RxError in the receiving direction; the clock signal includes a sending direction clock TxClk and a receiving direction clock RxClk; the control signal includes TxEnable, RxReady, HardReset, TxReset, RxReset, SignalDetect and Loss of Lock.

[0020] According to the SerDes core-granular design method of the present invention, further, the configuration interface includes an IIC interface and a JTAG interface.

[0021] According to the SerDes core design method of the present invention, further, the control unit is used to coordinate and manage the working status of the SerDes core, including loopback mode control, PRBS generation and detection, electrical parameter adjustment, forward error correction control, parallel interface data bit width configuration and data transmission rate control.

[0022] According to the SerDes core design method of the present invention, further, the clock module is used to generate the clock signal required by the SerDes core and manage the phase relationship between the clocks.

[0023] According to the SerDes core-based design method of the present invention, further, the SerDes core is connected to an endpoint device or a switching chip as an independent core, the endpoint device is a processor or a DSP, and the switching chip is used to realize data exchange between multiple cores.

[0024] According to the SerDes core-based design method of the present invention, further, the endpoint device or the switch chip is connected to the SerDes core via a parallel interface to achieve high-speed data transmission.

[0025] The beneficial effects achieved by adopting the above technical solution are:

[0026] The present invention achieves the following effects by designing the three interfaces of the SerDes core (high-speed serial interface, parallel interface and configuration interface) and the physical medium adaptation layer (PMA), control unit and clock module.

[0027] 1. Flexible interface configuration: The high-speed serial interface supports multiple high-speed transmission protocols to achieve high-speed data transmission with external devices; the parallel interface data bus width and operating clock frequency can be selected by software to adapt to different application requirements; the configuration interface allows dynamic adjustment of parameters to improve system adaptability.

[0028] 2. Efficient structural collaboration: The PMA implements signal conversion and physical layer functions to ensure internal and external communication compatibility; the control unit coordinates functions such as loopback mode and forward error correction to ensure the coordinated operation of various modules; the clock module manages the clock phase relationship to ensure data transmission stability.

[0029] 3. Development efficiency and cost optimization: SerDes core particles are independently designed, verified and integrated, and modifications do not affect other modules, shortening the development cycle. Different performance core particles can be flexibly selected and combined (different performance core particles refer to SerDes core particles with different transmission protocol support capabilities, data bus bit widths, operating clock frequencies or electrical parameter configurations), reducing repeated design and lowering development costs.

[0030] 4. Improved inter-chip / system communication efficiency is reflected in the following aspects: ① Serial interfaces supporting high-speed transmission protocols such as Ethernet, RapidIO, and PCIe enable high-bandwidth, low-latency data transmission between the chip / system and external devices, meeting high-speed communication requirements. ② The parallel interface between the PCS and PMA utilizes a configurable data bus width (e.g., 64-bit, 128-bit) and a synchronous clock to increase data throughput per unit time between chiplets and internal chiplets, significantly improving efficiency compared to serial transmission. ③ The PMA integrates a serializer, deserializer, clock data recovery (CDR), and equalizer to compensate for signal transmission losses, ensuring signal accuracy and stability over long-distance communications and reducing retransmissions or delays caused by signal distortion. ④ The control unit coordinates functions such as loopback mode and forward error correction (FEC), dynamically adjusting parameters in conjunction with the configuration interface (IIC / JTAG) to optimize communication link quality in real time and avoid efficiency bottlenecks associated with fixed configurations. ⑤ The clock module generates precise clocks and manages phase relationships, and cooperates with elastic buffers to solve the problem of data alignment across clock domains, ensuring the timing consistency of high-speed parallel data transmission and reducing communication delays caused by clock deviation. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings of the embodiments of the present invention. The drawings are only used to illustrate some embodiments of the present invention, but not to limit all embodiments of the present invention thereto.

[0032] Figure 1 1 is a diagram showing the overall architecture of a SerDes core particle according to an embodiment of the present invention;

[0033] Figure 2is a block diagram of the PMA structure of an embodiment of the present invention;

[0034] Figure 3 1 is a schematic diagram of the structure of an endpoint device with a SerDes core according to an embodiment of the present invention;

[0035] Figure 4 FIG. 1 is a schematic diagram of the structure of a switching chip with a SerDes core particle according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following will be combined with the accompanying drawings of specific embodiments of the present invention to clearly and completely describe the exemplary embodiments of the present invention. Unless otherwise defined, technical or scientific terms used in the present invention should be given the common meanings understood by people with ordinary skills in the relevant field.

[0037] like Figure 1 As shown, this embodiment discloses a SerDes core-division design method, including the following steps:

[0038] Step S101 : Design the interface of the SerDes core particle, including a high-speed serial interface (Serial Interface) for communicating with the outside of the chip / system, a parallel interface (Parallel Interface) for communicating with the core particles inside the chip / system, and a configuration interface (Configuration Interface) for configuring parameters.

[0039] The serial interface supports high-speed transmission protocols such as Ethernet, RapidIO, and PCIe, enabling high-speed data transmission with external devices or equipment.

[0040] The parallel interface is a parallel interface between the PCS and the PMA, which is used to achieve the connection between the SerDes core and the core inside the chip / system. The data bus width and operating clock frequency can be selected by software based on application requirements, and the operating clock is parallel to the data.

[0041] The configuration interface includes the IIC interface and the JTAG interface, allowing the user or the system to dynamically adjust the parameters of the SerDes core according to needs.

[0042] Step S102 : Designing a SerDes core particle. The SerDes core particle includes a physical medium attachment (PMA), a control unit, and a clock module.

[0043] Figure 2This is the structural diagram of the PMA. The PMA uses a parallel interface to connect to the PCS of the chip / system's internal core particles, and connects to external devices or equipment through a high-speed serial interface to provide the necessary signal conversion and physical layer functions to ensure compatibility with external systems.

[0044] The control unit is used to coordinate and manage the working status of the SerDes core particles, including loopback mode control, PRBS generation and detection, electrical parameter adjustment, forward error correction control, parallel interface data width configuration and data transmission rate control, etc., to ensure that the various parts of the SerDes core particles work together to achieve efficient data transmission and configuration management.

[0045] The clock module is responsible for generating the clock signals required by each module of the SerDes core and managing the phase relationship between these clocks.

[0046] The parallel interface between the PCS and PMA is used to transmit data signals, clock signals, and control signals. The details of each signal are shown in Table 1.

[0047] Table 1 Parallel interface signals between PCS and PMA

[0048]

[0049]

[0050] An application example is given below to facilitate a better understanding of the present invention.

[0051] In traditional integrated circuit design, endpoint devices (such as processors and DSPs) and switch chips typically integrate serializers / deserializers (SerDes) with digital logic on the same chip or die. While this integration approach simplifies system design to a certain extent, its limitations are becoming increasingly apparent as technology evolves and application requirements diversify.

[0052] After the SerDes was separated from these devices and formed into independent core particles, the structure of endpoint devices and switch chips changed significantly, such as Figure 3 and Figure 4 As shown, this will significantly improve the flexibility and scalability of the system.

[0053] Unless otherwise specifically stated, the relative steps, numerical expressions and values ​​of the components and steps set forth in these embodiments do not limit the scope of the present invention.

[0054] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Reference can be made to the common and similar parts between the various embodiments. For the systems disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method description.

[0055] The units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of function in the above description. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person of ordinary skill in the art may use different methods to implement the described functions for each specific application, but such implementation is not considered to be beyond the scope of the present invention.

[0056] Those skilled in the art will appreciate that all or part of the steps in the above method can be performed by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disk. Alternatively, all or part of the steps in the above embodiment can be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or software functional modules. The present invention is not limited to any specific combination of hardware and software.

[0057] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the above-described embodiments, those skilled in the art should understand that any person skilled in the art can modify or easily conceive of changes to the technical solutions described in the above-described embodiments within the technical scope disclosed by the present invention, or replace some of the technical features therein with equivalents. Such modifications, changes, or replacements do not deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A SerDes core-division design method, characterized in that: The following steps are involved: Designing interfaces for the SerDes coreparticle, including a high-speed serial interface, a parallel interface, and a configuration interface; enabling high-speed data transmission with external devices or equipment through the high-speed serial interface; enabling docking of the SerDes coreparticle with coreparticles within the chip / system through the parallel interface; and dynamically adjusting parameters of the SerDes coreparticle through the configuration interface. A SerDes core particle is designed, wherein the SerDes core particle includes a physical medium adaptation layer (PMA), a control unit, and a clock module.

2. The SerDes core-based design method according to claim 1, wherein: The high-speed serial interface supports at least one of Ethernet, RapidIO, and PCIe protocols.

3. The SerDes core-based design method according to claim 1, wherein: The parallel interface is a parallel interface between the PCS and the PMA, and is used to transmit data signals, clock signals, and control signals.

4. The SerDes core-based design method according to claim 3, wherein: The data signal includes the data signal TxData and the valid indication signal TxData Valid in the sending direction, the data signal RxData, the valid indication signal RxData Valid and the error indication signal RxError in the receiving direction; the clock signal includes the sending direction clock TxClk and the receiving direction clock RxClk; the control signals include TxEnable, RxReady, HardReset, TxReset, RxReset, Signal Detect and Loss of Lock.

5. The SerDes core-based design method according to claim 1, wherein: The configuration interface includes an IIC interface and a JTAG interface.

6. The SerDes core-based design method according to claim 1, wherein: The control unit is used to coordinate and manage the working status of the SerDes core particle, including loopback mode control, PRBS generation and detection, electrical parameter adjustment, forward error correction control, parallel interface data bit width configuration and data transmission rate control.

7. The SerDes core-based design method according to claim 1, wherein: The clock module is used to generate the clock signal required by the SerDes core and manage the phase relationship between clocks.

8. The SerDes core-based design method according to claim 1, wherein: The SerDes core is connected to an endpoint device or a switching chip as an independent core. The endpoint device is a processor or a DSP. The switching chip is used to implement data exchange between multiple cores.

9. The SerDes core-based design method according to claim 8, characterized in that: The endpoint device or switch chip is connected to the SerDes core particle through a parallel interface to achieve high-speed data transmission.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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