Pixel, and display device and electronic device including same

Abstract

The invention relates to a pixel and a display device and an electronic device including the same. The pixel includes: a first transistor including a first electrode connected to a first power line, a first gate electrode connected to a first node, and a second electrode connected to a second node; a second transistor connected between the data line and the first node, and including a gate electrode connected to the first scan line; a light emitting element including a first electrode connected to a second electrode of the first transistor and a second electrode connected to a second power line; and a first capacitor and a second capacitor connected in series between the first node and the first electrode of the light emitting element.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0032949 filed in the Korean Intellectual Property Office on March 8, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Various embodiments of the present disclosure relate to pixels, and display devices and electronic devices including the pixels. Background Art

[0004] With the development of information technology, the importance of display devices as a medium connecting users and information has been recognized. Due to the importance of display devices, the use of various types of display devices (such as liquid crystal display devices and organic light emitting display devices) has increased.

[0005] A display device can use pixels to display an image. Each pixel can store the voltage of a data signal and generate light at a specific brightness based on the amount of current flowing from a first drive power to a second drive power through a light-emitting element. Here, if a data signal of a desired voltage is not stored in each pixel due to a change in the voltage of the first drive power, an image of desired brightness may not be displayed. Summary of the Invention

[0006] Various embodiments of the present disclosure relate to a pixel capable of displaying an image with desired brightness regardless of a change in voltage of a first driving power, and a display device and an electronic device including the pixel.

[0007] According to an embodiment of the present disclosure, a pixel may include: a first transistor including a first electrode connected to a first power line, a first gate electrode connected to a first node, and a second electrode connected to a second node; a second transistor connected between a data line and the first node and including a gate electrode connected to a first scan line; a light-emitting element including a first electrode connected to the second electrode of the first transistor and a second electrode connected to the second power line; and a first capacitor and a second capacitor connected in series between the first node and the first electrode of the light-emitting element.

[0008] In an implementation, the first transistor may further include a second gate electrode, and the second gate electrode may be connected to the second node.

[0009] In an embodiment, the pixel may further include: a third transistor connected between the third power line and the first node and including a gate electrode connected to the second scan line; and a fourth transistor connected between the first electrode of the light emitting element and the fourth power line and including a gate electrode connected to the third scan line.

[0010] In an embodiment, when the second transistor is turned on, the fourth transistor may be set to an on state.

[0011] In an embodiment, when the second transistor is turned on, the fourth transistor may be set to an off state.

[0012] In an embodiment, the on-period of the third transistor and the on-period of the fourth transistor may overlap during some periods, and the on-period of the second transistor and the on-period of the third transistor may not overlap.

[0013] In an embodiment, the pixel may further include: a fifth transistor connected between the first power line and the first electrode of the first transistor, and including a gate electrode connected to the first emission control line; and a sixth transistor connected between the second node and the first electrode of the light emitting element, and including a gate electrode connected to the second emission control line.

[0014] In an embodiment, the sixth transistor may have a turn-on period overlapping with the turn-on period of the third transistor during the first period, the fifth transistor may have a turn-on period overlapping with the turn-on period of the third transistor during the second period, and the first period and the second period may not overlap.

[0015] In an embodiment, the fourth transistor may be set to an on state during the first period and the second period.

[0016] According to an embodiment of the present disclosure, a display device may include: a pixel assembly including pixels connected to a scan line, an emission control line, and a data line; a scan driver driving the scan line; a data driver driving the data line; and an emission driver driving the emission control line. One of the pixels connected to the i-th horizontal line and the j-th data line (where i and j can each be a positive integer) may include: a first transistor including a first electrode connected to a first power line, a first gate electrode connected to a first node, and a second electrode and a second gate electrode connected to a second node; a second transistor connected between the data line and the first node and turned on when a first enable scan signal is provided to the first scan line of the i-th scan line; a light-emitting element including a first electrode connected to the second electrode of the first transistor and a second electrode connected to the second power line; and a first capacitor and a second capacitor connected in series between the first node and the first electrode of the light-emitting element.

[0017] In an embodiment, one of the pixels may further include: a third transistor, connected between the third power line and the first node, and turned on when the second enable scan signal is provided to the second scan line of the i-th scan line; and a fourth transistor, connected between the first electrode of the light emitting element and the fourth power line, and turned on when the third enable scan signal is provided to the third scan line of the i-th scan line.

[0018] In an embodiment, one of the pixels may further include: a fifth transistor, connected between the first power line and the first electrode of the first transistor, and turned off when a first emission disable control signal is provided to the first emission control line of the i-th emission control line; and a sixth transistor, connected between the second node and the first electrode of the light emitting element, and turned off when a second emission disable control signal is provided to the second emission control line of the i-th emission control line.

[0019] In an embodiment, one of the pixels may be driven with a first period, a second period, a third period, and a fourth period separated from each other, and the scan driver may provide a second enable scan signal and a third enable scan signal during the first period and the second period, and may provide a first enable scan signal during the third period.

[0020] In an embodiment, the scan driver may provide a third enable scan signal during a third period.

[0021] In an embodiment, the emission driver may provide a first emission disable control signal during the first period and the third period, and may provide a second emission disable control signal during the second period and the third period.

[0022] In an embodiment, the emission driver may provide a first enable emission control signal to the first emission control line to turn on the fifth transistor during the fourth period, and the emission driver may provide a second enable emission control signal to the second emission control line to turn on the sixth transistor during the fourth period.

[0023] In an embodiment, first driving power may be supplied to the first power line, second driving power having a lower voltage than the first driving power may be supplied to the second power line, a voltage of reference power may be supplied to the third power line, and a voltage of initialization power may be supplied to the fourth power line.

[0024] In an embodiment, each of the reference power and the initialization power may maintain a constant voltage.

[0025] According to an embodiment of the present disclosure, an electronic device may include: a display module including a display panel and displaying an image on the display panel; a sensing module sensing an input corresponding to the image displayed on the display module; and a processor and an auxiliary processor controlling the display module and the sensing module. At least one pixel included in the display panel may include: a first transistor including a first electrode connected to a first power line, a first gate electrode connected to a first node, and a second electrode and a second gate electrode connected to a second node; a second transistor connected between a data line and the first node and including a gate electrode connected to a first scan line; a light-emitting element including a first electrode connected to the second electrode of the first transistor and a second electrode connected to a second power line; and first and second capacitors connected in series between the first node and the first electrode of the light-emitting element.

[0026] In an embodiment, at least one pixel may further include: a third transistor connected between the third power line and the first node and including a gate electrode connected to the second scan line; a fourth transistor connected between the first electrode of the light emitting element and the fourth power line and including a gate electrode connected to the third scan line; a fifth transistor connected between the first power line and the first electrode of the first transistor and including a gate electrode connected to the first emission control line; and a sixth transistor connected between the second node and the first electrode of the light emitting element and including a gate electrode connected to the second emission control line.

[0027] The objects of the present disclosure are not limited to the above-mentioned objects, and other unmentioned objects will be clearly understood by those skilled in the art from the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 It shows Figure 1 Schematic diagram of an embodiment of a scan driver and an emission driver is shown in FIG.

[0030] Figure 3 is a schematic diagram illustrating an equivalent circuit of a pixel according to an embodiment of the present disclosure.

[0031] Figure 4 Is shown driving Figure 3 The waveforms of an embodiment of the pixel method are shown in FIG.

[0032] 5A to 5D are waveforms showing a process of operating pixels corresponding to a pixel driving method.

[0033] Figure 6 Is shown driving Figure 3The waveforms of an embodiment of the pixel method are shown in FIG.

[0034] Figure 7 is a schematic diagram illustrating an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present disclosure. The present disclosure can be implemented in various forms and is not limited to the embodiments to be described herein below.

[0036] In the accompanying drawings, in order to more clearly illustrate the present disclosure, parts that are not related to the present disclosure will be omitted. Reference should be made to the accompanying drawings, in which similar reference numerals are used to represent similar components in different drawings. Therefore, the reference numerals mentioned above can be used in other drawings.

[0037] In addition, the expression "same" may mean "substantially the same." In other words, the expression "same" may include a range that can be accepted by those skilled in the art. Other expressions may also be expressions in which the term "substantially" is omitted.

[0038] In the accompanying drawings, some embodiments are described in conjunction with functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, line connectors and other electrical circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. For blocks, units and / or modules implemented by microprocessors or other similar hardware, software can be used to program them and control them to perform the various functions discussed herein, and they can be selectively driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by dedicated hardware, or can be implemented by a combination of dedicated hardware that performs some functions and a processor that performs other functions (e.g., one or more programmed microprocessors and related circuits). In addition, in some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules can be physically separated into two or more discrete blocks, units and / or modules that interact with each other. In some embodiments, without departing from the scope of this disclosure, blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules.

[0039] When an element, such as a layer, is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there can be intervening elements or layers. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers. For this purpose, the term “connected” can refer to a physical connection, an electrical connection, and / or a fluid connection, with or without intervening elements. Furthermore, when an element is referred to as being “in contact with” or “in contact with” another element, etc., the element can be “electrically in contact with” or “physically in contact with” the other element; or “indirectly in contact with” or “directly in contact with” the other element.

[0040] It will be understood that although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, the first element discussed below may be referred to as the second element without departing from the teachings of the present disclosure.

[0041] Throughout the specification and claims, for purposes of its meaning and interpretation, the phrase "at least one of" is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B." Throughout the specification and claims, for purposes of its meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or." For example, "A and / or B" may be understood to mean "A, B, or A and B." The terms "and" and "or" may be used in conjunction or separately and may be understood to be equivalent to "and / or."

[0042] However, the present disclosure is not limited to the following embodiments and can be modified into various forms. Each embodiment to be described below can be implemented alone or combined with at least one other embodiment to make various combinations of the embodiments.

[0043] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as commonly understood by those skilled in the art to which the present disclosure belongs. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted as an ideal or overly formal meaning unless clearly defined in the specification.

[0044] Figure 1 is a schematic diagram illustrating a display device 100 according to an embodiment of the present disclosure. Figure 2 It shows Figure 1Schematic diagram of an embodiment of the scan driver 130 and the emission driver 140 is shown in FIG.

[0045] refer to Figure 1 , a display device 100 according to an embodiment of the present disclosure may include a pixel assembly 110 (or a display panel), a data driver 120 , a scan driver 130 , an emission driver 140 , a power supply 150 , and a timing controller 160 .

[0046] The pixel assembly 110 may include pixels PX connected to scan lines SL1 to SLn, data lines DL1 to DLm, emission control lines EL1 to ELn, and power lines PL1, PL2, PL3, and PL4 (where n and m may each be a natural number of 2 or greater).

[0047] Each of the scan lines SL1 to SLn may include three scan lines, such as Figure 2 As shown in . For example, the scan line SL1 may include a first scan line SL11, a second scan line SL21, and a third scan line SL31. For example, the scan line SLn may include a first scan line SL1n, a second scan line SL2n, and a third scan line SL3n.

[0048] Pixels PX can be selected on a horizontal line basis (for example, pixels PX connected to the same scan line can form a single horizontal line) when a first enabling scan signal is applied to the first scan lines SL11 to SL1n. Each of the pixels PX to which the first enabling scan signal is applied can receive a data signal from a corresponding data line (one of DL1 to DLm). Pixels PX receiving a data signal can generate light of a specific brightness corresponding to the voltage of the data signal.

[0049] The scan driver 130 may receive a scan driving signal SCS from the timing controller 160. The scan driving signal SCS may include at least one scan start signal and a clock signal for driving the scan driver 130. The scan driver 130 may generate a first enable scan signal, a second enable scan signal, and a third enable scan signal while shifting the scan start signal in response to the clock signal.

[0050] In order to achieve the above purpose, Figure 2 As shown in FIG, the scan driver 130 may include a first scan driver 132, a second scan driver 134, and a third scan driver 136. Depending on the design, at least some of the scan drivers 132, 134, and 136 may be integrated into a single driving circuit, module, etc.

[0051] The first scan driver 132 may receive the first scan start signal FLM1 and generate a first enabling scan signal while shifting the first scan start signal FLM1 in response to a clock signal. The first scan driver 132 may sequentially provide the first enabling scan signal to the first scan lines SL11 to SL1n.

[0052] The second scan driver 134 may receive the second scan start signal FLM2 and generate a second enabling scan signal while shifting the second scan start signal FLM2 in response to the clock signal. The second scan driver 134 may sequentially provide the second enabling scan signal to the second scan lines SL21 to SL2n.

[0053] The third scan driver 136 may receive the third scan start signal FLM3 and generate a third enabling scan signal while shifting the third scan start signal FLM3 in response to the clock signal. The third scan driver 136 may sequentially provide the third enabling scan signal to the third scan lines SL31 to SL3n.

[0054] The first enable scan signal, the second enable scan signal, and the third enable scan signal may be set to a gate-on voltage to allow the transistor included in the pixel PX to be turned on. Figure 3 As shown in , each of the first enabling scan signal, the second enabling scan signal, and the third enabling scan signal to be supplied to the N-type transistor may be set to a high level voltage.

[0055] The data driver 120 may receive output data Dout and a data drive signal DCS from the timing controller 160. The data drive signal DCS may include a sampling signal and / or a timing signal for driving the data driver 120. The data driver 120 may generate a data signal based on the data drive signal DCS and the output data Dout. For example, the data driver 120 may generate an analog data signal based on the grayscale value of the output data Dout. The data driver 120 may provide the data signal in units of one horizontal period.

[0056] The emission driver 140 may receive an emission driving signal ECS from the timing controller 160. The emission driving signal ECS may include an emission start signal and a clock signal for driving the emission driver 140. The emission driver 140 may generate a disable emission control signal while shifting the emission start signal in response to the clock signal.

[0057] like Figure 2As shown in FIG, each of the emission control lines EL1 to ELn may include two emission control lines. For example, the emission control line EL1 may include a first emission control line EL11 and a second emission control line EL21. For example, the emission control line ELn may include a first emission control line EL1n and a second emission control line EL2n. The emission driver 140 may generate a first emission disable control signal and a second emission disable control signal while shifting the emission start signal in response to a clock signal.

[0058] In order to achieve the above purpose, Figure 2 As shown in FIG, the transmit driver 140 may include a first transmit driver 142 and a second transmit driver 144. Depending on the design, at least some of the transmit drivers 142 and 144 may be integrated into a single driver circuit, module, or the like.

[0059] The first emission driver 142 may receive the first emission start signal EFLM1 and generate a first disabling emission control signal while shifting the first emission start signal EFLM1 in response to a clock signal. The first emission driver 142 may sequentially provide the first disabling emission control signal to the first emission control lines EL11 to EL1n.

[0060] The second emission driver 144 may receive the second emission start signal EFLM2 and generate a second disable emission control signal while shifting the second emission start signal EFLM2 in response to the clock signal. The second emission driver 144 may sequentially provide the second disable emission control signal to the second emission control lines EL21 to EL2n.

[0061] The first emission disable control signal and the second emission disable control signal may be set to a gate-off voltage to allow the transistor included in the pixel PX to be turned off. Figure 3 As shown in , each of the first emission disable control signal and the second emission disable control signal to be supplied to the N-type transistor may be set to a low level voltage.

[0062] The timing controller 160 may receive input data Din and a timing control signal TCS from the host system through an interface. For example, the timing controller 160 may receive input data Din and a timing control signal TCS from at least one of a graphics processing unit (GPU), a central processing unit (CPU), and an application processor (AP) included in the host system. The timing control signal TCS may include various signals including a clock signal.

[0063] The timing controller 160 may generate a scan driving signal SCS, a data driving signal DCS, and an emission driving signal ECS based on the timing control signal TCS. The scan driving signal SCS, the data driving signal DCS, and the emission driving signal ECS may be provided to the scan driver 130, the data driver 120, and the emission driver 140, respectively.

[0064] The timing controller 160 may rearrange the input data Din to match the specifications of the display device 100. In addition, the timing controller 160 may correct the input data Din to generate output data Dout and provide the output data Dout to the data driver 120. In an embodiment, the timing controller 160 may correct the input data Din in response to optical measurement results obtained during a manufacturing process.

[0065] The power supply 150 may generate various types of power required for driving the display apparatus 100. For example, the power supply 150 may generate a first driving power VDD, a second driving power VSS, an initialization power VINT, and a reference power VREF.

[0066] A first driving power VDD may be provided to provide a driving current to the pixel PX. A second driving power VSS may be provided to receive a driving current from the pixel PX. During a period in which the pixel PX is set to an emission state, the first driving power VDD may be set to a voltage higher than the voltage of the second driving power VSS.

[0067] Initialization power VINT can be provided to initialize the first electrode (or anode electrode) of the light-emitting element included in each of the pixels PX. For example, the initialization power VINT can maintain a constant voltage. For example, the initialization power VINT can be a voltage that turns off the light-emitting element when provided to the anode electrode of the light-emitting element. The reference power VREF can be provided to the gate electrode of the driving transistor included in each of the pixels PX. For example, the reference power VREF can maintain a constant voltage. For example, the reference power VREF can be a specific voltage within the voltage range of the data signal. For example, the reference power VREF can be a voltage lower than the data signal.

[0068] The first driving power VDD generated by the power supply 150 can be supplied to the first power line PL1, the second driving power VSS can be supplied to the second power line PL2, the initialization power VINT can be supplied to the third power line PL3, and the reference power VREF can be supplied to the fourth power line PL4. The first power line PL1, the second power line PL2, the third power line PL3, and the fourth power line PL4 can be commonly connected to the pixel PX, but the embodiments of the present disclosure are not limited thereto.

[0069] In an embodiment, the first power line PL1 may be composed of multiple power lines. This power line may be connected to different pixels PX. In an embodiment, the second power line PL2 may be composed of multiple power lines. This power line may be connected to different pixels PX. In an embodiment, the third power line PL3 may be composed of multiple power lines. This power line may be connected to different pixels PX. In an embodiment, the fourth power line PL4 may be composed of multiple power lines. This power line may be connected to different pixels PX.

[0070] In an embodiment of the present disclosure, the display device 100 may be a flat display device, a curved display device in which a portion of the pixel component 110 is curved, a flexible display device in which a portion can be folded or bent, or a stretchable display device in which a portion can be stretched.

[0071] In an embodiment of the present disclosure, the display device 100 may be a device configured to display video or still images, and may be included in portable electronic devices such as mobile phones, smart phones, tablet personal computers (tablet PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). In an embodiment of the present disclosure, the display device 100 may be included in electronic devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices.

[0072] Figure 3 is a schematic diagram illustrating an equivalent circuit of a pixel PXij according to an embodiment of the present disclosure. Figure 3 Pixels PXij positioned on an i-th horizontal line and a j-th vertical line are schematically shown.

[0073] refer to Figure 3 , a pixel PXij according to an embodiment of the present disclosure can be connected to corresponding signal lines SLi, DLj, and ELi. For example, a pixel PXij can be connected to the i-th scan line SLi, the i-th emission control line ELi, and the j-th data line DLj (wherein i can be a positive integer of n or less, and j is a positive integer of m or less). The i-th scan line SLi can include a plurality of scan lines SL1i, SL2i, and SL3i. The i-th emission control line ELi can include a plurality of emission control lines EL1i and EL2i. The pixel PXij can also be connected to power lines PL1 to PL4.

[0074] The pixel PXij according to an embodiment of the present disclosure may include a light emitting element LD and a pixel circuit configured to control the amount of current to be supplied to the light emitting element LD.

[0075] The light-emitting element LD may be connected between the first power line PL1 and the second power line PL2. For example, the first electrode (e.g., the anode electrode) of the light-emitting element LD may be connected to the first power line PL1 via the sixth transistor T6, the second node N2, the first transistor T1, and the fifth transistor T5. The second electrode (e.g., the cathode electrode) of the light-emitting element LD may be connected to the second power line PL2. The light-emitting element LD may generate light having a brightness corresponding to the amount of current supplied from the pixel circuit.

[0076] An organic light emitting diode may be selected as the light emitting element LD. In addition, an inorganic light emitting diode such as a micro light emitting diode (LED) or a quantum dot light emitting diode may be selected as the light emitting element LD. The light emitting element LD may be an element formed by a combination of an organic material and an inorganic material. Although Figure 3 The pixel PXij is shown to include a single light emitting element LD, but the present disclosure is not limited thereto, and the pixel PXij in the embodiment may include a plurality of light emitting elements LD. The light emitting elements LD may be connected to each other in series, in parallel, or in series-parallel.

[0077] The pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a first capacitor Cst, and a second capacitor Chold. In an embodiment, each of the first to sixth transistors T1 to T6 may be an oxide semiconductor transistor. For example, each of the first to sixth transistors T1 to T6 may include an active layer (or semiconductor layer) including an oxide semiconductor layer. In an embodiment, each of the first to sixth transistors T1 to T6 may be an N-type oxide semiconductor transistor.

[0078] A first electrode of the first transistor T1 (or driving transistor) may be connected to a second electrode of the fifth transistor T5. A second electrode of the first transistor T1 may be connected to a second node N2. A first gate electrode of the first transistor T1 may be connected to the first node N1. A second gate electrode (or back gate electrode) of the first transistor T1 may be connected to the second node N2. The first transistor T1 may control the amount of current to be supplied from the first driving power VDD to the second driving power VSS via the light emitting element LD in response to the voltage of the first node N1.

[0079] The first transistor T1 may be formed of a double-gate transistor including a first gate electrode and a second gate electrode. When the second gate electrode is connected to the second node N2, the gate-source voltage and the driving current of the first transistor T1 may be stably maintained.

[0080] The second transistor T2 may be connected between the j-th data line DLj and the first node N1. A gate electrode of the second transistor T2 may be connected to the first scan line SL1i. When a first enable scan signal GW (or a first high-level scan signal GW) is supplied to the first scan line SL1i, the second transistor T2 may be turned on to electrically connect the j-th data line DLj to the first node N1.

[0081] The third transistor T3 may be connected between the third power line PL3 and the first node N1. A gate electrode of the third transistor T3 may be connected to the second scan line SL2i. When the second enable scan signal GR (or the second high-level scan signal GR) is supplied to the second scan line SL2i, the third transistor T3 may be turned on to electrically connect the third power line PL3 to the first node N1. When the third power line PL3 and the first node N1 are electrically connected to each other, the voltage of the reference power VREF may be supplied to the first node N1.

[0082] The fourth transistor T4 may be connected between the first electrode of the light-emitting element LD and the fourth power line PL4. The gate electrode of the fourth transistor T4 may be connected to the third scan line SL3i. When the third enable scan signal GI (or the third high-level scan signal GI) is supplied to the third scan line SL3i, the fourth transistor T4 may be turned on to electrically connect the fourth power line PL4 to the first electrode of the light-emitting element LD.

[0083] When the fourth power line PL4 and the first electrode of the light-emitting element LD are electrically connected to each other, the voltage of the initialization power VINT can be provided from the fourth power line PL4 to the first electrode of the light-emitting element LD, and the parasitic capacitor Cp formed equivalent to the light-emitting element LD can be discharged, thereby enhancing the black rendering performance.

[0084] The fifth transistor T5 may be connected between the first power line PL1 and the first electrode of the first transistor T1. The gate electrode of the fifth transistor T5 may be connected to the first emission control line EL1i. The fifth transistor T5 may be turned off when a first disable emission control signal (or a low-level first emission control signal EM1) is supplied to the gate electrode of the fifth transistor T5, and may be turned on when a first enable emission control signal (or a high-level first emission control signal EM1) is supplied to the gate electrode of the fifth transistor T5. When the fifth transistor T5 is turned on, a current path along which a drive current can flow in the pixel PXij may be formed.

[0085] The sixth transistor T6 may be connected between the second node N2 and the first electrode of the light-emitting element LD. The second node N2 may be a node electrically connected to the second electrode of the first transistor T1 and the first electrode of the sixth transistor T6. The gate electrode of the sixth transistor T6 may be connected to the second emission control line EL2i. The sixth transistor T6 may be turned off when the second emission disable control signal (or the low-level second emission control signal EM2) is supplied to the gate electrode of the sixth transistor T6, and may be turned on when the second emission enable control signal (or the high-level second emission control signal EM2) is supplied to the gate electrode of the sixth transistor T6.

[0086] When the sixth transistor T6 is turned on, the second node N2 and the first electrode of the light-emitting element LD can be electrically connected to each other. When the sixth transistor T6 is turned on, a current path along which a driving current can be supplied to the light-emitting element LD can be formed. When the sixth transistor T6 is turned off, the second node N2 and the first electrode of the light-emitting element LD can be electrically disconnected from each other, thereby interrupting the current path along which the driving current can flow to the light-emitting element LD.

[0087] The first capacitor Cst may be connected between the first node N1 and the second node N2. A voltage corresponding to the data signal may be stored in the first capacitor Cst.

[0088] The second capacitor Chold may be connected between the second node N2 and the first electrode of the light emitting element LD. The second capacitor Chold may stabilize the voltage of the second node N2.

[0089] Figure 4 Is shown driving Figure 3 The waveforms of an embodiment of the method are shown for the pixel PXij. 5A to 5D are waveforms showing a process of operating pixels corresponding to a pixel driving method.

[0090] refer to Figure 4 , the pixel PXij may be driven with a first period P1, a second period P2, a third period P3, and a fourth period P4 that are separated from each other.

[0091] The first period P1 may be a period for initializing the first capacitor Cst. The second period P2 may be a period for compensating the threshold voltage of the first transistor T1. The third period P3 may be a period in which the voltage of the data signal is stored in the pixel PXij. The fourth period P4 may be a period in which the pixel PXij (or the light emitting element LD) emits light.

[0092] refer to Figure 5ADuring the first period P1, the second enable scan signal GR may be supplied to the second scan line SL2i, and the third enable scan signal GI may be supplied to the third scan line SL3i. In addition, during the first period P1, the first disable emission control signal (or the low-level first emission control signal EM1) may be supplied to the first emission control line EL1i.

[0093] If the first emission disable control signal (or the low-level first emission control signal EM1) is supplied to the first emission control line EL1i, the fifth transistor T5 may be turned off. If the fifth transistor T5 is turned off, the electrical connection between the first power line PL1 and the first transistor T1 may be interrupted, and thus, the light emitting element LD may be set to a non-emission state.

[0094] If the second enable scan signal GR is supplied to the second scan line SL2i, the third transistor T3 is turned on. If the third transistor T3 is turned on, the voltage of the reference power VREF may be supplied to the first node N1.

[0095] If the third enable scan signal GI is supplied to the third scan line SL3i, the fourth transistor T4 may be turned on. If the fourth transistor T4 is turned on, the voltage of the initialization power VINT may be supplied to the first electrode and the second node N2 of the light emitting element LD. The first capacitor Cst may be initialized with the voltage of the reference power VREF and the voltage of the initialization power VINT.

[0096] refer to Figure 5B During the second period P2, the first emission control line EL1i may be interrupted from supplying the first emission control signal (or the low-level first emission control signal EM1), and the second emission control line EL2i may be supplied with the second emission control signal (or the low-level second emission control signal EM2). During the second period P2, the second enable scan signal GR may be supplied to the second scan line SL2i, and the third enable scan signal GI may be supplied to the third scan line SL3i.

[0097] If the first emission control line EL1i is interrupted from supplying the first emission disable control signal (or the low-level first emission control signal EM1) (or if the first emission enable control signal (or the high-level first emission control signal EM1) is supplied), the fifth transistor T5 may be turned on. If the fifth transistor T5 is turned on, the voltage of the first driving power VDD may be supplied to the first electrode of the first transistor T1.

[0098] If the second emission control line EL2i is supplied with a second disable emission control signal (or a low-level second emission control signal EM2), the sixth transistor T6 may be turned off. If the sixth transistor T6 is turned off, the second node N2 and the first electrode of the light emitting element LD may be electrically disconnected from each other.

[0099] If the third enable scan signal GI is supplied to the third scan line SL3i, the fourth transistor T4 is turned on. If the fourth transistor T4 is turned on, the voltage of the initialization power VINT may be supplied to the first electrode of the light emitting element LD.

[0100] If the second enable scan signal GR is supplied to the second scan line SL2i, the third transistor T3 is turned on. If the third transistor T3 is turned on, the voltage of the reference power VREF may be supplied to the first node N1.

[0101] The voltage of the reference power VREF can be set to enable the first transistor T1 to conduct, so that the voltage of the second node N2 can increase in response to the current supplied from the first drive power VDD to the second node N2 via the first transistor T1. During the second period P2, the voltage of the second node N2 can increase to a value obtained by subtracting the absolute threshold voltage of the first transistor T1 from the reference power VREF. In other words, during the second period P2, a voltage corresponding to the threshold voltage of the first transistor T1 can be stored in the first capacitor Cst.

[0102] The width of the second period P2 can be determined by the supply time of the first emission enable control signal (or the high-level first emission control signal EM1) and the second enable scan signal GR. In other words, in an embodiment of the present disclosure, the threshold voltage compensation time (i.e., the second period P2) of the first transistor T1 can be controlled by controlling the supply time of the first emission enable control signal (or the high-level first emission control signal EM1) and the second enable scan signal GR.

[0103] refer to Figure 5C During the third period P3, the first disable emission control signal (or the low-level first emission control signal EM1) may be provided to the first emission control line EL1i, the second disable emission control signal (or the low-level second emission control signal EM2) may be provided to the second emission control line EL2i, the first enable scan signal GW may be provided to the first scan line SL1i, and the third enable scan signal GI may be provided to the third scan line SL3i.

[0104] If the first emission control signal (or the low-level first emission control signal EM1) is supplied to the first emission control line EL1i, the fifth transistor T5 may be turned off. If the second emission control signal (or the low-level second emission control signal EM2) is supplied to the second emission control line EL2i, the sixth transistor T6 may be turned off. If the third enable scan signal GI is supplied to the third scan line SL3i, the fourth transistor T4 may be turned on so that the voltage of the initialization power VINT can be supplied to the first electrode of the light-emitting element LD.

[0105] If the first enable scan signal GW is supplied to the first scan line SL1i, the second transistor T2 may be turned on. If the second transistor T2 is turned on, a data signal may be supplied from the j-th data line DLj to the first node N1. During the third period P3, a voltage VN1 of the first node N1 and a voltage VN2 of the second node N2 may be expressed by Equation 1.

[0106] [Equation 1]

[0107] VN1=Vdata

[0108] VN2=VREF-Vth1

[0109] In Equation 1, Vdata may be the voltage of the data signal, and Vth1 may be the threshold voltage of the first transistor T1 .

[0110] In Equation 1, for convenience of explanation, the second node N2 has been described as maintaining the voltage of VREF-Vth1 during the third period P3, but embodiments of the present disclosure are not limited thereto.

[0111] For example, during the third period P3, the voltage VN1 of the first node N1 may change from the voltage of the reference power VREF to the voltage Vdata of the data signal, and the voltage VN2 of the second node N2 may change through coupling of the first capacitor Cst. However, since the second electrode of the second capacitor Chold (for example, the electrode connected to the first electrode of the light emitting element LD) maintains the voltage of the initialization power VINT, the change of the voltage VN2 of the second node N2 may be minimized.

[0112] For example, during the third period P3 , the voltage VN2 of the second node N2 may vary in response to the ratio of the first capacitor Cst and the second capacitor Chold, so that a variation in the voltage VN2 of the second node N2 may be minimized.

[0113] refer to Figure 5DDuring the fourth period P4, the first emission control signal enabled (or the high-level first emission control signal EM1) may be provided to the first emission control line EL1i, and the second emission control signal enabled (or the high-level second emission control signal EM2) may be provided to the second emission control line EL2i.

[0114] If the first emission control signal (or the high-level first emission control signal EM1) is supplied to the first emission control line EL1i, the fifth transistor T5 may be turned on so that the first power line PL1 and the first electrode of the first transistor T1 may be electrically connected to each other. If the second emission control signal (or the high-level second emission control signal EM2) is supplied to the second emission control line EL2i, the sixth transistor T6 may be turned on so that the second electrode of the first transistor T1 and the first electrode of the light-emitting element LD may be electrically connected to each other.

[0115] The first transistor T1 can provide a driving current of a voltage corresponding to the first node N1 from the first driving power VDD to the second driving power VSS via the light emitting element LD. Therefore, during the fourth period P4, the light emitting element LD can generate light with brightness corresponding to the driving current.

[0116] In a comparative example, when the second capacitor Chold is positioned between the first power line PL1 and the second node N2, the voltage of the second node N2 may change due to changes in the voltage of the first drive power VDD supplied to the first power line PL1. Therefore, an image of desired brightness may not be displayed on the pixel PXij. In particular, when the voltage of the second node N2 changes due to changes in the voltage of the first drive power VDD during the third period P3 in which the voltage of the data signal is supplied to the pixel PXij, the voltage of the desired data signal may not be stored in the pixel PXij.

[0117] Compared to the comparative example, in the embodiments of the present disclosure, the second capacitor Chold can be connected between the second node N2 and the first electrode of the light-emitting element LD, thereby stably maintaining the voltage of the second node N2 regardless of changes in the voltage of the first drive power VDD. For example, the first electrode of the light-emitting element LD can be maintained at the voltage of the initialization power VINT during the third period P3 in which the voltage of the data signal is supplied to the pixel PXij. Therefore, the voltage of the desired data signal can be stored in the pixel PXij.

[0118] For example, the pixel assembly 110 may be provided with a check pattern in which the pixel assembly 110 is divided into a plurality of horizontal regions, with some regions set to an emitting state and the remaining regions set to a non-emitting state. In an embodiment, mura of the comparative example was measured to be approximately 3.08%, and mura of the embodiment of the present disclosure was measured to be approximately 1.22%. For example, with the present disclosure, display quality can be further enhanced.

[0119] Figure 6 Is shown driving Figure 3 The waveforms of an embodiment of the method are shown for the pixel PXij.

[0120] refer to Figure 3 and Figure 6 , the pixel PXij can be driven by a first period P1, a second period P2, a third period P3a and a fourth period P4 separated from each other. The first period P1, the second period P2 and the fourth period P4 can be separated from each other. Figure 4 The periods P1, P2 and P4 of the driving method are the same, and repeated description thereof will be omitted.

[0121] The third period P3a may be a period in which the voltage of the data signal is stored in the pixel PXij. During the third period P3a, the first emission disable control signal (or the low-level first emission control signal EM1) may be supplied to the first emission control line EL1i, the second emission disable control signal (or the low-level second emission control signal EM2) may be supplied to the second emission control line EL2i, and the first enable scan signal GW may be supplied to the first scan line SL1i.

[0122] If the first emission control line EL1i is supplied with a first emission disable signal (or a low-level first emission control signal EM1), the fifth transistor T5 may be turned off. If the second emission control line EL2i is supplied with a second emission control signal (or a low-level second emission control signal EM2), the sixth transistor T6 may be turned off.

[0123] If the first enable scan signal GW is supplied to the first scan line SL1i, the second transistor T2 is turned on. If the second transistor T2 is turned on, the data signal can be supplied from the j-th data line DLj to the first node N1. The voltage of the first node N1 and the voltage of the second node N2 during the third period P3a can be expressed as the above equation 1.

[0124] During the third period P3a, the voltage of the first node N1 may change from the voltage of the reference power VREF to the voltage Vdata of the data signal, and the voltage of the second node N2 may change through coupling of the first capacitor Cst. The voltage of the second node N2 may change in response to a ratio of the first capacitor Cst, the second capacitor Chold, and the parasitic capacitor Cp, thereby minimizing a change in the voltage of the second node N2.

[0125] Figure 7 is a schematic diagram illustrating an electronic device 1000 according to an embodiment of the present disclosure.

[0126] refer to Figure 7 , the electronic device 1000 according to an embodiment of the present disclosure may output various information through the display module 1140. If the processor 1110 executes an application stored in the memory 1120, the display module 1140 may provide application information to the user through the display panel 1141.

[0127] The processor 1110 can obtain external input through the input module 1130 or the sensor module 1161 and execute an application corresponding to the external input. For example, when a user selects a camera icon (or a camera application icon) displayed on the display panel 1141, the processor 1110 can obtain user input through the input sensor 1161-2 and activate the camera module 1171. The processor 1110 can transmit image data corresponding to an image captured by the camera module 1171 to the display module 1140. The display module 1140 can display an image corresponding to the captured image on the display panel 1141.

[0128] When personal information authentication is performed through the display module 1140, the fingerprint sensor 1161-1 can obtain input fingerprint information as input data. The processor 1110 can compare the input data obtained by the fingerprint sensor 1161-1 with the verification data stored in the memory 1120 and can execute the application based on the comparison result. The display module 1140 can display information executed according to the logic of the application on the display panel 1141. The fingerprint sensor 1161-1 can obtain fingerprint information in the entire area of ​​the display module 1140 (or display panel 1141).

[0129] When the music streaming icon displayed on the display module 1140 is selected, the processor 1110 may obtain a user input through the input sensor 1161-2 and activate a music streaming application stored in the memory 1120. If a music play command is input in the music streaming application, the processor 1110 may activate the sound output module 1163 and provide the user with sound information corresponding to the music play command.

[0130] So far, a brief description of the operation of the electronic device 1000 has been provided. Hereinafter, the configuration of the electronic device 1000 will be described in detail. Some of the components of the electronic device 1000 to be described below may be integrated into a single component, or one component may be separated into two or more components.

[0131] The electronic device 1000 can communicate with the external electronic device 2000 through a network (e.g., a short-range wireless communication network or a long-range wireless communication network). In an embodiment, the electronic device 1000 may include a processor 1110, a memory 1120, an input module 1130, a display module 1140, a power module 1150, an internal module 1160, and an external module 1170. In an embodiment, in the electronic device 1000, at least one of the aforementioned components may be omitted, or one or more other components may be added. In an embodiment, some of the aforementioned components (e.g., the sensor module 1161, the antenna module 1162, or the sound output module 1163) may be integrated into another component (e.g., the display module 1140).

[0132] The processor 1110 may execute software to control at least one other component (e.g., hardware or software component) of the electronic device 1000 connected to the processor 1110 and perform various data processing or computing operations. In an embodiment, as at least part of the data processing or computing operation, the processor 1110 may store a command or data received from another component (e.g., the input module 1130, the sensor module 1161, or the communication module 1173) in the volatile memory 1121, process the command or data stored in the volatile memory 1121, and store the resulting data in the non-volatile memory 1122.

[0133] The processor 1110 may include a main processor 1111 and an auxiliary processor 1112. The main processor 1111 may include a central processing unit (CPU) 1111-1. The main processor 1111 may also include one or more of a graphics processing unit (GPU) 1111-2, a communication processor (CP), and an image signal processor (ISP). The main processor 1111 may also include a neural processing unit (NPU) 1111-3. NPU 1111-3 may be a processor dedicated to processing artificial intelligence models. The artificial intelligence model may be generated through machine learning. The artificial intelligence model may include multiple artificial neural network layers. The artificial neural network may be a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q network, or a combination of two or more of the foregoing networks, but the present disclosure is not limited thereto. The artificial intelligence model may include not only a hardware structure, but also additional or alternative software structures. At least two of the aforementioned processing units and processors may be implemented as a single integrated component (e.g., a single chip). In another embodiment, the processing unit and the processor may be implemented as separate components (eg, multiple chips).

[0134] The auxiliary processor 1112 may include a controller 1112-1. The controller 1112-1 may include an interface conversion circuit and a timing control circuit. For example, the controller 1112-1 may include Figure 1 1. The timing controller 160 shown in FIG. Controller 1112-1 can receive an image signal from the main processor 1111, and can convert the image signal in a data format into a format corresponding to the specification of the interface with the display module 1140, and output the image data. Controller 1112-1 can output various control signals to drive the display module 1140.

[0135] The auxiliary processor 1112 may further include a data conversion circuit 1112-2, a gamma correction circuit 1112-3, a rendering circuit 1112-4, a touch control circuit 1112-5, etc. The data conversion circuit 1112-2 may receive image data from the controller 1112-1, compensate the image data based on the characteristics of the electronic device 1000 or the user's settings to display an image at a desired brightness, or may convert the image data to reduce power consumption or compensate for afterimages.

[0136] The gamma correction circuit 1112-3 may convert image data, a gamma reference voltage, etc. so that an image to be displayed on the electronic device 1000 may have a desired gamma characteristic. The rendering circuit 1112-4 may receive image data from the controller 1112-1 and render the image data in consideration of the pixel arrangement on the display panel 1141 applied to the electronic device 1000, etc.

[0137] The touch control circuit 1112 - 5 may provide a touch signal to the input sensor 1161 - 2 and receive a sensing signal from the input sensor 1161 - 2 in response to the touch signal.

[0138] At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, the rendering circuit 1112-4, and the touch control circuit 1112-5 may be integrated into another component (e.g., the main processor 1111 or the controller 1112-1). At least one of the data conversion circuit 1112-2, the gamma correction circuit 1112-3, and the rendering circuit 1112-4 may be integrated into the source driver 1143 to be described below.

[0139] The memory 1120 may store various data to be used in at least one component of the electronic device 1000 (e.g., the processor 1110 or the sensor module 1161) and input data or output data for commands related to the various data. In addition, the memory 1120 may store various setting data corresponding to user settings. The memory 1120 may include one or more of a volatile memory 1121 and a non-volatile memory 1122.

[0140] The input module 1130 may receive commands or data to be used in components of the electronic device 1000 (e.g., the processor 1110, the sensor module 1161, or the sound output module 1163) from an external device (e.g., a user or an external electronic device 2000) disposed outside the electronic device 1000.

[0141] The input module 1130 may include a first input module 1131 configured to receive commands or data from a user and a second input module 1132 configured to receive commands or data from an external electronic device 2000. The first input module 1131 may include a microphone, a mouse, a keyboard, a key (e.g., a button) or a pen (e.g., a passive pen or an active pen). The second input module 1132 may support a specified protocol that can be connected to the external electronic device 2000 in a wired or wireless manner. In an embodiment, the second input module 1132 may include a high-definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface or an audio interface. The second input module 1132 may include a connector, such as an HDMI connector, a USB connector, an SD card connector or an audio connector (e.g., a headphone connector), for physically connecting to the external electronic device 2000.

[0142] The display module 1140 can provide visual information to the user. The display module 1140 may include a display panel 1141, a gate driver 1142, a source driver 1143, and a voltage generating circuit 1144. The display module 1140 may also include a window, a base, and a bracket to protect the display panel 1141. The display module 1140 may include Figure 1 At least some components of the display device 100 shown in FIG.

[0143] The display panel 1141 (or display) may include a liquid crystal display panel, an organic light emitting display panel, or an inorganic light emitting display panel. The type of the display panel 1141 is not limited to a specific type. The display panel 1141 may be a rigid type panel or a flexible type panel that is rollable or foldable. The display module 1140 may further include a support, a bracket, or a heat sink that supports the display panel 1141. The display panel 1141 may include Figure 1 In other words, the display panel 1141 may include Figure 1 Each of the pixels PX may include Figure 3 The pixel circuit and light emitting element LD shown in .

[0144] The gate driver 1142 may be mounted on the display panel 1141 as a driver chip. The gate driver 1142 may be integrated on the display panel 1141. For example, the gate driver 1142 may include an amorphous silicon TFT gate (ASG) driver circuit, a low temperature polysilicon (LTPS) TFT gate driver circuit, or an oxide semiconductor TFT gate (OSG) driver circuit internalized in the display panel 1141. The gate driver 1142 may receive a control signal from the controller 1112-1 and output a scan signal to the display panel 1141 in response to the control signal. The gate driver 1142 may include Figure 1The scan driver 130 shown in FIG.

[0145] The display module 1140 may further include an emission driver (not shown). Figure 7 ). The emission driver may output an emission control signal to the display panel 1141 in response to a control signal received from the controller 1112-1. The emission driver may be formed separately from the gate driver 1142 or may be integrated into the gate driver 1142. The emission driver may include Figure 1 The transmit driver 140 shown in FIG.

[0146] The source driver 1143 may receive a control signal from the controller 1112-1, convert the image data into an analog voltage (eg, a data signal) in response to the control signal, and output the data signal to the display panel 1141. The source driver 1143 may include Figure 1 The data driver 120 is shown in FIG.

[0147] The source driver 1143 may be integrated into another component (eg, the controller 1112-1). The functions of the interface conversion circuit and the timing control circuit of the controller 1112-1 may be integrated into the source driver 1143. The voltage generating circuit 1144 may output various voltages required to drive the display panel 1141. For example, the voltage generating circuit 1144 may include Figure 1 The power supply 150 is shown in FIG.

[0148] In an embodiment, the source driver 1143 may convert data included in the image data received from the processor 1110 and corresponding to red (R), green (G), and blue (B) into a red data signal (or data voltage), a green data signal, and a blue data signal, and provide the data signals to a plurality of pixel columns included in the display panel 1141 during a single horizontal period.

[0149] The power module 1150 can provide power to the components of the electronic device 1000. The power module 1150 may include a battery to store power voltage. The battery may include a non-rechargeable primary battery and a rechargeable secondary battery or fuel cell. The power module 1150 may include a power management integrated circuit (PMIC). The PMIC can provide optimized power to each of the aforementioned modules and the modules to be described below. The power module 1150 may include a wireless power transceiver electrically connected to the battery. The wireless power transceiver may include multiple coil antenna radiators. In an embodiment, at least some components of the voltage generating circuit 1144 and the power module 1150 may be integrated into a single component. For example, the voltage generating circuit 1144 may be included in the power module 1150.

[0150] The electronic device 1000 may further include an internal module 1160 and an external module 1170. The internal module 1160 may include a sensor module 1161, an antenna module 1162, and a sound output module 1163. The external module 1170 may include a camera module 1171, an optical module 1172, and a communication module 1173.

[0151] The sensor module 1161 can sense input from the user's body or input from the pen of the first input module 1131 and generate an electrical signal or data value corresponding to the input. The sensor module 1161 can include one or more of a fingerprint sensor 1161-1, an input sensor 1161-2, and a digitizer 1161-3.

[0152] Fingerprint sensor 1161 - 1 may generate a data value corresponding to the user's fingerprint.

[0153] The input sensor 1161-2 may generate a data value corresponding to coordinate information of an input from the user's body or an input from a pen. The input sensor 1161-2 may generate a data value corresponding to the amount of change in capacitance caused by the input. The input sensor 1161-2 may sense input from a passive pen, or transmit data to or receive data from an active pen.

[0154] The input sensor 1161-2 can measure bio-signals related to bio-information such as blood pressure, body fluids, or body fat. For example, when a user brings a part of his / her body into contact with the sensor layer or sensing panel and remains still for a certain period of time, the input sensor 1161-2 can sense the bio-signal based on the change in the electric field caused by the part of his / her body and output the information desired by the user to the display module 1140.

[0155] The digitizer 1161-3 can generate data values ​​corresponding to coordinate information input from the pen. The digitizer 1161-3 can generate data values ​​corresponding to electromagnetic changes caused by the input. The digitizer 1161-3 can sense input from a passive pen, or transmit data to or receive data from an active pen.

[0156] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be implemented as a sensor layer formed on the display panel 1141 through a continuous process. At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be provided above the display panel 1141. Any one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 (for example, the digitizer 1161-3) may be provided below the display panel 1141.

[0157] At least two or more of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be formed so as to be integrated into a single sensing panel using the same process. In the case where at least two or more of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 are integrated into a single sensing panel, the sensing panel may be disposed between the display panel 1141 and a window disposed above the display panel 1141. In an embodiment, the sensing panel may be disposed on the window, and the position of the sensing panel is not particularly limited.

[0158] At least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be embedded in the display panel 1141. In other words, during a process of forming components (e.g., light emitting elements, transistors, etc.) included in the display panel 1141, at least one of the fingerprint sensor 1161-1, the input sensor 1161-2, and the digitizer 1161-3 may be formed simultaneously with the components.

[0159] The sensor module 1161 may generate an electrical signal or data value corresponding to an internal condition or an external condition of the electronic device 1000. Although not shown, the sensor module 1161 may further include, for example, a gesture sensor, a gyro sensor, an atmospheric sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an infrared (IR) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illumination sensor.

[0160] The antenna module 1162 may include one or more antennas to transmit signals or power to or receive signals or power from an external device. In an embodiment, the communication module 1173 may transmit signals to or receive signals from the external electronic device 2000 via an antenna suitable for the communication scheme. The antenna pattern of the antenna module 1162 may be integrated into a component of the display module 1140 (e.g., the display panel 1141 of the display module 1140) or the input sensor 1161-2.

[0161] The sound output module 1163 may be a device for outputting sound signals to a device provided outside the electronic device 1000, and may include, for example, a speaker and a receiver, the speaker being used for general purposes such as reproducing multimedia or recording data, and the receiver being used for telephone reception. In an embodiment, the receiver may be formed integrally with or separately from the speaker. The sound output mode of the sound output module 1163 may be integrated into the display module 1140.

[0162] The camera module 1171 can capture still images or videos. In an embodiment, the camera module 1171 may include one or more lenses, image sensors, or image signal processors. The camera module 1171 may also include an infrared camera capable of sensing the user's presence, the user's position, the user's line of sight, etc.

[0163] The light module 1172 may provide light. The light module 1172 may include a light emitting diode or a xenon lamp. The light module 1172 may operate in conjunction with the camera module 1171 or independently thereof.

[0164] The communication module 1173 can form a wired or wireless communication channel between the electronic device 1000 and the external electronic device 2000, and support communication through the formed communication channel. The communication module 1173 may include a wireless communication module such as a cellular communication module, a short-range wireless communication module, a global navigation satellite system (GNSS) communication module, a wired communication module such as a local area network (LAN) communication module, and at least one of a power line communication module. The communication module 1173 can communicate with the external electronic device 2000 via a short-range communication network such as Bluetooth, WiFi Direct or Infrared Data Association (IrDA) or a long-range communication network such as a cellular network, the Internet or a computer network (e.g., LAN or WAN). The various types of communication modules 1173 described above can be implemented as a single chip, or can be implemented as separate chips.

[0165] The input module 1130 , the sensor module 1161 , the camera module 1171 , and the like interlocked with the processor 1110 may be used to control the operation of the display module 1140 .

[0166] The processor 1110 may output commands or data to the display module 1140, the sound output module 1163, the camera module 1171, or the optical module 1172 based on input data received from the input module 1130. For example, the processor 1110 may generate image data in response to input data applied via a mouse, an active pen, or the like, and output the image data to the display module 1140, or may generate command data in response to the input data and output the command data to the camera module 1171 or the optical module 1172. In the event that no input data is received from the input module 1130, the processor 1110 may convert the operating mode of the electronic device 1000 into a low power mode or a sleep mode, thereby reducing power consumption of the electronic device 1000.

[0167] The processor 1110 can output commands or data to the display module 1140, the sound output module 1163, the camera module 1171, or the optical module 1172 based on the sensing data received from the sensor module 1161. For example, the processor 1110 can compare the authentication data applied from the fingerprint sensor 1161-1 with the authentication data stored in the memory 1120 and execute an application based on the comparison result. The processor 1110 can execute a command based on the sensing data sensed by the input sensor 1161-2 or the digitizer 1161-3, or output corresponding image data to the display module 1140. In the case where the sensor module 1161 includes a temperature sensor, the processor 1110 can receive temperature data for the measured temperature from the sensor module 1161 and further perform a brightness correction operation on the image data based on the temperature data.

[0168] The processor 1110 may receive measurement data regarding the user's presence, the user's position, the user's line of sight, etc. from the camera module 1171. The processor 1110 may also perform brightness correction operations on the image data based on the measurement data. For example, the processor 1110, having determined the presence of the user through input from the camera module 1171, may output image data whose brightness has been corrected by the data conversion circuit 1112-2 or the gamma correction circuit 1112-3 to the display module 1140.

[0169] Some of the aforementioned components may be connected to each other through a communication scheme that can be used between peripheral devices (e.g., a bus, general-purpose input / output (GPIO), a serial peripheral interface (SPI), a mobile industry processor interface (MIPI), or a hyperpath interconnect (UPI) link), and thus signals (e.g., commands or data) may be exchanged between them. The processor 1110 may communicate with the display module 1140 through an interface. For example, one of the aforementioned communication schemes may be used, and the interface is not limited to the aforementioned communication schemes.

[0170] In the pixel and the display device and the electronic device including the pixel according to the embodiment of the present disclosure, the voltage of the desired data signal can be stored in the pixel regardless of the change in the voltage of the first driving power.

[0171] Furthermore, in the pixel according to the embodiment of the present disclosure, and the display device and the electronic device including the pixel, an image with desired brightness can be displayed regardless of the change in the voltage of the first driving power.

[0172] The above description is an example of the technical features of the present disclosure, and those skilled in the art will be able to make various modifications and changes. Therefore, the embodiments of the present disclosure described above can be implemented individually or in combination with each other.

[0173] Therefore, the embodiments disclosed in this disclosure are not intended to limit the technical spirit of this disclosure, but are intended to describe the technical spirit of this disclosure, and the scope of the technical spirit of this disclosure is not limited by these embodiments. The scope of protection of this disclosure should be interpreted by the appended claims, and it should be understood that all technical spirits within the scope of equivalents are included within the scope of this disclosure.

Claims

1. A pixel comprising: a first transistor including a first electrode connected to the first power line, a first gate electrode connected to the first node, and a second electrode connected to the second node; a second transistor connected between the data line and the first node and including a gate electrode connected to the first scan line; a light emitting element including a first electrode connected to the second electrode of the first transistor and a second electrode connected to a second power line; as well as A first capacitor and a second capacitor are connected in series between the first node and the first electrode of the light emitting element.

2. The pixel according to claim 1, wherein The first transistor further includes a second gate electrode, and The second gate electrode is connected to the second node.

3. The pixel according to claim 1, further comprising: a third transistor connected between a third power line and the first node and including a gate electrode connected to a second scan line; as well as The fourth transistor is connected between the first electrode of the light emitting element and a fourth power line and includes a gate electrode connected to a third scan line.

4. The pixel according to claim 3, wherein When the second transistor is turned on, the fourth transistor is set to an on state.

5. The pixel according to claim 3, wherein When the second transistor is turned on, the fourth transistor is set to an off state.

6. The pixel according to claim 3, wherein The conduction period of the third transistor and the conduction period of the fourth transistor overlap during some periods, and A turn-on period of the second transistor and a turn-on period of the third transistor do not overlap.

7. The pixel according to claim 3, further comprising: a fifth transistor connected between the first power line and the first electrode of the first transistor and including a gate electrode connected to a first emission control line; as well as A sixth transistor is connected between the second node and the first electrode of the light emitting element and includes a gate electrode connected to a second emission control line.

8. The pixel according to claim 7, wherein: The sixth transistor has a conduction period during the first period that overlaps with a conduction period of the third transistor, The fifth transistor has a turn-on period during the second period that overlaps with the turn-on period of the third transistor, and The first period and the second period do not overlap.

9. The pixel according to claim 8, wherein: The fourth transistor is set to an on state during the first period and the second period.

10. A display device comprising: a pixel assembly including pixels connected to scan lines, emission control lines, and data lines; A scan driver for driving the scan lines; A data driver, driving the data line; as well as an emission driver, driving the emission control line, Among the pixels, one pixel connected to the i-th horizontal line and the j-th data line includes: a first transistor including a first electrode connected to the first power line, a first gate electrode connected to the first node, and a second electrode and a second gate electrode connected to the second node; a second transistor connected between the data line and the first node and turned on when a first enable scan signal is supplied to the first scan line of the i-th scan line; a light emitting element including a first electrode connected to the second electrode of the first transistor and a second electrode connected to a second power line; and a first capacitor and a second capacitor connected in series between the first node and the first electrode of the light emitting element, and Here, i and j are each positive integers. The display device according to claim 10 , wherein: The one of the pixels further comprises: a third transistor connected between a third power line and the first node and turned on when a second enable scan signal is supplied to the second scan line of the i-th scan line; and A fourth transistor is connected between the first electrode of the light emitting element and a fourth power line, and is turned on when a third enabling scan signal is supplied to the third scan line of the i-th scan line.

12. The display device according to claim 11, wherein The one of the pixels further comprises: a fifth transistor connected between the first power line and the first electrode of the first transistor and turned off if a first disable emission control signal is supplied to the first emission control line of the i-th emission control line; and A sixth transistor is connected between the second node and the first electrode of the light emitting element and is turned off when a second emission disable control signal is supplied to the second emission control line of the i-th emission control line.

13. The display device according to claim 12, wherein: The one of the pixels is driven with a first period, a second period, a third period, and a fourth period separated from each other, and The scan driver provides the second enabling scan signal and the third enabling scan signal during the first period and the second period, and provides the first enabling scan signal during the third period.

14. The display device according to claim 13, wherein: The scan driver provides the third enable scan signal during the third period.

15. The display device according to claim 13, wherein The emission driver provides the first emission disable control signal during the first period and the third period, and provides the second emission disable control signal during the second period and the third period.

16. The display device according to claim 15, wherein The emission driver provides a first enable emission control signal to the first emission control line during the fourth period to turn on the fifth transistor, and The emission driver provides a second enable emission control signal to the second emission control line during the fourth period to turn on the sixth transistor.

17. The display device according to claim 11, wherein A first driving power is supplied to the first power line, a second driving power having a voltage lower than that of the first driving power is supplied to the second power line, The voltage of the reference power is supplied to the third power line, and A voltage of initialization power is supplied to the fourth power line.

18. The display device according to claim 17, wherein: Each of the reference power and the initialization power maintains a constant voltage.

19. An electronic device comprising: a display module comprising a display panel and displaying an image on the display panel; a sensing module for sensing an input corresponding to the image displayed on the display module; as well as The processor and the auxiliary processor control the display module and the sensing module, Wherein, at least one pixel included in the display panel includes: a first transistor including a first electrode connected to the first power line, a first gate electrode connected to the first node, and a second electrode and a second gate electrode connected to the second node; a second transistor connected between the data line and the first node and including a gate electrode connected to the first scan line; a light emitting element including a first electrode connected to the second electrode of the first transistor and a second electrode connected to a second power line; and A first capacitor and a second capacitor are connected in series between the first node and the first electrode of the light emitting element.

20. The electronic device according to claim 19, wherein The at least one pixel further comprises: a third transistor connected between a third power line and the first node and including a gate electrode connected to a second scan line; a fourth transistor connected between the first electrode of the light emitting element and a fourth power line and including a gate electrode connected to a third scan line; a fifth transistor connected between the first power line and the first electrode of the first transistor and including a gate electrode connected to a first emission control line; and A sixth transistor is connected between the second node and the first electrode of the light emitting element and includes a gate electrode connected to a second emission control line.

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