Managing cross temperature exposure in memory systems

Abstract

The invention relates to managing cross-temperature exposure in a memory system. A memory system controller may identify a temperature associated with a write operation at a logical block address (LBA) of a first memory device during a boot sequence, wherein the LBA is associated with a physical address of the first memory device that stores a portion of boot sequence data. The memory system controller may select a read setting based on a difference between an operating temperature of the first memory device during the boot sequence and the temperature associated with the write operation at the LBA of the first memory device. Accordingly, the memory system controller may perform a read operation to read the portion of the boot sequence data from the physical address associated with the LBA according to the read setting.

Description

[0001] Cross Reference

[0002] This patent application claims priority to U.S. patent application No. 18 / 781,803, filed by Coppola et al. on July 23, 2024, entitled “MANAGING CROSS-TEMPERATURE EXPOSURE IN MEMORY SYSTEMS,” and U.S. provisional patent application No. 63 / 562,127, filed by Coppola et al. on March 6, 2024, entitled “MANAGING CROSS-TEMPERATURE EXPOSURE IN MEMORY SYSTEMS,” each of which is assigned to its assignee and each of which is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The following relates to one or more systems of memory, including techniques for managing cross-temperature exposure in the memory system. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, the memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, the memory device can write (e.g., program, set, assign) a state to a memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic DRAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described as either volatile or nonvolatile. A memory cell configured in a nonvolatile configuration can maintain a stored logic state for an extended period of time, even in the absence of an external power source. A memory cell configured in a volatile configuration can lose its stored state when disconnected from the external power source. Summary of the Invention

[0006] A memory system is described. The memory system may include: one or more memory devices; and processing circuitry coupled to the one or more memory devices and configured to cause the memory system to: identify, during a boot sequence of the memory system, a temperature associated with a write operation at a logical block address (LBA) of a first memory device of the one or more memory devices, the LBA being associated with a physical address of the first memory device storing a portion of boot sequence data; select a read setting from a plurality of read settings based on a difference between an operating temperature of the first memory device during the boot sequence of the memory system and the temperature associated with the write operation at the LBA of the first memory device; and read the portion of the boot sequence data from the physical address associated with the LBA according to the read setting.

[0007] A host system is described. The host system may include: one or more interfaces including one or more signal paths operable to communicate with one or more memory systems; and processing circuitry coupled to the one or more interfaces and configured to cause the host system to: transmit one or more commands to a first memory system of the one or more memory systems, each command indicating a logical block address (LBA) range where a portion of boot sequence data is stored; transmit an indication to enable a cross-temperature management program at the first memory system to the first memory system; and receive the boot sequence data from the first memory system during a boot sequence of the first memory system based on transmitting the indication to enable the cross-temperature management program.

[0008] A system is described. The system may include: a memory system including one or more controllers and one or more memory devices coupled to the one or more controllers; and a host system coupled to the memory system and including the one or more controllers, the one or more controllers of the host system being configured to cause the host system to: transmit one or more commands to the memory system, each command indicating a respective logical block address (LBA) range storing a portion of boot sequence data; and transmit an indication to the memory system to enable a cross-temperature management routine at the memory system, the one or more controllers of the memory system being configured to cause the memory system to: select a read setting from a plurality of read settings based on a difference between an operating temperature of a first memory device of the one or more memory devices and a temperature associated with a write operation at an LBA of the first memory device; and read a portion of the boot sequence data from a physical address associated with the LBA according to the read setting. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1

[0014] An example of a system supporting techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein is presented.

[0010] Figure 2 An example of a process flow supporting techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein is presented.

[0011] Figure 3 An example of a process flow supporting techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein is presented.

[0012] Figure 4 A block diagram is shown of a memory system supporting techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein.

[0013] Figure 5 A block diagram is shown of a host system supporting techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein.

[0014] Figure 6 and 7 A flow chart illustrating one or more methods supporting techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein is shown. DETAILED DESCRIPTION

[0015] Some memory systems (e.g., NAND systems) may experience cross-temperature exposure during access operations (e.g., read and write operations), which can reduce the likelihood of correctly reading data during read operations, introduce delays into such access operations, or both. For example, one or more memory system controllers of a memory system may write data to one or more memory cells while the memory system is operating at a relatively extreme temperature (e.g., relatively high, relatively low). In such an example, if the data is read while the memory system is operating at a temperature significantly different from the relatively extreme temperature (e.g., relatively low, relatively high), the one or more memory system controllers may need to apply multiple read operations, each with various reference voltage levels, in order to correctly read the data. That is, if the difference (e.g., range) between the write temperature of the data (e.g., the temperature of the memory system during the write operation) and the read temperature of the data (e.g., the temperature of the memory system during the read operation) meets a threshold, the memory system may have experienced cross-temperature exposure of the data. In some cases, during a boot sequence (e.g., a process in which the memory system is powered on and one or more host applications are starting up), one or more memory system controllers may attempt to read boot sequence data (e.g., data corresponding to a boot sequence at one or more host applications) from one or more memory devices, where this boot sequence data may be affected by cross-temperature exposure. Consequently, the one or more memory system controllers may be required to apply multiple read operations to correctly obtain the boot sequence data, which may increase boot sequence latency, leading to host application timeouts and other issues.

[0016] According to the techniques described herein, a memory system may maintain information (e.g., in a table) that provides an association between a logical block address (LBA) corresponding to a physical address storing a portion of boot sequence data and a temperature (also referred to herein as a write temperature) at which the portion of boot sequence data was written. Thus, during a boot sequence, one or more memory system controllers may identify the operating temperature of the memory system and, from the information (e.g., the table), the corresponding write temperature for each portion of boot sequence data. Based on identifying the operating temperature and the corresponding write temperature for each portion of boot sequence data, the one or more memory system controllers may select corresponding read settings (e.g., a reference voltage, a trim setting) to read each portion of boot sequence data based on (e.g., based on, in response to) the difference between the operating temperature of the memory system and the corresponding write temperature. Thus, based on the selected read settings, the memory system may perform a single read operation (as opposed to multiple read operations in other systems and techniques) at each physical address associated with the LBA listed in the table to obtain the boot sequence data, thereby reducing latency during the boot sequence, among other advantages.

[0017] In addition to its applicability in memory systems as described herein, the techniques for managing cross-temperature exposure in memory systems can generally be implemented to improve the performance of various electronic devices and systems, including artificial intelligence (AI) applications, augmented reality (AR) applications, virtual reality (VR) applications, and games. Some electronic device applications, including high-performance applications such as AI, AR, VR, and games, may be associated with relatively high processing requirements to meet user expectations. Therefore, increasing the processing power of an electronic device by reducing response time, improving power consumption, reducing complexity, increasing data throughput or access speed, reducing communication time, or increasing memory capacity or density, among other performance indicators, can improve the user experience or appeal. Implementing the techniques described herein can improve the performance of an electronic device by reducing the number of read operations at a memory system during a boot sequence of the memory system, which can reduce processing or latency time, improve response time, or otherwise improve the user experience, among other advantages.

[0018] Features of the present disclosure are illustrated and described in the context of systems, devices, and circuits. Features of the present disclosure are further illustrated and described in the context of process flows and flow charts.

[0019] Figure 1 An example of a system 100 supporting techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein is shown. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle, an Internet of Things (IoT)-enabled device, an embedded computer (e.g., an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0020] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0021] The system 100 may include a host system 105, which may be coupled to a memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause the host system 105 to perform various operations according to examples as described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and a software stack executed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or a device therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although Figure 1 One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0022] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise communicate control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110, or otherwise supported between the host system controller 106 and the memory system controller 115. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface for each memory device 130 included in the memory system 110, or via a respective physical host interface for each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0023] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1 , two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, if memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0024] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations, such as reading data, writing data, erasing data, or refreshing data at the memory devices 130, as well as other such operations, which can be collectively referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data (e.g., in response to or otherwise associated with commands from the host system 105) with the host system 105 and one or more memory devices 130. For example, the memory system controller 115 may convert responses (e.g., data packets or other signals) associated with the memory devices 130 into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations such as error detection operations or error correction operations, encryption operations, cache operations, media management operations, background flushing, health monitoring, and address translation between logical addresses (e.g., LBAs) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0026] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic for performing the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115. Additionally or alternatively, the local memory 120 may serve as a cache for the memory system controller 115. For example, if data is read from or written to the memory device 130, the data may be stored in the local memory 120 and the data may be available in the local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a cache policy (e.g., with reduced latency relative to the memory device 130).

[0028] although Figure 1 The example of the memory system 110 in FIG. 1 has been described as including a memory system controller 115, but in some cases, the memory system 110 may not include a memory system controller 115. For example, the memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by the host system 105) or one or more local controllers 135, which may each be located within the memory device 130, to perform the functions attributed herein to the memory system controller 115. Generally, in some cases, one or more functions attributed herein to the memory system controller 115 may instead be performed by the host system 105, the local controller 135, or any combination thereof. In some cases, a memory device 130 that is at least partially managed by the memory system controller 115 may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0030] In some examples, the memory devices 130 may include (e.g., on the same die, within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1 As illustrated in FIG, memory device 130 - a may include a local controller 135 - a, and memory device 130 - b may include a local controller 135 - b.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to store one bit of information each, which may be referred to as single-level cells (SLCs). Additionally, or alternatively, the NAND memory device 130 may include memory cells configured to store multiple bits of information each, which may be referred to as multi-level cells (MLCs) if the memory cells are configured to store two bits of information each, three-level cells (TLCs) if the memory cells are configured to store three bits of information each, quad-level cells (QLCs) if the memory cells are configured to store four bits of information each, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity in supporting circuitry.

[0033] In some cases, a plane 165 may refer to a group of blocks 170, and, in some cases, concurrent operations may be performed on different planes 165. For example, as long as different blocks 170 are in different planes 165, concurrent operations may be performed on memory cells within different blocks 170. In some cases, individual blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d located in planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., including blocks in one or more planes of memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells within different pages 175 that have the same page address in their respective planes 165 (e.g., related to command decode, page address decode circuitry, or other circuitry shared across planes 165).

[0034] In some cases, block 170 can include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 can share (e.g., be coupled to) a common word line, and memory cells in the same string can share (e.g., be coupled to) a common digit line (which may alternatively be referred to as a bit line).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof), but can be erased at a second granularity (e.g., at a block granularity). That is, a page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., concurrently programmed or read as part of a single program or read operation), while a block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it is overwritten with new data. Thus, for example, in some cases, a used page 175 is not updated until the entire block 170 containing the page 175 has been erased.

[0036] In some cases, the memory system controller 115 or the local controller 135 may perform operations on the memory device 130 (e.g., as part of one or more media management algorithms), such as wear leveling, background flushing, garbage collection, erasure, block scanning, health monitoring, or other, or any combination thereof. For example, within the memory device 130, a block 170 may have some pages 175 containing valid data and some pages 175 containing invalid data. To avoid waiting for all pages 175 in a block 170 to have invalid data in order to erase and reuse the block 170, an algorithm called "garbage collection" may be invoked to allow the block 170 to be erased and released as a free block for subsequent write operations. Garbage collection may refer to a set of media management operations that include, for example: selecting a block 170 containing valid and invalid data; selecting a page 175 in the block containing valid data; copying the valid data from the selected page 175 to a new location (e.g., a free page 175 in another block 170); marking 175 the data in the previously selected page 175 as invalid; and erasing the selected block 170. Thus, the number of erased blocks 170 may be increased so that more blocks 170 are available for storing subsequent data (e.g., data subsequently received from the host system 105).

[0037] The system 100 may include any number of non-transitory computer-readable media that support techniques for managing cross-temperature exposure in a memory system. For example, the host system 105 (e.g., the host system controller 106), the memory system 110 (e.g., the memory system controller 115), or the memory device 130 (e.g., the local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media storing instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., by the host system controller 106), by the memory system 110 (e.g., by the memory system controller 115), or by the memory device 130 (e.g., by the local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions as described herein.

[0038] The host system 105 may operate one or more applications (e.g., user programs), wherein such applications may have relatively strict system boot sequence times (e.g., short startup times). Therefore, during the boot sequence of the system 100, if an application does not properly boot (e.g., load or start) within a threshold duration (e.g., a timeout range), the application may time out, resulting in a failure to load the application at the host system 105. For example, during the boot sequence, the host system 105 may request boot sequence data associated with a first application from the memory system 110, wherein the memory system controller 115 may read the boot sequence data from the memory device 130 and transmit the boot sequence data to the host system 105, thereby enabling the host system 105 to boot the first application. As described herein, the boot sequence data may be data associated with the boot sequence of the application operated by the host system 105, such as data associated with a logo for the boot sequence of the host application, data associated with a description displayed at the host system 105 during the boot sequence of the application, or the like.

[0039] In some cases, due to cross-temperature exposure, the system 100 may experience increased latency during the boot sequence, which may lead to application timeouts at the host system 105, among other challenges. For example, when data written at a relatively high temperature (or low temperature) is subsequently read at a relatively low temperature (or high temperature), the memory system 110 may experience cross-temperature exposure, which may cause the host system controller 106, the memory system controller 115, or the local controller 135 to erroneously read the data. That is, if the difference between the write temperature of the data and the read temperature of the data satisfies a threshold range, the memory system 110 may experience cross-temperature exposure during a read operation.

[0040] The threshold range between the write temperature of the data and the read temperature of the data may vary for different types of memory cells of page 175 (e.g., SLC, TLC, MLC, and other types). Furthermore, the threshold range may vary depending on the endurance of memory system 110, the data retention metric of memory system 110, or both. As illustrative examples, the threshold range between the write temperature of the data and the read temperature of the data may be 10 degrees Celsius, 20 degrees Celsius, 50 degrees Celsius, or 100 degrees Celsius, among others. Thus, if the difference between the read temperature of the data and the write temperature of the data is above the threshold range, the memory system controller 115 may be unable to correctly read the data. It should be understood that such threshold ranges are examples, and any threshold range between the write temperature and the read temperature of the data may cause the memory system 110 to experience cross-temperature exposure.

[0041] In some cases, the memory system controller 115 (e.g., mNAND device) may include firmware algorithms to mitigate the effects of cross-temperature exposure. For example, if data has experienced cross-temperature exposure and cannot be read (e.g., the data is corrupted), the memory system controller 115 (e.g., according to a firmware algorithm stored in the local memory 120) may perform various read operations according to different read settings (e.g., reference voltages, trim settings, or other parameters of the read operation) until the data is correctly read. Such read settings may be stored as a list in one or more pages 175 of the memory device 130 and loaded into the local memory 120 of the memory system controller 115 in response to the memory system controller 115 being unable to correctly read data. Furthermore, each read setting may be associated with a range between a write temperature and a read temperature.

[0042] However, applying various read operations with different read settings can further increase latency at the memory system 110 during the read operation, at least in part because the memory system controller 115 can perform multiple read operations with multiple read settings, resulting in relatively slower read performance. Therefore, during a boot sequence of the system 100, the memory system 110 can experience cross-temperature exposure during a read operation of the boot sequence data and attempt to perform multiple read operations, each with a corresponding read setting, in order to correctly read the boot sequence data, which can result in increased latency during the boot sequence, as well as various other challenges.

[0043] According to the techniques described herein, the memory system 110 may maintain information, such as a table 185, in one or more pages 175 of a memory device 130 (e.g., nonvolatile memory), wherein the information (e.g., table 185) provides an association between LBAs 190 (e.g., LBA 190-a, LBA 190-b, LBA 190-c, and LBA 190-n) and write temperatures 195 (e.g., write temperature 195-a, write temperature 195-b, write temperature 195-c, ​​and write temperature 195-n) for boot sequence data at each LBA 190, each LBA 190 corresponding to a respective physical address of the memory device 130 storing boot sequence data. Each LBA 190 (e.g., a list of LBAs for system boot data) may be a single LBA or a range of LBAs. Similarly, each write temperature 195 (eg, boot_data_write_operation_temperature) can be a single temperature or a temperature range of the memory system 110 during a write operation of a portion of the boot sequence data.

[0044] As an illustrative example, LBA 190-a may be a single LBA corresponding to a single physical address storing a first portion of boot sequence data, and write temperature 195-a may be a temperature range (e.g., 25 degrees Celsius to 30 degrees Celsius) experienced by memory system 110 during a write operation of the first portion of boot sequence data. As another illustrative example, LBA 190-b may be a range of LBAs (e.g., LBA X to LBA Y) that may correspond to a range of physical addresses storing a second portion of boot sequence data, and write temperature 195-b may be a single temperature (e.g., 28 degrees Celsius) experienced by memory system 110 during a write operation of the second portion of boot sequence data. In some examples, memory system 110 may maintain a respective table 185 for each application operated by host system 105. In some other examples, memory system 110 may maintain a single table 185 that stores associations between LBAs 190 of boot sequence data and write temperatures 195 for all applications operating at host system 105.

[0045] Thus, during the boot sequence of system 100, memory system controller 115 can identify the operating temperature of memory system 110, such as the current operating temperature. For example, memory system 110 can include a thermal sensor, wherein during the boot sequence of memory system 110 (e.g., the NAND initialization phase), memory system controller 115 can obtain (e.g., read) the operating temperature of memory system 110 from the thermal sensor. In such an example, because memory system controller 115 reads the output of the thermal sensor during the NAND initialization phase, memory system controller 115 can obtain the operating temperature of memory system 110 before host system 105 requests boot sequence data. That is, in some examples, memory system controller 115 obtains the current operating temperature before receiving one or more read commands requesting boot sequence data from host system 105 (e.g., there is a thermal sensor that can be read before the system boots). In some other examples, memory system controller 115 can obtain the operating temperature of memory system 110 while receiving one or more read commands requesting boot sequence data from host system 105.

[0046] Based on or in conjunction with obtaining the operating temperature of the memory system 110, the memory system controller 115 may load a table 185 from one or more pages 175 of the memory device 130 (e.g., non-volatile memory) to the local memory 120 (e.g., volatile memory, RAM). Consequently, the memory system controller 115 may identify, from the table 185, a corresponding write temperature 195 for each portion of the boot sequence data. Based on identifying the operating temperature and corresponding write temperature 195 for each portion of the boot sequence data, the memory system controller 115 may select corresponding read settings (e.g., reference voltage, trim settings) for reading each portion of the boot sequence data based on the difference between the operating temperature of the memory system 110 and the corresponding write temperature 195. Thus, based on the selected read settings, the memory system controller 115 may, for example, perform a single read operation at each physical address associated with the LBA 190 listed in the table 185 to obtain the boot sequence data, thereby reducing delays during the boot sequence due to cross-temperature exposure and avoiding system boot timeouts, among other advantages.

[0047] Figure 2 An example of a process flow 200 is shown that supports techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein. Aspects of the process flow 200 may be implemented by aspects of the system 100, as described herein with reference to Figure 1For example, one or more operations of process flow 200 may be performed by memory system controller 115 , local controller 135 , or host system controller 106 . The techniques described in the context of process flow 200 may enable memory system controller 115 to generate and update table 185 .

[0048] At 205, the memory system controller 115 may receive one or more commands (e.g., vendor commands) from the host system controller 106, each command indicating a respective LBA range where a portion of the boot sequence data is to be stored. For example, the host system 105 may provide, via the one or more commands, a list of LBAs 190 to be read during the boot sequence of the system 100. Each of the one or more commands may have one or more (e.g., two) arguments (e.g., portions), where a first argument (e.g., first portion) may be a starting LBA 190 (e.g., LBA_Start) and / or a second argument (e.g., second portion) may be a quantity of LBAs 190 starting from the starting LBA 190 (e.g., LBA_Range). In some examples, one argument may indicate the starting LBA 190 and / or a quantity of LBAs 190 starting from the starting LBA 190. As an illustrative example, the memory system controller 115 may receive a first command indicating a starting LBA 190X and a quantity of LBAs 190Y. Thus, the memory system controller 115 may have an indication that the first portion of the boot sequence data is stored at the physical addresses associated with LBA X through LBA X+Y.

[0049] In some examples, the memory system controller 115 may receive one or more commands at 205 in response to the system image being written to the memory system 110. For example, when writing the system image, the host system 105 may transmit one or more commands (e.g., multiple transmissions of a vendor command) such that the host system 105 may provide the memory system controller 115 with the entire list of LBAs 190 that are read during the boot sequence of the system 100. In such an example, the entire list of LBAs 190 provided by the host system 105 may be fixed during system design (e.g., boot sequence data is not moved to other physical addresses of the memory device 130) such that the host system 105 transmits the command sequence at the beginning of the application lifecycle.

[0050] In some other examples, the memory system controller 115 may receive one or more second commands from the host system 105 indicating an updated LBA range for storing boot sequence data, wherein the host system 105 may provide the updated LBA range in response to a maintenance procedure at the memory system 110. For example, during a maintenance procedure (e.g., system maintenance), the boot sequence data may be stored at a physical address of the memory device 130 that is different from the physical address originally used to store the boot sequence data. Accordingly, the host system 105 may recognize such a change and transmit one or more second commands indicating an updated list of LBAs 190 to be read during the boot sequence of the system 100.

[0051] At 210, the memory system controller 115 may store the list of LBAs 190 provided at 205 in the table 185. That is, the memory system controller 115 may populate the table 185 with the list of LBAs 190 used during the boot sequence of the system 100. For example, the memory system controller 115 may load the table 185 from non-volatile memory to volatile memory and store each LBA or LBA range indicated by the one or more commands in a corresponding entry of the table 185.

[0052] At 215, the memory system controller may receive an indication from the host system controller 106 to enable a cross-temperature management program at the memory system 110, wherein the cross-temperature management program may be referred to herein as Figure 3 Further described. For example, the memory system controller 115 may maintain a register (e.g., a mode register, an information register, etc.) that indicates whether a cross-temperature management routine is enabled during a boot sequence of the system 100. Thus, at 215, the memory system controller 115 may receive an instruction from the host system controller 106 to set the register to a first value (e.g., a logic "1") or a second value (e.g., a default value or a logic "0").

[0053] If the register is set to the second value (e.g., logic "0"), the memory system controller 115 may not perform the cross-temperature management procedure during the boot sequence of the system 100, but may read the boot sequence data without utilizing the table 185 (e.g., during the boot sequence, if the boot sequence data is subjected to cross-temperature exposure, the memory system controller 115 may apply several read options to read the boot sequence data). Alternatively, if the host system 105 sets the value of the register to the first value (e.g., logic "1"), the memory system controller 115 may perform the cross-temperature management procedure utilizing the table 185, as described herein with reference to Figure 3 In some examples, the value of the register may enable or disable the crossover temperature management routine, as described herein with reference to Figure 3Table 1 shows an example of a register.

[0054] By enabling or disabling the cross-temperature management program using the register, the host system 105 can have the flexibility to determine whether to allocate time among different operations during the life of the system in order to minimize the effects of cross-temperature exposure during the boot sequence. That is, because the cross-temperature management program may have some additional operations during the life of the system 100 (e.g., in a powered-on state), the host system 105 can determine whether such operations are beneficial in minimizing the effects of cross-temperature exposure during the boot sequence of the system 100.

[0055] At 220, the memory system controller 115 may identify the write temperature 195 associated with the list of LBAs 190 during a corresponding write operation to write boot sequence data to the physical address associated with the list of LBAs 190 provided at 205. For example, during operation of the memory system 110, the memory system controller 115 may receive one or more write commands to write boot sequence data to the corresponding physical addresses of one or more memory devices 130, may perform one or more maintenance operations (e.g., garbage collection or flushing algorithms) and write boot sequence data to the corresponding physical addresses, or both. Thus, during such write operations, the memory system controller 115 may identify the write temperature 195 (e.g., the operating temperature of the memory device 130 at which the portion of the boot sequence data is being written) and store the write temperature 195 in the local memory 120 (e.g., volatile memory). In this way, the memory system controller 115 may track the corresponding write temperature 195 of the boot sequence data during operation of the memory system 110 (e.g., over the life of the system).

[0056] At 225, the memory system controller 115 may receive an indication to begin a power-off sequence (e.g., to enter a disconnected state or an idle state). For example, before powering off, the host system 105 may transmit a power-off notification command to the memory system 110 to notify the memory system 110 when to power off the system 100, the memory system 110, or both. Thus, during the duration between receiving the power-off notification and powering off, the memory system controller 115 may perform internal operations on one or more memory devices 130. In some examples, if the register is set to a first value (e.g., a logical value of "1") at 215, the host system 105 may transmit a power-off notification to the memory system controller 115, wherein the memory system controller 115 may perform operation 230 during the duration between receiving the power-off notification and powering off (e.g., a power-off notification delay).

[0057] For example, at 230, in response to receiving an indication to begin a power-down sequence, the memory system controller 115 may load table 185 from non-volatile memory into local memory 120 and examine the list of LBAs 190 in table 185. Based on loading table 185 into local memory 120, the memory system controller 115 may update table 185 to include the write temperature 195 identified at 220 for each LBA 190. That is, based on the LBA 190 in table 185, the memory system controller 115 may store the corresponding write temperature 195 for the boot sequence data stored at the associated physical address. In some examples, operation 230 may be performed each time an indication to begin a power-down sequence is received. Alternatively, if no boot sequence data has been written during operation of the memory system 110, the memory system controller 115 may skip performing operation 230. That is, the memory system controller 115 may update table 185 with the write temperature 195 based on whether boot sequence data has been written during operation of the memory system 110. At 235 , the memory system 110 , the system 100 , or both may enter an idle state (eg, an off state or a hibernation state) in response to receiving the power outage notification at 225 .

[0058] Figure 3 An example of a process flow 300 is shown that supports techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein. Aspects of the process flow 300 may be implemented by the system 100, as described herein with reference to Figure 1 For example, the operations of process flow 300 may be implemented by host system controller 106, memory system controller 115, local controller 135, or a combination of such devices. Process flow 300 may be referred to as a cross-temperature management procedure and may be executed during the NAND initialization phase of the boot sequence of system 100 (e.g., at each power-up of system 100).

[0059] At 305, the memory system controller 115 may identify the operating temperature of the memory system 110, the memory device 130, or both during a boot sequence of the system 100. For example, the memory system controller 115 may obtain the current operating temperature of the memory system 110 (e.g., Temp_Boot) from a thermal sensor embedded at the memory system 110 during a NAND initialization phase of the boot sequence of the system 100 (e.g., a preparation phase of the memory device 130).

[0060] At 310, the memory system controller 115 may load the table 185 from one or more pages 175 of the memory device 130 (e.g., non-volatile memory) to the local memory 120 (e.g., volatile memory or RAM) of the memory system controller 115. For example, before loading the table 185 into the local memory 120, the memory system controller 115 may identify (e.g., check) the registers (e.g., as referred to herein). Figure 2 Thus, if the value of the register is set to a first value (e.g., a logic “1”), the memory system controller 115 may have an indication that the crossover thermal management procedure is enabled and load the table 185 from one or more pages 175 of the memory device 130 to the local memory 120 of the memory system controller 115.

[0061] In some examples, the memory system controller 115 may load a portion of the table 185 into the local memory 120, perform operations 315 through 330, and transfer the portion of the table 185 back to the corresponding page 175 of the memory device 130. Thus, the memory system controller 115 may load a second portion of the table into the local memory 120, perform operations 315 through 330, and transfer the portion of the table 185 back to the corresponding page 175 of the memory device 130. Alternatively, the memory system controller 115 may load the entire table 185 into the local memory 120 and perform operations 315 through 330.

[0062] In some examples, if the memory system controller 115 maintains a respective table 185 for each application at the host system 105, the memory system controller 115 may simultaneously load each respective table 185 into the local memory 120, perform operations 315 through 330 using each respective table 185, and return each respective table 185 to the respective page 175 of the memory device 130. Alternatively, in such examples, the memory system controller 115 may load a first table 185 of the respective tables 185 into the local memory 120, perform operations 315 through 330 using the first table 185, and return the first table 185 to the respective page 175 of the memory device 130. The memory system controller 115 may repeat such operations for each table 185.

[0063] At 315, based on loading the table 185 into the local memory 120, the memory system controller 115 may identify a corresponding write temperature 195 (e.g., boot_data_write_operation_temperature) for each LBA 190 associated with the boot sequence data. As an illustrative example, the memory system controller 115 may identify a write temperature 195-a for a first portion of the boot sequence data written to a first physical address associated with LBA 190-a, identify a write temperature 195-b for a second portion of the boot sequence data written to a second physical address associated with LBA 190-b, identify a write temperature 195-c for a third portion of the boot sequence data written to a third physical address associated with LBA 190-c, and identify a write temperature 195-n for an Nth portion of the boot sequence data written to an Nth physical address associated with LBA 190-n. Thus, using the table 185, the memory system controller 115 may identify a corresponding write temperature 195 associated with the boot sequence data stored at the corresponding LBA 190.

[0064] At 320, the memory system controller 115 may select a corresponding read setting from a read setting list (e.g., from a plurality of read settings) based on a difference (e.g., Delta_Temp) between the operating temperature of the memory system 110 and the corresponding write temperature 195 (e.g., based on Delta_Temp, Delta_Temp=Temp_Boot−boot_data_write_operation_temperature). That is, the memory system controller 115 may compare the operating temperature of the memory system 110 with each of the write temperatures 195 to obtain a difference.

[0065] For example, the memory system controller 115 may load a list of available read settings from one or more pages 175 of the memory device 130 (e.g., non-volatile memory) into the local memory 120 (e.g., volatile memory). Each read setting in the list may be a different reference voltage or trim setting and associated with a corresponding temperature range (e.g., a cross-temperature range). Thus, the memory system controller 115 may select a corresponding read setting from the plurality of read settings to read each portion of the boot sequence data, wherein the temperature range associated with the corresponding read setting corresponds to a corresponding difference between the operating temperature of the memory system 110 and the corresponding write temperature 195.

[0066] In some illustrative examples, memory system controller 115 may identify the operating temperature as a first temperature (e.g., 25 degrees Celsius) and identify the write temperature 195-a associated with boot sequence data stored at a physical address associated with LBA 190-a as a second temperature different from the first temperature (e.g., 50 degrees Celsius). Memory system controller 115 may determine the difference between the operating temperature of memory system 110 and write temperature 195-a as a value, such as -25 degrees Celsius (e.g., 25-50 = -25 or an absolute value of 25). Therefore, memory system controller 115 may identify a read setting from the read setting list that has a temperature range that includes and / or encompasses the value (e.g., -25 degrees Celsius or an absolute value of 25 degrees Celsius, between -20 degrees Celsius and -30 degrees Celsius, or between 20 degrees Celsius and 30 degrees Celsius). In this way, memory system controller 115 may identify a read setting for reading boot sequence data associated with LBA 190-a.

[0067] In some other illustrative examples, memory system controller 115 may identify the operating temperature as 100 degrees Celsius and the write temperature 195-a associated with boot sequence data stored at the physical address associated with LBA 190-a as 25 degrees Celsius. Thus, memory system controller 115 may determine the difference between the operating temperature of memory system 110 and write temperature 195-a as 75 degrees Celsius (e.g., 100-25=75). Therefore, memory system controller 115 may identify a read setting from the read setting list that has a temperature range of 75 degrees Celsius. Thus, memory system controller 115 may identify a read setting for reading boot sequence data associated with LBA 190-a.

[0068] At 325, the memory system controller 115 may utilize the corresponding read settings selected at 320 to read boot sequence data from the physical address associated with LBA 190. That is, the memory system controller 115 may apply the selected read settings to obtain boot sequence data during the boot sequence of the system 100. For example, the memory system controller 115 may use the first read setting selected at 320 to read a portion of the boot sequence data associated with LBA 190-a, and use the second read setting selected at 320 to read a portion of the boot sequence data associated with LBA 190-b (e.g., the read settings for reading portions of boot sequence data associated with different LBAs 190 may be different). In this way, the memory system controller 115 may use the corresponding read settings to correctly read the boot sequence data in the event of cross-temperature exposure while also minimizing the impact on read performance. That is, the memory system controller 115 may use the corresponding read settings to perform a single read operation when reading boot sequence data from LBA 190, thereby reducing latency during the boot sequence of the system 100.

[0069] At 330 , the memory system controller 115 may transmit the boot sequence data to the host system 105 in response to reading the boot sequence data according to the corresponding read settings.

[0070] Figure 4 A block diagram 400 is shown of a memory system 420 that supports techniques for managing cross-temperature exposure in a memory system according to examples disclosed herein. The memory system 420 may be a memory system 420 as described in reference to FIG. Figures 1 to 3 , LBA write temperature component 425, read setup component 430, read operation component 435, device temperature component 440, data communication component 445, LBA range component 450, register component 455, power down sequence component 460, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) can communicate directly or indirectly with each other (e.g., via one or more buses).

[0071] The LBA write temperature component 425 may be configured to or otherwise support means for identifying, during a boot sequence of the memory system, a temperature associated with a write operation at an LBA of a first memory device of the memory system, the LBA being associated with a physical address of the first memory device storing a portion of boot sequence data. The read setting component 430 may be configured to or otherwise support means for selecting a read setting from a plurality of read settings based on a difference between an operating temperature of the first memory device during a boot sequence of the memory system and a temperature associated with a write operation at the LBA of the first memory device. The read operation component 435 may be configured to or otherwise support means for reading a portion of the boot sequence data from a physical address associated with the LBA according to the read setting.

[0072] In some examples, to support identifying a temperature associated with a write operation at an LBA, the LBA write temperature component 425 may be configured as or otherwise support means for identifying a temperature from a table comprising a plurality of LBAs and a plurality of temperatures, each of the plurality of temperatures being associated with a respective write operation at each of the plurality of LBAs.

[0073] In some examples, the LBA write temperature component 425 can be configured as or otherwise support means for loading a table from a non-volatile memory of the memory system to a volatile memory of the memory system based on the start of a boot sequence, wherein identifying the temperature from the table is based on loading the table into the volatile memory.

[0074] In some examples, LBA range component 450 may be configured as or otherwise support means for receiving one or more commands from a host system that each indicate an LBA range storing a respective portion of boot sequence data, wherein the plurality of LBAs included in the table are based on the LBA ranges received via the one or more commands.

[0075] In some examples, the first portion of the one or more commands includes a starting LBA and the second portion of the one or more commands includes a quantity of LBAs starting from the starting LBA.

[0076] In some examples, the LBA write temperature component 425 can be configured or otherwise support means for identifying each of the plurality of temperatures during a corresponding write operation at each of the plurality of LBAs. In some examples, the LBA write temperature component 425 can be configured or otherwise support means for storing each of the plurality of temperatures in a corresponding entry in a table based on the identification.

[0077] In some examples, the power off sequence component 460 can be configured as or otherwise support means for receiving an indication from the host system to initiate a power off sequence, wherein storing each of the plurality of temperatures is based on the indication to initiate the power off sequence.

[0078] In some examples, the device temperature component 440 can be configured as or otherwise support means for identifying an operating temperature of the first memory device during a boot sequence, wherein selecting the read setting is based on identifying the operating temperature of the first memory device.

[0079] In some examples, data communication component 445 can be configured or otherwise support means for transmitting a portion of the boot sequence data to the host system based on reading the portion of the boot sequence data from the physical address according to the read setting.

[0080] In some examples, identifying a temperature associated with a write operation of the LBA at the first memory device is based on a register at the memory system being set to a first value.

[0081] In some examples, register component 455 can be configured or otherwise support means for receiving an indication from a host system to set a register to a first value.

[0082] In some examples, the LBA write temperature component 425 can be configured to or otherwise support means for identifying, during a boot sequence, a second temperature associated with a second write operation at a second LBA of the first memory device, the second LBA being associated with a second physical address storing a second portion of the boot sequence data. In some examples, the read setting component 430 can be configured to or otherwise support means for selecting a second read setting from a plurality of read settings based on a difference between the operating temperature and the second temperature. In some examples, the read operation component 435 can be configured to or otherwise support means for reading the second portion of the boot sequence data from the second physical address according to the second read setting.

[0083] In some examples, the read settings include a reference voltage to be applied to one or more memory cells associated with the physical address.

[0084] In some examples, the plurality of read settings are stored in a non-volatile memory of the memory system.

[0085] In some examples, the described functionality of the memory system 420 or its various components may be supported by or may refer to at least a portion of at least one processor, where the at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more such elements). In some examples, the described functionality of the memory system 420 or its various components may be implemented at least in part by instructions (e.g., stored in memory, a non-transitory computer-readable medium) that are executable by the at least one processor.

[0086] Figure 5 A block diagram 500 is shown of a host system 520 supporting techniques for managing cross temperature exposure in a memory system according to examples as disclosed herein. The host system 520 may be a Figures 1 to 3 , LBA range update component 540, or any combination thereof. Components of each of these components or subcomponents thereof (e.g., one or more processors, one or more memories) may communicate directly or indirectly with each other (e.g., via one or more buses).

[0087] The LBA range indication component 525 may be configured to or otherwise support means for transmitting one or more commands to the memory system, each command indicating an LBA range in which a portion of the boot sequence data is stored. The register setting component 530 may be configured to or otherwise support means for transmitting to the memory system an indication to enable a cross-temperature management program at the memory system. The data communication component 535 may be configured to or otherwise support means for receiving boot sequence data from the memory system during a boot sequence of the memory system based on transmitting the indication to enable the cross-temperature management program.

[0088] In some examples, to support transmitting an indication to enable a cross-temperature management procedure, register setting component 530 can be configured as or otherwise support means for transmitting an indication for the memory system to set a register to a first value.

[0089] In some examples, LBA range update component 540 can be configured as or otherwise support means for transmitting one or more second commands to the memory system and based on a maintenance procedure at the memory system indicating an updated LBA range storing boot sequence data.

[0090] In some examples, the first portion of the one or more commands includes a starting LBA and the second portion of the one or more commands includes a quantity of LBAs starting from the starting LBA.

[0091] In some examples, the described functionality of the host system 520 or its various components may be supported by or may refer to at least a portion of at least one processor, where the at least one processor may include one or more processing elements (e.g., a controller, a microprocessor, a microcontroller, a digital signal processor, a state machine, discrete gate logic, discrete transistor logic, discrete hardware components, or any combination of one or more such elements). In some examples, the described functionality of the host system 520 or its various components may be implemented at least in part by instructions (e.g., stored in memory, a non-transitory computer-readable medium) that are executable by the at least one processor.

[0092] Figure 6 A flowchart showing a method 600 for supporting techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein. The operations of the method 600 may be implemented by a memory system or components thereof as described herein. For example, the operations of the method 600 may be implemented by a memory system or components thereof as described herein. Figures 1 to 4 In some examples, the memory system may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally, or alternatively, the memory system may use dedicated hardware to perform aspects of the described functions.

[0093] At 605, the method may include identifying a temperature associated with a write operation at an LBA of a first memory device of the memory system during a boot sequence of the memory system, the LBA being associated with a physical address of the first memory device storing a portion of boot sequence data. The operations of 605 may be performed according to examples as disclosed herein. For example, the memory system controller 115 (e.g., as described herein with reference to Figure 1 ) may include an LBA write temperature component 425 (eg, as described herein with reference to Figure 4 ), which identifies a temperature associated with a write operation at an LBA (e.g., as described herein, including reference to Figure 3 315 of the operation).

[0094] At 610, the method may include selecting a read setting from a plurality of read settings based on a difference between an operating temperature of the first memory device and a temperature of a write operation at an LBA associated with the first memory device during a boot sequence of the memory system. The operations of 610 may be performed according to examples as disclosed herein. For example, the memory system controller 115 (e.g., as described herein with reference to Figure 1 ) may include a read setup component 430 (e.g., as described herein with reference to Figure 4 ), which selects a read setting (e.g., as described herein, including reference Figure 3 320 of the operation).

[0095] At 615, the method may include reading a portion of the boot sequence data from a physical address associated with the LBA according to the read setting. The operation of 615 may be performed according to examples as disclosed herein. For example, a memory system controller (e.g., as described herein with reference to Figure 1 ) may include a read operation component 435 (e.g., as described in reference Figure 4 ), which performs a read operation of reading a portion of the boot sequence data according to the selected read settings (e.g., as described herein, including reference Figure 3 325 of the operation).

[0096] In some examples, an apparatus as described herein may perform a method or methods, such as method 600. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0097] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for: identifying, during a boot sequence of a memory system, a temperature associated with a write operation at an LBA of a first memory device of the memory system, the LBA being associated with a physical address of the first memory device storing a portion of boot sequence data; selecting a read setting from a plurality of read settings based on a difference between an operating temperature of the first memory device during the boot sequence of the memory system and the temperature associated with the write operation at the LBA of the first memory device; and reading the portion of the boot sequence data from the physical address associated with the LBA according to the read setting.

[0098] Aspect 2: The method, apparatus, or non-transitory computer-readable medium of Aspect 1, wherein identifying the temperature associated with the write operation at the LBA comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for identifying the temperature from a table comprising a plurality of LBAs and a plurality of temperatures, each of the plurality of temperatures being associated with a corresponding write operation at each of the plurality of LBAs.

[0099] Aspect 3: The method, apparatus, or non-transitory computer-readable medium of Aspect 2, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: loading the table from a non-volatile memory of the memory system to a volatile memory of the memory system based on the start of the boot sequence, wherein identifying the temperature from the table is based on loading the table into the volatile memory.

[0100] Aspect 4: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 2 to 3, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for receiving one or more commands from a host system, each indicating an LBA range in which a corresponding portion of the boot sequence data is stored, wherein the multiple LBAs included in the table are based on the LBA range received via the one or more commands.

[0101] Aspect 5: The method, apparatus, or non-transitory computer-readable medium of Aspect 4, wherein the first portion of the one or more commands includes a starting LBA and the second portion of the one or more commands includes a certain number of LBAs starting from the starting LBA.

[0102] Aspect 6: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 2 to 5, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for identifying each of the multiple temperatures during the corresponding write operation at each LBA in the multiple LBAs and storing each of the multiple temperatures to a corresponding entry in the table based on the identification.

[0103] Aspect 7: The method, apparatus, or non-transitory computer-readable medium of Aspect 6, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: receiving an indication from a host system to start a power-off sequence, wherein each of the plurality of temperatures stored is based on the indication to start the power-off sequence.

[0104] Aspect 8: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 7, further comprising operations, features, circuitry, logic, means, or instructions, or any combination thereof, for identifying the operating temperature of the first memory device during the boot sequence, wherein selecting the read setting is based on identifying the operating temperature of the first memory device.

[0105] Aspect 9: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 8, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transmitting the portion of the boot sequence data to a host system based on reading the portion of the boot sequence data from the physical address according to the read setting.

[0106] Aspect 10: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 9, wherein identifying the temperature associated with the write operation of the LBA at the first memory device is based on a register at the memory system being set to a first value.

[0107] Aspect 11: The method, apparatus, or non-transitory computer-readable medium of Aspect 10, further comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: receiving an indication from a host system to set the register to the first value.

[0108] Aspect 12: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 1 to 11, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: identifying a second temperature associated with a second write operation at a second LBA of the first memory device during the boot sequence, the second LBA being associated with a second physical address storing a second portion of the boot sequence data; selecting a second read setting from the plurality of read settings based on a difference between the operating temperature and the second temperature; and reading the second portion of the boot sequence data from the second physical address according to the second read setting.

[0109] Aspect 13: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1-12, wherein the read setting comprises a reference voltage applied to one or more memory cells associated with the physical address.

[0110] Aspect 14: The method, apparatus, or non-transitory computer-readable medium of any one of Aspects 1 to 13, wherein the plurality of read settings are stored in a non-volatile memory of the memory system.

[0111] Figure 7 A flowchart showing a method 700 for supporting techniques for managing cross-temperature exposure in a memory system according to examples as disclosed herein. The operations of the method 700 may be implemented by a host system or components thereof as described herein. For example, the operations of the method 700 may be implemented by a host system or components thereof as described herein. Figures 1 to 35. In some examples, the host system may execute a set of instructions to control the functional elements of the device to perform the described functions. In addition, or alternatively, the host system may use dedicated hardware to perform aspects of the described functions.

[0112] At 705, the method may include transmitting one or more commands to the memory system, each command indicating an LBA range in which a portion of the boot sequence data is stored. The operations of 705 may be performed according to examples as disclosed herein. For example, the host system controller 106 (e.g., as described herein with reference to Figure 1 ) may include an LBA range indication component 525 (e.g., as described in reference Figure 5 ), which transmits one or more commands to a memory system (e.g., as described herein, including reference Figure 2 205 of the operation).

[0113] At 710, the method may include transmitting an indication to the memory system that a cross-temperature management program is enabled at the memory system. The operation of 705 may be performed according to examples as disclosed herein. For example, the host system controller 106 (e.g., as described herein with reference to Figure 1 ) may include a register setting component 530 (e.g., as described in reference Figure 5 ), which transmits an indication that a crossover temperature management program is enabled (e.g., as described herein, including reference to Figure 2 215 of the operation).

[0114] At 715, the method may include receiving boot sequence data from the memory system based on transmitting an indication of enabling the cross-temperature management program during a boot sequence of the memory system. The operations of 715 may be performed according to examples as disclosed herein. For example, the host system controller 106 (e.g., as described herein with reference to Figure 1 ) may include a data communication component 535 (e.g., as described in reference Figure 5 ), which receives boot sequence data from a memory system (e.g., as described herein, including reference Figure 3 330 of the operation).

[0115] In some examples, an apparatus as described herein may perform a method or methods, such as method 700. The apparatus may include features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for performing the following aspects of the present disclosure, or any combination thereof:

[0116] Aspect 15: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuit systems, logic, means, or instructions, or any combination thereof, for: transmitting one or more commands to a memory system, each command indicating an LBA range in which a portion of boot sequence data is stored; transmitting an indication to the memory system to enable a cross-temperature management program at the memory system; and receiving the boot sequence data from the memory system during a boot sequence of the memory system based on transmitting the indication to enable the cross-temperature management program.

[0117] Aspect 16: A method, apparatus, or non-transitory computer-readable medium according to Aspect 15, wherein transmitting the indication to enable the cross-temperature management program includes operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for: transmitting an indication for the memory system to set a register to a first value.

[0118] Aspect 17: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 15 to 16, further comprising operations, features, circuit systems, logic, components, or instructions, or any combination thereof, for transmitting to the memory system and based on a maintenance program at the memory system one or more second commands indicating an updated LBA range for storing the boot sequence data.

[0119] Aspect 18: A method, apparatus, or non-transitory computer-readable medium according to any one of Aspects 15 to 17, wherein the first portion of the one or more commands includes a starting LBA and the second portion of the one or more commands includes a certain number of LBAs starting from the starting LBA.

[0120] It should be noted that the described techniques include possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, portions from two or more methods may be combined.

[0121] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, the signal may represent a signal bus, where the bus may have various bit widths.

[0122] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports signal flow between the components. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if any conductive path exists between the components that can readily support signal flow between the components. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components or an indirect conductive path between the connected components may include intermediate components such as switches, transistors, or other components. In some examples, the signal flow between the connected components may be interrupted for a period of time, for example, using one or more intermediate components such as switches or transistors.

[0123] The term "coupled" (e.g., "electrically coupled") may refer to a condition whereby components move from an open-circuit relationship (where signals are currently unable to communicate between the components via a conductive path) to a closed-circuit relationship (where signals are able to communicate between the components via a conductive path). If a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between the other components via conductive paths that previously did not allow signal flow.

[0124] The term "isolation" refers to a relationship between components where a signal cannot flow between them. If an open circuit exists between the components, the components are isolated from each other. For example, if a switch located between the components is open, the two components separated by the switch are isolated from each other. If a controller isolates two components, the controller causes a change that prevents a signal from flowing between the components using the conductive path that previously allowed signal flow.

[0125] The terms "if," "when," "based on," or "based at least in part on" are used interchangeably. In some instances, the terms "if," "when," "based on," or "based at least in part on" are interchangeable if they are used to describe a connection between conditional actions, conditional processes, or portions of processes.

[0126] The term "in response to" may refer to a condition or action that occurs at least in part, if not entirely, as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions that occur after the first condition or action).

[0127] In addition, the term "directly in response to" or "in direct response to" may refer to a condition or action that occurs as a direct result of a previous condition or action. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of the previous condition or action occurring, regardless of whether other conditions or actions occur. In some instances, a first condition or action may be performed and a second condition or action may occur directly as a result of the previous condition or action occurring, such that no other intervening conditions or actions occur between the earlier condition or action and the second condition or action, or a limited number of one or more intermediate steps or actions occur between the earlier condition or action and the second condition or action. Any condition or action described herein as being performed "based on," "based at least in part on," or "in response to" some other step, action, event, or condition may be performed additionally or alternatively (e.g., in alternative instances) "in direct response to" or "directly in response to" this other condition or action, unless otherwise specified.

[0128] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate (e.g., silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, etc.). In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or any other doping means.

[0129] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be capped by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "switched on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor may be "switched off" or "deactivated."

[0130] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "superior to other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0131] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. When only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0132] The functions described herein may be implemented in hardware, software executed by a processing system (e.g., one or more processors, one or more controllers, control circuitry, processing circuitry, logic circuitry), firmware, or any combination thereof. If implemented in software executed by a processing system, the functions may be stored on or transmitted over a computer-readable medium as one or more instructions (e.g., code). Due to the nature of software, the functions described herein may be implemented using software executed by a processing system, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functions may be physically located at various locations, including portions distributed so that the functions are implemented at different physical locations.

[0133] For example, the illustrative blocks and modules described herein may be implemented or executed using one or more processors (e.g., DSPs, ASICs, FPGAs, discrete gate logic or discrete transistor logic, discrete hardware components, other programmable logic devices, or any combination thereof) designed to perform the functions described herein. A processor may be an example of a microprocessor, a controller, a microcontroller, a state machine, or other type of processor. A processor may also be implemented as at least one of one or more computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0134] As used herein (including in the claims), "or" as used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, so that a list such as at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an example step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0135] As used herein (including in the claims), the articles "a" and "an" preceding nouns are open-ended and should be understood to refer to "at least one" of those nouns or "one or more" of those nouns. Thus, the terms "a," "at least one," "one or more," and "at least one of one or more" may be interchangeable. For example, if a claim recites a "component" that performs one or more functions, each of the individual functions may be performed by a single component or by any combination of multiple components. Thus, the term "component" having a characteristic or performing a function may refer to "at least one of one or more components" that has a particular characteristic or performs a particular function. Subsequent references to a component introduced with the article "a" using the terms "the" or "said" may refer to any one or all of the one or more components. For example, a component introduced with the article "a" may be understood to mean "one or more components," and subsequent references in the claims to "said component" may be understood to be equivalent to references to "at least one of one or more components." Similarly, subsequent reference to a component introduced as "one or more components" using the term "the" or "said" may refer to any or all of the one or more components. For example, reference to "one or more components" later in a claim may be understood as equivalent to reference to "at least one of the one or more components."

[0136] Computer-readable media include both non-transitory computer storage media and communication media, and the communication media include any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0137] This description is provided to enable one skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory system comprising: one or more memory devices; and processing circuitry coupled to the one or more memory devices and configured to cause the memory system to: identifying, during a boot sequence of the memory system, a temperature associated with a write operation at a logical block address (LBA) of a first memory device of the one or more memory devices, the LBA being associated with a physical address of the first memory device storing a portion of boot sequence data; selecting a read setting from a plurality of read settings based on a difference between an operating temperature of the first memory device during the boot sequence of the memory system and the temperature associated with the write operation at the LBA of the first memory device; and The portion of the boot sequence data is read from the physical address associated with the LBA according to the read setting.

2. The memory system of claim 1 , wherein to identify the temperature associated with the write operation at the LBA, the processing circuitry is configured to cause the memory system to: The temperature is identified from a table comprising a plurality of LBAs and a plurality of temperatures, each of the plurality of temperatures being associated with a respective write operation at each LBA of the plurality of LBAs.

3. The memory system of claim 2 , wherein the processing circuitry is further configured to cause the memory system to: The table is loaded from a non-volatile memory of the memory system to a volatile memory of the memory system based on initiation of the boot sequence, wherein identifying the temperature from the table is based on loading the table into the volatile memory.

4. The memory system of claim 2 , wherein the processing circuitry is configured to cause the memory system to: One or more commands are received from a host system, each indicating an LBA range where a respective portion of the boot sequence data is stored, wherein the plurality of LBAs included in the table are based on the LBA ranges received via the one or more commands. 5 . The memory system of claim 4 , wherein a first portion of the one or more commands includes a starting LBA and a second portion of the one or more commands includes a quantity of LBAs starting from the starting LBA.

6. The memory system of claim 2, wherein the processing circuitry is configured to cause the memory system to: identifying each of the plurality of temperatures during the corresponding write operation at each LBA in the plurality of LBAs; and Each of the plurality of temperatures is stored to a respective entry in the table based on the identification.

7. The memory system of claim 6, wherein the processing circuitry is configured to cause the memory system to: An indication to initiate a power down sequence is received from a host system, wherein storing each of the plurality of temperatures is based on the indication to initiate the power down sequence.

8. The memory system of claim 1 , wherein the processing circuitry is configured to cause the memory system to: The operating temperature of the first memory device is identified during the boot sequence, wherein selecting the read setting is based on identifying the operating temperature of the first memory device.

9. The memory system of claim 1 , wherein the processing circuitry is configured to cause the memory system to: The portion of the boot sequence data is transferred to a host system based on reading the portion of the boot sequence data from the physical address according to the read setting.

10. The memory system of claim 1, wherein identifying the temperature associated with the write operation of the LBA at the first memory device is based on a register at the memory system being set to a first value.

11. The memory system of claim 10, wherein the processing circuitry is configured to cause the memory system to: An indication is received from a host system to set the register to the first value.

12. The memory system of claim 1 , wherein the processing circuitry is configured to cause the memory system to: identifying, during the boot sequence, a second temperature associated with a second write operation at a second LBA of the first memory device, the second LBA being associated with a second physical address storing a second portion of the boot sequence data; selecting a second read setting from the plurality of read settings based on a difference between the operating temperature and the second temperature; and The second portion of the boot sequence data is read from the second physical address according to the second read setting.

13. The memory system of claim 1, wherein the read settings comprise a reference voltage to be applied to one or more memory cells associated with the physical address.

14. The memory system of claim 1, wherein the plurality of read settings are stored in a non-volatile memory of the memory system.

15. A host system comprising: one or more interfaces comprising one or more signal paths operable to communicate with one or more memory systems; as well as processing circuitry coupled to the one or more interfaces and configured to cause the host system to: transmitting one or more commands to a first memory system of the one or more memory systems, each command indicating a logical block address (LBA) range where a portion of boot sequence data is stored; transmitting to the first memory system an indication to enable a crossover thermal management procedure at the first memory system; and During a boot sequence of the first memory system, the boot sequence data is received from the first memory system based on transmitting the indication to enable the cross-temperature management procedure.

16. The memory system of claim 15, wherein to transmit the indication to enable the cross-temperature management procedure, the processing circuitry is configured to cause the host system to: An indication is transmitted for the first memory system to set a register to a first value.

17. The host system of claim 15, wherein the processing circuitry is further configured to cause the host system to: One or more second commands are transmitted to the first memory system and based on a maintenance procedure at the first memory system that indicate an updated LBA range in which to store the boot sequence data.

18. The host system of claim 15, wherein a first portion of the one or more commands includes a starting LBA and a second portion of the one or more commands includes a quantity of LBAs starting from the starting LBA.

19. A system comprising: a memory system comprising one or more controllers and one or more memory devices coupled to the one or more controllers; as well as a host system coupled to the memory system and comprising one or more controllers, the one or more controllers of the host system configured to cause the host system to: transmitting one or more commands to the memory system, each command indicating a corresponding logical block address (LBA) range storing a portion of boot sequence data; and transmitting to the memory system an indication to enable a crossover thermal management procedure at the memory system, the one or more controllers of the memory system being configured to cause the memory system to: selecting a read setting from a plurality of read settings based on a difference between an operating temperature of a first memory device of the one or more memory devices and a temperature associated with a write operation at a LBA of the first memory device; and A portion of the boot sequence data is read from a physical address associated with the LBA according to the read setting.

20. The system of claim 19, wherein the one or more controllers of the memory system are configured to cause the memory system to: The temperature associated with the write operation at each of the plurality of LBAs is identified from a table comprising a plurality of LBAs and a plurality of temperatures each associated with a respective write operation at the LBA, wherein selecting the read setting is based on identifying the temperature from the table.

21. The system of claim 19, wherein to transmit the indication to enable the cross-temperature management procedure, the one or more controllers of the host system are configured to cause the host system to: An indication is transmitted for the memory system to set a register to a first value, wherein selecting the read setting is based on the register being set to the first value.

22. The system of claim 19, wherein the one or more controllers of the memory system are configured to cause the memory system to: The operating temperature of the first memory device is identified during a boot sequence of the memory system, wherein selecting the read setting is based on identifying the operating temperature.

23. The system of claim 19, wherein a first portion of the one or more commands includes a starting LBA and a second portion of the one or more commands includes a quantity of LBAs starting from the starting LBA.

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