Decoder circuit and decoding method used therefor
By optimizing the operation process of the decoder circuit and reducing the number of read/write times of the memory, the problem of excessive power consumption in the prior art is solved, and a decoder circuit design with lower energy consumption is achieved.
Patent Information
- Application Number
- CN202410319729.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-07
- Filing Date
- 2024-03-20
- Publication Date
- 2025-09-09
AI Technical Summary
Existing decoder circuits consume excessive power when performing hardware calculations, primarily due to the high number of bits of information leading to frequent memory read/write operations.
A novel decoding method is adopted to reduce the number of read/write times of the variable node unit to the memory. The operation process of the decoder circuit is adjusted to reduce power consumption by utilizing the combination of channel value memory, sign memory, gradient descent bit memory, variable node unit, check node unit, first barrel shifter and decision bit output unit.
The power consumption of the decoder circuit is significantly reduced, especially by reducing the number of memory read/write times, thereby reducing the energy consumption of hardware calculations.
Smart Images
Figure CN120612974A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a decoding mechanism, and more particularly to a decoder circuit and a decoding method used in the decoder circuit. Background Art
[0002] Generally speaking, a circuit element (such as a conventional variable node unit) within a conventional decoder circuit needs to read / write bit information stored in one or more specific memories each time it performs a corresponding sum operation. Currently, in existing mechanisms, the number of bits of bit information in the one or more specific memories is too large, resulting in excessive power consumption when performing hardware calculations in the conventional decoder circuit. Summary of the Invention
[0003] Therefore, one of the objectives of the present invention is to provide a decoder circuit and a decoding method with a novel algorithm mechanism to solve the problems of the prior art.
[0004] According to an embodiment of the present invention, a decoder circuit is disclosed. The decoder circuit includes a channel value memory, a sign memory, a gradient descent bit memory, a variable node unit, a first barrel shifter, a check node unit, a second barrel shifter, and a decision bit output unit. The channel value memory is used to receive and store input data as a channel value, wherein the channel value is stored in the channel value memory in the form of a sign bit and a plurality of value size bits. The sign memory is used to store a sign value. The gradient descent bit memory is used to store difference information corresponding to the channel value. The variable node unit is coupled to the channel value memory, the sign memory, and the gradient descent bit memory, and is used to generate a first output value and a second output value based on the channel value. The first barrel shifter is coupled to the variable node unit and is used to convert the first output value from a variable node domain to a check node domain to generate a converted first output value. A check node unit is coupled to the first barrel shifter and configured to generate check-variable information based on the converted first output value or a sign value stored in the sign memory. A second barrel shifter is coupled to the check node unit and configured to convert the check-variable information from the check node field to the variable node field to generate converted check-variable information for the variable node unit. A decision bit output unit is coupled to the gradient descent bit memory and the channel value memory and configured to generate and determine output data based on difference information corresponding to the channel value in the channel value memory and the channel value stored in the gradient descent bit memory.
[0005] According to an embodiment of the present invention, a decoding method used in a decoder circuit is disclosed. The decoding method includes: providing a channel value memory to receive and store input data as a channel value, wherein the channel value is stored in the channel value memory in the form of a sign bit and a plurality of magnitude bits; providing a sign memory to store a sign value; providing a gradient descent bit memory to store difference information corresponding to the channel value; providing a variable node unit to generate a first output value and a second output value based on the channel value; providing a first barrel shifter to convert the first output value from a variable node field to a check node field to generate a converted first output value; providing a check node unit to generate check-variable information based on the converted first output value or a sign value stored in the sign memory; providing a second barrel shifter to convert the check-variable information from the check node field to the variable node field to generate converted check-variable information to the variable node unit; and generating and determining output data based on the difference information corresponding to the channel value in the channel value memory and the channel value stored in the gradient descent bit memory. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figure 1 FIG. 4 is a schematic diagram of a decoder circuit in a flash memory controller according to an embodiment of the present invention.
[0007] Figure 2 According to one embodiment of the present invention, Figure 1 A schematic diagram of a flash memory controller showing a decoder circuit is shown.
[0008] Figure 3 FIG. 4 is a schematic diagram of an operation flow of a decoding method of a decoder circuit according to an embodiment of the present invention.
[0009]
Explanation of symbols
[0010] 100:Decoder circuit
[0011] 105: Channel value memory
[0012] 110:Symbol Memory
[0013] 115: Gradient Descent Bit Memory
[0014] 120: variable node unit
[0015] 125: Check node unit
[0016] 130: First Bucket Shifter
[0017] 135: Second barrel shifter
[0018] 140: Decision bit output unit
[0019] 200: Flash memory controller
[0020] 201: Host device
[0021] 202: Flash memory
[0022] 205: Randomizer
[0023] 210: Encoder
[0024] 215:Derandomizer DETAILED DESCRIPTION
[0025] The present invention aims to provide a decoding method and decoder circuit capable of reducing power consumption when a decoder circuit reads or writes a memory (or register). This method and decoder circuit utilize a novel algorithm to reduce the number of reads and writes to at least one memory, thereby reducing power consumption. The decoding method and decoder circuit provided by the present invention are applicable to all application-specific integrated circuit (ASIC) products and all field-programmable gate array (FPGA) products.
[0026] Please refer to Figure 1 , Figure 1 FIG2 is a schematic diagram of a decoder circuit 100 within a flash memory controller according to an embodiment of the present invention. The decoder circuit 100 includes a channel value memory 105, a sign memory 110, such as a q sign memory, a gradient descent bit memory 115, a variable node unit (VNU) 120, a check node unit (CNU) 125, a first barrel shifter 130, a second barrel shifter 135, and a decision bit output unit 140. The variable node unit 120, the check node unit 125, and the decision bit output unit 140 are all implemented as hardware circuits or firmware circuits.
[0027] Specifically, the value of an input data initially received by the decoder circuit 100 is stored in the channel value memory 105. In one embodiment, the decoder circuit 100 is applied to a storage device, for example, and thus the value of the received input data may be data read from one or more flash memories of the storage device. If the decoder circuit 100 is applied to a communication system, the value of the received input data may be data received from a mobile communication device such as a mobile phone. In addition, the channel value memory 105 may receive and store the value of the input data in the form of a code word. Next, the variable node unit 120 reads the input data (i.e., the stored code word) from the channel value memory 105.
[0028] It should be noted that in the following paragraphs, “channel value” is uniformly used to represent a value received by the decoder circuit 100 and stored in the channel value memory 105 . Furthermore, when the decoder circuit 100 is applied to a storage device having one or more flash memories, for example, a sensing read is performed on the potential of a specific bit of a codeword stored in the flash memory. For example, a reference voltage level is used to read the potential of the specific bit to generate a sign bit and a plurality of magnitude bits representing the potential of the specific bit. The sign bit is used to indicate on which side of the reference voltage level the potential of the specific bit is located, and the plurality of magnitude bits are used to indicate an absolute value of the difference between the potential of the specific bit and the reference voltage level. The greater the number of magnitude bits used, the more accurate the sensing read result can be. Therefore, in this embodiment, in practice, a channel value stored in the channel value memory 105 refers to a channel value including the sign bit and the plurality of magnitude bits. Similarly, when the decoder circuit 100 is applied to a communication system, for example, a channel value may include a numerical value transmitted by a transmission medium / channel in the communication system and may also be stored in the channel value memory 105 via a sign bit and multiple value size bits.
[0029] In one embodiment, the decoder circuit 100 is a low-density parity check code (LDPC) code decoder circuit and performs an LDPC decoding operation based on a standard column-layered min-sum algorithm. The variable node unit 120 is configured to perform a vertical step summation operation in the LDPC decoding operation, and the check node unit 125 is configured to perform a horizontal step minimization operation in the LDPC decoding operation.
[0030] The following briefly describes the concept of the row-level minimum-sum algorithm. An input data is a binary LDPC codeword C. The corresponding parity check matrix has M rows and N columns and is represented by H. Each column of the corresponding parity check matrix H corresponds to a corresponding check node, and each row of the corresponding parity check matrix H corresponds to a variable node. N(c) = {v:H cv =1} to represent a set of variable nodes that participate in the operation of a check node c, and M(v)={c:H cv =1} to represent a set of check nodes that participate in the operation of a variable node v. v Represented as the intrinsic message of a variable node v, R cv It is represented as a check-to-variable message transmitted from a check node c to a variable node v, which can also be called an R message. cv It is represented as a variable-to-check message transmitted from a variable node v to a check node c, which can also be called a Q value (Q message). A codeword with N bits is divided into G groups of the same size, and the G groups are represented as N0, N0, ..., N G-1 , and the corresponding parity check matrix H is also divided into G block columns of the same size. The iterative decoding concept of the layered minimum-sum algorithm can be described by the following equation. First, at the initialization:
[0031] L cv =I v for v=0,1,…,N-1,c=0,1,…,M-1;
[0032] Then, during the iterative decoding process from the first iteration to the maximum iteration number, for each of the G groups, that is, group N g , where g = 0, 1, ... G-1, in the horizontal step for the connection to a specific group N g Each check node c of the variable node v has a value R cv The algorithm is expressed as follows:
[0033]
[0034] Furthermore, in the vertical step for the g Each variable node v, Q value L cv With L v The calculation and update of the value of is expressed as follows:
[0035]
[0036]
[0037] In the iterative decoding process of the layered minimum-sum algorithm in this row, L v The positive / negative sign of the value is used to make a hard decision to determine the information of the specific bit ('0' or '1'). When a valid codeword is found, the above-mentioned iterative decoding operation can be interrupted and the decoding operation is completed.
[0038] In practice, in order to reduce the power consumption of memory storage and access when performing the above-mentioned iterative decoding operation, an embodiment of the present invention adjusts and controls the operation of the variable node unit 120 based on the concept of the above-mentioned row-level minimum-sum algorithm to reduce the read / write requirements of the variable node unit 120 for one or more memories, thereby achieving the purpose of reducing power consumption.
[0039] When the first iterative decoding operation is performed on the information sensed and read from the specific bit (i.e., a channel value), the variable node unit 120 reads a sign bit and multiple value size bits corresponding to the channel value from the channel value memory 105. During the subsequent iterative decoding operations of the same decoding operation, the variable node unit 120 will not read the sign bit from the channel value memory 105, but will only read the multiple value size bits to reduce the read / write operations on the channel value memory 105. Therefore, each subsequent iteration can reduce the reading of one bit. Furthermore, regarding reading and writing of the q-value symbol memory 110, the variable node unit 120 does not write to the q-value symbol memory 110 during the first iterative decoding operation. In subsequent decoding operations, only when a first output value processed, calculated, or updated by the variable node unit 120 changes will a symbol value of the changed first output value be written and stored in the q-value symbol memory 110 to replace and update the previously stored symbol value. A symbol value, for example, uses a single bit of information, '1' or '0', to indicate whether the symbol value is positive or negative, or uses a single bit of information, '0' or '1', to indicate whether the symbol value is positive or negative. Furthermore, with respect to reading / writing the gradient descent bit memory 115, the variable node unit 120 does not write to the gradient descent bit memory 115 during the first iterative decoding operation. Furthermore, in subsequent iterative decoding operations, only when a second output value processed, calculated, or updated by the variable node unit 120 changes will a sign value of the changed second output value be written to the gradient descent bit memory 115.
[0040] It should be noted that compared to the conventional decoding technology, the variable node unit 120 updates and generates the Q value to a conventional barrel shifter and updates and stores the L v The variable node unit 120 in the embodiment of the present invention is changed to update and generate a first output value to replace the output of the Q value and update and generate a second output value to replace the L value. v The output of the sign value of the value can reduce the number of memory read / write times.
[0041] The following briefly describes the process of multiple iterative decoding operations. Initially, during the first iterative decoding operation, the variable node unit 120 reads a channel value ch_v from the channel value memory 105. At this time, the variable node unit 120 reads a sign bit and a plurality of magnitude bits corresponding to the channel value ch_v from the channel value memory 105. Next, the variable node unit 120 uses the channel value ch_v as the first output value and the second output value. The first output value (i.e., the channel value ch_v) is read by the first barrel shifter 130 and serves as the input of the first barrel shifter 130. The second output value (i.e., the channel value ch_v) is not written by the variable node unit 120 to the gradient descent bit memory 115. Next, the first barrel shifter 130 converts the first output value from the variable node domain to the check node domain to generate a converted first output value. Next, since the variable node unit 120 does not write a symbol value of the first output value to the q-value symbol memory 110 in the first iterative decoding operation, the check node unit 125 does not need to read the symbol value of the q-value symbol memory 110, but only needs to calculate the symbol value based on the R value R cv The algorithm formula is used to minimize the converted first output value to generate and output an R value (i.e., check-variable information). Then, the second barrel shifter 135 is used to convert the R value from the check node field to the variable node field to generate a converted R value.
[0042] Then, during the second iterative decoding operation, the variable node unit 120 generates and updates the first output value according to the following formula:
[0043] qval_out i =abs(ch_v)+ΣR-R i
[0044] where qval_out i is the first output value generated and updated by the second iterative decoding operation; abs(ch_v) is an absolute value of the channel value ch_v. Therefore, in practice, the variable node unit 120 only needs to read multiple value bits of the channel value ch_v from the channel value memory 105 to calculate the absolute value during the second iterative decoding operation, without having to read the sign bit of the channel value ch_v; ∑R is the sum of the converted R values of multiple adjacent bits previously generated by the variable node unit 120; R iis the converted R value generated by the second barrel shifter 135 in the previous iterative decoding operation. In addition, since in the second iterative decoding operation, the first output value generated by the variable node unit 120 has changed from the channel value ch_v in the first iterative decoding operation to the above qval_out i Therefore, when the value of the first output value changes, the variable node unit 120 will change the first output value (ie, qval_out i ) (i.e. abs(qval_out i )) is written into the q-value symbol memory 110, replacing the symbol value originally recorded in the q-value symbol memory 110. Similarly, the operations and functions of the first barrel shifter 130, the second barrel shifter 135, and the check node unit 125 in the second iterative decoding operation are the same as or similar to those in the first iterative decoding operation, and thus are not repeated here.
[0045] Then, in the third iterative decoding operation (or the subsequent n-th iterative decoding operation), the operation of the variable node unit 120 is similar to that in the second iterative decoding operation, and the first output value qval_out is also calculated and updated. i =abs(ch_v)+∑RR i At this time, the variable node unit 120 can read a previous symbol value stored in the previous iterative decoding operation from the q-value symbol memory 110, and compare the previous symbol value with a symbol value of the current first output value. When the previous symbol value is different from the symbol value of the current first output value, the variable node unit 120 will write the symbol value of the current first output value into the q-value symbol memory 110, replacing the symbol value originally recorded in the q-value symbol memory 110.
[0046] Furthermore, with respect to generating and updating the second output value, initially during the first iterative decoding operation, the variable node unit 120 reads a channel value ch_v from the channel value memory 105. At this time, the variable node unit 120 reads a sign bit and a plurality of magnitude bits corresponding to the channel value ch_v from the channel value memory 105. Subsequently, the variable node unit 120 uses the channel value ch_v as the second output value. At this time, the second output value (i.e., the channel value ch_v) is not written to the gradient descent bit memory 115 by the variable node unit 120. Subsequently, during the second iterative decoding operation, the variable node unit 120 generates and updates the second output value according to the following formula:
[0047] app_out=abs(ch_v)+∑R
[0048] Where app_out is the second output value generated and updated by the second iterative decoding operation; abs(ch_v) is the absolute value of the channel value ch_v; and ∑R is the sum of the converted R values of multiple adjacent bits generated previously. Since the second output value generated by the variable node unit 120 has changed from a value not recorded and stored in the first iterative decoding operation to the value of app_out during the second iterative decoding operation, when the value of the second output value changes, the variable node unit 120 writes the absolute value of the second output value (i.e., app_out) (i.e., abs(app_out)) to the gradient descent bit memory, replacing the sign value previously recorded in the gradient descent bit memory. Next, during the third iterative decoding operation (or the subsequent n-th iterative decoding operation), the variable node unit 120 operates similarly to the second iterative decoding operation, and similarly calculates and updates the second output value app_out=abs(ch_v)+∑R. At this time, the variable node unit 120 may read a previous symbol value stored in the gradient descent bit memory during the previous iterative decoding operation and compare the previous symbol value with a symbol value of the current second output value. Only when the previous symbol value differs from the symbol value of the current second output value will the variable node unit 120 write the symbol value of the current second output value into the gradient descent bit memory, replacing the symbol value originally recorded in the gradient descent bit memory.
[0049] The symbol values stored in the gradient descent bit memory are equivalent to the noise information during decision making, i.e., the difference information, which can also be considered as the gradient descent bits. Therefore, when making a hard decision, the decision bit output unit 140 performs an XOR (exclusive OR) operation on a channel value stored in the channel memory and a corresponding symbol value (i.e., the difference information) stored in the gradient descent bit memory to remove the difference information and obtain the correct bit information as the output data / information of the hard decision execution.
[0050] In summary, compared to conventional techniques that use a single memory to store codeword decision information, if the codeword is 30,000 bits, more than half (i.e., over 10,000 bits) of the memory would need to store bit data '1'. However, if the present invention is employed, under the same conditions, the memory may only require a few hundred bits to store bit data '1', significantly reducing power consumption. Furthermore, embodiments of the present invention reduce the number of times a sign bit stored in channel value memory 105 is read. Data writing to the memory is not required during the first iterative decoding operation, and data writing to the memory is only required when the data value changes, thereby significantly reducing power consumption.
[0051] Figure 2 According to one embodiment of the present invention, Figure 1 FIG. 1 is a schematic diagram of a flash memory controller 200 of a decoder circuit 100. Figure 2 As shown, the flash memory controller 200 is coupled between a host device 200 and a flash memory 202. The flash memory controller 200 includes a randomizer 205, a de-randomizer 215, an encoder 210, and Figure 1 The decoder circuit 100 is shown, and the flash memory 202 includes multiple flash memory chips, such as NAND flash memory chips. For example, when a host device 201 wishes to write a piece of data to one or more flash memory chips in the flash memory 202, the data to be written (e.g., simply referred to as a write data) is first transmitted to the flash memory controller 200. The randomizer 205 performs a randomization operation on the write data to generate randomized write data, eliminating data skew in the write data to reduce the occurrence of bit errors. The encoder 210 then performs an encoding operation (e.g., low-density parity-check code (LDPC) encoding, but not limited to) on the randomized write data to generate encoded write data. The encoded write data is then written to the one or more flash memory chips in the flash memory 202. In addition, when the host device 201 wants to read a piece of data from one or more flash memory chips in the flash memory 202, the data to be read (for example, referred to as a piece of read data) will first be transmitted to the flash memory controller 200, and the decoder circuit 100 will be based on Figure 1The novel iterative decoding operation described in the embodiment is used to perform a decoding process (such as, but not limited to, LDPC decoding) on the read data to generate decoded read data to significantly reduce the power consumption of the flash memory controller 200. The decoded read data is then transmitted to the derandomizer 215. The derandomizer 215 then performs a derandomization process on the decoded data to generate derandomized read data, which is then transmitted to the host device 201. The randomizer 205 and the derandomizer 215 operate in pair. In another embodiment, the flash memory controller 200 may not include the randomizer 205 and the derandomizer 215; this example is also applicable to the present invention.
[0052] In order to enable readers to more clearly understand the spirit of the invention, please refer to Figure 3 , Figure 3 FIG. 1 is a flowchart of a decoding method of a decoder circuit according to an embodiment of the present invention. The steps are described below:
[0053] Step S300: providing and using a channel value memory to receive and store input data as a channel value, wherein the channel value is stored in the channel value memory in the form of a sign bit and a plurality of value size bits;
[0054] Step S305: providing and using a symbol memory to store a symbol value;
[0055] Step S310: providing and using a gradient descent bit memory to store difference information corresponding to the channel value;
[0056] Step S315: providing and using a variable node unit to generate a first output value and a second output value according to the channel value;
[0057] Step S320: providing and using a first barrel shifter to convert the first output value from a variable node field to a check node field to generate a converted first output value;
[0058] Step S325: providing and using a check node unit to generate a check-variable information according to the converted first output value and / or the symbol value stored in the symbol memory;
[0059] Step S330: providing and using a second barrel shifter to convert the check-variable information from the check node field to the variable node field to generate a converted check-variable information to the variable node unit; and
[0060] Step S335 : generating and determining output data according to the difference information corresponding to the channel value in the channel value memory and the channel value stored in the gradient descent bit memory.
[0061] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.
Claims
1. A decoder circuit comprising: a channel value memory for receiving and storing input data as a channel value, wherein the channel value is stored in the channel value memory in the form of a sign bit and a plurality of value size bits; a symbol memory for storing a symbol value; a gradient descent bit memory for storing difference information corresponding to the channel value; a variable node unit coupled to the channel value memory, the sign memory, and the gradient descent bit memory, for generating a first output value and a second output value according to the channel value; a first barrel shifter coupled to the variable node unit, for converting the first output value from a variable node field to a check node field to generate a converted first output value; a check node unit coupled to the first barrel shifter, for generating a check-variable information according to the converted first output value or the symbol value stored in the symbol memory; a second barrel shifter coupled to the check node unit, for converting the check-variable information from the check node field to the variable node field to generate converted check-variable information to the variable node unit; as well as A decision bit output unit is coupled to the gradient descent bit memory and the channel value memory, and is used to generate and decide an output data according to the difference information corresponding to the channel value of the channel value memory and the channel value stored in the gradient descent bit memory.
2. The decoder circuit according to claim 1, wherein During a first iterative decoding operation, the variable node unit reads the sign bit and the plurality of magnitude bits corresponding to the channel value from the channel value memory and uses the channel value as the first output value; the first barrel shifter is configured to convert the first output value from the variable node field to the check node field to generate the converted first output value; The check node unit is used to perform a minimization operation according to the converted first output value to generate and output the check-variable information without reading the sign memory; the second barrel shifter is used to convert the check-variable information from the check node field to the variable node field to generate the converted check-variable information.
3. The decoder circuit according to claim 2, wherein: When performing a second iterative decoding operation, the variable node unit generates and updates the first output value according to the following formula: where qval_out i is the first output value generated and updated by the second iterative decoding operation; abs(ch_v) is an absolute value of the channel value ch_v, and the variable node unit only reads the multiple value size bits from the channel value memory to calculate the absolute value during the second iterative decoding operation, and does not read the sign bit of the channel value; ∑R is a sum of multiple post-conversion check-variable information of multiple adjacent bits previously generated by the variable node unit; R i The first output value is a post-conversion check-variable information generated by the second barrel shifter in the previous iterative decoding operation. The variable node unit writes and stores an absolute value of the first output value into the symbol memory when performing the second iterative decoding operation.
4. The decoder circuit according to claim 3, wherein: When performing an iterative decoding operation for the third time or more, the variable node unit reads a previous symbol value stored in the previous iterative decoding operation from the symbol memory, compares the previous symbol value with a symbol value of the current first output value, and only when the previous symbol value is different from the symbol value of the current first output value will the variable node unit write the symbol value of the current first output value into the symbol memory to replace the previous symbol value.
5. The decoder circuit according to claim 1, wherein: When performing a first iterative decoding operation, the variable node unit reads the sign bit and the multiple value size bits corresponding to the channel value from the channel value memory, uses the channel value as the second output value, and the second output value is not written to the gradient descent bit memory by the variable node unit at this time.
6. The decoder circuit according to claim 5, wherein: When performing a second iterative decoding operation, the variable node unit generates and updates the second output value according to the following formula: Wherein app_out is the second output value generated and updated by the second iterative decoding operation; abs(ch_v) is an absolute value of the channel value; ∑R is a sum of multiple converted check-variable information of multiple adjacent bits previously generated by the variable node unit; during the second iterative decoding operation, the variable node unit writes the absolute value of the updated second output value to the gradient descent bit memory as the difference information corresponding to the channel value.
7. The decoder circuit according to claim 6, wherein: When performing a third or later iterative decoding operation, the variable node unit generates and updates the second output value according to the formula app_out=abs(ch_v)+∑R. The variable node unit reads a previous symbol value stored in the gradient descent bit memory during a previous iterative decoding operation from the gradient descent bit memory, compares the previous symbol value in the gradient descent bit memory with a symbol value of the current second output value, and only when the previous symbol value in the gradient descent bit memory is different from the symbol value of the current second output value does the variable node unit write the symbol value of the current second output value into the gradient descent bit memory, thereby updating the difference information corresponding to the channel value.
8. The decoder circuit according to claim 1, wherein: The decision bit output unit performs an exclusive OR operation on the channel value in the channel value memory and the difference information to generate and hard-decide the output data.
9. The decoder circuit according to claim 1, wherein: Used and included in a flash memory controller.
10. A decoding method for use in a decoder circuit, comprising: A channel value memory is provided to receive and store input data as a channel value, wherein the channel value is stored in the channel value memory in the form of a sign bit and a plurality of value size bits; Providing a symbol memory to store a symbol value; Providing a gradient descent bit memory to store difference information corresponding to the channel value; Providing a variable node unit to generate a first output value and a second output value according to the channel value; providing a first barrel shifter to convert the first output value from a variable node field to a check node field to generate a converted first output value; providing a check node unit to generate a check-variable information according to the converted first output value or the symbol value stored in the symbol memory; providing a second barrel shifter to convert the check-variable information from the check node field to the variable node field to generate converted check-variable information to the variable node unit; as well as An output data is generated and determined according to the difference information corresponding to the channel value of the channel value memory and the channel value stored in the gradient descent bit memory.
11. The decoding method according to claim 10, wherein: Also includes: When performing a first iteration of decoding operation: Using the variable node unit to read the sign bit and the plurality of value size bits corresponding to the channel value from the channel value memory, and using the channel value as the first output value; Using the first barrel shifter to convert the first output value from the variable node field to the check node field to generate the converted first output value; using the check node unit to perform a minimization operation based on the converted first output value to generate and output the check-variable information without reading the symbol memory; as well as The second barrel shifter is used to convert the check-variable information from the check node field to the variable node field to generate the converted check-variable information.
12. The decoding method according to claim 11, wherein: Also included are: When performing a second iterative decoding operation, the variable node unit is used to generate and update the first output value according to the following formula: where qval_out i is the first output value generated and updated by the second iterative decoding operation; abs(ch_v) is an absolute value of the channel value ch_v, and the variable node unit only reads the multiple value size bits from the channel value memory to calculate the absolute value during the second iterative decoding operation, and does not read the sign bit of the channel value; ∑R is a sum of multiple post-conversion check-variable information of multiple adjacent bits previously generated by the variable node unit; R i The first output value is a post-conversion check-variable information generated by the second barrel shifter in the previous iterative decoding operation. The variable node unit writes and stores an absolute value of the first output value into the symbol memory when performing the second iterative decoding operation.
13. The decoding method according to claim 12, wherein: Also includes: When performing an iterative decoding operation for the third time or more, the variable node unit is used to read a previous symbol value stored in the previous iterative decoding operation from the symbol memory, and the previous symbol value is compared with a symbol value of the current first output value. When the previous symbol value is different from the symbol value of the current first output value, the variable node unit will write the symbol value of the current first output value into the symbol memory to replace the previous symbol value.
14. The decoding method according to claim 10, wherein: Also includes: When performing a first iterative decoding operation, the variable node unit is used to read the sign bit and the multiple value size bits corresponding to the channel value from the channel value memory, and the channel value is used as the second output value. At this time, the second output value will not be written to the gradient descent bit memory by the variable node unit.
15. The decoding method according to claim 14, wherein: Also includes: When performing a second iterative decoding operation, the variable node unit is used to generate and update the second output value according to the following formula: Wherein app_out is the second output value generated and updated by the second iterative decoding operation; abs(ch_v) is an absolute value of the channel value; ∑R is a sum of multiple converted check-variable information of multiple adjacent bits previously generated by the variable node unit; during the second iterative decoding operation, the variable node unit writes the absolute value of the updated second output value to the gradient descent bit memory as the difference information corresponding to the channel value.
16. The decoding method according to claim 15, wherein: Also includes: When performing a third or later iterative decoding operation, the variable node unit is used to generate and update the second output value according to the formula app_out=abs(ch_v)+∑R. The variable node unit reads a previous symbol value stored in the gradient descent bit memory during a previous iterative decoding operation from the gradient descent bit memory, compares the previous symbol value in the gradient descent bit memory with a symbol value of the current second output value, and only when the previous symbol value in the gradient descent bit memory is different from the symbol value of the current second output value does the variable node unit write the symbol value of the current second output value into the gradient descent bit memory to update the difference information corresponding to the channel value.
17. The decoding method according to claim 10, wherein: Also includes: The decision bit output unit is used to perform an exclusive OR operation on the channel value in the channel value memory and the difference information to generate and hard-decide the output data.