Memory device

Abstract

A memory device may include a first cell array chip including a first memory cell array; a first peripheral circuit chip including a first page buffer circuit electrically connected to the first memory cell array; an input / output (I / O) chip includes a first pad circuit, a second pad circuit, a first I / O circuit electrically connected to the first pad circuit, and a second I / O circuit electrically connected to the second pad circuit. The memory device may further include a second cell array chip including a second memory cell array; and a second peripheral circuit chip including a second page buffer circuit electrically connected to the second memory cell array.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based upon and claims the benefit of priority from Korean Patent Application No. 10-2024-0032839 filed on March 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Embodiments of the present disclosure relate to a memory device, and more particularly, to a memory device having a structure in which a plurality of chips are stacked in a vertical direction. Background Art

[0003] With the recent trend in the semiconductor industry toward miniaturization and higher efficiency, reducing the size of semiconductor chips has become a major task. Against this backdrop, there is an increasing demand for structural and functional improvements in memory semiconductor devices.

[0004] Vertical memory architectures have become one of the key solutions to meet this need. Specifically, in a vertical memory architecture, as the number of memory cell array levels increases, the area occupied by the memory cell array within the memory device decreases. However, due to technical and physical limitations, the reduction in peripheral circuit area may not be as significant as the reduction in memory cell array area.

[0005] In addition, as memory cell array chips are stacked, the distance between the memory cell array and the peripheral circuit increases, which increases the load applied to the peripheral circuit. Therefore, the increase in load will reduce the performance of the memory device. Summary of the Invention

[0006] Embodiments of the present disclosure provide a memory device having a structure capable of improving the net die of a semiconductor chip included in the memory device and minimizing a load applied to the memory device when the memory device performs an input / output (I / O) operation.

[0007] Technical aspects of the embodiments of the present disclosure are not limited to the above-mentioned aspects; other aspects may be apparent to those of ordinary skill in the art based on the following description.

[0008] According to an embodiment of the present disclosure, a memory device can be provided, which includes: a first cell array chip including a first memory cell array; a first peripheral circuit chip including a first page buffer circuit electrically connected to the first memory cell array; an input / output chip including a first pad circuit, a second pad circuit, a first input / output circuit electrically connected to the first pad circuit, and a second input / output circuit electrically connected to the second pad circuit; a second cell array chip including a second memory cell array; and a second peripheral circuit chip including a second page buffer circuit electrically connected to the second memory cell array.

[0009] According to an embodiment of the present disclosure, a memory device can be provided, which includes: a first cell array chip including a first memory cell array; a first peripheral circuit chip including a first page buffer circuit electrically connected to the first memory cell array; a second cell array chip including a second memory cell array; and a second peripheral circuit chip including a second page buffer circuit, a first pad circuit, a second pad circuit, a first input / output circuit electrically connected to the first pad circuit, and a second input / output circuit electrically connected to the second pad circuit, wherein the second page buffer circuit is electrically connected to the second memory cell array and is formed on one surface of the second peripheral circuit chip, and wherein the first pad circuit, the second pad circuit, the first input / output circuit and the second input / output circuit are formed on another surface of the second peripheral circuit chip.

[0010] According to an embodiment of the present disclosure, a memory device can be provided, which includes: a first cell array chip including a first memory cell array; a first peripheral circuit chip including a first page buffer circuit electrically connected to the first memory cell array; an input / output chip including a first pad circuit, a second pad circuit, a first input / output circuit electrically connected to the first pad circuit, and a second input / output circuit electrically connected to the second pad circuit; a second cell array chip including a second memory cell array; a second peripheral circuit chip including a second page buffer circuit electrically connected to the second memory cell array; a third cell array chip including a third memory cell array; and a third peripheral circuit chip including a third page buffer circuit electrically connected to the third memory cell array. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram illustrating a storage device according to an embodiment;

[0013] Figure 2 is a block diagram illustrating a memory device according to an embodiment;

[0014] Figure 3 is a diagram showing a method according to an embodiment of the present invention. Figure 1 a diagram of a structure of a memory device;

[0015] Figure 4 and Figure 5 is a diagram showing a memory device according to an embodiment;

[0016] Figure 6 and Figure 7 is a diagram showing a memory device according to an embodiment;

[0017] Figure 8 is a diagram showing a memory device according to an embodiment;

[0018] Figure 9A and Figure 9B is a diagram illustrating an operating method of a memory device according to an embodiment;

[0019] Figure 10A and Figure 10B is a diagram illustrating an operating method of a memory device according to an embodiment;

[0020] Figure 11A and Figure 11B is a diagram illustrating an operating method of a memory device according to an embodiment;

[0021] Figure 12A and Figure 12B is a diagram illustrating an operating method of a memory device according to an embodiment;

[0022] Figures 13 to 16 are diagrams showing a memory device according to an embodiment;

[0023] Figures 17 to 20 are diagrams showing a memory device according to an embodiment;

[0024] Figure 21 is a diagram showing a memory device according to an embodiment;

[0025] Figure 22 is a diagram showing a memory device according to an embodiment;

[0026] Figure 23 is a diagram showing a memory device according to an embodiment;

[0027] Figure 24 is a diagram showing a memory device according to an embodiment;

[0028] Figure 25 is a diagram showing a memory device according to an embodiment; and

[0029] Figure 26is a block diagram of an example in which a memory device according to an embodiment is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0030] Hereinafter, non-limiting exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same reference numerals are used to represent the same elements, and repeated descriptions thereof may be omitted.

[0031] It will be understood that when an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.

[0032] Figure 1 is a block diagram illustrating a storage device 10 according to an embodiment.

[0033] Reference Figure 1 The storage device 10 may include a storage medium configured to store data in response to a request from a host. For example, the storage device 10 may include at least one of a solid-state drive (SSD), an embedded memory, and a removable external memory. If the storage device 10 is an SSD, the storage device 10 may be a device compliant with the Non-Volatile Memory Express (NVMe) standard.

[0034] When the storage device 10 is an embedded memory or an external memory, the storage device 10 may be a device compliant with the Universal Flash Storage (UFS) or Embedded Multimedia Card (eMMC) standards. Each of the host and the storage device 10 may generate and send packets compliant with the adopted standard protocol. In an embodiment, the storage device 10 may be an embedded memory embedded in the storage device 10. For example, the storage device 10 may include an eMMC or embedded UFS storage device. In an embodiment, the storage device 10 may be an external memory that is detachably attached to another system. For example, the storage device 10 may include a UFS memory card, Compact Flash (CF), Secure Digital (SD), Micro SD, Mini SD, Extreme Digital (xD), or Memory Stick.

[0035] Reference Figure 1 , the memory device 10 may include a memory controller 100 and a memory device 200 .

[0036] The memory controller 100 may control read, write, and erase operations on the memory device 200 by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 200. In this case, when the memory device 200 performs read and write operations, data DATA may be transmitted and received between the memory controller 100 and the memory device 200.

[0037] In an embodiment, the memory controller 100 may control the memory device 200 to read data stored in the memory device 200 in response to a read request from the host HOST, or write data to the memory device 200 in response to a write request from the host HOST. In an embodiment, the memory device 10 may perform operations such as wear leveling management, bad block management, and garbage collection.

[0038] The memory device 200 may include a first cell array chip CAC1, a first peripheral circuit chip PC1, an input / output (I / O) chip IOC, a second peripheral circuit chip PC2, and a second cell array chip CAC2. The first cell array chip CAC1, the first peripheral circuit chip PC1, the I / O chip IOC, the second peripheral circuit chip PC2, and the second cell array chip CAC2 may each be a semiconductor chip formed on a separate wafer and then cut. Each of the first cell array chip CAC1 and the second cell array chip CAC2 may include a memory cell array. The first peripheral circuit chip PC1 may include a circuit for controlling the memory cell array included in the first cell array chip CAC1. The second peripheral circuit chip PC2 may include a circuit for controlling the memory cell array included in the second cell array chip CAC2. The I / O chip IOC may include a pad circuit and an I / O circuit, the pad circuit being connected to the bonding pad, and the I / O circuit sending data to and receiving data from the first peripheral circuit chip PC1 and the second peripheral circuit chip PC2. Refer to the following Figure 2 Component blocks included in each of the first cell array chip CAC1, the first peripheral circuit chip PC1, the I / O chip 10C, the second peripheral circuit chip PC2, and the second cell array chip CAC2 are described.

[0039] Figure 2 is a block diagram of a memory device 200 according to an embodiment. Figure 1 To describe Figure 2 , and repeated descriptions may be omitted. Although for the sake of brevity, Figure 2 Only the first cell array chip CAC1, the first peripheral circuit chip PC1 and the I / O chip IOC are shown in FIG. Figure 2The memory device 200 may further include a second cell array chip CAC2 and a second peripheral circuit chip PC2. In this case, the second cell array chip CAC2 may have a configuration similar to that of the first cell array chip CAC1, and the second peripheral circuit chip PC2 may have a configuration similar to that of the first peripheral circuit chip PC1.

[0040] Reference Figure 2 , the memory device 200 may include a first cell array chip CAC1, a first peripheral circuit chip PC1, and an I / O chip 10C.

[0041] The first peripheral circuit chip PC1 may include a voltage generator 210, an address decoder 220, a control logic circuit 240, and a page buffer circuit 250. The first cell array chip CAC1 may include a memory cell array 230. The I / O chip PC1 may include an I / O circuit 260.

[0042] The voltage generator 210 can generate various voltages for performing read, write, and erase operations on the memory cell array 230 based on the voltage control signal CTRL_Vol. Specifically, the voltage generator 210 can generate a word line voltage VWL, such as a program voltage, a read voltage, a pass voltage, an erase verification voltage, or a program verification voltage. In addition, the voltage generator 210 can generate a string selection line voltage or a ground selection line voltage based on the voltage control signal CTRL_Vol. In addition, the voltage generator 210 can generate an erase voltage to be provided to the memory cell array 230.

[0043] The address decoder 220 may select one of a plurality of memory regions MR1 ​​to MRz (z is a natural number of 1 or greater) of the memory cell array 230 , one of the word lines WL of the selected memory region, and one of a plurality of string selection lines SSL.

[0044] The memory cell array 230 may be connected to word lines WL, string select lines SSL, ground select lines GSL, and bit lines BL. The memory cell array 230 may be connected to the address decoder 220 through the word lines WL, string select lines SSL, and ground select lines GSL, and to the page buffer circuit 250 through the bit lines BL. The memory cell array 230 may include a plurality of memory regions MR1 ​​to MRz.

[0045] Each of the plurality of memory regions MR1 ​​to MRz may include a plurality of memory cells and a plurality of select transistors. The memory cells may be connected to a word line WL, and the select transistors may be connected to a string select line SSL or a ground select line GSL. Each of the plurality of memory regions MR1 ​​to MRz may include a plurality of memory pages. A memory page may correspond to a data programming unit or a data reading unit. As used herein, a memory region may refer to a group of a plurality of memory cells. Alternatively, each memory region may correspond to a memory block.

[0046] In an embodiment, the memory cell array 230 may include a three-dimensional (3D) memory cell array including a plurality of NAND strings. Each NAND string may include memory cells, each of which is connected to a word line WL vertically stacked on a substrate. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the memory cell array 230 may include a two-dimensional (2D) memory cell array including a plurality of NAND strings arranged in rows and columns.

[0047] The control logic circuit 240 may output various control signals for performing read, write, and erase operations on the memory cell array 230 based on the command CMD, the address ADDR, and the control signal CTRL. The control logic circuit 240 may provide a row address X-ADDR to the address decoder 220, a column address Y-ADDR to the page buffer circuit 250, and a voltage control signal CTRL_Vol to the voltage generator 210.

[0048] Page buffer circuit 250 may include multiple page buffers PB1 to PBn (n is a natural number of 1 or greater). Multiple page buffers PB1 to PBn may correspond to multiple memory regions MR1 ​​to MRz, respectively. Page buffer circuit 250 may operate as a write driver or a sense amplifier depending on the operating mode. During a read operation, page buffer circuit 250 may sense the bit line BL of a selected memory cell under the control of control logic circuit 240. The sensed data may be stored in a latch included in page buffer circuit 250. Page buffer circuit 250 may transfer the data stored in the latch to I / O circuit 260 under the control of control logic circuit 240.

[0049] The I / O circuit 260 may temporarily store data DATA provided from outside the memory device 200. The I / O circuit 260 may temporarily store read data from the memory device 200 and output the data to the outside at a specified time. In addition, the I / O circuit 260 may temporarily store write data DATA provided from the outside and provide the data DATA to the page buffer circuit 250 at a specified time.

[0050] Figure 3is a diagram showing a method according to an embodiment of the present invention. Figure 1 The structure of the memory device 200 is shown in FIG. Figure 1 and Figure 2 To describe Figure 3 , and repeated descriptions can be omitted.

[0051] Figure 3 Shown Figure 1 An example of the structure of the memory device 200 is shown. Figure 3 The memory device 200 may include first to fifth semiconductor layers L1 to L5. The second semiconductor layer L2 may be located below the first semiconductor layer L1 in a vertical direction (i.e., a first direction D1). The third semiconductor layer L3 may be located below the second semiconductor layer L2 in the first direction D1. The fourth semiconductor layer L4 may be located below the third semiconductor layer L3 in the first direction D1. The fifth semiconductor layer L5 may be located below the fourth semiconductor layer L4 in the first direction D1.

[0052] As used herein, the vertical direction may be defined as a first direction D1, the second direction D2 may be defined as a direction perpendicular to the first direction D1, and the third direction D3 may be defined as a direction perpendicular to the first direction D1 and the second direction D2. In addition, the second direction D2 may also be referred to as a first lateral direction, and the third direction D3 may also be referred to as a second lateral direction.

[0053] In an embodiment, the memory device 200 may have a symmetrical structure with respect to the third semiconductor layer L3 . Figure 1 The first cell array chip CAC1 may be formed in the first semiconductor layer L1. Figure 1 The first peripheral circuit chip PC1 may be formed in the second semiconductor layer L2. Figure 1 The I / O chip 10C may be formed in the third semiconductor layer L3. Figure 1 The second cell array chip CAC2 may be formed in the fourth semiconductor layer L4. Figure 1 The second peripheral circuit chip PC2 may be formed in the fifth semiconductor layer L5.

[0054] The memory device 200 may include a chip-to-chip (C2C) structure. Here, the C2C structure may refer to a structure in which a cell region (eg, a first cell region CELL1; see Figure 25 ) of at least one upper chip and including a peripheral circuit region PERI (reference Figure 25 ) are manufactured separately and connected to each other by using bonding technology.

[0055] In an embodiment, the first cell array chip CAC1 and the first peripheral circuit chip PC1 may be connected to each other using a bonding technology to have a C2C structure. In addition, the second cell array chip CAC2 and the second peripheral circuit chip PC2 may be connected to each other using a bonding technology to have a C2C structure. Figure 25 Provides a detailed description of the C2C structure.

[0056] Figure 4 and Figure 5 2 is a diagram showing a memory device 200a and a memory device 200b according to an embodiment. Specifically, Figure 4 and Figure 5 Corresponding to the Figure 3 The cross-sectional view of the memory device 200 is taken along line II'. Figures 1 to 3 describe Figure 4 and Figure 5 , and repeated descriptions can be omitted.

[0057] Reference Figure 4 , the memory device 200a may include a first cell array chip CAC1, a first peripheral circuit chip PC1, an I / O chip 10C, a second peripheral circuit chip PC2, a second cell array chip CAC2, a first bonding pad PD1, a second bonding pad PD2, contact plugs PT11, PT12, PT21, and PT22, contact bonding pads PBP11, PBP12, PBP21, and PBP22, metal patterns MP11, MP12, MP21, and MP22, and first to fourth connection units CN1a to CN4a. In addition, the first bonding pad PD1 and the second bonding pad PD2 may be located on the first cell array chip CAC1. The memory device 200a may be connected to the memory controller 100 (refer to FIG. 1 ) through the first bonding pad PD1 and the second bonding pad PD2. Figure 1 ) for communication. As used herein, a contact bonding pad may refer to a conductive pad for electrical connection between a contact plug and another component. In this case, the other component electrically connected to the contact plug may be, for example, another contact plug or another semiconductor chip. The first peripheral circuit chip PC1 may be electrically connected to the first cell array chip CAC1 through metal patterns MP11 and MP12 by using a bonding technology. The first peripheral circuit chip PC1 may be electrically connected to the I / O chip 10C through a first connection unit CN1a and a second connection unit CN2a. The second peripheral circuit chip PC2 may be electrically connected to the I / O chip 10C through a third connection unit CN3a and a fourth connection unit CN4a. The second peripheral circuit chip PC2 may be electrically connected to the second cell array chip CAC2 through metal patterns MP21 and MP22 by using a bonding technology.

[0058] The first cell array chip CAC1 may include a first memory cell array MCA1. The first memory cell array MCA1 may include a first memory region MR1 and a second memory region MR2. The first memory cell array MCA1 is shown as including two memory regions for descriptive purposes only and not for limiting purposes. That is, the first memory cell array MCA may include more than two memory regions.

[0059] The first peripheral circuit chip PC1 may include a first page buffer circuit PBC1. The first page buffer circuit PBC1 may include a first page buffer PB1 and a second page buffer PB2. The first page buffer circuit PBC1 is shown as including two page buffers, which is merely descriptive and not intended to be limiting. That is, the first page buffer circuit PBC1 may include more than two page buffers.

[0060] The second cell array chip CAC2 may include a second memory cell array MCA2. The second memory cell array MCA2 may include a third memory region MR3 and a fourth memory region MR4. The second memory cell array MCA2 is shown as including two memory regions, which is merely descriptive and not intended to be limiting. That is, the second memory cell array MCA2 may include more than two memory regions.

[0061] The second peripheral circuit chip PC2 may include a second page buffer circuit PBC2. The second page buffer circuit PBC2 may include a third page buffer PB3 and a fourth page buffer PB4. The second page buffer circuit PBC2 is shown as including two page buffers, which is merely descriptive and not intended to be limiting. That is, the second page buffer circuit PBC2 may include more than two page buffers.

[0062] The I / O chip 10C may include a first I / O circuit 301, a second I / O circuit 302, a first pad circuit 303, and a second pad circuit 304. Each of the first I / O circuit 301 and the second I / O circuit 302 may correspond to Figure 2The first I / O circuit 301 may be spaced apart from the second I / O circuit 302 in the third direction D3. The first pad circuit 303 may be closer to the first I / O circuit 301 than the second I / O circuit 302. The second pad circuit 304 may be closer to the second I / O circuit 302 than the first I / O circuit 301. The first storage region MR1, the first page buffer PB1, the third page buffer PB3, and the third storage region MR3 may be closer to the first I / O circuit 301 than the second I / O circuit 302. The second storage region MR2, the second page buffer PB2, the fourth page buffer PB4, and the fourth storage region MR4 may be closer to the second I / O circuit 302 than the first I / O circuit 301.

[0063] The I / O chip 10C can be divided into a first I / O unit 10C_A1 and a second I / O unit 10C_A2. As used herein, the first I / O unit 10C_A1 may refer to an area including the first I / O circuit 301 and the first pad circuit 303. The second I / O unit 10C_A2 may refer to an area including the second I / O circuit 302 and the second pad circuit 304.

[0064] The first pad circuit 303 may be a circuit configured to electrically connect the first I / O circuit 301 to the first bonding pad PD1. The second pad circuit 304 may be a circuit configured to electrically connect the second I / O circuit 302 to the second bonding pad PD2. The first bonding pad PD1 may be electrically connected to the first pad circuit 303 via contact plugs PT11 and PT21. The contact plugs PT11 and PT12 may pass through the first cell array chip CAC1. The contact plugs PT21 and PT22 may pass through the first peripheral circuit chip PC1. The contact plug PT11 may be electrically connected to the contact plug PT21 via the contact bonding pad PBP11. The contact plug PT21 may be electrically connected to the I / O chip 10C via the contact bonding pad PBP21. The contact plug PT12 may be electrically connected to the contact plug PT22 via the contact bonding pad PBP12. The contact plug PT22 may be electrically connected to the I / O chip 10C via the contact bonding pad PBP22. In an embodiment, the contact bonding pads PBP11 and PBP12 may be between the first cell array chip CAC1 and the first peripheral circuit chip PC1. In an embodiment, the contact bonding pads PBP21 and PBP22 may be between the first peripheral circuit chip PC1 and the I / O chip 10C.

[0065] According to an embodiment, a first contact portion may be provided through the first peripheral circuit chip PC1 and the first cell array chip CAC1. For example, the first contact portion may include a contact plug PT11 and a contact plug PT21. According to an embodiment, a second contact portion may be provided through the first peripheral circuit chip PC1 and the first cell array chip CAC1. The second contact portion may include a contact plug PT12 and a contact plug PT21.

[0066] The memory device 200 a may perform an I / O operation (eg, a write operation or a read operation) related to the data DATA by using an I / O circuit close to each memory region.

[0067] In an embodiment, the memory device 200a can write data DATA to the first cell array chip CAC1 or read data DATA from the first cell array chip CAC1 through the first path PATH1. The first path PATH1 may refer to a path passing through the first cell array chip CAC1, the first peripheral circuit chip PC1, and the I / O chip 10C. In this case, the memory device 200a can process the input and output of data related to the first storage region MR1 by using the first page buffer PB1 and the first I / O circuit 301, and process the input and output of data related to the second storage region MR2 by using the second page buffer PB2 and the second I / O circuit 302.

[0068] In an embodiment, the memory device 200a can write data DATA to the second cell array chip CAC2 or read data DATA from the second cell array chip CAC2 through the second path PATH2. The second path PATH2 may refer to a path passing through the second cell array chip CAC2, the second peripheral circuit chip PC2, and the I / O chip 10C. In this case, the memory device 200a can process the input and output of data related to the third storage region MR3 by using the third page buffer PB3 and the first I / O circuit 301, and can process the input and output of data related to the fourth storage region MR4 by using the fourth page buffer PB4 and the second I / O circuit 302.

[0069] The memory device 200a can perform 1-channel communication with the memory controller 100. That is, the memory device 200a can send and receive data DATA to and from the memory controller 100 through the first bonding pad PD1 and the second bonding pad PD2 in response to a first command received from the memory controller 100. The data DATA may include first data DATA1 and second data DATA2. The first data DATA1 may correspond to a low bit among the bits constituting the data DATA, and the second data DATA2 may correspond to a high bit among the bits constituting the data DATA. However, embodiments of the present disclosure are not limited thereto, and the first data DATA1 may correspond to a high bit among the bits constituting the data DATA, and the second data DATA2 may correspond to a low bit among the bits constituting the data DATA.

[0070] In an embodiment, the size unit of the data DATA input and output between the memory device 200a and the memory controller 100 may be 16 bits. In this case, the memory device 200a may operate as a wide I / O interface. The first data DATA1 may correspond to the lower 8 bits of the data DATA, and the second data DATA2 may correspond to the upper 8 bits of the data DATA.

[0071] In an embodiment, the size unit of the data DATA input and output between the memory device 200a and the memory controller 100 may be 8 bits. In this case, the first data DATA1 may correspond to the lower 4 bits of the data DATA, and the second data DATA2 may correspond to the upper 4 bits of the data DATA.

[0072] Reference Figure 5 , the memory device 200b may include Figure 4 Hereinafter, repeated description may be omitted, and the following description focuses on Figure 5 The memory device 200b is connected to Figure 4 The difference between the memory devices 200a.

[0073] However, with Figure 4 The memory device 200a is different. Figure 5 The first peripheral circuit chip PC1 of the memory device 200b can be electrically connected to the first I / O unit IO_A1 through the first connection unit CN1b. Similarly, Figure 5 The second peripheral circuit chip PC2 of the memory device 200b may be electrically connected to the second I / O unit IO_A2 through the second connection unit CN2b.

[0074] The memory device 200 b may process an I / O operation related to the first cell array chip CAC1 by using the first I / O circuit 301 , and may perform an I / O operation related to the second cell array chip CAC2 by using the second I / O circuit 302 .

[0075] In an embodiment, the memory device 200b can write or read first data DATA1 to or from the first cell array chip CAC1 via a first path PATH1. The first path PATH1 may refer to a path passing through the first cell array chip CAC1, the first peripheral circuit chip PC1, and the first I / O unit IOC_A1. In this case, the memory device 200b can process the input and output of the first data DATA1 related to the first memory cell array MCA1 by using the first page buffer circuit PBC1 and the first I / O circuit 301.

[0076] In an embodiment, the memory device 200b can write or read the second data DATA2 to or from the second cell array chip CAC2 via a second path PATH2. The second path PATH2 may refer to a path passing through the second cell array chip CAC2, the second peripheral circuit chip PC2, and the second I / O unit IOC_A2. In this case, the memory device 200b can process the input and output of the second data DATA2 related to the second memory cell array MCA2 by using the second page buffer circuit PBC2 and the second I / O circuit 302.

[0077] The memory device 200b can perform 2-channel communication with the memory controller 100. The memory device 200b can transmit and receive first data DATA1 to and from the memory controller 100 through the first bonding pad PD1 in response to a first command received from the memory controller 100. The memory device 200b can transmit and receive second data DATA2 to and from the memory controller 100 through the second bonding pad PD2 in response to a second command received from the memory controller 100. In this case, the second command may be a command different from the first command.

[0078] In an embodiment, the size unit of the first data DATA1 and the second data DATA2 input and output between the memory device 200b and the memory controller 100 may be 16 bits. In this case, the memory device 200b can operate as a wide I / O interface. The first data DATA1 may correspond to 16-bit data, and the second data DATA2 may also correspond to 16-bit data.

[0079] In an embodiment, the size unit of the first data DATA1 and the second data DATA2 input and output between the memory device 200b and the memory controller 100 may be 8 bits. In this case, the first data DATA1 may correspond to 8-bit data, and the second data DATA2 may also correspond to 8-bit data.

[0080] Figure 6 and Figure 7 2 is a diagram showing a memory device 200c and a memory device 200d according to an embodiment. Specifically, Figure 6 and Figure 7 Corresponding to the Figure 3 The cross-sectional view of the memory device 200 is taken along line II'. Figure 4 and Figure 5 To describe Figure 6 and Figure 7 , and repeated descriptions can be omitted.

[0081] Reference Figure 6 , the memory device 200c may include Figure 4 Hereinafter, repeated description may be omitted, and the following description focuses on Figure 6 The memory device 200c is connected to Figure 4 The difference between the memory devices 200a.

[0082] Figure 6 The memory device 200c may include a first edge pad EPD1 and a second edge pad EPD2. The first edge pad EPD1 may be Figure 4 The second edge pad EPD2 may be a component corresponding to the first bonding pad PD1 of the memory device 200a. Figure 4 The first edge pad EPD1 may be electrically connected to the first pad circuit 303 . The second edge pad EPD2 may be electrically connected to the second pad circuit 304 .

[0083] The first edge pad EPD1 and the second edge pad EPD2 may be spaced apart from each other in the third direction D3. The first edge pad EPD1 and the second edge pad EPD2 may be between the first peripheral circuit chip PC1 and the I / O chip 10C. However, embodiments of the present invention are not limited thereto, and the first edge pad EPD1 and the second edge pad EPD2 may be disposed between the second peripheral circuit chip PC2 and the I / O chip 10C.

[0084] In an embodiment, the first edge pad EPD1 and the second edge pad EPD2 may be electrically connected to the memory controller 100 by using a wire bonding process.

[0085] In an embodiment, the first edge pad EPD1 and the second edge pad EPD2 may be electrically connected to the memory controller 100 through a thin film cable.

[0086] In an embodiment, the first edge pad EPD1 and the second edge pad EPD2 may be electrically connected to the memory controller 100 through a conductive epoxy material.

[0087] Reference Figure 7 , the memory device 200d may include Figure 5 Hereinafter, repeated description may be omitted, and the following description focuses on Figure 7 The memory device 200d and Figure 5 The difference between the memory devices 200b.

[0088] Figure 7 The memory device 200d may include a first edge pad EPD1 and a second edge pad EPD2. The first edge pad EPD1 may be Figure 5 The second edge pad EPD2 may include a component corresponding to the first bonding pad PD1 of the memory device 200b. Figure 5 The component corresponding to the second bonding pad PD2 of the memory device 200b. Figure 7 In the memory device 200d, the first edge pad EPD1 and the second edge pad EPD2 may be arranged at the same Figure 6 , and therefore repeated description can be omitted.

[0089] Figure 8 FIG. 2 is a diagram showing a memory device 200e according to an embodiment. Figure 6 and Figure 7 To describe Figure 8 , and repeated descriptions can be omitted.

[0090] Reference Figure 8 , you can do this by adding multiple Figure 7 The memory device 200d is stacked in two stages to obtain the memory device 200e. However, the embodiments of the present disclosure are not limited to stacking multiple Figure 7 In another case, multiple memory devices 200d may be stacked in two stages. Figure 6 The memory devices 200c are stacked in two stages. In addition, at least two memory devices may be stacked.

[0091] Figure 8The memory device 200e may include a first memory device 200e_1 and a second memory device 200e_2. The first memory device 200e_1 may include a first cell array chip CAC1, a first peripheral circuit chip PC1, a first I / O chip 10C1, a second peripheral circuit chip PC2, and a second cell array chip CAC2. The second memory device 200e_2 may include a third cell array chip CAC3, a third peripheral circuit chip PC3, a second I / O chip 10C2, a fourth peripheral circuit chip PC4, and a fourth cell array chip CAC4.

[0092] The first peripheral circuit chip PC1 may be located below the first cell array chip CAC1. The first I / O chip 10C1 may be located below the first peripheral circuit chip PC1. The second peripheral circuit chip PC2 may be located below the first I / O chip 10C1. The second cell array chip CAC2 may be located below the second peripheral circuit chip PC2. The third cell array chip CAC3 may be located below the second cell array chip CAC2. The third peripheral circuit chip PC3 may be located below the third cell array chip CAC3. The second I / O chip 10C2 may be located below the third peripheral circuit chip PC3. The fourth peripheral circuit chip PC4 may be located below the second I / O chip 10C2. The fourth cell array chip CAC4 may be located below the fourth peripheral circuit chip PC4.

[0093] The first cell array chip CAC1 and the first peripheral circuit chip PC1 may be bonded to each other through the metal patterns MP11 and MP12. The second cell array chip CAC2 and the second peripheral circuit chip PC2 may be bonded to each other through the metal patterns MP21 and MP22. The third cell array chip CAC3 and the third peripheral circuit chip PC3 may be bonded to each other through the metal patterns MP31 and MP32. The fourth cell array chip CAC4 and the fourth peripheral circuit chip PC4 may be bonded to each other through the metal patterns MP41 and MP42.

[0094] The first peripheral circuit chip PC1 and the first I / O chip 10C1 may be electrically connected to each other via a first connection unit CN1e. The second peripheral circuit chip PC2 and the first I / O chip 10C1 may be electrically connected to each other via a second connection unit CN2e. The third peripheral circuit chip PC3 and the second I / O chip 10C2 may be electrically connected to each other via a third connection unit CN3e. The fourth peripheral circuit chip PC4 and the second I / O chip 10C2 may be electrically connected to each other via a fourth connection unit CN4e. However, the second cell array chip CAC2 and the third cell array chip CAC3 may not be electrically connected to each other and may be physically connected to each other only via an adhesive or an insulating material.

[0095] The first memory device 200 e_1 may provide first data DATA1 and second data DATA2 to the memory controller 100 or receive first data DATA1 and second data DATA2 from the memory controller 100 in response to a command received from the memory controller 100 .

[0096] The second memory device 200 e_2 may provide third and fourth data DATA3 and DATA4 to the memory controller 100 or receive third and fourth data DATA3 and DATA4 from the memory controller 100 in response to a command received from the memory controller 100 .

[0097] In an embodiment, the first edge pad EPD1 may be electrically connected to the third edge pad EPD3 using a wire bonding process. The second edge pad EPD2 may be electrically connected to the fourth edge pad EPD4 using a wire bonding process. The third edge pad EPD3 and the fourth edge pad EPD4 may be electrically connected to an external device using a wire bonding process.

[0098] In an embodiment, the first edge pad EPD1 may be electrically connected to the third edge pad EPD3, the second edge pad EPD2 may be electrically connected to the fourth edge pad EPD4, and the third and fourth edge pads EPD3 and EPD4 may be electrically connected to external devices via a thin film cable.

[0099] In an embodiment, the first edge pad EPD1 may be electrically connected to the third edge pad EPD3 through a conductive epoxy material. The second edge pad EPD2 may be electrically connected to the fourth edge pad EPD4 through a conductive epoxy material. The third edge pad EPD3 and the fourth edge pad EPD4 may be electrically connected to an external device through a conductive epoxy material.

[0100] Figure 9A and Figure 9B FIG. 2 is a diagram showing an operation method of the memory device 200 according to an embodiment. Figures 1 to 5 To describe Figure 9A and Figure 9B , and repeated descriptions can be omitted.

[0101] Reference Figure 9A and Figure 9B , the memory device 200 may include a first memory cell array MCA1, a first page buffer circuit PBC1, a first I / O cell IOC_A1a, a second I / O cell IOC_A2a, a second page buffer circuit PBC2, and a second memory cell array MCA2.

[0102] The first memory cell array MCA1 may be formed in Figure 1The first memory cell array MCA1 may include a first memory region MR1u to an eighth memory region MR8u. Although the first memory cell array MCA1 is shown as including eight memory regions as an example, the first memory cell array MCA1 may include more than Figure 9A and Figure 9B Fewer or more storage areas as shown in .

[0103] The first page buffer circuit PBC1 may be formed at Figure 1 The first page buffer circuit PBC1 may include a first page buffer PB1u to an eighth page buffer PB8u. Although the first page buffer circuit PBC1 is shown as including eight page buffers as an example, the first page buffer circuit PBC1 may include more than Figure 9A and Figure 9B Fewer or more page buffers as shown in .

[0104] In an embodiment, the first to eighth page buffers PB1u to PB8u may overlap the first to eighth storage regions MR1u to MR8u, respectively, in the first direction D1. For example, the first storage region MR1u and the first page buffer PB1u may overlap each other in the first direction D1. For example, the sixth storage region MR6u and the sixth page buffer PB6u may overlap each other in the first direction D1.

[0105] The first I / O cell IOC_A1a and the second I / O cell IOC_A2a may be formed at Figure 1 The first I / O cell 10C_A1a may include a first I / O circuit 301 and a first pad circuit 303. The second I / O cell 10C_A2a may include a second I / O circuit 302 and a second pad circuit 304. The first I / O cell 10C_A1a and the second I / O cell 10C_A2a may be spaced apart from each other in the second direction D2. The first I / O circuit 301 and the first pad circuit 303 may be spaced apart from each other in the second direction D2 and may be electrically connected to each other via wiring. The second I / O circuit 302 and the second pad circuit 304 may be spaced apart from each other in the second direction D2 and may be electrically connected to each other via wiring.

[0106] The second page buffer circuit PBC2 may be formed at Figure 1 The second page buffer circuit PBC2 may include a first page buffer PB1d to an eighth page buffer PB8d. Although the second page buffer circuit PBC2 is shown as including eight page buffers as an example, the second page buffer circuit PBC2 may include more than Figure 9A and Figure 9BFewer or more page buffers as shown in .

[0107] The second memory cell array MCA2 may be formed in Figure 1 The second memory cell array MCA2 may include a first memory region MR1d to an eighth memory region MR8d. Although the second memory cell array MCA2 is shown as including eight memory regions as an example, the second memory cell array MCA2 may include more than Figure 9A and Figure 9B Fewer or more storage areas as shown in .

[0108] In an embodiment, the first to eighth page buffers PB1d to PB8d may overlap with the first to eighth storage regions MR1d to MR8d, respectively, in the first direction D1. For example, the fourth storage region MR4d and the fourth page buffer PB4d may overlap with each other in the first direction D1. For example, the fifth storage region MR5d and the fifth page buffer PB5d may overlap with each other in the first direction D1.

[0109] In an embodiment, the first page buffer circuit PBC1 may be formed in Figure 1 The first peripheral circuit chip PC1 may be formed on one surface of the first peripheral circuit chip PC1, and the first I / O cell IOC_A1a and the second I / O cell IOC_A2a may be formed on Figure 1 The first peripheral circuit is on the other surface of the chip PC1.

[0110] In an embodiment, the second page buffer circuit PBC2 may be formed in Figure 1 The first I / O cell IOC_A1a and the second I / O cell IOC_A2a may be formed on one surface of the second peripheral circuit chip PC2. Figure 1 The second peripheral circuit is on the other surface of the chip PC2.

[0111] When reading or writing data stored in the first memory cell array MCA1 , the memory device 200 may perform an operation of reading or writing data by using the first page buffer circuit PBC1 and the first I / O unit IOC_A1 a .

[0112] In the examples, reference Figure 9A , the memory device 200 may read data from or write data to the first memory region MR1u through the first page buffer PB1u and the first I / O circuit 301 .

[0113] In the examples, reference Figure 9B, the memory device 200 can read data from the sixth memory region MR6u or write data to the sixth memory region MR6u through the sixth page buffer PB6u and the first I / O circuit 301.

[0114] When reading data stored in or writing data to the second memory cell array MCA2 , the memory device 200 may perform an operation of reading or writing data by using the second page buffer circuit PBC2 and the second I / O unit IOC_A2 a .

[0115] In the examples, reference Figure 9A , the memory device 200 can read data from the fifth memory region MR5 d or write data to the fifth memory region MR5 d through the fifth page buffer PB5 d and the second I / O circuit 302 .

[0116] In the examples, reference Figure 9B , the memory device 200 can read data from the fourth memory region MR4 d or write data to the fourth memory region MR4 d through the fourth page buffer PB4 d and the second I / O circuit 302 .

[0117] Figure 10A and Figure 10B FIG. 2 is a diagram showing an operation method of the memory device 200 according to an embodiment. Figures 1 to 5 、 Figure 9A and Figure 9B To describe Figure 10A and Figure 10B , and repeated descriptions can be omitted.

[0118] The following description focuses on Figure 10A and Figure 10B The operation of the memory device 200 is shown to be similar to Figure 9A and Figure 9B The differences between the operations of the memory device 200 are shown.

[0119] Reference Figure 10A and Figure 10B When reading data from or writing data to a storage area included in the first memory cell array MCA1, the memory device 200 may perform the operation of reading or writing data by using an I / O circuit close to each storage area.

[0120] In the examples, reference Figure 10A, the memory device 200 can read data from or write data to the third storage region MR3u through the third page buffer PB3u and the first I / O circuit 301. In this case, the distance between the third storage region MR3u and the first I / O circuit 301 can be smaller than the distance between the third storage region MR3u and the second I / O circuit 302.

[0121] In the examples, reference Figure 10B , the memory device 200 can read data from or write data to the sixth storage region MR6u through the sixth page buffer PB6u and the second I / O circuit 302. In this case, the distance between the sixth storage region MR6u and the second I / O circuit 302 can be smaller than the distance between the sixth storage region MR6u and the first I / O circuit 301.

[0122] When data is read from or written to the memory device 200 , the memory device 200 may perform the operation of reading or writing data through an I / O circuit close to each memory region.

[0123] In the examples, reference Figure 10A , the memory device 200 can read data from or write data to the sixth storage region MR6d through the sixth page buffer PB6d and the second I / O circuit 302. In this case, the distance between the sixth storage region MR6d and the second I / O circuit 302 can be smaller than the distance between the sixth storage region MR6d and the first I / O circuit 301.

[0124] In the examples, reference Figure 10B , the memory device 200 can read data from or write data to the fourth storage region MR4d through the fourth page buffer PB4d and the first I / O circuit 301. In this case, the distance between the fourth storage region MR4d and the first I / O circuit 301 can be smaller than the distance between the fourth storage region MR4d and the second I / O circuit 302.

[0125] Figure 11A and Figure 11B FIG. 2 is a diagram showing an operation method of the memory device 200 according to an embodiment. Figures 1 to 5 、 Figure 9A and Figure 9B To describe Figure 11A and Figure 11B , and repeated descriptions can be omitted.

[0126] The following description focuses on Figure 11A and Figure 11B The operation of the memory device 200 shown in FIG. Figure 9A and Figure 9B The differences between the operations of the memory device 200 shown in FIG.

[0127] Reference Figure 11A and Figure 11B ,and Figure 9A and Figure 9B The first I / O unit IOC_A1a and the second I / O unit IOC_A2a are different. Figure 11A and Figure 11B The first I / O cell 10C_A1b and the second I / O cell 10C_A2b in the circuit may be spaced apart from each other in the third direction D3. The first pad circuit 303 and the second pad circuit 304 may be spaced apart from each other in the third direction D3. The first I / O circuit 301 and the first pad circuit 303 may be spaced apart from each other in the second direction D2 and may be electrically connected to each other via wiring. The second I / O circuit 302 and the second pad circuit 304 may be spaced apart from each other in the second direction D2 and may be electrically connected to each other via wiring.

[0128] When reading or writing data stored in the first memory cell array MCA1 , the memory device 200 may perform an operation of reading or writing data by using the first page buffer circuit PBC1 and the first I / O unit IOC_A1 a .

[0129] In the examples, reference Figure 11A , the memory device 200 may read data from or write data to the first memory region MR1u through the first page buffer PB1u and the first I / O circuit 301 .

[0130] In the examples, reference Figure 11B , the memory device 200 can read data from the eighth memory region MR8u or write data to the eighth memory region MR8u through the eighth page buffer PB8u and the first I / O circuit 301.

[0131] When reading or writing data stored in the second memory cell array MCA2 , the memory device 200 may perform operations of reading or writing data by using the second page buffer circuit PBC2 and the second I / O unit IOC_A2 a .

[0132] In the examples, reference Figure 11A , the memory device 200 can read data from or write data to the seventh memory region MR7 d through the seventh page buffer PB7 d and the second I / O circuit 302 .

[0133] In the examples, reference Figure 11B , the memory device 200 can read data from the second memory region MR2 d or write data to the second memory region MR2 d through the second page buffer PB2 d and the second I / O circuit 302 .

[0134] Figure 12A and Figure 12B FIG. 2 is a diagram showing an operation method of the memory device 200 according to an embodiment. Figures 1 to 5 、 Figure 11A and Figure 11B To describe Figure 12A and Figure 12B , and repeated descriptions can be omitted.

[0135] The following description focuses on Figure 12A and Figure 12B The operation of the memory device 200 shown in FIG. Figure 11A and Figure 11B The differences between the operations of the memory device 200 shown in FIG.

[0136] Reference Figure 12A and Figure 12B When reading data from or writing data to a storage area included in the first memory cell array MCA1, the memory device 200 may perform the operation of reading or writing data by using an I / O circuit close to each storage area.

[0137] In the examples, reference Figure 12A , the memory device 200 can read data from or write data to the fifth storage region MR5u through the fifth page buffer PB5u and the first I / O circuit 301. In this case, the distance between the fifth storage region MR5u and the first I / O circuit 301 can be smaller than the distance between the fifth storage region MR5u and the second I / O circuit 302.

[0138] In the examples, reference Figure 12B , the memory device 200 can read data from or write data to the eighth storage region MR8u through the eighth page buffer PB8u and the second I / O circuit 302. In this case, the distance between the eighth storage region MR8u and the second I / O circuit 302 can be smaller than the distance between the eighth storage region MR8u and the first I / O circuit 301.

[0139] When reading or writing data from or to a storage area included in the second memory cell array MCA2, the memory device 200 may perform the operation of reading or writing data by using an I / O circuit close to each storage area.

[0140] In the examples, reference Figure 12A , the memory device 200 can read data from or write data to the fourth storage region MR4d through the fourth page buffer PB4d and the second I / O circuit 302. In this case, the distance between the fourth storage region MR4d and the second I / O circuit 302 can be smaller than the distance between the fourth storage region MR4d and the first I / O circuit 301.

[0141] In the examples, reference Figure 12B , the memory device 200 can read data from or write data to the second storage region MR2d through the second page buffer PB2d and the first I / O circuit 301. In this case, the distance between the second storage region MR2d and the first I / O circuit 301 can be smaller than the distance between the second storage region MR2d and the second I / O circuit 302.

[0142] Figures 13 to 16 1 and 2 are diagrams showing a memory device 200a, a memory device 200b, a memory device 200c, and a memory device 200d according to an embodiment. Figure 13 It shows Figure 4 FIG. 2 is a diagram illustrating connections between chips included in the memory device 200 a. Figure 14 It shows Figure 5 FIG. 2 is a diagram illustrating connections between chips included in the memory device 200 b. Figure 15 It shows Figure 6 FIG. 2 is a diagram showing connections between chips included in the memory device 200 c. Figure 16 It shows Figure 7 FIG. 2 is a diagram showing connections between chips included in the memory device 200d. Figures 4 to 7 To describe Figures 13 to 16 , and repeated descriptions can be omitted.

[0143] Reference Figure 13 and Figure 15, the first peripheral circuit chip PC1 can be electrically connected to the I / O chip 10C through the first connection unit CN1a and the second connection unit CN2a. The first connection unit CN1a may include a through-silicon via (TSV) TSV11 and a TSV connection unit BP11. The second connection unit CN2a may include a TSV TSV12 and a TSV connection unit BP12. The second peripheral circuit chip PC2 may be electrically connected to the I / O chip 10C through the third connection unit CN3a and the fourth connection unit CN4a. The third connection unit CN3a may include a TSV TSV21, a TSV connection unit BP21, and a TSV connection unit BP31. The fourth connection unit CN4a may include a TSV TSV22, a TSV connection unit BP22, and a TSV connection unit BP32.

[0144] TSV TSV11 may pass through the first peripheral circuit chip PC1 and be electrically connected to TSV connection unit BP11. TSV connection unit BP11 and TSV connection unit BP21 may be electrically connected to the first I / O circuit 301. TSV TSV21 may pass through the I / O chip 10C and be electrically connected to TSV connection unit BP21 and TSV connection unit BP31. TSV TSV31 may pass through the second peripheral circuit chip PC2 and electrically connect TSV connection unit BP31 to the components included in the second peripheral circuit chip PC2. TSV TSV12 may pass through the first peripheral circuit chip PC1 and be electrically connected to TSV connection unit BP12. TSV connection unit BP12 and TSV connection unit BP22 may be electrically connected to the second I / O circuit 302. TSV TSV22 may pass through the I / O chip 10C and be electrically connected to TSV connection unit BP22 and TSV connection unit BP32. The TSV TSV32 may pass through the second peripheral circuit chip PC2 and electrically connect the TSV connection unit BP32 to components included in the second peripheral circuit chip PC2 .

[0145] Reference Figure 14 and Figure 16 , the first peripheral circuit chip PC1 may be electrically connected to the I / O chip 10C through the first connection unit CN1b. The first connection unit CN1b may include a TSV TSV11 and a TSV connection unit BP11. The TSV TSV11 may pass through the first peripheral circuit chip PC1 and be electrically connected to the TSV connection unit BP11. The TSV connection unit BP11 may be electrically connected to the TSV TSV61 (e.g., referring to the TSV connection unit BP11) through the first I / O circuit 301. Figures 21 to 22 ).

[0146] The second peripheral circuit chip PC2 can be electrically connected to the I / O chip 10C through the second connection unit CN2b. The second connection unit CN2b may include a TSV TSV22, a TSV connection unit BP22, and a TSV connection unit BP32. The TSV TSV22 may pass through the I / O chip 10C and be electrically connected to the TSV connection unit BP22. The TSV connection unit BP22 may be electrically connected to the TSV TSV61 (e.g., referring to FIG. 1 ) through the second I / O circuit 302. Figures 21 to 22 ). The TSV TSV32 may pass through the second peripheral circuit chip PC2 and electrically connect components included in the second peripheral circuit chip PC2 to the TSV connection unit BP32.

[0147] Reference Figure 13 and Figure 14 , the contact plug PT21 may be electrically connected to the first pad circuit 303 through the contact bonding pad PBP21. The contact plug PT22 may be electrically connected to the second pad circuit 304 through the contact bonding pad PBP22.

[0148] As used herein, a TSV connection unit may refer to a component provided for electrical connection between a TSV and another component.

[0149] In an embodiment, the TSV connection units BP11, BP12, BP21, BP22, BP31, and BP32 may include conductive pads. The conductive pads may include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), and ruthenium (Ru), or alloys thereof.

[0150] In an embodiment, the TSV connection units BP11, BP12, BP21, BP22, BP31, and BP32 may include conductive bumps. The conductive bumps may include metals such as tin (Sn), copper (Cu), silver (Ag), gold (Au), tungsten (W), bismuth (Bi), zirconium (Zr), zinc (Zn), cobalt (Co), and nickel (Ni), or alloys thereof.

[0151] Figures 17 to 20 are diagrams showing a memory device 200f, a memory device 200g, a memory device 200h, and a memory device 200i according to an embodiment. Figures 13 to 16 To describe Figures 17 to 20 , and repeated descriptions can be omitted.

[0152] Reference Figure 17 , Figure 17 The memory device 200f may correspond to Figure 13However, with the memory device 200a. Figure 13 The memory device 200a is different. Figure 17 The memory device 200f may not include an I / O chip IOC, and Figure 17 The second peripheral circuit chip PC2_DB of the memory device 200f may include Figure 13 Components included in the I / O chip IOC.

[0153] Reference Figure 18 , Figure 18 The memory device 200g may correspond to Figure 14 However, with the memory device 200b Figure 14 The memory device 200b is different. Figure 18 The memory device 200g may not include an I / O chip IOC, and Figure 18 The second peripheral circuit chip PC2_DB of the memory device 200g may include Figure 14 Components included in the I / O chip IOC.

[0154] Reference Figure 19 , Figure 19 The memory device 200h may correspond to Figure 15 However, with the memory device 200c Figure 15 The memory device 200c is different. Figure 19 The memory device 200h may not include an I / O chip IOC, and Figure 19 The second peripheral circuit chip PC2_DB of the memory device 200h may include Figure 15 Components included in the I / O chip IOC.

[0155] Reference Figure 20 , Figure 20 The memory device 200i may correspond to Figure 16 However, with the memory device 200d. Figure 16 The memory device 200d is different. Figure 20 The memory device 200i may not include an I / O chip IOC, and Figure 20 The second peripheral circuit chip PC2_DB of the memory device 200h may include Figure 16 Components included in the I / O chip IOC.

[0156] exist Figures 17 to 20 , the second peripheral circuit chip PC2_DB is shown as including Figures 13 to 16 The I / O chip IOC includes components, and Figures 17 to 20 The first peripheral circuit chip PC1 may include Figures 13 to 16 Components included in the I / O chip IOC.

[0157] Reference Figures 17 to 20 The second peripheral circuit chip PC2_DB may include a second page buffer circuit PBC2, a first I / O circuit 301, a second I / O circuit 302, a first pad circuit 303, and a second pad circuit 304. The second page buffer circuit PBC2 may be formed on the front side cell FS of the second peripheral circuit chip PC2_DB. The first I / O circuit 301, the second I / O circuit 302, the first pad circuit 303, and the second pad circuit 304 may be formed on the back side cell BS of the second peripheral circuit chip PC2_DB.

[0158] Reference Figure 17 and Figure 19 , the first peripheral circuit chip PC1 may be electrically connected to the back side unit BS of the second peripheral circuit chip PC2_DB through the first connection unit CN1c and the second connection unit CN2c.

[0159] The first connection unit CN1c may include a TSV TSV11 and a TSV connection unit BP11. The TSV TSV11 may pass through the first peripheral circuit chip PC1 and be electrically connected to the TSV connection unit BP11. The TSV connection unit BP11 may be electrically connected to the first I / O circuit 301.

[0160] The second connection unit CN2c may include a TSV TSV12 and a TSV connection unit BP12. The TSV TSV12 may pass through the first peripheral circuit chip PC1 and be electrically connected to the TSV connection unit BP12. The TSV connection unit BP12 may be electrically connected to the second I / O circuit 302. The TSV TSV22 may pass through the second peripheral circuit chip PC2_DB and be electrically connected to the TSV connection unit BP22.

[0161] The front side unit FS and the back side unit BS of the second peripheral circuit chip PC2_DB may be electrically connected to each other through the third connection unit CN3 c and the fourth connection unit CN4 c.

[0162] The third connection unit CN3 c may include a TSV TSV21 and a TSV connection unit BP21 . The TSV TSV21 may pass through the second peripheral circuit chip PC2_DB and be electrically connected to the TSV connection unit BP21 . The TSV connection unit BP21 may be electrically connected to the first I / O circuit 301 .

[0163] The fourth connection unit CN4c can electrically connect the front side unit FS and the back side unit BS of the second peripheral circuit chip PC2_DB to each other. The fourth connection unit CN4c may include a TSV TSV22 and a TSV connection unit BP22. The TSV TSV22 may pass through the second peripheral circuit chip PC2_DB and be electrically connected to the TSV connection unit BP22. The TSV connection unit BP22 may be electrically connected to the second I / O circuit 302.

[0164] Reference Figure 18 and Figure 20 , the first and second peripheral circuit chips PC1_DB may be electrically connected to each other through the first and second connection units CN1d and CN2d.

[0165] The first connection unit CN1 d may include a TSV TSV11 and a TSV connection unit BP11 . The TSV TSV11 may pass through the first peripheral circuit chip PC1 and be electrically connected to the TSV connection unit BP11 . The TSV connection unit BP11 may be electrically connected to the first I / O circuit 301 .

[0166] The second connection unit CN2d may include a TSV TSV22 and a TSV connection unit BP22. The TSV TSV22 may pass through the second peripheral circuit chip PC2_DB and be electrically connected to the TSV connection unit BP22. The TSV connection unit BP22 may be electrically connected to the second I / O circuit 302.

[0167] Figure 21 is a diagram illustrating a memory device 200j according to an embodiment.

[0168] Reference Figure 21, the memory device 200j may include a first cell array chip CAC1, a first peripheral circuit chip PC1, a second cell array chip CAC2, a second peripheral circuit chip PC2, an I / O chip 10C, a third peripheral circuit chip PC3, a third cell array chip CAC3, a fourth peripheral circuit chip PC4, and a fourth cell array chip CAC4. In addition, the memory device 200j may include a first bonding pad PD1, a second bonding pad PD2, metal patterns MP11, MP12, MP21, MP22, MP31, MP32, MP41, and MP42, contact plugs PT11, PT12, PT21, PT22, PT31, PT32, PT41, and PT42, contact bonding pads PBP11, PBP12, PBP21, PBP22, PBP31, PBP32, PBP41, and PBP42, TSVs TSV11, TSV12, TSV21, TSV22, TSV31, TSV32, TSV33, TSV34, TSV41, TSV42, TSV43, TSV44, TSV51, TSV52, TSV61, and TSV62, and a TSV connection unit BP11. BP12, BP21, BP22, BP31, BP32, BP33, BP34, BP41, BP42, BP43, BP44, BP51, BP52, BP61 and BP62.

[0169] Contact plugs PT11 and PT12 may pass through the first cell array chip CAC1. Contact plugs PT21 and PT22 may pass through the first peripheral circuit chip PC1. Contact plugs PT31 and PT32 may pass through the second cell array chip CAC2. Contact plugs PT41 and PT42 may pass through the second peripheral circuit chip PC2.

[0170] The first bonding pad PD1 may be electrically connected to the contact bonding pad PBP11 through the contact plug PT11. The second bonding pad PD2 may be electrically connected to the contact bonding pad PBP12 through the contact plug PT12. The contact plug PT11 may be electrically connected to the contact plug PT21 through the contact bonding pad PBP11. The contact plug PT12 may be electrically connected to the contact plug PT22 through the contact bonding pad PBP12. The contact plug PT21 may be electrically connected to the contact plug PT31 through the contact bonding pad PBP21. The contact plug PT22 may be electrically connected to the contact plug PT32 through the contact bonding pad PBP22. The contact plug PT31 may be electrically connected to the contact plug PT41 through the contact bonding pad PBP31. The contact plug PT32 may be electrically connected to the contact plug PT42 through the contact bonding pad PBP32. The contact plug PT41 may be electrically connected to the I / O chip 10C through the contact bonding pad PBP41. The contact plugs PT42 may be electrically connected to the I / O chip IOC through the contact bonding pads PBP42.

[0171] Components included in the first peripheral circuit chip PC1 can transmit and receive data to and from the I / O chip 10C through TSVs TSV11, TSV12, TSV21, TSV22, TSV31, and TSV32. TSVs TSV11 and TSV12 may pass through the first peripheral circuit chip PC1. TSVs TSV21 and TSV22 may pass through the second cell array chip CAC2. TSVs TSV31 and TSV32 may pass through the second peripheral circuit chip PC2.

[0172] TSVs TSV11 and TSV12 may be electrically connected to components of the first peripheral circuit chip PC1. TSV TSV11 may be electrically connected to TSV TSV21 via TSV connection unit BP11. TSV TSV12 may be electrically connected to TSV TSV22 via TSV connection unit BP12. TSV TSV21 may be electrically connected to TSV TSV31 via TSV connection unit BP21. TSV TSV22 may be electrically connected to TSV TSV32 via TSV connection unit BP22. TSV TSV31 may be electrically connected to the I / O chip 10C via TSV connection unit BP31. TSV TSV32 may be electrically connected to the I / O chip 10C via TSV connection unit BP32.

[0173] Components included in the second peripheral circuit chip PC2 can transmit and receive data to and from the I / O chip 10C through TSVs TSV33 and TSV34. TSVs TSV33 and TSV34 may pass through the second peripheral circuit chip PC2. TSVs TSV33 may electrically connect the components included in the second peripheral circuit chip PC2 to TSV connection units BP33. TSVs TSV34 may electrically connect the components included in the second peripheral circuit chip PC2 to TSV connection units BP34. TSV connection units BP33 may electrically connect TSVs TSV33 to the I / O chip 10C. TSV connection units BP34 may electrically connect TSVs TSV34 to the I / O chip 10C.

[0174] Components included in the third peripheral circuit chip PC3 can transmit and receive data to and from the I / O chip 10C through TSVs TSV43 and TSV44. TSVs TSV43 and TSV44 may pass through the third peripheral circuit chip PC3. TSVs TSV43 may electrically connect the components included in the third peripheral circuit chip PC3 to TSV connection unit BP43. TSVs TSV44 may electrically connect the components included in the third peripheral circuit chip PC3 to TSV connection unit BP44. TSV connection unit BP43 may electrically connect TSVs TSV43 to the I / O chip 10C. TSV connection unit BP34 may electrically connect TSVs TSV34 to the I / O chip 10C.

[0175] Components included in the fourth peripheral circuit chip PC4 can transmit and receive data to and from the I / O chip 10C through TSVs TSV41, TSV42, TSV51, TSV52, TSV61, and TSV62. TSVs TSV41 and TSV42 may pass through the third peripheral circuit chip PC3. TSVs TSV51 and TSV52 may pass through the third cell array chip CAC3. TSVs TSV61 and TSV62 may pass through the fourth peripheral circuit chip PC4.

[0176] TSV TSV41 may be electrically connected to TSV TSV51 through TSV connection unit BP51. TSV TSV42 may be electrically connected to TSV TSV52 through TSV connection unit BP52. TSV TSV51 may be electrically connected to TSV TSV61 through TSV connection unit BP61. TSV TSV52 may be electrically connected to TSV TSV62 through TSV connection unit BP62. TSV TSV61 and TSV62 may be electrically connected to components of the fourth peripheral circuit chip PC4.

[0177] The first bonding pad PD1 and the second bonding pad PD2 may be disposed on the first cell array chip CAC1. The first peripheral circuit chip PC1 may be located below the first cell array chip CAC1. The second cell array chip CAC2 may be located below the first peripheral circuit chip PC1. The second peripheral circuit chip PC2 may be located below the second cell array chip CAC2. The I / O chip 10C may be located below the second peripheral circuit chip PC2. The third peripheral circuit chip PC3 may be disposed below the I / O chip 10C. The third cell array chip CAC3 may be located below the third peripheral circuit chip PC3. The fourth peripheral circuit chip PC4 may be located below the third cell array chip CAC3. The fourth cell array chip CAC4 may be located below the fourth peripheral circuit chip PC4.

[0178] The first cell array chip CAC1 can be bonded to the first peripheral circuit chip PC1 through metal patterns MP11 and MP12. The second cell array chip CAC2 can be bonded to the second peripheral circuit chip PC2 through metal patterns MP21 and MP22. The third cell array chip CAC3 can be bonded to the third peripheral circuit chip PC3 through metal patterns MP31 and MP32. The fourth cell array chip CAC4 can be bonded to the fourth peripheral circuit chip PC4 through metal patterns MP41 and MP42.

[0179] The first peripheral circuit chip PC1 may be electrically connected to the I / O chip 10C through first and second connection units. Each of the first and second connection units may include a TSV and pass through the first peripheral circuit chip PC1, the second cell array chip CAC2, and the second peripheral circuit chip PC2.

[0180] In an embodiment, the I / O chip 10C may further include a buffer chip. The buffer chip may be a chip configured to interface signals transmitted and received between the memory controller 100 and the first cell array chip CAC1, the second cell array chip CAC2, the third cell array chip CAC3, and the fourth cell array chip CAC4 to reduce the load on the I / O chip 10C.

[0181] Figure 22 FIG. 2 is a diagram showing a memory device 200k according to an embodiment. Figure 21 To describe Figure 22 , and repeated descriptions can be omitted.

[0182] The following description focuses on Figure 22 The memory device is 200k with Figure 21 The difference between the memory devices 200j.

[0183] Reference Figure 22 , the memory device 200k may include a first cell array chip CAC1, a first peripheral circuit chip PC1, a second cell array chip CAC2, a second peripheral circuit chip PC2, an I / O chip 10C, a third peripheral circuit chip PC3, a third cell array chip CAC3, a fourth peripheral circuit chip PC4, and a fourth cell array chip CAC4. In addition, the memory device 200k may include a first bonding pad PD1, a second bonding pad PD2, metal patterns MP11, MP12, MP21, MP22, MP31, MP32, MP41, and MP42, contact plugs PT11, PT12, PT21, PT22, PT31, PT32, PT41, and PT42, contact bonding pads PBP11, PBP12, PBP21, PBP22, PBP31, PBP32, PBP41, and PBP42, TSVs TSV11, TSV12, TSV21, TSV22, TSV31, TSV32, TSV41, TSV42, TSV51, TSV52, TSV61, and TSV62, and TSV connection units BP11, BP12, BP21, BP22, BP31, BP32, BP41, BP42, BP51, BP52, BP61 and BP62.

[0184] The first peripheral circuit chip PC1 can transmit and receive data to and from the I / O chip 10C through the second peripheral circuit chip PC2. Components included in the first peripheral circuit chip PC1 can transmit and receive data to and from the second peripheral circuit chip PC2 through TSVs TSV11, TSV12, TSV21, and TSV22.

[0185] TSVs TSV11 and TSV12 may pass through the first peripheral circuit chip PC1 , TSVs TSV21 and TSV22 may pass through the first cell array chip CAC1 , and TSVs TSV31 and TSV32 may pass through the second peripheral circuit chip PC2 .

[0186] TSVs TSV11 and TSV12 may be electrically connected to components of the first peripheral circuit chip PC1. TSV TSV11 may be electrically connected to TSV TSV21 via TSV connection unit BP11. TSV TSV12 may be electrically connected to TSV TSV22 via TSV connection unit BP12. TSV TSV21 may be electrically connected to the second peripheral circuit chip PC2 via TSV connection unit BP21. TSV TSV22 may be electrically connected to the second peripheral circuit chip PC2 via TSV connection unit BP22.

[0187] TSVs TSV31 and TSVs TSV32 may pass through the second peripheral circuit chip PC2. TSVs TSV31 and TSV32 may be electrically connected to components of the second peripheral circuit chip PC2. TSVs TSV31 may be electrically connected to the I / O chip 10C via TSV connection units BP31. TSVs TSV32 may be electrically connected to the I / O chip 10C via TSV connection units BP32.

[0188] TSVs TSV41 and TSVs TSV42 may pass through the third peripheral circuit chip PC3. TSVs TSV41 and TSV42 may be electrically connected to components of the third peripheral circuit chip PC3. TSVs TSV41 may be electrically connected to the I / O chip 10C via TSV connection units BP41. TSVs TSV42 may be electrically connected to the I / O chip 10C via TSV connection units BP42.

[0189] The fourth peripheral circuit chip PC4 can transmit and receive data to and from the I / O chip 10C through the third peripheral circuit chip PC3. Components included in the fourth peripheral circuit chip PC4 can transmit and receive data to and from the third peripheral circuit chip PC3 through TSVs TSV51, TSV52, TSV61, and TSV62.

[0190] TSVs TSV41 and TSV42 may pass through the third peripheral circuit chip PC3 , TSVs TSV51 and TSV52 may pass through the third cell array chip CAC3 , and TSVs TSV61 and TSV62 may pass through the fourth peripheral circuit chip PC4 .

[0191] The TSV TSV51 may be electrically connected to the third peripheral circuit chip PC3 through the TSV connection unit BP51. The TSV TSV52 may be electrically connected to the third peripheral circuit chip PC3 through the TSV connection unit BP52.

[0192] TSV TSV51 may be electrically connected to TSV TSV61 through TSV connection unit BP61. TSV TSV52 may be electrically connected to TSV TSV62 through TSV connection unit BP62. TSV TSV61 and TSV62 may be electrically connected to components of the fourth peripheral circuit chip PC4.

[0193] In an embodiment, the memory device 200k may not include the I / O chip 10C. In this case, the third peripheral circuit chip PC3 of the memory device 200k may have the same Figures 17 to 20That is, the page buffer circuit may be formed on the front surface of the third peripheral circuit chip PC3, and the first I / O circuit 301, the second I / O circuit 302, the first pad circuit 303, and the second pad circuit 304 may be formed on the rear surface of the third peripheral circuit chip PC3.

[0194] Figure 23 FIG. 2 is a diagram showing a memory device 2001 according to an embodiment. Figure 21 To describe Figure 23 , and repeated descriptions can be omitted.

[0195] The following description focuses on Figure 23 The memory device 2001 and Figure 21 The difference between the memory devices 200j.

[0196] Reference Figure 23 , the memory device 2001 may include a first cell array chip CAC1, a first peripheral circuit chip PC1, an I / O chip 10C, a second peripheral circuit chip PC2, a second cell array chip CAC2, a third peripheral circuit chip PC3, a third cell array chip CAC3, a first bonding pad PD1, a second bonding pad PD2, metal patterns MP11, MP12, MP21, MP22, MP31 and MP32, contact plugs PT11, PT12, PT21 and PT22, contact bonding pads PBP11, PBP12, PBP21 and PBP22, TSVs TSV11, TSV12, TSV21, TSV22, TSV23, TSV24, TSV31, TSV32, TSV41 and TSV42, and TSV connection units BP11, BP12, BP21, BP22, BP23, BP24, BP31, BP32, BP41 and BP42.

[0197] The chips included in the memory device 2001 may be arranged asymmetrically with respect to the I / O chip 10C. Specifically, the first peripheral circuit chip PC1 may be located below the first cell array chip CAC1. The I / O chip 10C may be located below the first peripheral circuit chip PC1. The second peripheral circuit chip PC2 may be located below the I / O chip 10C. The second cell array chip CAC2 may be located below the second peripheral circuit chip PC2. The third peripheral circuit chip PC3 may be located below the second cell array chip CAC2. The third cell array chip CAC3 may be located below the third peripheral circuit chip PC3.

[0198] The first cell array chip CAC1 may be bonded to the first peripheral circuit chip PC1 through the metal patterns MP11 and MP12. The second cell array chip CAC2 may be bonded to the second peripheral circuit chip PC2 through the metal patterns MP21 and MP22. The third cell array chip CAC3 may be bonded to the third peripheral circuit chip PC3 through the metal patterns MP31 and MP32.

[0199] The contact plugs PT11 and PT12 may pass through the first cell array chip CAC1 , and the contact plugs PT21 and PT22 may pass through the first peripheral circuit chip PC1 .

[0200] The first bonding pad PD1 may be electrically connected to the contact bonding pad PBP11 through the contact plug PT11. The second bonding pad PD2 may be electrically connected to the contact bonding pad PBP12 through the contact plug PT12. The contact plug PT11 may be electrically connected to the contact bonding pad PT21 through the contact bonding pad PBP11. The contact plug PT12 may be electrically connected to the contact plug PT22 through the contact bonding pad PBP12. The contact plug PT21 may be electrically connected to the I / O chip 10C through the contact bonding pad PBP21. The contact plug PT22 may be electrically connected to the I / O chip 10C through the contact bonding pad PBP22.

[0201] TSVs TSV11 and TSV12 may pass through the first peripheral circuit chip PC1. TSVs TSV21, TSV22, TSV23, and TSV24 may pass through the second peripheral circuit chip PC2. TSVs TSV31 and TSV32 may pass through the second cell array chip CAC2. TSVs TSV41 and TSV42 may pass through the third peripheral circuit chip PC3.

[0202] TSVs TSV11 and TSV12 may be electrically connected to components included in the first peripheral circuit chip PC1. TSV TSV11 may be electrically connected to the I / O chip 10C through a TSV connection unit BP11. TSV TSV12 may be electrically connected to the I / O chip 10C through a TSV connection unit BP12.

[0203] TSV TSV21 may be electrically connected to the I / O chip 10C through TSV connection unit BP21. TSV TSV22 may be electrically connected to the I / O chip 10C through TSV connection unit BP22. TSV TSV23 may be electrically connected to the I / O chip 10C through TSV connection unit BP23. TSV TSV24 may be electrically connected to the I / O chip 10C through TSV connection unit BP24.

[0204] TSVs TSV23 and TSV24 may be electrically connected to components included in the second peripheral circuit chip PC2. TSV TSV21 may be electrically connected to TSV TSV31 via a TSV connection unit BP31. TSV TSV22 may be electrically connected to TSV TSV32 via a TSV connection unit BP32. TSV TSV31 may be electrically connected to TSV TSV41 via a TSV connection unit BP41. TSV TSV32 may be electrically connected to TSV TSV42 via a TSV connection unit BP42. TSVs TSV41 and TSV42 may be electrically connected to components included in the third peripheral circuit chip PC3.

[0205] In an embodiment, the memory device 2001 may not include the I / O chip 10C. In this case, the second peripheral circuit chip PC2 of the memory device 2001 may have the same Figures 17 to 20 That is, the page buffer circuit may be formed on the front surface of the second peripheral circuit chip PC2, and the first I / O circuit 301, the second I / O circuit 302, the first pad circuit 303, and the second pad circuit 304 may be formed on the rear surface of the second peripheral circuit chip PC2.

[0206] Figure 24 is a diagram illustrating a memory device 200m according to an embodiment.

[0207] Reference Figure 24 , the memory device 200m may include a first cell array chip CAC1, a first peripheral circuit chip PC1, a second peripheral circuit chip PC2, a second cell array chip CAC2, a first bonding pad PD1, a second bonding pad PD2, metal patterns MP11, MP12, MP21 and MP22, contact plugs PT11, PT12 and PT22, and contact bonding pads PBP11, PBP12 and PBP22.

[0208] The first cell array chip CAC1 may be bonded to the first peripheral circuit chip PC1 through the metal patterns MP11 and MP12 , and the second cell array chip CAC2 may be bonded to the second peripheral circuit chip PC2 through the metal patterns MP21 and MP22 .

[0209] The memory device 200m can be divided into a first memory device 200m_1 and a second memory device 200m_2. The first memory device 200m_1 may include a first cell array chip CAC1 and a first peripheral circuit chip PC1. The second memory device 200m_2 may include a second cell array chip CAC2 and a second peripheral circuit chip PC2.

[0210] The first peripheral circuit chip PC1 may include a page buffer circuit configured to write data to or read data from the memory cell array of the first cell array chip CAC1. The first peripheral circuit chip PC1 may include an I / O circuit configured to perform I / O operations related to the first cell array chip CAC1.

[0211] The second peripheral circuit chip PC2 may include a page buffer circuit configured to write data to or read data from the memory cell array of the second cell array chip CAC2. The second peripheral circuit chip PC2 may include an I / O circuit configured to perform I / O operations related to the second cell array chip CAC2.

[0212] The contact plugs PT11 and PT12 may pass through the first cell array chip CAC1 , and the contact plug PT22 may pass through the first peripheral circuit chip PC1 .

[0213] The contact plug PT11 may electrically connect the first bonding pad PD1 to the contact bonding pad PBP11. The contact plug PT12 may electrically connect the second bonding pad PD2 to the contact bonding pad PBP12.

[0214] The contact bonding pad PBP11 may electrically connect the contact plug PT11 to the first peripheral circuit chip PC1. The contact bonding pad PBP12 may electrically connect the contact plug PT11 to the contact plug PT22. The contact plug PT22 may be electrically connected to the second peripheral circuit chip PC2 through the contact bonding pad PBP22.

[0215] The first memory device 200m_1 may transmit and receive data to and from the memory controller 100 through the first bonding pad PD1. The second memory device 200m_2 may transmit and receive data to and from the memory controller 100 through the second bonding pad PD2.

[0216] In an embodiment, the first memory device 200 m_1 may write data to or read data from the memory cell array of the first cell array chip CAC1 through the first bonding pad PD1 .

[0217] In an embodiment, the second memory device 200m_2 may write data to or read data from the memory cell array of the second cell array chip CAC2 through the second bonding pad PD2.

[0218] Figure 25 is a diagram illustrating a memory device 1500 according to some embodiments of the present disclosure.

[0219] Reference Figure 25 , the memory device 1500 may have a chip-to-chip (C2C) structure. At least one upper chip including a cell region and a lower chip including a peripheral circuit region PERI may be manufactured separately, and then, the at least one upper chip and the lower chip may be connected to each other by a bonding method to realize the C2C structure. For example, the bonding method may refer to a method of electrically or physically connecting a bonding metal pattern formed in the uppermost metal layer of the upper chip to a bonding metal pattern formed in the uppermost metal layer of the lower chip. For example, in the case where the bonding metal pattern is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method. Alternatively, the bonding metal pattern may be formed of aluminum (Al) or tungsten (W).

[0220] The memory device 1500 may include at least one upper chip including a cell region. Figure 25 As shown, the memory device 1500 may include two upper chips. However, the number of upper chips is not limited thereto. In the case where the memory device 1500 includes two upper chips, a first upper chip including a first cell area CELL1, a second upper chip including a second cell area CELL2, and a lower chip including a peripheral circuit area PERI may be manufactured separately, and then, the first upper chip, the second upper chip, and the lower chip may be connected to each other by a bonding method to manufacture the memory device 1500. The first upper chip may be flipped over and then connected to the lower chip by a bonding method, and the second upper chip may also be flipped over and then connected to the first upper chip by a bonding method. Hereinafter, the upper and lower parts of each of the first upper chip and the second upper chip will be defined based on before each of the first upper chip and the second upper chip is flipped over. In other words, the upper part of the lower chip may refer to the upper part defined based on the +Z axis direction, and the upper part of each of the first upper chip and the second upper chip may refer to the upper part defined based on the Figure 25 The upper portion is defined in the -Z-axis direction. However, the embodiments of the present disclosure are not limited thereto. In certain embodiments, one of the first upper chip and the second upper chip may be flipped over and then connected to the corresponding chip by a bonding method.

[0221] Each of the peripheral circuit region PERI and the first and second cell regions CELL1 and CELL2 of the memory device 1500 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.

[0222] The peripheral circuit region PERI may include a first substrate 1210 and a plurality of circuit elements 1220a, 1220b, and 1220c formed on the first substrate 1210. An interlayer insulating layer 1215 including one or more insulating layers may be provided on the plurality of circuit elements 1220a, 1220b, and 1220c, and a plurality of metal lines electrically connected to the plurality of circuit elements 1220a, 1220b, and 1220c may be provided in the interlayer insulating layer 1215. For example, the plurality of metal lines may include first metal lines 1230a, 1230b, and 1230c connected to the plurality of circuit elements 1220a, 1220b, and 1220c; and second metal lines 1240a, 1240b, and 1240c formed on the first metal lines 1230a, 1230b, and 1230c. The plurality of metal lines may be formed of at least one of a variety of conductive materials. For example, the first metal lines 1230 a , 1230 b , and 1230 c may be formed of tungsten having a relatively high resistivity, and the second metal lines 1240 a , 1240 b , and 1240 c may be formed of copper having a relatively low resistivity.

[0223] In this embodiment, the first metal lines 1230a, 1230b, and 1230c and the second metal lines 1240a, 1240b, and 1240c are shown and described. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, at least one or more additional metal lines may also be formed on the second metal lines 1240a, 1240b, and 1240c. In this case, the second metal lines 1240a, 1240b, and 1240c may be formed of aluminum, and at least some of the additional metal lines formed on the second metal lines 1240a, 1240b, and 1240c may be formed of copper having a lower resistivity than the aluminum of the second metal lines 1240a, 1240b, and 1240c.

[0224] The interlayer insulating layer 1215 may be disposed on the first substrate 1210 and may include an insulating material such as silicon oxide and / or silicon nitride.

[0225] Each of the first cell region CELL1 and the second cell region CELL2 may include at least one memory block. The first cell region CELL1 may include a second substrate 1310 and a common source line 1320. A plurality of word lines 1330 (e.g., word lines 1331 to 1338) may be stacked on the second substrate 1310 in a direction perpendicular to the top surface of the second substrate 1310 (i.e., the Z-axis direction). String select lines and ground select lines may be disposed above and below the word lines 1330, and the plurality of word lines 1330 may be disposed between the string select lines and the ground select lines. Similarly, the second cell region CELL2 may include a third substrate 1410 and a common source line 1420. A plurality of word lines 1430 (e.g., word lines 1431 to 1438) may be stacked on the third substrate 1410 in a direction perpendicular to the top surface of the third substrate 1410 (i.e., the Z-axis direction). Each of the second substrate 1310 and the third substrate 1410 may be formed of at least one of a variety of materials and may be, for example, a silicon substrate, a silicon germanium substrate, a germanium substrate, or a substrate having a single crystal epitaxial layer grown on a single crystal silicon substrate. A plurality of channel structures CH may be formed in each of the first cell region CELL1 and the second cell region CELL2.

[0226] In some embodiments, as shown in region A1 corresponding to region A, a channel structure CH may be provided in the bitline bonding area BLBA and may extend in a direction perpendicular to the top surface of the second substrate 1310 to penetrate the word lines 1330, the string select lines, and the ground select lines. The channel structure CH may include a data storage layer, a channel layer, and a filling insulating layer. The channel layer may be electrically connected to the first metal line 1350c and the second metal line 1360c in the bitline bonding area BLBA. For example, the second metal line 1360c may be a bitline and may be connected to the channel structure CH via the first metal line 1350c. The second metal line 1360c (e.g., a bitline) may extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 1310.

[0227] In some embodiments, as shown in region A2 corresponding to region A, the channel structure CH may include a lower channel LCH and an upper channel UCH connected to each other. For example, the channel structure CH may be formed by a process for forming the lower channel LCH and a process for forming the upper channel UCH. The lower channel LCH may extend perpendicular to the top surface of the second substrate 1310 to penetrate the common source line 1320 and the word lines 1331 and 1332 (e.g., the lower word lines). The lower channel LCH may include a data storage layer, a channel layer, and a filling insulating layer, and may be connected to the upper channel UCH. The upper channel UCH may penetrate the word lines 1333 to 1338 (e.g., the upper word lines). The upper channel UCH may include a data storage layer, a channel layer, and a filling insulating layer, and the channel layer of the upper channel UCH may be electrically connected to the first metal line 1350c and the second metal line 1360c. As the channel length increases, due to the characteristics of the manufacturing process, it may be difficult to form a channel with a substantially uniform width. The memory device 1500 according to the present embodiment may include channels having improved width uniformity since the lower channel LCH and the upper channel UCH are formed through sequentially performed processes.

[0228] In the case where the channel structure CH includes a lower channel LCH and an upper channel UCH, as shown in area A2, the word line located near the boundary between the lower channel LCH and the upper channel UCH can be a dummy word line. For example, the word lines 1332 and 1333 adjacent to the boundary between the lower channel LCH and the upper channel UCH can be dummy word lines. In this case, data may not be stored in the memory cells connected to the dummy word lines. Alternatively, the number of pages corresponding to the memory cells connected to the dummy word lines can be less than the number of pages corresponding to the memory cells connected to the general word lines. The voltage level applied to the dummy word line can be different from the voltage level applied to the general word line, and thus the effect of the uneven channel width between the lower channel LCH and the upper channel UCH on the operation of the memory device can be reduced.

[0229] Meanwhile, in region A2, the number of word lines 1331 and 1332 (e.g., lower word lines) penetrated by the lower channel LCH is less than the number of word lines 1333 to 1338 (e.g., upper word lines) penetrated by the upper channel UCH. However, the embodiments of the present disclosure are not limited thereto. In some embodiments, the number of lower word lines penetrated by the lower channel LCH may be equal to or greater than the number of upper word lines penetrated by the upper channel UCH. Furthermore, the structural features and connection relationships of the channel structure CH disposed in the second cell region CELL2 may be substantially the same as those of the channel structure CH disposed in the first cell region CELL1.

[0230] In the bit line bonding area BLBA, the first through electrode THV1 may be disposed in the first cell area CELL1, and the second through electrode THV2 may be disposed in the second cell area CELL2. Figure 25 As shown, the first through-electrode THV1 may penetrate the common source line 1320 and the plurality of word lines 1330. In some embodiments, the first through-electrode THV1 may also penetrate the second substrate 1310. The first through-electrode THV1 may include a conductive material. Alternatively, the first through-electrode THV1 may include a conductive material surrounded by an insulating material. The second through-electrode THV2 may have the same shape and structure as the first through-electrode THV1.

[0231] In some embodiments, the first through-electrode THV1 and the second through-electrode THV2 may be electrically connected to each other via a first through-metal pattern 1372d and a second through-metal pattern 1472d. The first through-metal pattern 1372d may be formed at the bottom end of the first upper chip including the first cell region CELL1, and the second through-metal pattern 1472d may be formed at the top end of the second upper chip including the second cell region CELL2. The first through-electrode THV1 may be electrically connected to the first metal line 1350c and the second metal line 1360c. A lower via 1371d may be formed between the first through-electrode THV1 and the first through-metal pattern 1372d, and an upper via 1471d may be formed between the second through-electrode THV2 and the second through-metal pattern 1472d. The first through-metal pattern 1372d and the second through-metal pattern 1472d may be connected to each other by a bonding method.

[0232] Additionally, in the bitline bonding area BLBA, an upper metal pattern 1252 may be formed in the uppermost metal layer of the peripheral circuit area PERI, and an upper metal pattern 1392 having the same shape as the upper metal pattern 1252 may be formed in the uppermost metal layer of the first cell area CELL1. The upper metal pattern 1392 of the first cell area CELL1 and the upper metal pattern 1252 of the peripheral circuit area PERI may be electrically connected to each other via a bonding method. In the bitline bonding area BLBA, a second metal line 1360c (e.g., a bit line) may be electrically connected to a page buffer included in the peripheral circuit area PERI. For example, some circuit elements 1220c of the peripheral circuit area PERI may constitute the page buffer, and the second metal line 1360c (e.g., a bit line) may be electrically connected to the circuit elements 1220c constituting the page buffer via the upper bonding metal pattern 1370c of the first cell area CELL1 and the upper bonding metal pattern 1270c of the peripheral circuit area PERI.

[0233] Continue to refer to Figure 25In the word line bonding area WLBA, the word lines 1330 of the first cell region CELL1 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the second substrate 1310 and may be connected to a plurality of cell contact plugs 1340 (e.g., contact plugs 1341 to 1347). First metal lines 1350b and second metal lines 1360b may be sequentially connected to the cell contact plugs 1340 connected to the word lines 1330. In the word line bonding area WLBA, the cell contact plugs 1340 may be connected to the peripheral circuit region PERI through an upper bonding metal pattern 1370b of the first cell region CELL1 and an upper bonding metal pattern 1270b of the peripheral circuit region PERI.

[0234] The cell contact plug 1340 may be electrically connected to a row decoder included in the peripheral circuit region PERI. For example, some circuit elements 1220b of the peripheral circuit region PERI may constitute a row decoder, and the cell contact plug 1340 may be electrically connected to the circuit elements 1220b constituting the row decoder via the upper bonding metal pattern 1370b of the first cell region CELL1 and the upper bonding metal pattern 1270b of the peripheral circuit region PERI. In some embodiments, the operating voltage of the circuit elements 1220b constituting the row decoder may be different from the operating voltage of the circuit elements 1220c constituting the page buffer. For example, the operating voltage of the circuit elements 1220c constituting the page buffer may be greater than the operating voltage of the circuit elements 1220b constituting the row decoder.

[0235] Similarly, in the word line bonding area WLBA, the word lines 1430 of the second cell region CELL2 may extend in a second direction (e.g., the X-axis direction) parallel to the top surface of the third substrate 1410 and may be connected to a plurality of cell contact plugs 1440 (e.g., contact plugs 1441 to 1447). The cell contact plugs 1440 may be connected to the peripheral circuit region PERI through the upper metal pattern of the second cell region CELL2, the lower and upper metal patterns of the first cell region CELL1, and the cell contact plugs 1348.

[0236] In the word line bonding area WLBA, an upper bonding metal pattern 1370b may be formed in the first cell region CELL1, and an upper bonding metal pattern 1270b may be formed in the peripheral circuit region PERI. The upper bonding metal pattern 1370b of the first cell region CELL1 and the upper bonding metal pattern 1270b of the peripheral circuit region PERI may be electrically connected to each other by a bonding method. The upper bonding metal pattern 1370b and the upper bonding metal pattern 1270b may be formed of aluminum, copper, or tungsten.

[0237] In the external pad bonding area PA, a lower metal pattern 1371e may be formed in the lower portion of the first cell region CELL1, and an upper metal pattern 1472a may be formed in the upper portion of the second cell region CELL2. The lower metal pattern 1371e of the first cell region CELL1 and the upper metal pattern 1472a of the second cell region CELL2 may be connected to each other in the external pad bonding area PA by a bonding method. Similarly, the upper metal pattern 1372a may be formed in the upper portion of the first cell region CELL1, and the upper metal pattern 1272a may be formed in the upper portion of the peripheral circuit region PERI. The upper metal pattern 1372a of the first cell region CELL1 and the upper metal pattern 1272a of the peripheral circuit region PERI may be connected to each other by a bonding method.

[0238] Common source line contact plugs 1380 and 1480 may be disposed in the external pad bonding area PA. Common source line contact plugs 1380 and 1480 may be formed of a conductive material, such as a metal, a metal compound, and / or doped polysilicon. Common source line contact plug 1380 of the first cell region CELL1 may be electrically connected to common source line 1320, and common source line contact plug 1480 of the second cell region CELL2 may be electrically connected to common source line 1420. First metal line 1350a and second metal line 1360a may be sequentially stacked on common source line contact plug 1380 of the first cell region CELL1, and first metal line 1450a and second metal line 1460a may be sequentially stacked on common source line contact plug 1480 of the second cell region CELL2.

[0239] Input / output pads (eg, first input / output pad 1205, second input / output pad 1405, and third input / output pad 1406) may be disposed in the external pad landing area PA. Figure 25 , a lower insulating layer 1201 may cover the bottom surface of the first substrate 1210, and first input / output pads 1205 may be formed on the lower insulating layer 1201. The first input / output pads 1205 may be connected to at least one of the plurality of circuit elements 1220a provided in the peripheral circuit region PERI through the first input / output contact plugs 1203, and may be separated from the first substrate 1210 by the lower insulating layer 1201. In addition, a side insulating layer may be provided between the first input / output contact plugs 1203 and the first substrate 1210 to electrically isolate the first input / output contact plugs 1203 from the first substrate 1210.

[0240] An upper insulating layer 1401 covering the top surface of the third substrate 1410 may be formed on the third substrate 1410. Second input / output pads 1405 and / or third input / output pads 1406 may be provided on the upper insulating layer 1401. The second input / output pads 1405 may be connected to at least one of the plurality of circuit elements 1220 a provided in the peripheral circuit region PERI through second input / output contact plugs 1403 and 1303, and the third input / output pads 1406 may be connected to at least one of the plurality of circuit elements 1220 a provided in the peripheral circuit region PERI through third input / output contact plugs 1404 and 1304.

[0241] In some embodiments, the third substrate 1410 may not be provided in a region where the input / output contact plugs are provided. For example, as shown in region B, the third input / output contact plugs 1404 may be separated from the third substrate 1410 in a direction parallel to the top surface of the third substrate 1410 and may penetrate the interlayer insulating layer 1415 of the second cell region CELL2 to connect to the third input / output pads 1406. In this case, the third input / output contact plugs 1404 may be formed by at least one of various processes.

[0242] In some embodiments, as shown in region B1 corresponding to region B, the third input / output contact plug 1404 may extend along a third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 1404 may gradually increase toward the upper insulating layer 1401. In other words, the diameter of the channel structure CH described in region A1 may gradually decrease toward the upper insulating layer 1401, but the diameter of the third input / output contact plug 1404 may gradually increase toward the upper insulating layer 1401. For example, the third input / output contact plug 1404 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other by a bonding method.

[0243] In some embodiments, as shown in region B2 corresponding to region B, the third input / output contact plug 1404 may extend along a third direction (e.g., the Z-axis direction), and the diameter of the third input / output contact plug 1404 may gradually decrease toward the upper insulating layer 1401. In other words, similar to the channel structure CH, the diameter of the third input / output contact plug 1404 may gradually decrease toward the upper insulating layer 1401. For example, the third input / output contact plug 1404 may be formed together with the cell contact plug 1440 before the second cell region ELL2 and the first cell region CELL1 are bonded to each other.

[0244] In some embodiments, the input / output contact plug may overlap with the third substrate 1410. For example, as shown in region C, the second input / output contact plug 1403 may penetrate the interlayer insulating layer 1415 of the second cell region CELL2 along a third direction (e.g., the Z-axis direction) and may be electrically connected to the second input / output pad 1405 through the third substrate 1410. In this case, the connection structure between the second input / output contact plug 1403 and the second input / output pad 1405 may be implemented by various methods.

[0245] In some embodiments, as shown in region C1 corresponding to region C, an opening 1408 may be formed to penetrate the third substrate 1410, and the second input / output contact plug 1403 may be directly connected to the second input / output pad 1405 through the opening 1408 formed in the third substrate 1410. In this case, as shown in region C1, the diameter of the second input / output contact plug 1403 may gradually increase toward the second input / output pad 1405. However, embodiments of the present invention are not limited thereto, and in some embodiments, the diameter of the second input / output contact plug 1403 may gradually decrease toward the second input / output pad 1405.

[0246] In some embodiments, as shown in region C2 corresponding to region C, an opening 1408 may be formed through the third substrate 1410, and a contact portion 1407 may be formed in the opening 1408. One end of the contact portion 1407 may be connected to the second input / output pad 1405, and the other end of the contact portion 1407 may be connected to the second input / output contact plug 1403. Therefore, the second input / output contact plug 1403 may be electrically connected to the second input / output pad 1405 through the contact portion 1407 in the opening 1408. In this case, as shown in region "C2", the diameter of the contact portion 1407 may gradually increase toward the second input / output pad 1405, and the diameter of the second input / output contact plug 1403 may gradually decrease toward the second input / output pad 1405. For example, the second input / output contact plug 1403 may be formed together with the cell contact plug 1440 before the second cell region CELL2 and the first cell region CELL1 are bonded to each other, and the contact portion 1407 may be formed after the second cell region CELL2 and the first cell region CELL1 are bonded to each other.

[0247] In certain embodiments shown in region C3 corresponding to region C, compared to the embodiment of region C2, a barrier portion 1409 may also be formed on the bottom end of the opening 1408 of the third substrate 1410. The barrier portion 1409 may be a metal line formed in the same layer as the common source line 1420. Alternatively, the barrier portion 1409 may be a metal line formed in the same layer as the at least one word line 1430. The second input / output contact plug 1403 may be electrically connected to the second input / output pad 1405 via the contact portion 1407 and the barrier portion 1409.

[0248] Similar to the second input / output contact plug 1403 and the third input / output contact plug 1404 of the second cell area CELL2, the diameters of the second input / output contact plug 1303 and the third input / output contact plug 1304 of the first cell area CELL1 can gradually decrease toward the lower metal pattern 1371e, or can gradually increase toward the lower metal pattern 1371e.

[0249] Meanwhile, in some embodiments, a slit 1411 may be formed in the third substrate 1410. For example, the slit 1411 may be formed at a specific location in the external pad landing area PA. For example, as shown in area D, when viewed in a plan view, the slit 1411 may be located between the second input / output pad 1405 and the cell contact plug 1440. Alternatively, when viewed in a plan view, the second input / output pad 1405 may be located between the slit 1411 and the cell contact plug 1440.

[0250] In some embodiments, as shown in region D1 corresponding to region D, slits 1411 may be formed to penetrate the third substrate 1410. For example, the slits 1411 may be used to prevent microcracks from occurring in the third substrate 1410 when forming the opening 1408. However, the embodiments of the present disclosure are not limited thereto, and in some embodiments, the slits 1411 may be formed to have a depth of about 60% to about 70% of the thickness of the third substrate 1410.

[0251] In some embodiments, as shown in region D2 corresponding to region D, a conductive material 1412 may be formed in the slit 1411. For example, the conductive material 1412 may be used to discharge leakage current generated when the circuit elements in the external pad bonding region PA are driven to the outside. In this case, the conductive material 1412 may be connected to an external ground line.

[0252] In some embodiments, as shown in region D3 corresponding to region D, an insulating material 1413 may be formed in the slit 1411. For example, the insulating material 1413 may be used to electrically isolate the second input / output pad 1405 and the second input / output contact plug 1403 disposed in the external pad bonding area PA from the word line bonding area WLBA. Since the insulating material 1413 is formed in the slit 1411, a voltage supplied through the second input / output pad 1405 may be prevented from affecting a metal layer on the third substrate 1410 disposed in the word line bonding area WLBA.

[0253] Meanwhile, in some embodiments, the first input / output pad 1205, the second input / output pad 1405, and the third input / output pad 1406 may be selectively formed. For example, the memory device 1500 may be implemented to include only the first input / output pad 1205 disposed on the first substrate 1210, only the second input / output pad 1405 disposed on the third substrate 1410, or only the third input / output pad 1406 disposed on the first insulating layer 1401.

[0254] In some embodiments, at least one of the second substrate 1310 of the first cell region CELL1 and the third substrate 1410 of the second cell region CELL2 can serve as a sacrificial substrate and can be completely or partially removed before or after the bonding process. Additional layers can be stacked after the substrate removal. For example, the second substrate 1310 of the first cell region CELL1 can be removed before or after the bonding process between the peripheral circuit region PER1 and the first cell region CELL1, and then an insulating layer covering the top surface of the common source line 1320 or a conductive layer for connection can be formed. Similarly, the third substrate 1410 of the second cell region CELL2 can be removed before or after the bonding process between the first cell region CELL1 and the second cell region CELL2, and then an upper insulating layer 1401 covering the top surface of the common source line 1420 or a conductive layer for connection can be formed.

[0255] Figure 26 is a block diagram of an example in which a memory device according to an embodiment is applied to an SSD system 2000 .

[0256] Reference Figure 26 , the SSD system 2000 may include a host 2100 and an SSD 2200. The SSD 2200 may send and receive signals to and from the host 2100 through a signal connector, and receive power through a power connector. The SSD 2200 may include an SSD controller 2210, an auxiliary power supply 2220, a first storage device 2230, a second storage device 2240, and a third storage device 2250. Although Figure 26FIG. 2 shows that the SSD 2200 includes three storage devices as an example, but the SSD 2200 may include more than Figure 26 Fewer or more memory devices in the system.

[0257] Each of the first storage device 2230, the second storage device 2240, and the third storage device 2250 may be a vertically stacked NAND flash memory device. Each of the first storage device 2230, the second storage device 2240, and the third storage device 2250 may transmit and receive signals to and from the SSD controller 2210 through the first channel Ch1, the second channel Ch2, and the third channel Ch3. The first storage device 2230, the second storage device 2240, and the third storage device 2250 may be based on the above reference Figures 1 to 25 The described embodiments are implemented.

[0258] While non-limiting example embodiments of the present disclosure have been particularly shown and described with reference to the accompanying drawings, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A storage device comprising: A first cell array chip, comprising a first memory cell array; A first peripheral circuit chip includes a first page buffer circuit electrically connected to the first memory cell array; An input / output chip comprising a first pad circuit, a second pad circuit, a first input / output circuit electrically connected to the first pad circuit, and a second input / output circuit electrically connected to the second pad circuit; A second cell array chip, comprising a second memory cell array; as well as The second peripheral circuit chip includes a second page buffer circuit electrically connected to the second memory cell array.

2. The memory device according to claim 1, further comprising: a first bonding pad configured to electrically connect an external device to the memory device; as well as a second bonding pad configured to electrically connect the external device to the memory device, Wherein, the first peripheral circuit chip is located below the first unit array chip, Wherein, the input / output chip is located below the first peripheral circuit chip, Wherein, the second peripheral circuit chip is located below the input / output chip, Wherein, the second unit array chip is located below the second peripheral circuit chip, and The first bonding pad and the second bonding pad are on the first unit array chip.

3. The memory device according to claim 2, wherein: The storage device further includes: a first contact plug passing through the first peripheral circuit chip and the first cell array chip, the first contact plug being configured to electrically connect the first pad circuit to the first bonding pad; and A second contact plug passes through the first peripheral circuit chip and the first cell array chip, the second contact plug being configured to electrically connect the second pad circuit to the second bonding pad.

4. The memory device according to claim 1 , further comprising: a first edge pad configured to electrically connect an external device to the memory device; as well as a second edge pad configured to electrically connect the external device to the memory device, Wherein, the first peripheral circuit chip is located below the first unit array chip, Wherein, the input / output chip is located below the first peripheral circuit chip, Wherein, the second peripheral circuit chip is located below the input / output chip, Wherein, the second unit array chip is located below the second peripheral circuit chip, and The first edge pad and the second edge pad are between the first peripheral circuit chip and the second peripheral circuit chip.

5. The memory device according to claim 2, wherein The memory device is configured to transmit and receive first data to and from the external device through the first bonding pad and the second bonding pad in response to a first command received from the external device. The memory device according to claim 2 , wherein: The memory device is configured to: in response to a first command received from the external device, send first data to the external device and receive the first data from the external device through the first bonding pad, and in response to a second command received from the external device, send second data to the external device and receive the second data from the external device through the second bonding pad.

7. The memory device according to claim 1, wherein The first memory cell array includes a first storage area and a second storage area, Wherein, the second storage cell array includes a third storage area and a fourth storage area, The first page buffer circuit includes a first page buffer that overlaps with the first storage area in a vertical direction and a second page buffer that overlaps with the second storage area in the vertical direction, and The second page buffer circuit includes a third page buffer overlapping with the third storage area in the vertical direction and a fourth page buffer overlapping with the fourth storage area in the vertical direction.

8. The memory device according to claim 7, wherein: The memory device is configured as follows: providing the data stored in the first storage area to an external device through the first page buffer and the first input / output circuit; providing the data stored in the second storage area to the external device through the second page buffer and the first input / output circuit; providing the data stored in the third storage area to the external device through the third page buffer and the second input / output circuit; as well as The data stored in the fourth storage area is provided to the external device through the fourth page buffer and the second input / output circuit.

9. The memory device according to claim 7, wherein: The memory device is configured as follows: providing the data stored in the first storage area to an external device through the first page buffer and the first input / output circuit; providing the data stored in the third storage area to the external device through the third page buffer and the first input / output circuit; providing the data stored in the second storage area to the external device through the second page buffer and the second input / output circuit; as well as The data stored in the fourth storage area is provided to the external device through the fourth page buffer and the second input / output circuit.

10. The memory device according to claim 9, wherein The distance between the first storage area and the first input / output circuit is smaller than the distance between the second storage area and the first input / output circuit, and The distance between the third storage area and the first input / output circuit is smaller than the distance between the fourth storage area and the first input / output circuit.

11. A storage device comprising: A first cell array chip, comprising a first memory cell array; A first peripheral circuit chip includes a first page buffer circuit electrically connected to the first memory cell array; A second cell array chip, comprising a second memory cell array; as well as The second peripheral circuit chip includes a second page buffer circuit, a first pad circuit, a second pad circuit, a first input / output circuit electrically connected to the first pad circuit, and a second input / output circuit electrically connected to the second pad circuit. wherein the second page buffer circuit is electrically connected to the second memory cell array and is formed on one surface of the second peripheral circuit chip, and The first pad circuit, the second pad circuit, the first input / output circuit, and the second input / output circuit are formed on the other surface of the second peripheral circuit chip.

12. The memory device according to claim 11, further comprising: a first bonding pad configured to electrically connect an external device to the memory device; as well as a second bonding pad configured to electrically connect the external device to the memory device, Wherein, the first peripheral circuit chip is located below the first unit array chip, Wherein, the second peripheral circuit chip is located below the first peripheral circuit chip, Wherein, the second unit array chip is located below the second peripheral circuit chip, and The first bonding pad and the second bonding pad are on the first unit array chip.

13. The memory device according to claim 12, wherein: The storage device further includes: a first contact portion passing through the first peripheral circuit chip and the first cell array chip, the first contact portion being configured to electrically connect the first pad circuit to the first bonding pad; and A second contact portion passes through the first peripheral circuit chip and the first unit array chip, and is configured to electrically connect the second pad circuit to the second bonding pad.

14. The memory device according to claim 11, further comprising: a first edge pad configured to electrically connect an external device to the memory device; as well as a second edge pad configured to electrically connect the external device to the memory device, Wherein, the first peripheral circuit chip is located below the first unit array chip, Wherein, the second peripheral circuit chip is located below the first peripheral circuit chip, Wherein, the second unit array chip is located below the second peripheral circuit chip, and The first edge pad and the second edge pad are between the first peripheral circuit chip and the second peripheral circuit chip.

15. The memory device according to claim 11, wherein The first memory cell array includes a first storage area and a second storage area, Wherein, the second storage cell array includes a third storage area and a fourth storage area, The first page buffer circuit includes a first page buffer that overlaps with the first storage area in a vertical direction and a second page buffer that overlaps with the second storage area in the vertical direction, and The second page buffer circuit includes a third page buffer overlapping with the third storage area in the vertical direction and a fourth page buffer overlapping with the fourth storage area in the vertical direction.

16. The memory device according to claim 15, wherein The memory device is configured as follows: providing the data stored in the first storage area to an external device through the first page buffer and the first input / output circuit; providing the data stored in the third storage area to the external device through the third page buffer and the first input / output circuit; providing the data stored in the second storage area to the external device through the second page buffer and the second input / output circuit; as well as The data stored in the fourth storage area is provided to the external device through the fourth page buffer and the second input / output circuit.

17. The memory device according to claim 16, wherein: The distance between the first storage area and the first input / output circuit is smaller than the distance between the second storage area and the first input / output circuit, and The distance between the third storage area and the first input / output circuit is smaller than the distance between the fourth storage area and the first input / output circuit.

18. A memory device comprising: A first cell array chip, comprising a first memory cell array; A first peripheral circuit chip includes a first page buffer circuit electrically connected to the first memory cell array; An input / output chip comprising a first pad circuit, a second pad circuit, a first input / output circuit electrically connected to the first pad circuit, and a second input / output circuit electrically connected to the second pad circuit; A second cell array chip, comprising a second memory cell array; a second peripheral circuit chip comprising a second page buffer circuit electrically connected to the second memory cell array; A third cell array chip, comprising a third memory cell array; as well as The third peripheral circuit chip includes a third page buffer circuit electrically connected to the third memory cell array.

19. The memory device according to claim 18, further comprising: a first bonding pad configured to electrically connect an external device to the memory device; as well as a second bonding pad configured to electrically connect the external device to the memory device, Wherein, the first peripheral circuit chip is located below the first unit array chip, Wherein, the input / output chip is located below the first peripheral circuit chip, Wherein, the second peripheral circuit chip is located below the input / output chip, Wherein, the second unit array chip is located below the second peripheral circuit chip, Wherein, the third peripheral circuit chip is located below the second unit array chip, Wherein, the third unit array chip is located below the third peripheral circuit chip, Wherein, the first bonding pad and the second bonding pad are on the first unit array chip, and The third peripheral circuit chip is electrically connected to the input / output chip through at least one through silicon via (TSV).

20. The memory device according to claim 19, further comprising: a first contact portion passing through the first peripheral circuit chip and the first unit array chip, the first contact portion being configured to electrically connect the first pad circuit to the first bonding pad; as well as A second contact portion passes through the first peripheral circuit chip and the first unit array chip, and is configured to electrically connect the second pad circuit to the second bonding pad.

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