Decoding architecture for memory tile blocks

Abstract

The invention relates to a decoding architecture for a memory tile block. Word line patches of a memory array may each include a plurality of word line plates, which may each include a sheet of conductive material including a first portion extending in a first direction in a plane and a plurality of fingers extending in a second direction in the plane. A strut patch may include one or more struts extending vertically between the word line plate fingers. The memory cells may each be coupled with a respective word line plate finger and a respective strut. Word line decoding circuitry, pillar decoding circuitry, or both may be positioned underneath the memory array and in some cases may be shared between adjacent pillar tiles.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application. The parent application is an invention patent application filed on April 8, 2022, with application number 202280036942.8 and title “Decoding Architecture for Memory Slices.”

[0003] Cross Reference

[0004] This patent application is a national phase application of International Patent Application No. PCT / US2022 / 071623, filed by FANTINI et al. on April 8, 2022, entitled “DECODING ARCHITECTURE FOR MEMORY TILES,” which claims priority to U.S. Patent Application No. 17 / 231,668, filed by FANTINI et al. on April 15, 2021, entitled “DECODING ARCHITECTURE FOR MEMORYTILES,” each of which is assigned to its assignee and the entire text of each of which is expressly incorporated herein by reference. Technical Field

[0005] The technical field relates to decoding architectures for memory slices. Background Art

[0006] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states and store any of these states. To access stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write or program a state into the memory device.

[0007] There are various types of memory devices and memory cells, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Summary of the Invention

[0008] A device is described. The device may include: a first wordline slice block including a first wordline plate including a plurality of first wordlines, each of the plurality of first wordlines being coupled to one or more corresponding memory cells in a plurality of first memory cells; a first pillar slice block including a plurality of first pillars associated with the first wordline slice block, each first pillar being coupled to one or more corresponding first memory cells in the plurality of first memory cells; a second wordline slice block including a second wordline plate including a plurality of second wordlines, each of the plurality of second wordlines being coupled to one or more corresponding memory cells in a plurality of second memory cells; a second pillar slice, which is different from the first pillar slice, the second pillar slice including a plurality of second pillars each associated with the second word line slice and each coupled to one or more corresponding second memory cells of the plurality of second memory cells; and a first decoding circuit system associated with the first pillar slice and the second pillar slice, the first decoding circuit system being operable to activate the plurality of first word lines included in the first word line plate associated with the first pillar slice and the plurality of second word lines included in the second word line plate associated with the second pillar slice.

[0009] A device is described. The device may include: a first wordline slice including a first wordline plate including a plurality of first wordlines, each of the plurality of first wordlines being coupled to one or more corresponding memory cells in a plurality of first memory cells; a first pillar slice including a plurality of first pillars associated with the first wordline slice and each coupled to one or more corresponding first memory cells in the plurality of first memory cells; a second wordline slice including a second wordline plate including a plurality of second wordlines, each of the plurality of second wordlines being coupled to one or more corresponding memory cells in a plurality of second memory cells; a second pillar slice including a plurality of second pillars associated with the second wordline slice and each coupled to one or more corresponding second memory cells in the plurality of second memory cells; a first decoding circuit system associated with the first wordline slice and the second wordline slice; a second decoding circuit system associated with the first pillar slice; a third decoding circuit system associated with the second pillar slice; and a controller. , which is operable to cause the device to: use the first decoding circuit system to apply a first voltage to the first word line plate; use the first decoding circuit system to apply a second voltage to the second word line plate; use the second decoding circuit system to apply a third voltage to a first pillar of the plurality of first pillars included in the first pillar block, the first pillar being coupled to a first memory cell of the plurality of first memory cells, wherein the first memory cell is operable to be accessed at least in part based on applying the first voltage to the first word line plate and applying the third voltage to the first pillar; and use the third decoding circuit system to apply a fourth voltage to a second pillar of the plurality of second pillars included in the second pillar block, the second pillar being coupled to a second memory cell of the plurality of second memory cells, wherein the second memory cell is operable to be accessed at least in part based on applying the second voltage to the second word line plate and applying the fourth voltage to the second pillar.

[0010] A device is described. The device may include: a first word line slice block comprising a plurality of first word line plates stacked in a vertical direction, each of the plurality of first word line plates comprising a corresponding plurality of first word lines coupled to one or more corresponding memory cells in a plurality of first memory cells; a second word line slice block comprising a plurality of second word line plates stacked in the vertical direction, each of the plurality of second word line plates comprising a corresponding plurality of second word lines coupled to one or more corresponding memory cells in a plurality of second memory cells, wherein each second word line plate is positioned in the same plane as the corresponding first word line plate; a first pillar slice block comprising a plurality of first pillars associated with the first word line slice block and the second word line slice block, each first pillar coupled to a corresponding subset of first memory cells in the plurality of first memory cells or a corresponding subset of second memory cells in the plurality of second memory cells; and a third word line slice block comprising a plurality of third word line plates stacked in the vertical direction, the plurality of third word line plates Each third word line plate of the three word line plates includes a respective plurality of third word lines, each coupled to one or more respective memory cells in a plurality of third memory cells, wherein each third word line plate is positioned in the same plane as the corresponding first word line plate; a second pillar block comprising a plurality of second pillars associated with the third word line block, each second pillar coupled to a respective subset of third memory cells of the plurality of third memory cells; and a first decoding circuit system associated with the first pillar block and the second pillar block, the first decoding circuit system being positioned below the plurality of first memory cells, the plurality of second memory cells, and the plurality of third memory cells, wherein the first decoding circuit system is operable to activate a first word line plate of the plurality of first word line plates, a second word line plate of the plurality of second word line plates, and a third word line plate of the plurality of third word line plates, and wherein the first decoding circuit system is aligned with respective edges of the first pillar block and respective edges of the second pillar block. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 An example of a system supporting a decode architecture for memory slices according to examples as disclosed herein is described.

[0012] Figure 2 An example of a memory die supporting a decode architecture for memory slices according to examples as disclosed herein is illustrated.

[0013] Figure 3 Aspects of examples of a memory array supporting a decode architecture for memory slices according to examples as disclosed herein are described.

[0014] Figure 4A and 4BAspects of examples of a memory array supporting a decode architecture for memory slices according to examples as disclosed herein are described.

[0015] Figure 5A 、 5B 5C illustrate aspects of an example of a memory array supporting a decode architecture for memory slices according to examples as disclosed herein.

[0016] Figure 6 An example of an array architecture supporting a decode architecture for memory slices according to examples as disclosed herein is described.

[0017] Figure 7A An example of a memory cell architecture supporting a decode architecture for memory slices according to examples as disclosed herein is described.

[0018] Figure 7B An example of a pillar selector supporting a decode architecture for memory slices according to examples as disclosed herein is illustrated.

[0019] Figure 7C An example of a pillar tile supporting a decode architecture for a memory tile according to examples as disclosed herein is illustrated.

[0020] Figure 8A and 8B An example of a pillar tile architecture supporting a decode architecture for memory tiles according to examples as disclosed herein is illustrated.

[0021] Figure 9A and 9B Examples of word line drivers supporting a decoding architecture for memory tiles according to examples as disclosed herein are described.

[0022] Figure 10 A block diagram is shown of a memory device supporting a decoding architecture for memory slices according to examples as disclosed herein.

[0023] Figure 11 Flowcharts are shown illustrating one or several methods of supporting a decode architecture for memory slices according to examples as disclosed herein. DETAILED DESCRIPTION

[0024] The wordline plates of a memory array can each include a plurality of wordlines in a "comb-like" structure (e.g., a structure that can be viewed as having a ridge, fingers extending from the ridge, and spaces between each pair of adjacent fingers). The wordline plate can, for example, include a thin sheet of conductive material including a first portion extending in a plane along a first direction and a plurality of fingers extending in the plane along a second direction. Each finger of the wordline plate can represent a wordline as described herein, although wordlines (e.g., fingers) of the same wordline plate can be electrically coupled to each other via the ridges of the comb and can therefore be activated or deactivated together. A wordline plate can be activated to access corresponding memory cells of the memory array (e.g., memory cells coupled to the fingers of the wordline plate).

[0025] Wordline plates and corresponding memory cells can be stacked vertically above or below one or more other wordline plates and corresponding memory cells to form a level of a memory array. The wordline plate stack can be coupled with an electrode structure (e.g., a staircase as described elsewhere herein), and a wordline decoder can be operated to apply a voltage to any selected wordline plate of the wordline plate stack via the electrode structure to enable access to one or more memory cells coupled to the selected wordline plate. A wordline decoder for a wordline plate stack can include one or more wordline drivers, each configured to selectively activate or deactivate a corresponding wordline plate in the stack (e.g., a wordline plate coupled to the wordline driver). Wordline decoding circuitry can be positioned below the memory cells and wordline plates of the memory array. As used herein, a first set of one or more components being described as "under a second set of one or more components" (or alternatively, "under the second set of one or more components") may mean that the first set of one or more components are positioned between the second set of one or more components and a substrate (e.g., the first set of one or more components and the second set of one or more components are formed on the substrate) and are positioned within the footprint of the second set of one or more components. The circuitry below the memory array may be referred to as circuitry under the array (CuA) or alternatively, within the CuA region.

[0026] In some cases, two or more wordline plates in the same plane (e.g., wordline plates within different vertical stacks of wordline plates but at the same level or tier) can share electrodes and corresponding drivers for activating the wordline plates. For example, such sharing can advantageously reduce the footprint of support circuitry for operating the memory array (e.g., the area of ​​decoders and drivers within the CuA can be reduced), among other possible benefits. Memory cells coupled to the wordline plates that share the electrodes and drivers can be (or alternatively comprise) a page for accessing memory cells (e.g., a logical page for accessing memory cells of a memory array). In some cases, groups of electrodes coupled to different wordline plates at different tiers or planes of the stack can be referred to as stairs. A wordline decoder can be operable to activate any electrode of the electrode group to concurrently activate two or more corresponding wordline plates in the same plane but in different vertical stacks.

[0027] The memory cells can be accessed via a first voltage applied to a wordline plate coupled to the memory cells and a second voltage applied to pillars (e.g., electrodes extending vertically between wordline plate fingers) also coupled to the memory cells. A pillar tile can represent a portion of pillars within a memory array that can be accessed using the same set of complementary pillar decoders, such as one X-direction pillar decoder for decoding pillar access lines extending in the Y direction and one Y-direction pillar decoder for decoding pillar access lines extending in the X direction. The pillar access lines extending in the X and Y directions can be referred to as pillar row lines and pillar column lines, respectively, and pillar selectors at the intersection of pillar row lines and pillar column lines (e.g., for activating pillars of the tile) can be operated to activate based on activating the pillar row and pillar column lines.

[0028] In some cases, a pillar slice can be associated with multiple word line slices (e.g., each word line slice can include a certain number of word line plates, such as one or two word line plates). Associating a pillar slice with multiple word line slices (e.g., such that the pillar slice is larger than the word line slice and includes memory cells within multiple word line slices) can reduce the footprint of decoding circuitry for a memory array, such as by resulting in one set of complementary pillar decoders for all pillars of the pillar slice (e.g., as opposed to one set of complementary pillar decoders for each word line slice), one set of word line decoders for all word line plates of the pillar slice (e.g., a hierarchy of word line plates), or both.

[0029] As described herein, pillar decoding circuitry and word line decoding circuitry for a memory array can be positioned beneath the memory array (e.g., in a CuA), with at least a portion of the pillar decoding circuitry, word line decoding circuitry, or both for a pillar tile positioned beneath the pillar tile. In some cases, the pillar decoding circuitry, word line decoding circuitry, or both can be shared by multiple pillar tiles (e.g., a word line decoder can be coupled to a word line plate within two adjacent pillar tiles, or a pillar decoder can be coupled to a pillar access line included in two adjacent pillar tiles, or both), with the shared circuitry positioned beneath the pillar tiles with which it is shared. Sharing word line decoding circuitry across pillar tiles can also reduce the footprint of the decoding circuitry for the memory array because the number of word line decoders per pillar tile can be reduced (e.g., halved).

[0030] For these and other reasons, the decoding structures and configurations described herein can support a reduced area or footprint occupied by the decoding circuitry used to access memory cells (e.g., compared to some other memory array structures). The reduction in area occupied by the decoding circuitry can, for example, reduce the overall device footprint (e.g., by allowing all decoding circuitry for a memory array to be located below the memory array, rather than at least partially occupying some peripheral area), thereby allowing more memory cells to be included in a device with a given footprint, or both. Furthermore, the memory arrays described herein can support parallel or concurrent (e.g., at least partially simultaneous) access operations to two or more memory cells within the same page of memory cells. For example, memory cells coupled to different word lines and associated with a left-facing word line plate (e.g., having fingers extending to the left), a right-hand word line plate (e.g., having fingers extending to the right), or both can be accessed in parallel, which can increase access operation speed, data throughput, or both. These and other benefits described herein are merely exemplary, and additional benefits will be apparent to those of ordinary skill in the art.

[0031] First, in the reference Figures 1 to 3 Features of the present disclosure are described in the context of the memory systems, dies, and arrays described herein. Features of the present disclosure are further described in the context of the memory arrays and array architectures, along with various components thereof or associated therewith, as described with reference to Figures 4 through 9. These and other features of the present disclosure are further illustrated and described with reference to device diagrams and flow charts associated with a decode architecture for memory slices, as described with reference to Figures 4 through 9. Figures 10 to 11 describe.

[0032] Figure 1An example of a system 100 that supports a decode architecture for memory slices according to examples as disclosed herein is described. The system 100 may include a host device 105, a memory device 110, and a plurality of channels 115 coupling the host device 105 with the memory device 110. The system 100 may include one or more memory devices, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0033] System 100 may comprise a portion of an electronic device, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a vehicle, or other system. For example, system 100 may illustrate aspects of a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, or the like. Memory device 110 is a component of the system that is operable to store data for one or more other components of system 100.

[0034] At least a portion of system 100 may be an example of a host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to perform processes, such as a computing device, a mobile computing device, a wireless device, a graphics processing device, a computer, a laptop computer, a tablet computer, a smartphone, a cellular phone, a wearable device, an Internet-connected device, a vehicle controller, a system-on-a-chip (SoC), or some other fixed or portable electronic device, among other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functionality of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0035] Memory device 110 is operable to provide an independent device or component that provides a physical memory address / space that can be used or referenced by system 100. In some examples, memory device 110 can be configured to work with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 can be operable to support one or more of the following: a modulation scheme used to modulate signals; various pin configurations for communicating signals; various form factors for physical packaging of host device 105 and memory device 110; clock signaling and synchronization between host device 105 and memory device 110; timing conventions; or other factors.

[0036] Memory device 110 is operable to store data for components of host device 105. In some examples, memory device 110 can act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 through external memory controller 120). Such commands may include one or more of a write command for a write operation, a read command for a read operation, a refresh command for a refresh operation, or other commands.

[0037] Host device 105 may include one or more of an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or other components (e.g., one or more peripheral components or one or more input / output controllers). The components of host device 105 may be coupled to each other using a bus 135.

[0038] The processor 125 is operable to provide control or other functionality for at least a portion of the system 100 or at least a portion of the host device 105. The processor 125 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or a combination of these components. In such examples, the processor 125 can be an example of a central processing unit (CPU), a graphics processing unit (GPU), a general-purpose GPU (GPGPU), or a SoC, among other examples. In some examples, the external memory controller 120 can be implemented by or be part of the processor 125.

[0039] BIOS component 130 may be a software component including a BIOS operating as firmware that may initialize and run the various hardware components of system 100 or host device 105. BIOS component 130 may also manage the flow of data between processor 125 and the various components of system 100 or host device 105. BIOS component 130 may include a program or software stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0040] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more sectors), each memory cell operable to store at least one bit of data. A memory device 110 that includes two or more memory dies may be referred to as a multi-die memory or a multi-die package or a multi-chip memory or a multi-chip package.

[0041] Memory die 160 may be an example of a two-dimensional (2D) array of memory cells or an example of a three-dimensional (3D) array of memory cells. A 2D memory die 160 may include a single memory array 170. A 3D memory die 160 may include two or more memory arrays 170 that may be stacked on top of each other or positioned adjacent to each other (e.g., relative to a substrate). In some examples, the memory arrays 170 in a 3D memory die 160 may be referred to as a level, tier, layer, or die. A 3D memory die 160 may include any number of stacked memory arrays 170 (e.g., two high, three high, four high, five high, six high, seven high, eight high). In some examples, multiple levels, tiers, or layers of memory cells (e.g., stacked vertically) may be considered a single 3D memory array 170 (e.g., as opposed to a stack of multiple memory arrays 170).

[0042] The device memory controller 155 may include circuitry, logic, or components operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and may be operable to receive, transmit, or execute commands, data, or control information related to the components of the memory device 110. The device memory controller 155 may be operable to communicate with one or more of the external memory controller 120, one or more memory dies 160, or the processor 125. In some examples, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160.

[0043] The local memory controller 165 (e.g., local to the memory die 160) may include circuitry, logic, or components operable to control the operation of the memory die 160. In some examples, the local memory controller 165 may be operable to communicate with the device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some examples, the memory device 110 may not include a device memory controller 155 and a local memory controller 165, or an external memory controller 120 may perform the various functions described herein. Thus, the local memory controller 165 may be operable to communicate with the device memory controller 155, with other local memory controllers 165, or directly with the external memory controller 120 or the processor 125, or a combination thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165, or both, may include a receiver for receiving signals (e.g., from the external memory controller 120), a transmitter for transmitting signals (e.g., to the external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuits or controllers operable to support the described operations of the device memory controller 155 or the local memory controller 165, or both.

[0044] The external memory controller 120 is operable to facilitate communication of one or more of information, data, or commands between a component of the system 100 or host device 105 (e.g., the processor 125) and the memory device 110. The external memory controller 120 may convert or translate communications exchanged between the components of the host device 105 and the memory device 110. In some examples, the external memory controller 120 or other components of the system 100 or host device 105, or their functionality, described herein, may be implemented by the processor 125. For example, the external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by the processor 125 or other components of the system 100 or host device 105. Although the external memory controller 120 is depicted as being external to the memory device 110, in some examples, the external memory controller 120 or its functionality described herein may be implemented by one or more components of the memory device 110 (e.g., the device memory controller 155, the local memory controller 165), or vice versa.

[0045] Components of host device 105 can exchange information with memory device 110 using one or more channels 115. Channels 115 can operate to support communication between external memory controller 120 and memory device 110. Each channel 115 can be an example of a transmission medium that carries information between host device 105 and the memory device. Each channel 115 can include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. A signal path can be an example of a conductive path that is operable to carry a signal. For example, a channel 115 can include a first terminal that includes one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. A pin can be an example of a conductive input or output point of a device of system 100, and a pin can be operable to serve as part of a channel.

[0046] Lanes 115 (and associated signal paths and terminals) can be dedicated to conveying one or more types of information. For example, lanes 115 may include one or more command and address (CA) lanes 186, one or more clock signal (CK) lanes 188, one or more data (DQ) lanes 190, one or more other lanes 192, or a combination thereof. In some examples, signaling can be conveyed via lanes 115 using single data rate (SDR) signaling or double data rate (DDR) signaling. In SDR signaling, one modulation symbol (e.g., signal level) of a signal can be registered for each clock cycle (e.g., on either the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of a signal can be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0047] A memory array as described herein may include any number of word line slice blocks, wherein each word line slice block includes a vertical stack of one or more word line plates (e.g., a vertical stack of one or more combs). The word line plates within the vertical stack can be independently activated or deactivated by associated word line decoding circuitry. Pillars can extend vertically between fingers of a word line plate (which can extend horizontally), and each memory cell of the memory array can be coupled to a corresponding word line (e.g., a corresponding finger of a corresponding word line plate) and a corresponding pillar. Each pillar can be independently activated or deactivated using one or more pillar access lines (e.g., based on one or more pillar access lines for a pillar being coupled to a corresponding pillar selector for that pillar). A pillar tile may include a set of pillars that can be decoded (e.g., independently activated or deactivated) using the same set of pillar decoding circuitry, which may be or include a pair of complementary pillar decoders for the pillar tile (e.g., an X-direction pillar decoder for the pillar tile and a Y-direction pillar decoder for the pillar tile, wherein each pillar is activated or deactivated via a corresponding Y-direction pillar access line and a corresponding X-direction pillar access line). In some cases, a pillar tile may include multiple word line tiles (e.g., for pillars within a pillar tile, memory cells coupled to the pillars may in turn be coupled to word lines included in multiple word line tiles).

[0048] Word line and pillar decoding circuitry for word line slices and pillar slices within a memory array may be positioned below the memory array (e.g., within the footprint of the memory array, above a substrate on which the memory array is formed, or both). For example, pillar decoding circuitry for a pillar slice may be positioned below the pillar slice (e.g., within the footprint of the pillar slice). Additionally or alternatively, pillar decoding circuitry, word line decoding circuitry, or both may be shared across pillar slices and positioned below those pillar slices. In some cases, additional circuitry may also be positioned below the pillar slices as described herein, such as, for example, sense amplifiers. The decoding structures and configurations as described herein may beneficially support a reduced area occupied by decoding circuitry or other circuitry associated with operating the memory cells of a memory array (e.g., compared to other memory array configurations), and in some cases may allow all support circuitry for a memory array to be positioned below the memory array (e.g., as a CuA).

[0049] Figure 2 An example of a memory die 200 supporting a decode architecture for a memory slice block according to examples as disclosed herein is illustrated. The memory die 200 may be a memory die 200 as described in reference to Figure 1An example of a memory die 160 is described. In some examples, the memory die 200 may be referred to as a memory chip, a memory device, or an electronic memory device. The memory die 200 may include one or more memory cells 205, which may each be programmed to store a different logical state (e.g., a programming state of a set of two or more possible states). For example, the memory cell 205 may be operable to store one bit of information at a time (e.g., a logical 0 or a logical 1). In some examples, the memory cell 205 (e.g., a multi-level memory cell 205) may be operable to store more than one bit of information at a time (e.g., a logical 00, a logical 01, a logical 10, a logical 11). In some examples, the memory cells 205 may be arranged in an array, such as with reference to FIG. Figure 1 Memory array 170 is described.

[0050] Figure 2 Various features related to the electrical operation of the memory array may be described, but the physical location and configuration of components may vary. Figure 2 For example, Figure 2 The illustrated features may represent the positioning of memory cells 205 at the intersection of respective access lines (e.g., row lines 210 and column lines 215), may represent the electrical functionality of memory cells and other array components, or both, although memory arrays may in some cases have relative access lines formed by Figure 2 The physical architecture or structure described herein is different from the physical architecture or structure (for example, as described below with reference to Figure 3 to 9 description).

[0051] In some cases, the memory cell 205 may use a configurable material (which may be referred to as a memory element, a memory storage element, a material element, a material storage element, a material portion, or a polarity write material portion, etc.) to store a logic state. The configurable material of the memory cell 205 may refer to a chalcogenide-based storage component, such as that described in reference to FIG. Figure 3 For example, chalcogenide memory elements can be used in phase change memory (PCM) cells, fixed-limit memory cells, or self-select memory cells.

[0052] Memory die 200 may include access lines (e.g., row lines 210 and column lines 215). Access lines may be formed from one or more conductive materials. In some examples, row lines 210 may be referred to as word lines. In some examples, column lines 215 may be referred to as digit lines or bit lines. In some cases, additional types of access lines may exist, as described elsewhere herein. References to access lines, row lines, column lines, word lines, digit lines, or bit lines, or the like, may be interchangeable without loss of understanding or operation. Memory cells 205 may be positioned, for example, at the intersection of row lines 210 (e.g., fingers of a word line plate) and column lines 215 (e.g., pillars or other vertical electrode structures).

[0053] In some cases, one or more column lines 215 (e.g., column line CL_j) may run perpendicular to the substrate and one or more row lines 210 (e.g., row line RL_i) may be on a different level than illustrated (e.g., each row line 210 may be a word line finger of a vertically stacked word line plate). In such cases, a memory cell 205 may be formed at the intersection of the column line CL_j and the row line RL_i (e.g., between a pillar and a word line finger of the stacked word line plate). One or more other memory cells 205 may be coupled to one or more other stacked word line plates ( Figure 2 One or more other row lines 210 (not shown) Figure 2 ) and the column line CL_j and one or more other row lines 210 ( Figure 2 ) and one or more other column lines 215 (eg, pillars, not depicted).

[0054] Operations such as reading and writing can be performed on memory cells 205 by activating or selecting access lines, such as one or more of row lines 210 or column lines 215. By biasing row lines 210 and column lines 215 (e.g., applying a voltage to row lines 210 or column lines 215), individual memory cells 205 can be accessed at their intersections. The intersection of row lines 210 and column lines 215 in a two-dimensional or three-dimensional configuration can be referred to as the address of the memory cell 205. An access line can be a conductive line coupled to a memory cell 205 and can be used to perform access operations on the memory cell 205.

[0055] Access to the memory cells 205 may be controlled by a row decoder 220 or a column decoder 225. For example, the row decoder 220 may receive a row address from the local memory controller 245 and activate the row lines 210 based on the received row address. The column decoder 225 may receive a column address from the local memory controller 245 and activate the column lines 215 based on the received column address. In some cases, the functions attributed herein to the column decoder 225 may be performed by one or more pillar decoders (e.g., complementary X-direction and Y-direction pillar decoders) configured to decode among the pillars of a pillar tile.

[0056] The sensing component 230 is operable to detect the state of the memory cell 205 (e.g., material state, resistance, threshold state) and determine the logic state of the memory cell 205 based on the stored state. The sensing component 230 may include one or more sense amplifiers used to amplify or otherwise convert the signal resulting from accessing the memory cell 205. The sensing component 230 may compare the signal detected from the memory cell 205 with a reference 235 (e.g., a reference voltage). The detected logic state of the memory cell 205 may be provided as an output of the sensing component 230 (e.g., to the input / output 240) and may indicate the detected logic state to another component of the memory device including the memory die 200.

[0057] The local memory controller 245 can control access to the memory cell 205 through various components (eg, row decoder 220, column decoder 225, sensing component 230). The local memory controller 245 can be as shown in FIG. Figure 1 1. An example of a local memory controller 165 is described. In some examples, one or more of the row decoder 220, column decoder 225, and sense component 230 can be co-located with a local memory controller 245. The local memory controller 245 can be operable to receive one or more of commands or data from one or more different memory controllers (e.g., an external memory controller 120 associated with the host device 105, another controller associated with the memory die 200), translate the commands or data (or both) into information that can be used by the memory die 200, perform one or more operations on the memory die 200, and communicate data from the memory die 200 to the host device 105 based on performing the one or more operations. The local memory controller 245 can generate row signals and column address (e.g., pillar address) signals to activate the target row lines 210 and the target column lines 215. The local memory controller 245 can also generate and control various voltages or currents used during operation of the memory die 200. In general, the amplitude, shape, or duration of the applied voltages or currents discussed herein may vary and may be different for the various operations discussed in operating memory die 200 .

[0058] The local memory controller 245 is operable to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include a write operation, a read operation, a refresh operation, a precharge operation, or an activate operation, among others. In some examples, the access operations may be performed or otherwise coordinated by the local memory controller 245 in response to various access commands (e.g., from the host device 105). The local memory controller 245 is operable to perform other access operations not listed here or other operations related to the operation of the memory die 200 but not directly related to accessing the memory cells 205.

[0059] The local memory controller 245 is operable to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logic state. The local memory controller 245 can identify the target memory cell 205 on which the write operation is to be performed. The local memory controller 245 can identify the target row line 210 and the target column line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 245 can activate the target row line 210 and the target column line 215 (e.g., apply a voltage to the row line 210 or the column line 215) to access the target memory cell 205. The local memory controller 245 can apply a specific signal (e.g., a write pulse) to the column line 215 during the write operation to store a specific state in the storage element of the memory cell 205. The pulse used as part of the write operation can include one or more voltage levels for a duration.

[0060] The local memory controller 245 is operable to perform a read operation (e.g., a sense operation) on one or more memory cells 205 of the memory die 200. During a read operation, the logic state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 245 can identify the target memory cell 205 on which the read operation is to be performed. The local memory controller 245 can identify the target row line 210 and the target column line 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 245 can activate the target row line 210 and the target column line 215 (e.g., apply a voltage to the row line 210 or the column line 215) to access the target memory cell 205. The sensing component 230 can detect a signal received from the memory cell 205 based on the pulse applied to the row line 210, the pulse applied to the column line, and / or the resistance or threshold characteristics of the memory cell 205. The sensing component 230 can amplify the signal. The local memory controller 245 can activate the sensing component 230 (e.g., latch the sensing component) and thereby compare the signal received from the memory cell 205 with the reference signal 235. Based on the comparison, the sensing component 230 can determine the logic state stored on the memory cell 205. The pulse used as part of the read operation can include one or more voltage levels for a duration.

[0061] As described herein, word line plates or their fingers may electrically correspond to row lines 210 or column lines 215, but the word line plates may be configured as a "comb-like" structure (e.g., a structure that may appear to have multiple fingers extending from a common ridge and spaces between each pair of adjacent fingers). The word line plates may be coupled to a word line decoder (e.g., row decoder 220) via electrodes that are operable to apply voltages to the word line plates for accessing associated memory cells. The word line decoders are operable to independently activate or deactivate individual word line plates within a vertical stack of word line plates. To reduce the footprint of support circuitry (e.g., word line decoding circuitry) for a memory device, two word line plates in the same plane (e.g., in different vertical stacks but at the same level within the stack) may share an electrode for activating the word line plates. The two word line plates sharing the electrode may be (or alternatively include) a page for accessing memory cells 205 (e.g., a logical page for accessing memory cells).

[0062] The memory cell 205 can be accessed via a first voltage applied to a word line plate coupled to the memory cell 205 and a second voltage applied to a pillar (e.g., a vertical electrode structure electrically isolated from the word line plate) coupled to the memory cell 205. In some cases, as shown in FIG. Figure 2 The column lines 215 or row lines 210 described may correspond to pillars as described herein. A pillar slice may be associated with a plurality of word line slices (e.g., each word line slice representing one or two word line plates or one or two vertical stacks thereof), wherein a pillar slice may represent a portion of a pillar within a memory array that may be accessed using a set of complementary decoders, such as a set of one X-direction pillar decoder and one Y-direction pillar decoder, wherein the X and Y directions may correspond to access lines coupled to a pillar selector, respectively, and which may be described in more detail elsewhere herein. In some instances, decoding circuitry including pillar decoders, word line decoders, or both may be positioned beneath the memory array as a CuA, possibly along with other support circuitry for operating the memory array (e.g., sensing component 230 or at least a sense amplifier thereof). Additionally or alternatively, word line decoders, pillar decoders, or both may in some cases be shared across adjacent pillar slices, which may reduce the footprint of support circuitry (e.g., decoding circuitry) for the memory device.

[0063] Figure 3 An example portion of a memory array 300 supporting a decoding architecture for memory slices according to examples as disclosed herein is illustrated. The memory array 300 may be a reference Figure 1 and 2Memory array 300 may include multiple levels of memory cells 310 stacked in a vertical direction relative to substrate 340 to create a memory cell stack 335, which may be as described in reference Figure 1 and 2 Thus, in some examples, the memory array 300 may be referred to as a 3D memory array. The memory array 300 may include word line plates 315 and pillars 325, which may be electrically used as reference Figure 2 Examples of word lines and bit lines (eg, row lines 210 and column lines 215) are described.

[0064] The wordline plate 315 may include a plurality of wordlines in a "comb-like" structure (e.g., a structure that may be viewed as a tool having a plurality of fingers extending from a common ridge and a space between each pair of adjacent fingers). The wordline plate 315 may, for example, include a thin sheet of conductive material including a first portion (e.g., a ridge) extending in a first direction within a plane and a plurality of fingers extending in a second direction within the plane. Each wordline plate 315 or its fingers may represent a wordline as described herein. The number of fingers (e.g., wordlines) and the length of the fingers may define the size of the wordline plate 315, where the size of the wordline plate may be based on the capacitance of the wordline plate 315 relative to one or more storage class memory (SCM) specifications. Various exemplary details of the comb-like structure, fingers, and other aspects of the wordline plate 315 may be further illustrated or described elsewhere herein.

[0065] Each pillar 325 can be selectively coupled to a corresponding pillar row line 320 via a pillar selector 345 (e.g., a transistor or a switching element). For example, a pillar column line 350 for a pillar 325 can be coupled to the pillar selector 345 for the pillar 325, and the pillar selector 345 can be selectively activated or deactivated based on the voltage of the pillar column line 350 (e.g., the voltage difference between the voltage of the pillar column line 350 and the voltage of the pillar row line 320). When activated (e.g., turned on, closed, conducting), the pillar selector 345 for the pillar 325 can couple the pillar 325 to the pillar row line 320 for the pillar 325, and thus the voltage of the pillar 325 can become equal to or approximately equal to the voltage of the pillar row line 320. In some cases, pillar selector 345 may be a transistor (e.g., a thin film transistor (TFT) or other type of transistor), and the gate of the transistor may be coupled to pillar column line 350, the source of the transistor may be coupled to pillar row line 320, and the drain of the transistor may be coupled to pillar 325. Thus, in some cases, pillar column line 350 may alternatively be referred to as a pillar gate line, and pillar row line 320 may alternatively be referred to as a pillar source line.

[0066] A pillar decoder as described herein is operable to selectively activate (e.g., apply a select voltage to) or deactivate (e.g., apply a deselect voltage to) a pillar column line 350 in a set of pillar column lines 350 associated with the pillar decoder, or selectively activate (e.g., apply a select voltage to) or deactivate (e.g., apply a deselect voltage to) a pillar row line 320 in a set of pillar row lines 320 associated with the pillar decoder. Figure 3 An example is described in which the pillar selectors 345, pillar row lines 320, and pillar column lines 350 are above the pillars 325, but it should be understood that the pillar selectors 345, pillar row lines 320, and pillar column lines 350 may alternatively be positioned below the pillars 325 (e.g., with a respective pillar selector 345 coupled to the bottom of each pillar 325).

[0067] Pillar column lines 350 and pillar row lines 320 may span and thus couple to pillar selectors 345 corresponding to rows or columns of pillars 325 coupled to memory cells, which in turn are coupled to a single word line plate, word line plates within a single word line slice block, or word line plates within multiple word line slice blocks, as described herein. One of ordinary skill in the art will appreciate that what direction (e.g., X or Y direction) is considered to be rows and columns may be arbitrary. In some cases, pillars 325 may correspond (e.g., in terms of one or more functionalities) to pillars 325 as described in reference to FIG. Figure 2 Similarly, the pillar decoders, pillar column lines 350, pillar row lines 320, and pillar selectors 345 may correspond (eg, in terms of one or more functionalities) to those described with reference to FIG. Figure 2 Column decoder 225 is described.

[0068] In some cases, pillars 325 coupled to the same pillar column line 350 can be viewed as a comb structure having vertical comb fingers (e.g., pillars 325) that can be selected via corresponding pillar row lines 320 (e.g., individually relative to other pillars 325 coupled to the same pillar column line 350), and each memory cell 310 can be positioned at the intersection of horizontal fingers of a word line plate 315 (e.g., a word line) and vertical fingers (e.g., pillars 325, which can be viewed as digit lines or portions of digit lines), but the teachings herein are not limited to such conceptualizations.

[0069] The memory array 300 may also include an insulating layer 305, a trench insulating layer 306, a via 330, and a substrate 340. Figure 3 The examples illustrate pillar row lines 320 and pillar column lines 350 as being above pillars 325, but in some implementations, pillar row lines 320 and pillar column lines 350 may alternatively be below pillars 325 (e.g., between pillars 325 and substrate 340).

[0070] The insulating layer 305 can be electrically insulating and can provide insulation between the alternating word line plates 315. As described herein, various logic states can be stored by programming the resistance of the memory cells 310. In some cases, programming the resistance includes passing a current through the memory cells 310, heating the memory cells 310, melting the material of the memory cells 310 (e.g., all or part), applying a voltage of a particular polarity to the memory cells, or any combination thereof. The insulating layer 305 can be composed of multiple sublayers, thereby creating one or more interfaces between the memory cells 310.

[0071] Memory array 300 may include an array of memory cell stacks 335, and each memory cell stack 335 may include a plurality of memory cells 310. Memory array 300 may be fabricated by forming a stack of conductive layers (e.g., wordline plates 315), each of which may be separated from adjacent conductive layers by one or more electrically insulating layers 305. The electrically insulating layers may include oxide or nitride materials, such as silicon oxide, silicon nitride, or other electrically insulating materials. In some cases, electrically insulating layer 305 may include one or more sublayers. The layers of memory array 300 may be formed on (e.g., over) a substrate 340, such as a silicon wafer, or any other semiconductor or oxide substrate. Vias 330 (e.g., openings) may be formed by removing material from the layer stack by etching, mechanical techniques, or both. In some cases, the CuA, as described herein, may refer to circuitry formed between the substrate 340 and the memory array (e.g., within the footprint of the memory array (which may correspond to or include the footprint of the memory cells 310, wordline plates 315, pillars 325, possibly along with associated interconnect structures), as opposed to peripheral circuitry that may be formed beside or otherwise outside the footprint of the memory array). For example, the CuA may be formed over the substrate 340, and then the memory array may be formed over the CuA.

[0072] In some cases, the memory cells 310 (e.g., memory elements) can be formed by removing material from the conductive layer to create recesses adjacent to the vias 330 and forming a variable resistance material in the recesses. For example, material can be removed from the conductive layer by etching, and the variable resistance material can be deposited in the resulting recesses to form the memory cells 310 (e.g., memory elements, which can be storage elements). Each via 330 can be filled with an electrically conductive material and a dielectric material to create a pillar 325, which can be coupled (e.g., selectively, such as using a pillar selector 345) to a pillar row line 320. In other words, the memory cells 310 in the memory cell stack 335 can share a common electrode (e.g., pillar 325). Thus, each memory cell 310 can be coupled to both the word line plate 315 and the pillar 325. In some cases, each pillar 325 (e.g., within each via 330) can be coupled to a first word line finger via a corresponding first memory cell and to a second word line finger via a corresponding second memory cell, as described in further detail with reference to FIG 4. The trench insulating layer 306 can be electrically insulating and can provide insulation between alternating (e.g., interdigitated) word line fingers of each word line plate 315 (e.g., word line fingers on each side of the via 330 in the direction of the pillar column line 350, where the word line fingers on opposite sides of the trench insulating layer 306 can extend away from the spine of their respective word line plates in parallel but opposite directions, e.g., where a first word line finger immediately adjacent to a side of the trench insulating layer 306 extends to the right and a second word line finger immediately adjacent to the opposite side of the trench insulating layer 306 extends to the left).

[0073] In some examples, the material of memory cell 310 (e.g., a memory element) may include a chalcogenide material or other alloy including selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some examples, a chalcogenide material primarily composed of selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some examples, a SAG alloy may also include silicon (Si), and such a chalcogenide material may be referred to as a SiSAG alloy. In some examples, a SAG alloy may include silicon (Si) or indium (In), or a combination thereof, and such a chalcogenide material may be referred to as a SiSAG alloy or an InSAG alloy, respectively, or a combination thereof. In some examples, the chalcogenide glass may include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form. Other chalcogenide alloys not specifically listed here may also be employed.

[0074] In some examples, such as for a delimited memory cell or a self-selected memory cell 310, some or all of the set of logic states supported by the memory cell 310 may be associated with the same state, such as an amorphous state of the chalcogenide material as opposed to a crystalline state of the chalcogenide material (e.g., the material is operable to store different or multiple logic states while remaining in the amorphous state). In some such examples, the memory cell 310 may be an example of a self-selected memory cell 310. In such examples, the material used in the memory cell 310 may be based on an alloy (e.g., the alloys listed above) and may be operable to undergo a state change during normal operation of the memory cell (e.g., due to ion migration or separation within the memory cell 310). For example, the self-selected memory cell 310 may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logic state (e.g., a reset state) and the low threshold voltage state may correspond to a second logic state (e.g., a set state). In some examples, memory cell 310 may alternately switch between amorphous and crystalline states during operation, where the amorphous and crystalline states correspond to different resistances or threshold voltages and thus different logic states, and in some cases this operation may be referred to as a phase change operation.

[0075] In some cases, during a programming (writing) operation of a self-selected memory cell 310, the polarity of one or more pulses used for the writing operation can affect (determine, set, program) a particular behavior or characteristic of the material of the memory cell 310, such as the threshold voltage of the material. The difference in the threshold voltage of the material of the memory cell 310 depending on the logical state stored by the material of the memory cell 310 (e.g., the difference between the threshold voltage when the material stores a logic state of '0' and the threshold voltage when the material stores a logic state of '1') can correspond to a read window of the memory cell 310.

[0076] Various techniques may be used to form materials or components on substrate 340. These may include, for example, chemical vapor deposition (CVD), metal organic vapor deposition (MOCVD), physical vapor deposition (PVD), sputter deposition, atomic layer deposition (ALD), or molecular beam epitaxy (MBE), among other thin film growth techniques. Materials may be removed using various techniques, which may include, for example, chemical etching (also known as "wet etching"), plasma etching (also known as "dry etching"), or chemical mechanical planarization.

[0077] As described herein, the regions separating the memory cells 310, such as the insulating layer 305, the trench insulating layer 306, or both, can include one or more interfaces. In some examples, the interfaces of the insulating layer 305 separate the stacked memory cells 310 in a vertical direction. In other words, the memory cells 310 can be stacked on top of each other and separated from each other by the interfaces. In some examples, the interfaces of the trench insulating layer 306 separate the word line fingers from each other in a horizontal direction.

[0078] The memory cells 310 described herein may include, but are not limited to, phase change materials. Other types of memory cells 310 may include, for example, resistive memory or resistive RAM. In some cases, resistive RAM may use metal oxide materials, and the resistance of the metal oxide material may be changed by controlling the ionic state of atoms in the material or by controlling the number or position of atomic vacancies (e.g., missing atoms) in the material.

[0079] Figure 4A and 4B Examples of memory arrays 400-a and 400-b supporting a decoding architecture for memory slices according to examples as disclosed herein are illustrated. For example, Figure 4A and 4B Various views (e.g., top views) of cross-sections of example 3D memory arrays 400-a and 400-b are illustrated, which may be examples of 3D memory arrays according to examples as disclosed herein. A plurality of openings 460 may be formed through alternating planes of conductive material 445 (e.g., wordline planes or wordline plates), dielectric material 418, and, for example, a second dielectric material in trench 450. As shown, the diameters of the plurality of openings 460 may be substantially the same width as the trench 450. In some examples, the diameters of the plurality of openings 460 may be greater than the width of the trench 450.

[0080] Each of the plurality of openings 460 may be substantially concentric with a different corresponding conductive contact. Figure 4A and 4B , pillars 480 (e.g., circular pillars 480) can be formed in a geometric pattern in each corresponding opening 460, for example, formed above and coupled with a corresponding conductive contact (e.g., which can be a pillar selector 345 or coupled with the pillar selector). In some examples, the openings 460 (e.g., and corresponding pillars 480) can be square or another shape. In some cases, multiple openings 460 can have a staggered (e.g., hexagonal) arrangement of conductive contacts associated with the pillars 480. For example, a corresponding conductive contact can be surrounded by six other conductive contacts.

[0081] A staggered pattern may refer to any pattern in which the positions of objects (e.g., contacts, openings 460, or pillars 480) in a first row are offset in a given direction from the positions of objects (e.g., contacts, openings 460, or pillars 480) in a second row adjacent to the first row. For example, a staggered pattern may have objects (e.g., contacts, openings 460, or pillars 480) that are adjacent to each other in the x-direction (e.g., rows or horizontal direction) but not in the y-direction (e.g., columns or vertical direction). For example, Figure 4A and 4B As illustrated in , the conductive contacts may be adjacent to each other and in line with each other in the x-direction. However, the conductive contacts may not be adjacent to each other in the y-direction and may, for example, alternate (e.g., skip) rows in the y-direction. Although Figure 4A and 4B The spacing between the conductive contacts is shown to be substantially the same throughout the substrate, but examples according to the present disclosure are not limited thereto. For example, the spacing between the conductive contacts can vary throughout the substrate.

[0082] Figure 4B The 3D memory array is shown to include a variety of storage element materials 465, each including a chalcogenide material or other storage element positioned between at least one word line plate, at least one pillar 480, and at least one dielectric material 418. In some examples (e.g., depending on decoding optimizations), each pillar 480 can be coupled with a respective pillar selector (e.g., a switching element, such as a transistor) positioned at the top, bottom, or both the top and bottom of the 3D memory array 400 (e.g., below or above a set of word line plates).

[0083] Figure 5A 、 5B 5C illustrate examples of memory arrays 500-a, 500-b, and 500-c supporting a decode architecture for memory slices according to examples as disclosed herein. For example, Figure 5A 、 5B 5C may illustrate various views of cross-sections of example 3D memory arrays 500-a, 500-b, and 500-c, which may be examples of 3D memory arrays according to examples as disclosed herein, wherein Figure 5A and 5B is a top view and Figure 5C Memory arrays 500-a, 500-b, and 500-c may include similar Figure 4A and 4BFeatures of the memory array 400 are described. A specific separation trench 450', which may be filled with an insulating material or a dielectric material, may be formed between two sub-arrays (e.g., a first sub-array 500-a1 and a second sub-array 500-a2), so that the first sub-array 500-a1 and the second sub-array 500-a2 can be electrically isolated from each other. In some examples, the memory array 500-a may include a set of vertically stacked word line plates separated from each other by respective dielectric layers (see FIG. Figure 5C ).

[0084] The word line plates can be formed from the conductive material 445 of the memory arrays 500-a, 500-b and 500-c. In the first sub-array 500-a1, the first word line plate (e.g., of the first word line plate stack) can be isolated from the second word line plate (e.g., of the second word line plate stack) in the same plane using a dielectric material extending in a serpentine shape (e.g., the shape of the trench 450). In the second sub-array 500-a2, the third word line plate (e.g., of the third word line plate stack) can similarly be isolated from the fourth word line plate (e.g., of the fourth word line plate stack) in the same plane using a dielectric material extending in a serpentine shape (e.g., the shape of the trench 450). The first word line plate and the second word line plate can be isolated from the third word line plate and the fourth word line plate by the separation trench 450'. In Figures 5A to 5C The number of separation trenches 450' and sub-arrays 500-a1 and 500-a2 may not be limited to Figures 5A to 5C For example, multiple separation trenches 450' can be formed in the 3D memory array as needed (eg, to isolate various sub-arrays of the 3D memory array).

[0085] Utilizing separation trenches 450′ filled with an insulating or dielectric material (which may also be referred to as separation layers) can reduce power consumption of a 3D memory array while complying with SCM specifications. For example, compared to a 3D memory array in which multiple sub-arrays are coupled to each other, a 3D memory array interposed with several separation layers can experience a corresponding decrease in capacitance of the memory array (e.g., of the individual sub-arrays) and can further reduce power consumption without increasing decoding burden.

[0086] like Figure 5AAs shown in FIG, in some examples, after forming trenches 450 in a serpentine shape in a 3D memory array 500-a, portions of the trenches 450 can be selected as separation trenches 450', which can be used to divide the 3D memory array 500-a into a first sub-array 500-a1 and a second sub-array 500-a2. For example, the separation trenches 450' can be subjected to another etching operation so that the two sub-arrays on either side of a particular separation trench 450' can be separated, which can sever one or more word line plate structures to create separate word line plates or a set (e.g., a stack) of word line plates on either side of the separation trench 450'. In some examples, during subsequent processing steps, the separation trenches 450' can be filled with an insulating material or a dielectric material, for example, without any other material (e.g., a storage element material or a conductive material) formed therein. In some examples, portions from the serpentine trench 450 can be used as separation trenches 450 ′ between different groups of word line plate fingers (eg, every X fingers, where X is some number).

[0087] In another example, a group of sub-arrays may be formed on the same substrate, and a separation layer 450' may be deposited on one or both sides of each sub-array along the horizontal direction of the serpentine trench 450, so that the group of sub-arrays can be electrically isolated from each other. In another example, after forming a 3D memory array and based on one or more dimensions of the 3D memory array, a certain number of separation trenches 450' may be formed to divide the 3D memory array into a group of sub-arrays, wherein an etching operation may be performed on the memory array to form the separation trenches 450'.

[0088] The position where the separation trench 450' (or separation layer 450') is formed can be adjusted according to the size of the 3D memory array to achieve the desired size of the sub-array or both, as determined by Figure 5B and 5C For example, relative to Figure 5B The first sub-array 500-b1 and the second sub-array 500-b2 illustrated in FIG. 4 adjust the positions of the separation trenches 450'. In some examples, a 3D memory array can be formed based on an example pitch of adjacent pillars.

[0089] In some examples, the insertion of separation layer 450' can help the corresponding capacitance value be low enough so that the word line can be biased by a driver that consumes a desired low amount of energy (for example, in some cases, the energy used to drive the word line can be calculated as (1 / 2CV 2 )). In addition, using pillars to partition a 3D memory array can support decode CuA optimizations, such as minimizing the number of pillar decoders, sense amplifiers, or the like, while complying with SCM specifications based on higher-level memory array segmentation (e.g., due to wordline cutting with the insertion of separation layer 450').

[0090] In some examples, each pillar 480 can be coupled to a corresponding pillar selector (e.g., a switching element or transistor) positioned at the top, bottom, or both the top and bottom of the 3D memory array (e.g., below or above the set of word line plates), depending on the decoding implementation. Spatially relative terms, including but not limited to, "top," "bottom," "lower," "upper," "below," "under," "above," and the like, if used herein, are used to describe the spatial relationship of one element(s) to another element(s) for ease of description. Such spatially relative terms encompass different orientations of the device other than the specific orientation depicted in the figures and described herein. For example, if the structure depicted in the figures were inverted or flipped, portions previously described as below or below other elements would now be above or above those other elements.

[0091] Figure 6 An example of an array architecture 600 supporting a decode architecture for memory tiles according to examples as disclosed herein is illustrated. The array architecture 600 may represent an array including a plurality of pillars 630, which may represent, for example, reference Figure 3 Examples of pillars described elsewhere herein are provided. For example, each pillar 630 may extend through a material stack comprising alternating layers of dielectric or insulating material and a word line plate. Each pillar 630 may also be coupled to one or more memory cells (e.g., two memory cells) at each word line plate layer. Figure 6 The illustrated views may represent a top or bottom view of the array, such that the struts 630 may extend into and out of the page. The struts 630 may be arranged in rows and columns throughout the array architecture 600, for example, including columns for clarity of vision. Figure 6 Unillustrated positions (e.g., pillar columns and rows) may largely fill each word line slice 605. Although pillars 630 are shown arranged in a linear fashion, pillars 630 may additionally or alternatively be arranged in another geometric pattern (e.g., staggered), as described with reference to Figures 4 and 5.

[0092] The array architecture 600 can include a plurality of word line slice blocks 605, which can each represent a set of word line plates separated from the word lines of other word line slice blocks 605, for example, by steps 620 and 625 and by slots 655 (e.g., slots 655-a, 655-b, 655-c, and 655-d). Each word line slice block 605 can include one or more sets of two independently addressable word line plates, which can face each other (e.g., as an interlocking comb structure, which can alternatively be referred to as a comb with interdigitated fingers, but such details may be found in the accompanying drawings). Figure 6 Omitted and for clarity relative to Figure 6), and they may be separated by dielectric or insulating materials in serpentine or other shapes, as described with reference to Figures 4 and 5. Additionally or alternatively, word line slice block 605 may represent a vertical stack of word line plates (e.g., memory cells coupled thereto) that may be independently (e.g., individually) activated or deactivated using a word line decoder. The word line plates within word line slice block 605 may be positioned at alternating layers of the material stack, as described with reference to Figures 4 and 5. Figure 3 As described, a word line plate of the array architecture 600 can be positioned above or below one or more other word line plates of the same word line slice block 605 .

[0093] The size of word line slice block 605 (e.g., length and width, based on the number and length of fingers of the associated word line plates) can be based on the capacitance of word line slice block 605 or the word line plates therein relative to one or more SCM specifications (e.g., can be sized to meet SCM specifications).

[0094] Wordline decoding circuitry (e.g., one or more wordline decoders) can be used to access or activate different wordline plates (and therefore different wordlines) at different levels of the stack (e.g., tiers) and at different locations in the array architecture 600. For example, a wordline decoder can activate one or more selected wordline plates of a wordline plate stack (e.g., having multiple tiers) via a staircase 620 or 625 (e.g., electrodes or a series of electrodes having different heights) while deactivating or maintaining deactivation of one or more other wordline plates of the stack. Similarly, pillar decoding circuitry (e.g., pillar decoders) can be used to access or activate different pillars 630, which can activate or access a pillar row line (e.g., a pillar source line) or a pillar column line (e.g., a pillar gate line) associated with a selected pillar 630.

[0095] To reduce the footprint of decoding circuitry, sense amplifiers, or other support circuitry for operating a memory array having array architecture 600 (e.g., to support implementation of such circuitry as a CuA), two word line plates from different word line slices 605 can share a staircase 620 or 625. The two word line plates that share electrodes within staircase 620 or 625 can be (or alternatively include) pages 610 or 615 (e.g., logical pages for accessing memory cells) for accessing memory cells at the same level of array architecture 600. For example, a first page 610 (e.g., an even page) can include two first word line plates extending (e.g., to the left and right) away from a first staircase 620, and a second page 615 (e.g., an odd page) can include two second word line plates extending (e.g., to the left and right) away from a second staircase 625. Thus, for example, the word lines or fingers of the right-extending word line plate of the first page 610 may be interlocked with (but separated from by) the word lines or fingers of the left-extending word line plate of the second page 615 .

[0096] In some instances, reference Figure 6 , the word line decoding circuitry included in the CuA below the pillar slice block 635 can be operated to activate (e.g., individually) any word line plate in a set of vertically stacked word line plates (e.g., levels) in the word line slice block 605 included in the pillar slice block 635. The word line decoder of the decoding circuitry can include or be coupled with one or more word line drivers, and each word line driver can be associated with (e.g., coupled to) a word line plate or a pair of word line plates in the same respective level of the word line plate stack (e.g., word line plates associated with adjacent word line slice blocks 605 and coupled to a shared ladder 620 or 625) (e.g., the word line plates of the pair can be coplanar with each other). Thus, activating a word line driver can activate a selected word line plate of the word line plate stack (e.g., one or more word line plates coupled to the word line driver).

[0097] For example, a first word line driver of (e.g., included therein or coupled thereto) a first word line decoder may be operable to activate a first selected word line plate within a first word line slice block 605 to the left of a first staircase 620 and (e.g., concurrently) activate a second selected word line plate within a second word line slice block 605 to the right of the first staircase 620. The first selected word line plate within the first word line slice block 605 to the left of the first staircase 620 and the second selected word line plate within the second word line slice block 605 to the right of the first staircase 620 may both be coupled to the same electrode within the first staircase 620, and thus the first word line driver may concurrently activate two word line plates, and thus the corresponding pages 610, within two adjacent word line slice blocks by applying a select voltage to a shared electrode within the first staircase 620 for the two word line plates. The second word line driver of the first word line decoder can be similarly operable to activate a third selected word line plate within the first word line slice block 605 and a fifth selected word line plate within the second word line slice block 605, wherein the third selected word line and the fifth selected word line can be positioned above or below the first word line plate and the second word line plate, respectively, in the word line plate stack.

[0098] The second word line decoder can be similarly operable to activate a driver to activate or access a first selected word line plate within the first word line slice block 605 to the left of the second staircase 625 and (e.g., concurrently) activate a second selected word line plate within the second word line slice block 605 to the right of the second staircase 625, e.g., by applying a select voltage to electrodes within the second staircase 625 that are coupled to the two selected word line plates and thereby select a corresponding page 615 of the memory cell.

[0099] In some examples, for example, based on being able to concurrently access half of the memory cells associated with two different word line slices 605 or levels thereof (e.g., via the respective first or second word line plates of those two word line slices 605), a page 610 or 615 can include the same or substantially the same number of memory cells as included within a word line slice 605 or a level thereof (e.g., plane, level). For example, sharing the electrodes of a ladder 620 or 625 between two word line plates can reduce the total number of ladder electrodes and the total number of word line decoders associated with the array architecture 600 (e.g., can be halved) compared to an architecture in which word line plates within adjacent word line slices 605 do not share electrodes (e.g., in which the ladder is dedicated to a single word line slice 605 rather than a pair or other group of word line slices 605).

[0100] Each first word line plate can be selectively activated using a corresponding first word line driver of a first word line decoder (e.g., first decoding circuitry), and each second word line plate can be selectively activated using a corresponding second word line driver of a second word line decoder. In some examples, to activate a first word line plate (or a pair of first word line plates), the first word line decoder can activate or apply a voltage to a corresponding electrode within the first staircase 620 (e.g., using a corresponding word line driver of the word line decoder). Similarly, to activate a second word line plate (or a pair of second word line plates), the second word line decoder can selectively activate or apply a voltage to a corresponding electrode within the second staircase 625 (e.g., using a corresponding word line driver of the word line decoder).

[0101] Similarly, to reduce the footprint of the CuA and other peripheral or support circuitry for the array architecture, a pillar tile 635 can be associated with multiple wordline tiles 605 (e.g., any number of wordline tiles 605, such as 15 or 16 wordline tiles 605). In some cases, for example, based on one or more connectivity and spacing constraints (e.g., to reduce connectivity between the clustered array and the CuA), a pillar tile 635 can include or be associated with a non-integer number of wordline tiles 605 (e.g., based on independence between wordline tiles 605 and pillar tiles 635). A pillar tile 635 can represent a portion of the pillars 630 of the array architecture 600 that can be accessed using a set of complementary decoders, such as one X-direction pillar decoder for decoding pillar lines running in the Y direction (e.g., a first pillar decoder for decoding pillar column lines) and one Y-direction pillar decoder for decoding pillar lines running in the X direction (e.g., a second pillar decoder for decoding pillar row lines).

[0102] The pillar tile 635 can define (e.g., independently of the boundaries of the word line tile 605) the total area (e.g., maximum area) of the pillars 630 and associated memory cells that can be decoded using a first pillar decoder (e.g., in the X direction) and a corresponding second pillar decoder (e.g., in the Y direction). The size of the pillar tile 635 (e.g., length and width, based on the length of the pillar decoder and the associated number of pillars 630) can be based on the capacitance of the pillar tile 635 relative to one or more SCM specifications (e.g., can be sized to comply with the SCM specifications).

[0103] A first pillar decoder and a second pillar decoder (e.g., a pillar decoding circuit system) for the pillar tile 635 can be used to selectively access the pillars 630 within the pillar tile 635. For example, the first pillar decoder can be used to access or activate the pillar column line and the second pillar decoder can be used to selectively access or activate the pillar row line. The pillar column line can activate one or more switching components coupled to the pillar column line, and the one or more switching components can couple the pillar 630 to the activated pillar row line and thereby select or activate the pillar 630 associated with the activated pillar column line and the activated pillar row line (e.g., because the switching component, such as the pillar selector 345, can be activated based on the difference between the voltage of the corresponding pillar column line and the voltage of the corresponding pillar row line, where, for example, the switching component is or includes a transistor, the corresponding pillar row line can be coupled to the source or drain of the switching component). A voltage can be applied to the pillar 630 via the pillar row line (e.g., when the associated pillar selector is activated).

[0104] In some cases, for example, if a multi-TFT decoder is positioned below each pillar 630 (e.g., for coupling pillars 630 and pillar row lines to activate pillars 630, as pillar selectors 345), the first and second pillar decoders may represent areas for contacting other decoders that may operate at a more global level (e.g., device level). In the case where a single TFT is positioned below each pillar 630, the first and second pillar decoders may represent the decoding levels for the pillars of the pillar tile 635.

[0105] Associating a pillar slice 635 with multiple word line slices 605 (e.g., such that the pillar slice 635 is larger than the word line slice 605 and includes pillars 630 coupled to memory cells within multiple word line slices 605) can reduce the footprint of the pillar decoder, for example, by supporting one pillar decoder or a set of complementary pillar decoders for all pillars 630 of the pillar slice 635 (e.g., relative to supporting one pillar decoder or a set of complementary pillar decoders for each word line slice 605).

[0106] In some cases, word line decoding circuitry (e.g., word line decoders and word line drivers) operable to access word line plates in pillar slice 635 can be located below a memory array having array architecture 600 (e.g., can be included in a CuA of the memory array). For example, all or a portion of the word line decoding circuitry for a word line plate included in pillar slice 635 (and therefore word line slice 605) can be located below pillar slice 635 (e.g., between pillar slice 635 and the substrate, within the footprint of pillar slice 635). In some examples, at least a portion of the word line decoding circuitry for pillar slice 635 can be below the pillar slice and aligned with (e.g., adjacent to or positioned proximate to) an edge of pillar slice 635 (e.g., aligned with an edge of the footprint of pillar slice 635), and can be shared between one or more adjacent pillar slices 635 (e.g., also operable to access word line plates in one or more adjacent pillar slices 635).

[0107] Similarly, pillar decoding circuitry (e.g., a pillar decoder) operable to access pillars 630 in a pillar tile 635 may be positioned below a memory array having the array architecture 600 (e.g., may be included in a CuA of the memory array). For example, all or a portion of the pillar decoding circuitry for pillars 630 included in a pillar tile 635 may be positioned below the pillar tile 635 (e.g., between the pillar tile 635 and the substrate, within the footprint of the pillar tile 635). In some examples, at least a portion of the pillar decoding circuitry may be below the pillar tile 635 and aligned with (e.g., adjacent to or positioned proximate to) an edge of the pillar tile 635 (e.g., aligned with an edge of the footprint of the pillar tile 635) and may be shared between one or more adjacent pillar tiles 635 (e.g., also operable to access pillars 630 in one or more adjacent pillar tiles 635).

[0108] Memory cells can be accessed (e.g., for read or write operations) by activating corresponding pillars 630 and word line plates. For example, a first pillar decoder for pillar slice 635 can be used to apply a first voltage to a pillar column line and a second complementary pillar decoder for pillar slice 635 can be used to apply a second voltage to a pillar row line, which can activate or access a corresponding pillar 630 (e.g., at the intersection of the pillar column line and the pillar row line). Similarly, a third voltage can be applied to a word line plate (e.g., the word line plate can be activated) using word line decoding circuitry for pillar slice 635 to access a memory cell coupled to the activated pillar 630. For example, the memory cell can be coupled to the word line plate and pillar 630 and can be accessed based on the corresponding voltages applied to the word line plate and pillar 630.

[0109] In some cases, the array architecture 600 can support parallel or simultaneous access operations to two or more memory cells within the same page 610 or 615 (e.g., two or more memory cells coupled to pillars 630 in the same column of pillars 630), which can increase access operation speed and / or data throughput. In some cases, two or more memory cells associated with the same column of pillars 630 can be accessed concurrently as long as memory cells on opposite sides of the same word line finger are not accessed concurrently. For example, within a pillar tile 635, one pillar column line can be activated by a first pillar decoder, and every other pillar row line (or some other subset of pillar row lines in which no two pillar row lines are adjacent) can be concurrently activated by a second pillar decoder, thereby concurrently activating every other pillar 630 within a column of pillars 630 (or some other subset of pillars 630 in which no two activated pillars are adjacent within a column). In some such cases, one word line plate per word line slice block 605 can be activated at a time by a corresponding word line decoder (e.g., for a given activated pillar 630, one memory cell can be accessed based on concurrently activating the word line plate coupled to the one memory cell among a plurality of vertically stacked word line plates coupled to the memory cell coupled to the pillar 630). And in some cases, word line plates within any number of even pages 610 or odd pages 615 can be concurrently activated by a corresponding word line decoder, thus supporting concurrent access to two or more memory cells associated with the same column of pillars 630 across any number of word line slice blocks 605.

[0110] Additionally or alternatively, in some cases, the array architecture 600 may support partially parallel access operations of two or more memory cells within the same page 610 or 615 (e.g., two or more memory cells coupled to pillars 630 in the same row of pillars 630), which may increase access operation speed and / or data throughput. For example, within a pillar tile 635, a first pillar column line may be activated by a first pillar decoder, and every other pillar row line (or some other subset of pillar row lines in which no two pillar row lines are adjacent) may be concurrently activated by a second pillar decoder, thereby concurrently activating every other pillar 630 within a first column of pillars 630 (or some other subset of pillars 630 in which no two activated pillars are adjacent within the first column). One or more word line plates may also be concurrently activated by one or more corresponding word line decoders to access memory cells coupled to the activated pillars 630 within the first row. Subsequently, the first pillar column line may be deactivated by the first pillar decoder, and the second pillar column line may be activated by the first pillar decoder, possibly while one or more word line plates remain activated.

[0111] Thus, based on activating different pillar column lines in a sequential manner, different memory cells coupled to pillars 630 in different rows of pillars 630 can be accessed while one or more word line plates remain activated. In some cases, the same pillar row line(s) can also remain activated while one or more word line plates remain activated, such that different memory cells coupled to different pillars 630 in the same one or more rows of pillars 630 but in different columns of pillars 630 can be accessed in a partially parallel manner (e.g., while the same set of one or more word line plates remain activated, while the same set of one or more pillar row lines remain activated, or both). And in some cases, different pillar row lines can be activated when different pillar column lines are activated, such that different memory cells coupled to different pillars 630 in different rows of pillars 630 and different columns of pillars 630 can be accessed in a partially parallel manner. In some cases, this partially parallel access may occur for two or more memory cells distributed across the left-hand word line plate and the right-hand word line plate of page 610 or page 615.

[0112] Figure 7A An example of a memory cell architecture 705 supporting a decoding architecture for a memory tile according to an example as disclosed herein is illustrated. The memory cell architecture 705 may be used for a memory cell 750, which may be an example of a memory cell that may be included within a memory array described herein. The memory cell 750 may be accessed via a corresponding word line 720 (e.g., word line 720-a or word line 720-b) and a pillar 740 (e.g., a bit line or a selectable portion thereof). The pillar 740 may represent a reference Figures 3 to 6 Examples of pillars described herein, as well as other examples described herein. Word line 720-a can represent a first word line finger of a first word line plate, and word line 720-b can represent a second word line finger of a second word line plate, as described herein. For example, as described with reference to FIG. 4 (e.g., and other examples), the fingers of the first and second word line plates can extend in parallel but in opposite directions (e.g., one to the right and away from the spine of the first word line plate, the other to the left and away from the spine of the second word line plate) and can be interlocked with each other. Figure 7A The illustrated view may represent a top view of the memory cell architecture 705 such that the pillars 740 may extend out of the page.

[0113] The memory cell architecture 705 may include a first memory cell 750-a (e.g., which may be or include a first chalcogenide element) and a second memory cell 750-b (e.g., which may be or include a second chalcogenide element). As described herein, the chalcogenide element may be a storage element including one or more chalcogenide glasses for storing a logic state within the memory cell 750. The memory cells 750-a and 750-b may be coupled to the pillar 740 via first electrodes 730-a and 730-b, respectively. The memory cells 750-a and 750-b may be coupled to the corresponding word line 720 via second electrodes 725-a and 725-b, respectively. The first electrode 730 can provide a sufficient level of conductivity while preventing direct contact between the memory cell 750 and the pillar 740, and the second electrode 725 can similarly provide a sufficient level of conductivity while preventing direct contact between the memory cell 750 and the corresponding word line 720, for example to reduce contamination (e.g., chemical contamination between the chalcogenide glass and the material of the word line 720 or pillar 740). In some cases, the first electrode 730 and the second electrode 725 can represent carbon electrodes or carbon-based electrodes. The memory cell architecture 705 can further include one or more dielectric materials 745 (e.g., to provide electrical insulation between two or more components).

[0114] In some cases, the overall shape of the memory cell architecture 705 (e.g., of a pair of complementary memory cells 750 at the same level of the vertical stack of word line plates and on either side of the pillars 740) can be a rectangular shape. For example, the shape of the memory cell architecture 705 can include a first dimension in the y-direction (e.g., P Y ), the first dimension may be larger than the second dimension in the x direction (eg, P X ), or vice versa.

[0115] Figure 7B An example of a pillar selector 710 supporting a decoding architecture for a memory slice according to examples as disclosed herein is illustrated. The pillar selector 710 may represent a reference Figure 3 The examples of pillar selectors 345 described herein, as well as other examples described herein. Pillar selectors 710 may represent transistors (e.g., TFTs or other types of transistors) and may be positioned below the memory cell architecture 705. For example, the pillar selectors may be positioned below corresponding pillars 740 and may be coupled to the corresponding pillars. Figure 7B The illustrated view may represent a top view of the pillar selector 710 such that the pillars may be positioned on top (out of the page) of the pillar selector 710. The pillar selector 710 may be operable to select the pillar 740 during an access operation to the memory cell architecture 705 by coupling the pillar 740 with a pillar row line (e.g., a pillar source line), such as described in reference to FIG. Figure 3 described.

[0116] The pillar selector 710 (e.g., a TFT) may include a gate 755, a gate oxide material 765, and a channel material 760. The channel material 760 may be a semiconductor (e.g., a polysilicon material) or other material suitable for use as a transistor channel and may be coupled to the gate 755 via the gate oxide material 765. The gate 755 may be formed in a U-shape in the z-direction (where the two sides of the U extend upward out of the page and the bottom of the U is below the channel material and the gate oxide material 765, where the gate oxide material may also be formed in a similar (e.g., concentric) U-shape in some cases). Thus, for example, Figure 7B Both sides of the gate 755 described in the figure can be connected under the gate oxide material 765 to form one gate 755. This transistor gate structure can increase the driving capability of the pillar selector 710.

[0117] In some cases, the effective transistor width of the pillar selector 710 (and therefore the corresponding drive strength of the pillar selector 710, based on the transistor width) can be greater than (e.g., twice) the physical width of the pillar selector 710 in the x-direction based on both sides of the gate 755 (e.g., a U-shaped transistor architecture can have functional benefits similar to a dual-gate architecture). For example, this larger effective transistor width can increase the drive strength of the pillar selector 710 compared to other transistors with similar physical widths in the x-direction. Thus, for example, this U-shaped transistor gate architecture can allow for an increased effective width-to-length ratio of the pillar selector 710 while maintaining the elongated dimension of the gate 755 aligned with (e.g., parallel to) the elongated direction of the memory cell architecture 705 (e.g., both the gate 755 and the memory cell architecture 705 can be longer in the y-direction than in the x-direction).

[0118] This alignment can have space-saving benefits for a memory array as described herein. For example, in some cases, the dimension of the pillar selector 710 in the y-direction can be less than or equal to the dimension of the memory cell architecture 705 in the y-direction and / or the dimension of the pillar selector 710 in the x-direction can be less than or equal to the dimension of the memory cell 705 in the x-direction. Thus, the pillar selector 710 can be positioned (e.g., can be fitted) under the corresponding pillar 740 (e.g., and the corresponding memory cell architecture 705). The structure and alignment of the memory cell architecture 705 and the pillar selector 710 can therefore support increased drive capability of the pillar selector 710 (e.g., maximum drive capability of the pillar selector 710), overall space savings of the memory array, or both, as well as other possible benefits that will be apparent to one of ordinary skill in the art.

[0119] The gate 755 of the pillar selector 710 can be coupled to a pillar column line, and the source of the pillar selector 710 (e.g., the left or right side of the channel 760 in the x-direction) can be coupled to a pillar row line. Therefore, in some cases, the pillar column line can be referred to as a pillar gate line, and the pillar row line can be referred to as a pillar source line. The drain of the pillar selector 710 (e.g., the side of the channel 760 opposite the source in the x-direction) can be coupled to the pillar 740, so that, for example, when the corresponding pillar row line applies an activation voltage to the gate 755 of the pillar selector 710, the pillar selector 710 can couple the pillar 740 to the pillar row line.

[0120] Figure 7C An example of a pillar tile 715 that supports a decode architecture for memory tiles as described herein is illustrated. The pillar tile 715 may be a memory tile as described herein, for example with reference to Figure 6 4 and 5 .

[0121] The pillar tile 715 may include a plurality of pillar rows 775 and pillar columns 780 (e.g., rows and columns of pillars 740). Each pillar column 780 may be associated with a corresponding pillar column line (e.g., a pillar gate line) extending in the y-direction, and each pillar row 775 may be associated with a corresponding pillar row line (e.g., a pillar source line) extending in the x-direction. The pillar column lines may be associated with a first pillar decoder (e.g., a pillar gate line or a pillar column line decoder) for the pillar tile 715, and the pillar row lines may be associated with a second pillar decoder (e.g., a pillar source line or a pillar row line decoder) for the pillar tile 715.

[0122] The first pillar decoder can be operated to selectively activate (e.g., apply a select or activate voltage) or deactivate (e.g., apply a deselect or deactivate voltage to) the pillar column lines of the pillar tile 715 independently of each other (e.g., one at a time, or any subset or all of them concurrently). The second pillar decoder can be operated to selectively activate (e.g., apply a select or activate voltage) or deactivate (e.g., apply a deselect or deactivate voltage to) the pillar row lines of the pillar tile 715 (e.g., one at a time, or any subset or all of them concurrently). Thus, the pillar tile 715 can include the total area or number (e.g., maximum area) of pillars 740 and associated memory cells 750 that can be activated or selected using the first pillar decoder (e.g., in the X direction) and the second complementary pillar decoder (e.g., in the Y direction).

[0123] The pillars 740 of the pillar tiles 715 can be activated by applying a first voltage (e.g., a first select voltage) to the corresponding pillar column lines and applying a second voltage to the corresponding pillar row lines. Applying the first voltage can activate the pillar selectors 710 coupled to the pillar column lines. When activated, each pillar selector 710 can couple the corresponding pillar 740 on the pillar column line to the corresponding pillar row line. Applying a second voltage (e.g., a second select voltage) to the pillar row line can result in applying the second voltage (e.g., or a voltage close to the second voltage) to the pillar 740 positioned at the junction of the activated pillar column line and the pillar row line (e.g., based on the pillar 740 being coupled to the pillar row line via the corresponding, activated pillar selector 710). In such cases, the pillar 740 can be referred to as selected or activated.

[0124] Each pillar row 775 may include a first number of pillars 740 (eg, P X ), and each pillar row 780 may include a second number of pillars 740 distributed in the y direction (eg, P Y In some examples, there may be more pillars 740 included in pillar rows 775 than in pillar columns 780, or alternatively, there may be more pillars 740 included in pillar columns 780 than in pillar rows 775. Additionally or alternatively, based on the rectangular shape of an associated memory cell architecture (e.g., memory cell architecture 705), pillar tiles 715 may have different dimensions in the x-direction than in the y-direction (e.g., having a greater number of pillars 740 in the x-direction).

[0125] In some cases, the size of pillar tile 715 in the y-direction (e.g., the length of the pillar gate lines) can be based on the capacitance or other qualities of the pillar gate lines (e.g., pillar column lines) of pillar tile 715 so that the speed for activating the pillar gate lines can meet one or more thresholds (e.g., memory speed specifications). In some cases, the capacitance or other qualities of the pillar source lines can support the size of pillar tile 715 in the x-direction (e.g., the length of the pillar source lines) being greater than the size of pillar tile 715 in the y-direction, supporting pillar tile 715 including more pillars in the x-direction than in the y-direction, or both. However, it should be understood that pillar tile 715 can include any number of pillars 740 in any direction without departing from the teachings herein.

[0126] Pillar tile 715 may include multiple word line tiles as described elsewhere herein, and each of the multiple word line tiles may include one or more word line plates having a comb-like structure with interdigitated word line fingers. The word line plates within a word line tile may be stacked in the z-direction (outside the page). The fingers of each word line plate may extend horizontally in the x-direction across the respective word line tile.

[0127] The size of the word line drivers included in or coupled to the word line decoder can be determined based on the capacitance and desired actuation response time of the word line plates, and therefore the desired drive current capability. As the number of word line slices included in pillar slice block 715 increases, the number of word line plates in each vertical stack within the word line slice increases (e.g., the number of levels of the memory array in the z-direction), or both, the number of word line drivers used to drive (e.g., apply voltage to) the respective word line plates included in pillar slice block 715 can increase proportionally (e.g., the drive capability of the word line decoder can increase as the total capacity of the word line slice increases). In such cases, the area of ​​pillar slice block 715 occupied by such word line drivers (e.g., the area within the CuA) can therefore increase.

[0128] Figure 8A and 8B Respective examples of pillar tile architectures 800-a and 800-b supporting a decode architecture for memory tiles according to examples as disclosed herein are illustrated. Pillar tile architectures 800-a and 800-b may illustrate architectures in which decode circuitry and support circuitry for operating a memory array may be located beneath one or more pillar tiles 805 (e.g., may be implemented as a CuA for one or more pillar tiles 805). Pillar tile 805 may represent, for example, a memory array described herein with reference to a processor. Figure 67. The CuA for each pillar tile 805 may include word line decoding circuitry 810 (e.g., which may include a word line decoder), pillar decoding circuitry 815 (e.g., which may include a pillar decoder), and sense amplifiers 820 positioned below (e.g., within the footprint of) a corresponding set of memory cells and access lines included in the pillar tile 805, each of which may be examples of such components described elsewhere herein.

[0129] The word line decoding circuitry 810 may be shared across two or more adjacent pillar tiles 805. For example, the word line decoding circuitry 810 may be aligned with the edges of two or more pillar tiles 805 and may be shared across two or more pillar tiles 805. The word line decoding circuitry 810 may include a number of word line drivers, each of which is operable to drive a corresponding word line plate (or a set of corresponding word line plates, where multiple word line plates may be driven via a common electrode) to a desired voltage (e.g., a select voltage or a deselect voltage). In some cases, the word line decoding circuitry 810 may occupy a contiguous area underlying multiple pillar tiles 805 (e.g., across portions of their footprints) (e.g., a contiguous area underlying two or four pillar tiles 805, as shown in FIG8 ) and may include one or more word line decoders, each of which is operable to drive at least one word line plate within two or more of the overlying pillar tiles 805.

[0130] For example, a word line decoding circuitry 810 occupying a contiguous area underlying two or more pillar tiles 805 may be coupled to a first word line plate within a first pillar tile 805 of the two or more pillar tiles 805 and a second word line plate within a second pillar tile 805 of the two or more pillar tiles 805 (and possibly a third word line plate within a third pillar tile 805 of the two or more pillar tiles 805 and a fourth word line plate within a fourth pillar tile 805 of the two or more pillar tiles 805). The word line decoding circuitry 810 may thus be operable to activate (e.g., concurrently or non-concurrently) word line plates associated with two or more adjacent pillar tiles 805 (e.g., coupled to memory cells that are in turn coupled to pillars within the two or more adjacent pillar tiles 805). The word line decoding circuitry 810 may include one or more word line decoders, each of which may include multiple word line drivers. Each word line decoder may correspond to one or more word line slices and may be operable to activate or deactivate individual word line plates within the corresponding word line slice. For example, each word line decoder may include a set of word line drivers, where each word line driver is operable to activate one word line plate from a set (e.g., a stack) of word line plates within the corresponding word line slice, or, in some cases, may be operable to concurrently activate multiple word line plates, each in a different corresponding word line slice (e.g., a different stack, possibly at the same level within the different stacks) but coupled to the word line driver via a common electrode (e.g., a common ladder electrode). Thus, sharing word line decoders, drivers, or both across adjacent pillar slices 805 as described herein may reduce the number of word line decoders, drivers, or both included in word line decoding circuitry 810 positioned below individual pillar slices 805, thereby enhancing the ability to position all associated word line decoding circuitry 810 below the memory array for a memory array including multiple pillar slices 805.

[0131] The area occupied by the word line decoding circuitry 810 under a given pillar slice 805 may increase as the number of word line plates associated with each pillar slice 805 increases (e.g., based on the number of word line slices in the pillar slice 805, based on the number of word line plates within a word line slice, such as the number of levels of the memory array and thus the number of word line slices in the z-direction, or both). Figure 8A and 8B The view illustrated in FIGURE 8A may represent a top view of pillar slice 805, such that the stack of word line plates within a word line slice (e.g., each word line plate of the stack corresponding to one level of the memory array) may extend off the page. The area occupied by a contiguous region of word line decoding circuitry 810 may be associated with the number of word line drivers used to drive the respective word line plates in each pillar slice 805 (e.g., where each word line driver drives a respective word line plate within a corresponding word line slice or a group of respective word line plates within a group of corresponding word line slices).

[0132] In some cases, the size of each individual wordline driver can be independent of the number of wordline plates in pillar slice 805 (and therefore the number of wordline slices). For example, each wordline driver can drive one or more wordline plates, each having a known capacitance for a desired access voltage within a desired time period (e.g., a timing specification), and the size (e.g., transistor width) of each wordline driver can be associated with the corresponding drive strength of the wordline driver (e.g., for driving one or more wordline plates). Thus, the size of individual wordline drivers within wordline decoding circuitry 810 can be based on the size and electrical qualities (e.g., capacitance, length) of the wordline plates of the memory array.

[0133] The number of word line drivers associated with pillar slice 805 can be based on the number of independently addressable (e.g., capable of being activated or deactivated independently of one another) word line plates in pillar slice 805. For example, within a hierarchy of a memory array, the total number of word line fingers can depend on the number of pillars along a given dimension within pillar slice 805 (e.g., if word line fingers extend in the x-direction, the total number of word line fingers within pillar slice 805 can depend on the number of pillars included in a column of pillars spanning pillar slice 805 in the y-direction). Word line fingers can be grouped into separate word line plates within a hierarchy to reduce the capacitance of individual word line plates. For example, if a column of pillars within pillar slice 805 includes 1,024 pillars, then a hierarchy of pillar slice 805 can include 512 right-extending word line fingers and 512 left-extending word line fingers that can span pillar slice 805 in the y-direction, with each word line finger extending between two pillars in the column (e.g., as shown in Figures 4 and 5). It should be understood that these and any other specific numerical examples provided herein are for illustrative clarity only and do not limit the claims or the present disclosure.

[0134] Rather than a single word line comb having 512 fingers, two sets of 512 word line fingers can be divided across a set of separate word line plates (e.g., to reduce the capacitance associated with each individual word line plate). For example, in the y-direction within a given level of pillar slice 805, a first set of eight (8) word line plates, each having 64 fingers, can provide a total of 512 right-extending word line fingers, and a second set of eight word line plates, each having 64 fingers, can provide a total of 512 left-extending word line fingers. Each of the 16 word line plates can be included in a separate word line slice block, where the word line slice block can include a vertical stack of word line plates, each also having 64 fingers (e.g., stacked in the z-direction). The number of word line plates in the vertical stack can be equal to the number of levels of the memory array.

[0135] In some cases, each vertical stack of word line plates within pillar slice 805 (e.g., each word line plate) can be independently addressable. Within a vertical stack of word line plates, different word line plates can be independently addressable relative to each other (e.g., one word line plate can be activated or deactivated at a time within the vertical stack). For example, each vertical stack of word line plates within pillar slice 805 can be coupled with a different respective word line decoder, and the respective word line decoder for the vertical stack can include a different respective word line driver for each word line plate of the vertical stack. Thus, the number of word line drivers associated with operating the word line plates of pillar slice 805 can depend on the number of word line plates within each level of the pillar slice and the number of levels. For example, if, in the y-direction, pillar tile 805 includes eight vertical stacks of word line plates with right-extending fingers and eight vertical stacks of word line plates with left-extending fingers (where each vertical stack includes 64 word line plates), then a total of 1,024 independently addressable word line plates may be included in pillar tile 805, thus yielding a total of 1,024 associated word line drivers, which may be viewed as including a first group of 512 word line drivers associated with the word line plates with right-extending fingers and a second group of 512 word line drivers associated with the word line plates with left-extending fingers. Thus, through this sharing, for example, the number of word line drivers associated with pillar tile 805 may be equal to half the value determined by multiplying the number of levels in pillar tile 805 by the number of word line plates in each level (i.e., a value equal to the total number of word line plates of pillar tile 805), which may be viewed as two groups of word line drivers, each being half the product of the numbers.

[0136] If word line decoders (and therefore the drivers therein) are shared by adjacent pillar slices 805, the total number of word line drivers positioned under individual ones of the pillar slices 805 can be reduced. For example, as described elsewhere herein, a first word line plate (e.g., having rightward-extending fingers) in a first word line slice within a first pillar slice 805 can be coupled, by means of a common electrode, to word line drivers of a second word line plate (e.g., having leftward-extending fingers) in a second word line slice that is identical to the second pillar slice 805. For example, the first and second word line plates can be at the same level (e.g., can be coplanar) within their respective word line slices.

[0137] Thus, in this example, from the perspective of a single pillar tile 805, the number of associated word line drivers for the purpose of being placed under the pillar tile 805 can be reduced by half (e.g., the 512 word line drivers under the pillar tile 805 can be considered to include a first group of 256 word line drivers associated with the word line plate having rightward-extending fingers and a second group of 256 word line drivers associated with the word line plate having leftward-extending fingers), because some of the word line drivers associated with the pillar tile 805 can be positioned under an adjacent pillar tile. Furthermore, in this example, the word line decoders can be considered to be shared between a first word line tile within the first pillar tile 805 and a second word line tile within the second pillar tile 805, with individual word line decoders being positioned entirely under one of the two pillar tiles 805 or comprising a first portion positioned under the first pillar tile 805 and a second portion positioned under the second pillar tile 805. As shown in FIG. 8 , word line decoding circuitry positioned beneath pillar tile 805 may be aligned with one or more edges of pillar tile 805 (eg, adjacent one or more edges of the footprint of pillar tile 805 ).

[0138] In some cases, the CuA of each pillar tile 805 may additionally or alternatively include a pillar decoding circuit system 815 for activating pillars, each of which may be individually addressable in some cases. For example, a pillar decoder (e.g., a gate line pillar decoder or a source line pillar decoder) in the pillar decoding circuit system 815 may selectively activate and deactivate corresponding pillar column lines or pillar row lines of individual pillar rows or columns. As described herein, for example, with reference to FIG. 7 , activated pillar column lines and pillar row lines may activate corresponding pillars of the memory array at the junction of the pillar column lines and the pillar row lines. For example, a pillar column line may activate a corresponding pillar selector (or column thereof), for example, with reference to FIG. Figure 7B The pillar selector 710 described above is described, and the pillar row lines can be used to apply a voltage to the pillars via the activated pillar selector. In some cases, the pillar row lines and pillar column lines associated with the pillar decoder can have relatively low capacitance compared to the word line plate associated with the word line decoder. Thus, the pillar decoder can include pillar line drivers that each include one or more transistors that are smaller than the transistors associated with the word line drivers, and therefore, in some cases, the pillar decoding circuitry 815 under the pillar tile 805 can occupy an area that is smaller than the word line decoding circuitry 810 under the pillar tile 805.

[0139] The first portion of the pillar decoding circuitry 815 (e.g., a pillar column line or pillar gate line decoder) may be divided into two portions (e.g., subsets) each oriented in the x-direction within the pillar tile 805, wherein each of the two portions may be positioned near an opposite edge of the pillar tile 805 (e.g., may be respectively aligned with opposite edges, such as respectively abutting opposite edges of the footprint of the pillar tile 805). Figure 8A , a second portion of the pillar decoding circuitry 815 (e.g., a pillar row line or pillar source line decoder) may be oriented in the y-direction near a middle section of the pillar tile 805. In some cases, the second portion of the pillar decoding circuitry 815 may be further divided into two staggered (e.g., offset in the x-direction) portions (e.g., subsets), such as Figure 8A As described herein, the pillar decoders of the pillar decoding circuitry 815 are operable to selectively activate individual pillar row lines or pillar column lines. It should be understood that Figure 8A The pillar piece 805 shown in FIG. 8B or as otherwise described herein may be rotated 90 degrees clockwise or counterclockwise so that references to the x- and y-directions are reversed.

[0140] For example, two first portions of the pillar decoding circuit system 815 oriented in the x-direction may be operable to activate corresponding pillar column lines extending in the y-direction, and a second subset of the pillar decoding circuit system 815 extending in the y-direction may be operable to activate corresponding pillar row lines extending in the x-direction. By activating the pillar column lines (e.g., gate lines), the pillar decoders of the pillar decoding circuit system 815 may activate the gates of corresponding pillar selectors (or columns thereof) coupled to the activated pillar column lines. Similarly, by activating the pillar row lines (e.g., source lines), the pillar decoders of the pillar decoding circuit system 815 may activate the sources of corresponding pillar selectors (or corresponding rows thereof) coupled to the activated pillar row lines (e.g., and thereby apply a voltage to pillars positioned at the intersection of the pillar column lines and the pillar row lines).

[0141] The size of the pillar line drivers of the pillar decoding circuit system 815 (e.g., and therefore the size of the area occupied by the pillar decoder) can be based on the resistivity and capacitance of each pillar access line (e.g., a pillar column or row line), which can be based on the length of the access line, the number of pillar selectors coupled to the pillar access line, or both. For example, if the resistivity or capacitance of the pillar access line increases, then the driving capability of the associated pillar line driver (e.g., a transistor) can be increased in order to drive the access line to meet the desired timing specifications, which can result in an increased area (e.g., width) of the corresponding pillar line driver. In one example, the number of pillars and corresponding pillar selectors associated with each pillar column line in the y-direction can correspond to a first capacitance. The pillar line driver (e.g., a pillar gate line driver) associated with the corresponding pillar row line can drive a first current through the pillar column line over a time period to charge the pillar column line to a desired voltage. The pillar line driver can have a minimum width that supports such driving capability. Each pillar row line driver can be associated with a similar corresponding width for driving the corresponding pillar row line based on the resistivity and capacitance of the pillar row line.

[0142] In some cases, the pillar decoding circuitry 815 under the pillar tile 805 may include one pillar column line driver for each pillar column within the pillar tile 805 (e.g., for each pillar column line within the pillar tile 805) and one pillar row line driver for each pillar row within the pillar tile 805 (e.g., for each pillar row line within the pillar tile 805). Thus, the area of ​​the pillar decoding circuitry 815 under the pillar tile 805 may be based on the number of pillar columns and the number of pillar rows within the pillar tile 805. Beneficially, the area of ​​the pillar decoding circuitry 815 under the pillar tile 805 (e.g., based on the number of pillar line drivers or decoders in the pillar decoding circuitry 815) may be independent of the number of levels of the memory array, which may support an increase in levels while maintaining the ability to implement the pillar decoding circuitry 815 as a CuA, possibly along with other circuitry.

[0143] The remaining area of ​​the CuA of each pillar tile 805 (e.g., the area within the footprint of the pillar tile 805 that is not occupied by the word line decoding circuitry 810 or the pillar decoding circuitry 815) may include other circuitry used to support the operation of the pillar tile 805, such as the sense amplifiers 820. Each pillar tile 805 may include a certain number of sense amplifiers 820 used to support a desired number of parallel or concurrent access operations (e.g., parallelism) of multiple memory cells within the pillar tile. For example, each pillar tile may include a number of sense amplifiers 820 corresponding to (e.g., equal to) the number of pillar row lines (and therefore pillar rows) within the pillar tile 805. Although in Figure 8A and 8BSome locations for the sense amplifiers 820 are illustrated in FIG. 8 , but it should be understood that the sense amplifiers 820 may be positioned in any area under the pillar tile 805 not occupied by the decoding circuitry (eg, word line decoding circuitry 810 and pillar decoding circuitry 815).

[0144] Figure 8B The following describes a pillar block architecture 800-b including a plurality of pillar blocks 805. Figure 8B As described in , in some cases, the pillar decoding circuitry 815 (e.g., pillar decoders) in each pillar tile 805 may be aligned with respective edges of the pillar tile 805 (e.g., adjacent respective edges of the footprint of the pillar tile 805) and may be shared across adjacent pillar tiles 805. For example, pillar column decoders (e.g., occupying area and aligned with pillar tile 805 edges extending in the x-direction), source pillar decoders (e.g., occupying area and aligned with pillar tile 805 edges extending in the y-direction), or both may be shared between adjacent pillar tiles 805. If a pillar column decoder is shared between a first pillar tile 805 and an adjacent second pillar tile 805, the pillar column decoder may be operable to selectively and concurrently activate a first pillar column line within the first pillar tile 805 and a second pillar column line within the second pillar tile 805. Similarly, if a pillar row decoder is shared between a first pillar tile 805 and an adjacent second pillar tile 805, the pillar row decoder is operable to selectively and concurrently activate a first pillar row line within the first pillar tile 805 and a second pillar row line within the second pillar tile 805. This sharing of the pillar decoding circuitry 815 between the pillar tiles 805 can reduce the number of pillar line drivers per pillar tile 805 by half, and thus can beneficially reduce the number of pillar line drivers positioned beneath the pillar tiles 805 by half. For example, the number of pillar column line drivers beneath the pillar tile 805 can be equal to half the number of pillar columns (and therefore pillar column lines) of the pillar tile 805, the number of pillar row line drivers beneath the pillar tile 805 can be equal to half the number of pillar rows (and therefore pillar row lines) of the pillar tile 805, or both.

[0145] Figure 9A and 9BExamples of wordline drivers 900-a and 900-b supporting a decoding architecture for a memory tile according to examples disclosed herein are described. Wordline driver 900 may represent an example of a portion (e.g., among other portions) of a wordline decoder as described herein, for example, with reference to FIG8 . For example, wordline driver 900-a, wordline driver 900-b, one or more other wordline drivers 900, or any combination thereof may be included in a CuA beneath a respective memory array and may be used to activate one or more respective wordline plates of the memory array. A wordline decoder may include multiple wordline drivers 900 and may be operable to activate one wordline driver 900 at a time to activate one or more respective wordline plates coupled to the wordline driver 900. Wordline drivers 900-a and 900-b may be operable to activate or access the respective wordline plates by applying a voltage bias to electrodes coupled to the respective wordline plates, as described herein, for example, with reference to FIG8 .

[0146] Figure 9A A wordline driver 900-a is illustrated, which may include n-type transistors 905-a and 905-b (e.g., negative metal oxide semiconductor (N-MOS) transistors 905) and may be referred to as a 2N-MOS driver. The wordline driver 900-a is operable to drive (e.g., select or activate) a corresponding wordline plate. In some examples, a wordline plate signal 930-a may be output by the transistors 905-a and 905-b. The wordline plate signal 930-a may be applied to the wordline plate via electrodes coupled to the transistors 905-a and 905-b (e.g., coupled to the source of the transistor 905-a and the drain of the transistor 905-b). Based on one or more input signals to the wordline driver 900-a, the wordline plate signal 930-a may maintain the wordline plate inactive or may activate (e.g., select) the wordline plate. For example, the word line plate signal 930-a may be set in an inactive state (e.g., a low state) until a voltage combination is applied to transistors 905-a and 905-b, which may cause the word line plate signal 930-a to transition to an active state (e.g., a high state), for example, by applying a voltage bias to the electrode (e.g., and applied to the word line plate via the electrode) to activate the word line plate. The word line plate signal 930-a may transition from the active state to the inactive state in response to the voltage combination no longer being applied to transistors 905-a and 905-b.

[0147] The drain node of transistor 905-a may be configured to receive a slice select signal 915-a, and the source of transistor 905-b may be coupled to a lower voltage supply 920 (eg, ground). Figure 8AAs illustrated, the source node of transistor 905-a can be coupled to the drain node of transistor 905-b. The gate of transistor 905-a can be configured to receive a first tier select signal 925-a, and the gate of transistor 905-b can be configured to receive a second tier select signal 925-b. The nodes at the source of transistor 905-a and the drain of transistor 905-b can be further coupled to respective word line plates (e.g., via electrodes, such as the ladder electrodes described herein). In some cases, the tile select signal 915-a, the first tier select signal 925-a, or the second tier select signal 925-b can be provided by a memory controller (e.g., the local memory controller 165). In other cases, the tile select signal 915-a, the first tier select signal 925-a, or the second tier select signal 925-b can be provided by other aspects of word line decoding circuitry (e.g., a word line decoder including word line driver 900-a).

[0148] A word line driver 900-a can be associated with a word line plate of a word line plate stack in a word line slice block (e.g., positioned at any tier or level within the word line plate stack), as described herein. To activate a word line plate, the memory device can cause a slice select signal 915-a to transition from a deselect voltage to a select voltage (e.g., from a low to a high voltage) based on word line slice j, which includes a corresponding word line plate for the word line driver 900-a, being selected for activation. For example, the memory device can cause the slice select signal 915-a to transition from a deselect voltage to a select voltage based on a command from a host device or a controller of the memory device. In some cases, the slice select signal 915-a can be applied in a similar manner to each word line driver 900 associated with word line slice j.

[0149] Concurrently with causing the tile select signal 915-a to transition from a deselect voltage to a select voltage, the memory device may cause the first tier select signal 925-a to transition from a deselect voltage to a select voltage (e.g., from a low to a high voltage) based on the tier i including the corresponding word line plate for the word line driver 900-a being selected for activation. For example, the memory device may cause the first tier select signal 925-a to transition from a deselect voltage to a select voltage based on a command from a host device or a controller of the memory device. In some cases, the second tier select signal 925-b may be the complement of the first tier select signal 925-a and thus may transition in a complementary manner (e.g., from a high to a low voltage) based on the transition of the first tier select signal 925-a from the deselect voltage to the select voltage. In some cases, the first level select signal 925-a and the second level select signal 925-b may be applied in a similar manner to each word line driver 900 associated with level i, but also only the word line driver 900 for which the corresponding word line slice block is selected may cause the corresponding word line plate signal 930-a to transition to an activated state.

[0150] The block select signal 915-a, the first level select signal 925-a and the second level select signal 925-b can set the corresponding transistors 905-a and 905-b in an on or off state so that the word line plate signal 930-a (for example, the signal for activating the word line plate at level i within the word line block j) is set in an activated state when the corresponding word line plate is activated, or the word line plate signal 930-a is set in an inactive state when the corresponding word line plate is not activated. For example, when the word line plate is activated (e.g., to access one or more corresponding memory cells), the voltage difference between the activated states of the first level select signal 925-a and the word line plate signal 930-a may be greater than the threshold voltage of the transistor 905-a, such that the transistor 905-a may be turned on, and the voltage difference between the second level select signal 925-b and the lower voltage supply 920 may be less than the threshold voltage of the transistor 905-b, such that the transistor 905-b may be turned off (e.g., to reduce the possibility of a short to the lower voltage supply 920). Thus, based on the slice select signal 915-a, the first level select signal 925-a, and the second level select signal 925-b being in a particular voltage combination, the word line plate signal 930-a may transition to an activated state (e.g., a high voltage) (e.g., the slice select signal 915-a may be transmitted from the drain to the source of the transistor 905-a).

[0151] When the word line plate is not being accessed, the word line plate signal 930-a may be set to an inactive state (e.g., a low voltage, such as a ground voltage). For example, the voltage difference between the first level select signal 925-a and the word line plate signal 930-a may be less than the threshold voltage of transistor 905-a, and the voltage difference between the second level select signal 925-b and the lower voltage supply 920 may be greater than the threshold voltage of transistor 905-b, such that transistor 905-b may be turned on and transistor 905-a may be turned off. Thus, the slice select signal 915-a may not be coupled to the word line plate signal 930-a, and the word line plate signal 930-a may transition to the voltage of the lower voltage supply 920 through transistor 905-b. Additionally or alternatively, the slice select signal 915-a may transition to a deselect voltage (e.g., a low voltage) to set the word line plate signal 930-a to an inactive state.

[0152] Figure 9B An example of a word line driver 900-b is illustrated that may include a p-type transistor 910 (e.g., a positive metal oxide semiconductor (P-MOS) transistor) and an n-type transistor 905-c (e.g., such that the word line driver 900-b may have an N+P-MOS structure). The word line driver 900-b may be operable to drive (e.g., select or activate) a corresponding word line plate using a word line plate signal 930-b, which may represent a reference signal. Figure 9A The wordline plate signals are described.

[0153] The source node of transistor 910 may be configured to receive a first slice select signal 915-b (e.g., a signal that may be referred to as a positive slice select signal), and the source node of transistor 905-c may be configured to receive a second slice select signal 915-c (e.g., a signal that may be referred to as a negative slice select signal). The gate of transistor 910 may be configured to receive a first level select signal 925-c, and the gate of transistor 905-c may be configured to receive a second level select signal 925-d. Figure 9B As illustrated, the drain node of transistor 910 can be coupled to the drain node of transistor 905-b. The nodes at the drain of transistor 910 and the drain of transistor 905-c can further be coupled to respective word line plates (e.g., via electrodes such as the ladder electrodes described herein).

[0154] A word line driver 900-b can be associated with a word line plate of a word line plate stack in a word line slice block (e.g., positioned at any tier or level within the word line plate stack), as described herein. To activate a word line plate, the memory device can cause a first slice select signal 915-b to transition from a deselect voltage to a select voltage (e.g., from a low to a high voltage), cause a second slice select signal 915-c to transition from a deselect voltage to a select voltage (e.g., from a high to a low voltage), or both, based on word line slice j, which includes a corresponding word line plate for word line driver 900-b, being selected for activation. For example, the memory device can cause such transitions based on a command from a host device or a controller of the memory device. In some cases, the first slice select signal 915-b and the second slice select signal 915-c can be applied in a similar manner to each word line driver 900 associated with word line slice j.

[0155] Concurrently with causing the first slice select signal 915-b to transition from a deselect voltage to a select voltage, the second slice select signal 915-c to transition from a deselect voltage to a select voltage, or both, the memory device may cause the first level select signal 925-c (e.g., a signal that may be referred to as a positive level select signal) and the second level select signal 925-d (e.g., a signal that may be referred to as a negative level select signal) to transition from a deselect voltage to a select voltage (e.g., from a high to a low voltage, such as the voltage to the low voltage supply 920) based on the tier i including the corresponding word line plate for the word line driver 900-b being selected for activation. In some cases, the first level select signal 925-c and the second level select signal 925-d may be applied in a similar manner to each word line driver 900 associated with tier i, but also only the word line driver 900 for which the corresponding word line slice is selected may cause the corresponding word line plate signal 930-b to transition to an activated state.

[0156] The positive block select signal 915-b, the negative block select signal 915-c, the positive level select signal 925-c and the negative level select signal 925-d can set the corresponding transistors 910 and 905-c in an on or off state so that the word line plate signal 930-b (for example, the signal for activating the word line plate at level i in word line block j) is set in an activated state when the corresponding word line plate is activated, or the word line plate signal 930-b is set in an inactive state when the corresponding word line plate is not activated. For example, when the word line plate is activated (e.g., to access one or more corresponding memory cells), the voltage difference between the first level select signal 925-c and the first slice select signal 915-b may be greater than the threshold voltage of the transistor 910, such that the transistor 910 may be turned on, and the voltage difference between the second level select signal 925-d and the second slice select signal 915-c may be less than the threshold voltage of the transistor 905-c, such that the transistor 905-c may be turned off (e.g., to reduce the possibility of a short to the lower voltage supply 920). Thus, based on the first slice select signal 915-b, the first level select signal 925-c, the second level select signal 925-d, and the second slice select signal 915-c being in a particular voltage combination, the word line plate signal 930-b may transition to an activated state (e.g., a high voltage) (e.g., the first slice select signal 915-b may be transmitted from drain to drain of the transistor 910).

[0157] When the word line plate is not being accessed, the word line plate signal 930-b may be set to an inactive state (e.g., a low voltage, such as a ground voltage). For example, the voltage difference between the first level select signal 925-c and the first slice select signal 915-b may be less than the threshold voltage of transistor 910, and the voltage difference between the second level select signal 925-d and the second slice select signal 915-c may be greater than the threshold voltage of transistor 905-c, so that transistor 905-c may be turned on and transistor 910 may be turned off. Thus, the first slice select signal 915-b may not be coupled to the word line plate signal 930-b, and the word line plate signal 930-b may transition to the voltage of the lower voltage supply 920 through transistor 905-c. Additionally or alternatively, the first slice select signal 915-b may transition to a deselect voltage (e.g., a low voltage) to set the word line plate signal 930-b to an inactive state.

[0158] Thus, word line decoding circuitry for driving word line plates of a memory array may include a set of word line drivers 900-a, each of which may include two n-type transistors 905, a set of word line drivers 900-b, each of which may include an n-type transistor 905 and a p-type transistor 910, or both. The word line drivers 900 may each activate one or more word line plates by applying a voltage (e.g., an activation bias, such as a word line plate signal 930 having an activation voltage) to the one or more corresponding word line plates based on tile select and level select signals applied to the word line drivers 900.

[0159] The size (e.g., transistor width) of each wordline driver 900 can be associated with the corresponding drive strength of the wordline driver 900 (e.g., for driving a wordline plate). Thus, the size of a wordline driver 900 can be based on the amount of current and voltage that the driver 900 can apply to the corresponding wordline plate, which can be based on the size and electrical quality (e.g., capacitance) of the wordline plate. For example, if the capacitance or resistivity of a wordline plate increases, the drive capability of the associated wordline driver 900 can be increased for driving the wordline plate, which can result in an increased area (e.g., width) of the wordline driver 900. In some examples, the width of a wordline driver 900 can be based on the type of transistors of the wordline driver 900. For example, the width of an n-type transistor 905 can be the same as or different from the width of a p-type transistor 910 used to drive the corresponding wordline plate.

[0160] Figure 10 A block diagram 1000 is shown of a memory device 1020 that supports a decoding architecture for memory slices according to examples as disclosed herein. The memory device 1020 may be a memory device 1020 as described in reference to FIG. Figure 1 9. Memory device 1020 or its various components may be examples of means for performing various aspects of the decoding architecture for memory slices as described herein. For example, memory device 1020 may include a wordline decoding component 1025, a first pillar decoding component 1030, a second pillar decoding component 1035, a first pillar row decoding component 1040, a first pillar column decoding component 1045, a second pillar row decoding component 1050, a second pillar column decoding component 1055, or any combination thereof. Each of these components may communicate with each other, directly or indirectly (e.g., via one or more buses).

[0161] The word line decoding component 1025 can be configured to, or otherwise support, means for applying a first voltage to a first word line plate of a first word line slice associated with a first pillar slice using a first decoding circuitry, the first word line plate including a set of first word lines each coupled to one or more corresponding memory cells in a group of first memory cells, wherein the first pillar slice includes a set of first pillars each coupled to one or more corresponding first memory cells in the group of first memory cells. In some examples, the word line decoding component 1025 can be further configured to, or otherwise support, means for applying a second voltage to a second word line plate of a second word line slice associated with a second pillar slice using the first decoding circuitry, the second word line plate including a set of second word lines each coupled to one or more corresponding memory cells in a group of second memory cells, wherein the second pillar slice includes a set of second pillars each coupled to one or more corresponding second memory cells in the group of second memory cells.

[0162] The first pillar decoding component 1030 may be configured to, or otherwise support, means for applying a third voltage to a first pillar in the set of first pillars included in the first pillar tile using a second decoding circuit system associated with the first pillar tile, the first pillar being coupled to a first memory cell in the set of first memory cells, wherein the first memory cell is operable to be accessed based on applying the first voltage to the first word line plate and applying the third voltage to the first pillar. The second pillar decoding component 1035 may be configured to, or otherwise support, means for applying a fourth voltage to a second pillar in the set of second pillars included in the second pillar tile using a third decoding circuit system, the second pillar being coupled to a second memory cell in the set of second memory cells, wherein the second memory cell is operable to be accessed based on applying the second voltage to the second word line plate and applying the fourth voltage to the second pillar.

[0163] In some instances, the first decoding circuitry may be positioned below the set of first memory cells and the set of second memory cells, and the first decoding circuitry may be aligned with respective edges of the first pillar tile and respective edges of the second pillar tile.

[0164] In some examples, a third word line slice associated with the first pillar slice can include a third word line plate including a set of third word lines in the same plane as the set of first word lines, each of the plurality of third word lines being coupled to one or more respective memory cells of a plurality of third memory cells each coupled to a respective first pillar of the first pillar slice. The word line decoding component 1025 can further be configured to or otherwise support means for concurrently applying the first voltage to the first and third word line plates using the first decoding circuitry, wherein the first and third word line plates share a word line driver included in or coupled to the first decoding circuitry.

[0165] In some examples, a fourth word line plate associated with the first pillar slice can be addressed independently of the first word line plate and includes a set of fourth word lines in the same plane as the set of first word lines, each of the plurality of fourth word lines being coupled to one or more respective memory cells of a plurality of fourth memory cells each coupled to a respective first pillar of the first pillar slice, wherein each fourth word line is positioned between a pair of respective first word lines. The word line decoding component 1025 can be further configured to or otherwise support means for applying the first voltage to the fourth word line plate independently of the first word line plate using the first decoding circuitry, wherein the first and fourth word line plates are coupled to different word line decoders of the first decoding circuitry.

[0166] In some examples, the first word line slice block can include a set of first word line plates stacked in a vertical direction and including the first word line plates, wherein each first word line extends in a horizontal direction and each first pillar extends in the vertical direction. The word line decoding component 1025 can further be configured to or otherwise support means for applying the first voltage to one of the set of first word line plates for a corresponding access operation.

[0167] In some examples, the second decoding circuit system may include a first pillar decoder and a second pillar decoder, and the first pillar row decoding component 1040 may be configured to or otherwise support means for applying the third voltage to a pillar row line associated with the first pillar using the first pillar decoder. In some examples, the second decoding circuit system includes a first pillar decoder and a second pillar decoder, and the first pillar column decoding component 1045 may be configured to or otherwise support means for applying a fifth voltage to a pillar column line associated with the first pillar using the second pillar decoder, wherein a pillar selector for the first pillar is operable to couple the first pillar with the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the third voltage to the first pillar is based on coupling the first pillar with the pillar row line.

[0168] In some examples, the third decoding circuit system may include a third pillar decoder and a fourth pillar decoder, and the second pillar row decoding component 1050 may be configured to or otherwise support means for applying the fourth voltage to a pillar row line associated with the second pillar using the third pillar decoder. In some examples, the third decoding circuit system includes a third pillar decoder and a fourth pillar decoder, and the second pillar column decoding component 1055 may be configured to or otherwise support means for applying a fifth voltage to a pillar column line associated with the second pillar using the fourth pillar decoder, wherein a pillar selector for the second pillar is operable to couple the second pillar with the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the fourth voltage to the second pillar is based on coupling the second pillar with the pillar row line.

[0169] Figure 11 A flowchart illustrating a method 1100 for supporting a decoding architecture for a memory slice according to an example as disclosed herein is shown. The operations of the method 1100 may be implemented by a memory device or components thereof as described herein. For example, the operations of the method 1100 may be implemented by a memory device or components thereof as described herein. Figures 1 to 10 In some examples, the memory device may execute a set of instructions to control the functional elements of the device to perform the described functions. Additionally or alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0170] At 1105, the method may include applying a first voltage to a first word line plate of a first word line slice associated with a first pillar slice using a first decoding circuit system, the first word line plate including a set of first word lines each coupled to one or more corresponding memory cells in a group of first memory cells, wherein the first pillar slice includes a set of first pillars each coupled to one or more corresponding first memory cells in the group of first memory cells. The operations of 1105 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 1105 may be performed as described in reference to Figure 10 The described word line decoding component 1025 is performed.

[0171] At 1110, the method may include applying, using the first decoding circuitry, a second voltage to a second word line plate of a second word line slice associated with a second pillar slice, the second word line plate including a set of second word lines each coupled to one or more corresponding memory cells in a set of second memory cells, wherein the second pillar slice includes a set of second pillars each coupled to one or more corresponding second memory cells in the set of second memory cells. The operations of 1110 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 1110 may be performed as described with reference to Figure 10 The described word line decoding component 1025 is performed.

[0172] At 1115, the method may include applying a third voltage to a first pillar in the set of first pillars included in the first pillar tile using a second decoding circuit system associated with the first pillar tile, the first pillar being coupled to a first memory cell in the set of first memory cells, wherein the first memory cell is operable to be accessed based on applying the first voltage to the first word line plate and applying the third voltage to the first pillar. The operations of 1115 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 1115 may be as described with reference to Figure 10 The first pillar decoding component 1030 is described to perform.

[0173] At 1120, the method may include applying, using a third decoding circuit system, a fourth voltage to a second pillar in the set of second pillars included in the second pillar tile, the second pillar being coupled to a second memory cell in the set of second memory cells, wherein the second memory cell is operable to be accessed based on applying the second voltage to the second word line plate and applying the fourth voltage to the second pillar. The operations of 1120 may be performed according to examples as disclosed herein. In some examples, aspects of the operations of 1120 may be as described with reference to Figure 10 The second pillar decoding component 1035 is described to perform.

[0174] In some examples, an apparatus as described herein may perform one or more methods, such as method 1100. The apparatus may include operations, features, circuitry, logic, means, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for applying, using a first decoding circuitry, a first voltage to a first wordline plate of a first wordline slice associated with a first pillar slice, the first wordline plate including a set of first wordlines each coupled to one or more corresponding memory cells in a group of first memory cells, wherein the first pillar slice includes a set of first pillars each coupled to one or more corresponding first memory cells in the group of first memory cells. The apparatus may further include operations, features, circuitry, logic, means, or instructions for applying, using the first decoding circuitry, a second voltage to a second wordline plate of a second wordline slice associated with a second pillar slice, the second wordline plate including a set of second wordlines each coupled to one or more corresponding memory cells in a group of second memory cells, wherein the second pillar slice includes a set of second pillars each coupled to one or more corresponding second memory cells in the group of second memory cells. The apparatus may further include operations, features, circuit systems, logic, means, or instructions for: applying a third voltage to a first pillar in the set of first pillars included in the first pillar slice using a second decoding circuit system associated with the first pillar slice, the first pillar being coupled to a first memory cell in the set of first memory cells, wherein the first memory cell is operable to be accessed based on applying the first voltage to the first word line plate and applying the third voltage to the first pillar. The apparatus may further include operations, features, circuit systems, logic, means, or instructions for: applying a fourth voltage to a second pillar in the set of second pillars included in the second pillar slice using a third decoding circuit system, the second pillar being coupled to a second memory cell in the set of second memory cells, wherein the second memory cell is operable to be accessed based on applying the second voltage to the second word line plate and applying the fourth voltage to the second pillar.

[0175] In some examples of the method 1100 and apparatus described herein, the first decoding circuitry may be positioned below the set of first memory cells and the set of second memory cells, and the first decoding circuitry may be aligned with respective edges of the first pillar slice and respective edges of the second pillar slice.

[0176] In some examples of the methods 1100 and apparatus described herein, a third wordline slice associated with the first pillar slice may include a third wordline plate including a set of third wordlines coplanar with the set of first wordlines, each of the plurality of third wordlines being coupled to one or more respective memory cells of a plurality of third memory cells each coupled to a respective first pillar of the first pillar slice. The methods, apparatus, and non-transitory computer-readable media may further include operations, features, circuitry, logic, means, or instructions for concurrently applying the first voltage to the first and third wordline plates using the first decoding circuitry, wherein the first and third wordline plates share a wordline driver included in or coupled to the first decoding circuitry.

[0177] In some examples of the method 1100 and apparatus described herein, a fourth wordline plate associated with the first pillar slice is addressable independently of the first wordline plate and includes a set of fourth wordlines coplanar with the set of first wordlines, each of the plurality of fourth wordlines coupled to one or more respective memory cells of a plurality of fourth memory cells each coupled to a respective first pillar of the first pillar slice, wherein each fourth wordline is positioned between a pair of respective first wordlines. The method, apparatus, and non-transitory computer-readable medium may further include operations, features, circuitry, logic, means, or instructions for applying the first voltage to the fourth wordline plate independently of the first wordline plate using the first decoding circuitry, wherein the first and fourth wordline plates may be coupled to different wordline decoders of the first decoding circuitry.

[0178] In some examples of the method 1100 and apparatus described herein, the first word line slice block may include a set of first word line plates stacked in a vertical direction and including the first word line plates, wherein each first word line extends in a horizontal direction and each first pillar extends in the vertical direction. The methods, apparatus, and non-transitory computer-readable media may further include operations, features, circuitry, logic, means, or instructions for applying the first voltage to one of the set of first word line plates for a corresponding access operation.

[0179] In some examples of the method 1100 and apparatus described herein, the second decoding circuitry may include a first pillar decoder and a second pillar decoder. The methods, apparatus, and non-transitory computer-readable media may further include operations, features, circuitry, logic, means, or instructions for applying, using the first pillar decoder, the third voltage to a pillar row line associated with the first pillar and applying, using the second pillar decoder, a fifth voltage to a pillar column line associated with the first pillar, wherein a pillar selector for the first pillar is operable to couple the first pillar with the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the third voltage to the first pillar may be based on coupling the first pillar with the pillar row line.

[0180] In some examples of the method 1100 and apparatus described herein, the third decoding circuitry may include a third pillar decoder and a fourth pillar decoder. The methods, apparatus, and non-transitory computer-readable media may further include operations, features, circuitry, logic, means, or instructions for applying, using the third pillar decoder, the fourth voltage to a pillar row line associated with the second pillar and applying, using the fourth pillar decoder, a fifth voltage to a pillar column line associated with the second pillar, wherein a pillar selector for the second pillar is operable to couple the second pillar with the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the fourth voltage to the second pillar may be based on coupling the second pillar with the pillar row line.

[0181] It should be noted that the methods described herein describe possible implementations, and that operations and steps may be rearranged or otherwise modified and other implementations are possible. Additionally, portions from two or more methods may be combined.

[0182] A device is described. The device may include a first wordline slice, the first wordline slice including a first wordline plate including a set of first wordlines, each wordline in the set of first wordlines being coupled to one or more corresponding memory cells in a set of first memory cells. The device may further include a first pillar slice, the first pillar slice including a set of first pillars associated with the first wordline slice, each first pillar being coupled to one or more corresponding first memory cells in the set of first memory cells. The device may further include a second wordline slice, the second wordline slice including a second wordline plate including a set of second wordlines, each wordline in the set of second wordlines being coupled to one or more corresponding memory cells in a set of second memory cells. The device may further include a second pillar slice, different from the first pillar slice, the second pillar slice including a set of second pillars, each associated with the second wordline slice and each coupled to one or more corresponding second memory cells in the set of second memory cells. The apparatus may further include a first decoding circuit system associated with the first pillar tile and the second pillar tile, the first decoding circuit system being operable to activate the set of first word lines included in the first word line plate associated with the first pillar tile and the set of second word lines included in the second word line plate associated with the second pillar tile.

[0183] In some instances, the first decoding circuit system may be positioned below the set of first memory cells and the set of second memory cells (e.g., between a substrate and the set of first memory cells and the set of second memory cells) and may be aligned with respective edges of the first pillar slice and respective edges of the second pillar slice.

[0184] In some examples, the apparatus may include a third word line slice, the third word line slice including a third word line plate including a set of third word lines coplanar with the set of first word lines, each word line in the set of third word lines being coupled to one or more respective memory cells in a set of third memory cells that can each be coupled to a respective first pillar of the first pillar slice. The first decoding circuitry may be further operable to concurrently activate the set of first word lines of the first word line plate and the set of third word lines of the third word line plate.

[0185] In some examples, the first decoding circuitry may include or be coupled with a word line driver, which may be coupled with the first and third word line plates.

[0186] In some examples, the apparatus may include a fourth word line plate that is independently addressable from the first word line plate and includes a set of fourth word lines that are in the same plane as the set of first word lines, each word line in the set of fourth word lines being coupled to one or more corresponding memory cells in a set of fourth memory cells that can each be coupled to a corresponding first pillar of the first pillar slice, wherein each fourth word line can be positioned between a pair of corresponding first word lines.

[0187] In some examples, the first word line slice block includes a set of first word line plates stacked in a vertical direction (e.g., orthogonal to a substrate) and including the first word line plates, each first word line extending in a horizontal direction (e.g., parallel to the substrate) and each first pillar extending in the vertical direction.

[0188] In some examples, the first decoding circuitry is operable to activate one of the set of first word line plates for a corresponding access operation (eg, an operation to access one or more memory cells coupled to the one activated first word line plate).

[0189] In some examples, the apparatus may include a second decoding circuit system associated with the first pillar tile and operable to activate one or more first pillars of the set of first pillars. The second decoding circuit system may include two first subsets oriented in a first direction, the two first subsets being closer to opposite edges of the first pillar tile. The second decoding circuit system may further include a second subset oriented in a second direction.

[0190] In some examples, the two first subsets are operable to activate access lines that each extend in the second direction and are each coupled to a pillar selector for a corresponding column of the first pillar. The second subset is operable to activate access lines that each extend in the first direction and are each coupled to a pillar selector for a corresponding row of the first pillar.

[0191] In some examples, the apparatus may include second decoding circuitry, wherein at least a subset of the second decoding circuitry may be associated with the first pillar tile and the second pillar tile. At least the subset of the second decoding circuitry is operable to activate one or more first pillars of the set of first pillars and one or more second pillars of the set of second pillars.

[0192] In some examples, the apparatus may include a second decoding circuit system associated with the first pillar tile and operable to activate one or more first pillars of the set of first pillars, the second decoding circuit system including a first pillar decoder and a second pillar decoder. The apparatus may further include: a set of pillar column lines, each associated with a corresponding column of the first pillars and operable to be activated by the first pillar decoder; a set of pillar row lines, each associated with a corresponding row of the first pillars and operable to be activated by the second pillar decoder; and a set of pillar selectors. Each pillar selector is operable to be activated by a corresponding pillar column line to couple a corresponding first pillar of the set of first pillars to a corresponding pillar row line of the set of pillar row lines.

[0193] In some examples, the apparatus may include a set of sense amplifiers positioned below the set of first memory cells and associated with the first pillar tile. The set of sense amplifiers is operable to read one or more respective logic values ​​from one or more of the set of first memory cells. In some examples, the number of sense amplifiers in the set may be equal to the number of the set of pillar row lines.

[0194] In some examples, one or both of the first and second strut pieces may have a first length in a first direction and a second length in a second direction that is different from the first length.

[0195] In some examples, the first decoding circuitry may include a set of word line drivers, each of the set of word line drivers including at least a respective n-type transistor and a respective p-type transistor.

[0196] In some examples, the first decoding circuitry may include a set of word line drivers, each of the set of word line drivers including two or more respective n-type transistors.

[0197] Another device is described. The device may include a first wordline slice block, the first wordline slice block including a first wordline plate including a set of first wordlines, each wordline in the set of first wordlines being coupled to one or more corresponding memory cells in a set of first memory cells. The device may further include a first pillar slice block, the first pillar slice block including a set of first pillars associated with the first wordline slice and each coupled to one or more corresponding first memory cells in the set of first memory cells. The device may further include a second wordline slice block, the second wordline plate including a set of second wordlines, each wordline in the set of second wordlines being coupled to one or more corresponding memory cells in a set of second memory cells. The device may further include a second pillar slice block, the second pillar slice block including a set of second pillars associated with the second wordline slice and each coupled to one or more corresponding second memory cells in the set of second memory cells. The apparatus may further include: a first decoding circuitry associated with the first wordline slice and the second wordline slice; a second decoding circuitry associated with the first pillar slice; and a third decoding circuitry associated with the second pillar slice. The apparatus may further include a controller operable to cause the apparatus to apply a first voltage to the first wordline plate using the first decoding circuitry. The controller may further be operable to cause the apparatus to apply a second voltage to the second wordline plate using the first decoding circuitry. The controller may further be operable to cause the apparatus to apply a third voltage to a first pillar in the set of first pillars included in the first pillar slice, the first pillar being coupled to a first memory cell in the set of first memory cells, wherein the first memory cell is operable to be accessed based on applying the first voltage to the first wordline plate and applying the third voltage to the first pillar. The controller may be further operable to cause the device to apply a fourth voltage to a second pillar in the set of second pillars included in the second pillar tile using the third decoding circuit system, the second pillar being coupled to a second memory cell in the set of second memory cells, wherein the second memory cell is operable to be accessed based on applying the second voltage to the second word line plate and applying the fourth voltage to the second pillar.

[0198] In some instances, the first decoding circuit system may be positioned below the set of first memory cells and the set of second memory cells (e.g., between a substrate and the set of first memory cells and the set of second memory cells), and the first decoding circuit system may be aligned with respective edges of the first pillar slice and respective edges of the second pillar slice.

[0199] In some examples, the apparatus may include a third word line slice, the third word line slice including a third word line plate including a set of third word lines coplanar with the set of first word lines, each third word line in the set of third word lines being coupled to one or more respective memory cells in a set of third memory cells each coupled to a respective first pillar of the first pillar slice. In some examples, the controller may be further operable to cause the apparatus to concurrently apply the first voltage to the first and third word line plates using the first decoding circuitry, wherein the first and third word line plates may share a word line driver included in or coupled to the first decoding circuitry.

[0200] In some examples, the apparatus may include a fourth word line plate that is addressable independently of the first word line plate and includes a set of fourth word lines in the same plane as the set of first word lines, each word line in the set of fourth word lines being coupled to one or more respective memory cells in a set of fourth memory cells that can each be coupled to a respective first pillar of the first pillar tile, wherein each fourth word line can be positioned between a pair of respective first word lines. In some examples, the controller may be further operable to apply the first voltage to the fourth word line plate independently of the first word line plate using the first decoding circuitry, wherein the first and fourth word line plates can be coupled to different word line decoders of the first decoding circuitry.

[0201] In some examples, the first word line slice block may include a set of first word line plates stacked in a vertical direction (e.g., orthogonal to a substrate) and including the first word line plates, wherein each first word line extends in a horizontal direction (e.g., parallel to the substrate) and each first pillar extends in the vertical direction. In some examples, the controller may be further operable to apply the first voltage to one of the set of first word line plates for a corresponding access operation (e.g., an operation to access one or more memory cells coupled to the first word line plate to which the first voltage is applied).

[0202] In some examples, the second decoding circuitry may include a first pillar decoder and a second pillar decoder. The controller may be further operable to cause the apparatus to: apply the third voltage to a pillar row line associated with the first pillar using the first pillar decoder; and apply a fifth voltage to a pillar column line associated with the first pillar using the second pillar decoder, wherein a pillar selector for the first pillar is operable to couple the first pillar with the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the third voltage to the first pillar may be based on coupling the first pillar with the pillar row line.

[0203] In some examples, the third decoding circuitry may include a third pillar decoder and a fourth pillar decoder. The controller may be further operable to cause the apparatus to: apply the fourth voltage to a pillar row line associated with the second pillar using the third pillar decoder; and apply a fifth voltage to a pillar column line associated with the second pillar using the fourth pillar decoder, wherein a pillar selector for the second pillar is operable to couple the second pillar with the pillar row line based on applying the fifth voltage to the pillar column line, and wherein applying the fourth voltage to the second pillar may be based on coupling the second pillar with the pillar row line.

[0204] Another apparatus is described. The apparatus may include a first wordline slice block, the first wordline slice block including a set of first wordline plates stacked in a vertical direction, each first wordline plate of the set of first wordline plates including a set of first wordlines coupled to one or more corresponding memory cells in a set of first memory cells. The apparatus may further include a second wordline slice block, the second wordline slice block including a set of second wordline plates stacked in the vertical direction, each second wordline plate of the set of second wordline plates including a set of second wordlines coupled to one or more corresponding memory cells in a set of second memory cells, wherein each second wordline plate is positioned in the same plane as the corresponding first wordline plate. The apparatus may further include a first pillar slice block, the first pillar slice including a set of first pillars associated with the first wordline slice block and the second wordline slice block, each first pillar coupled to a corresponding subset of first memory cells within the set of first memory cells or a corresponding subset of second memory cells within the set of second memory cells. The apparatus may further include a third word line slice block comprising a set of third word line plates stacked in the vertical direction, each third word line plate of the set comprising a set of respective third word lines each coupled to one or more respective memory cells in a set of third memory cells, wherein each third word line plate is positioned in the same plane as the corresponding first word line plate. The apparatus may further include a second pillar slice block comprising a set of second pillars associated with the third word line slice block, each second pillar coupled to a respective subset of third memory cells in the set of third memory cells. The apparatus may further include first decoding circuitry associated with the first pillar slice and the second pillar slice, the first decoding circuitry being positioned below the set of first memory cells, the set of second memory cells, and the set of third memory cells (e.g., between a substrate and the set of first memory cells, the set of second memory cells, and the set of third memory cells). The first decoding circuit system can be operated to activate the first word line plate of the set of first word line plates, the second word line plate of the set of second word line plates, and the third word line plate of the set of third word line plates, and the first decoding circuit system can be aligned with the corresponding edge of the first pillar block and the corresponding edge of the second pillar block.

[0205] In some examples, the first decoding circuit system may be further operable to concurrently activate the set of corresponding first word lines of the first word line plate and the set of corresponding second word lines of the second word line plate, wherein the first word line plate and the second word line plate share a word line driver included in or coupled to the first decoding circuit system.

[0206] In some examples, the apparatus can include a set of fourth word line plates that are addressable independently of the set of first word line plates and are each positioned in the same plane as a corresponding first word line plate. Each fourth word line plate can include a set of respective fourth word lines that are each coupled to one or more respective memory cells in a set of fourth memory cells that can each be coupled to a respective first pillar of the first pillar tile, wherein each fourth word line can be positioned between a pair of respective first word lines.

[0207] The information and signals described herein may be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have multiple bit widths.

[0208] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication with each other (or in conductive contact with each other, or connected to each other, or coupled to each other) may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0209] The term "coupling" refers to a state where a signal is moved from an open-circuit relationship between components (where signals cannot currently pass between the components via a conductive path) to a closed-circuit relationship between the components (where signals can pass between the components via a conductive path). When a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via conductive paths that previously did not allow signal flow.

[0210] The term "isolation" refers to a relationship between components where signals cannot flow between them. Components are isolated from one another if an open circuit exists between them. For example, when a switch is open, two components separated by a switch positioned between them are isolated from one another. When a controller isolates two components, it introduces a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0211] As used herein, the term "layer" or "step" refers to a layer or sheet of a geometric structure (e.g., relative to a substrate). Each layer or step can have three dimensions (e.g., height, width, and depth) and can cover at least a portion of a surface. For example, a layer or step can be a three-dimensional structure in which two dimensions are greater than the third, such as a thin film. A layer or step can include different elements, components, and / or materials. In some examples, a layer or step can be composed of two or more sub-layers or sub-steps.

[0212] As used herein, the term "electrode" may refer to an electrical conductor and, in some examples, may serve as an electrical contact to a memory cell or other component of a memory array. An electrode may include a trace, a wire, a conductive line, a conductive layer, or the like that provides an electrically conductive path between elements or components of a memory array.

[0213] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate, or by any other doping method.

[0214] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain may be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), then the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, may cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor may be "turned on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor may be "turned off" or "deactivated."

[0215] The description set forth herein, along with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration," rather than "preferred" or "advantageous over other examples." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0216] In the accompanying drawings, similar components or features may have the same reference label. In addition, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0217] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions may be stored on a computer-readable medium as one or more instructions or codes or transmitted via a computer-readable medium as one or more instructions or codes. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein may be implemented using software executed by a processor, hardware, firmware, hard wiring, or a combination of any of these. Features implementing the functions may also be physically located at various locations, including being distributed so that portions of the functions are implemented at different physical locations.

[0218] For example, the various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed with a general purpose processor, a DSP, an ASIC, an FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0219] As used herein, including in the claims, "or" used in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, so that (for example) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be interpreted as a reference to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0220] Computer-readable media include both non-transitory computer storage media and communication media, and communication media includes any media that facilitates the transfer of computer programs from one place to another. Non-transitory storage media can be any available media that can be accessed by a general-purpose or special-purpose computer. By way of example and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), compact disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices or any other non-transitory media that can be used to carry or store the desired program code components in the form of instructions or data structures and can be accessed by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Moreover, any connection is appropriately referred to as computer-readable media. For example, if coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) is used to transmit software from a website, server or other remote source, then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave) are included in the definition of media. As used herein, disk and disc include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk, and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of these are also included within the scope of computer-readable media.

[0221] The description herein is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A device comprising: A first pillar tile includes a plurality of first pillars, each first pillar being coupled to one or more corresponding memory cells of the plurality of first memory cells; a second pillar tile including a plurality of second pillars, each second pillar being coupled to one or more corresponding second memory cells of the plurality of second memory cells; and A decoding circuit system is associated with the first pillar block and the second pillar block, and is operable to activate one or more of the plurality of first pillars included in the first pillar block and one or more of the plurality of second pillars included in the second pillar block.

2. The apparatus of claim 1, wherein the plurality of first pillars comprises a plurality of first pillar columns and a plurality of first pillar rows, and wherein the plurality of second pillars comprises a plurality of second pillar columns and a plurality of second pillar rows.

3. The apparatus of claim 2 , wherein the decoding circuitry is further operable to: A corresponding first pillar column of the plurality of first pillar columns in the first pillar tile and a corresponding second pillar column of the plurality of second pillar columns in the second pillar tile are activated, wherein the first pillar tile and the second pillar tile share a pillar column decoder coupled to the decoding circuit system.

4. The apparatus of claim 2 , wherein the decoding circuitry is further operable to: Activate a corresponding first pillar row of the plurality of first pillar rows in the first pillar tile and a corresponding second pillar row of the plurality of second pillar rows in the second pillar tile, wherein the first pillar tile and the second pillar tile share a pillar row decoder coupled to the decoding circuit system.

5. The apparatus of claim 1 , wherein the decoding circuitry is positioned below the plurality of first memory cells and the plurality of second memory cells, wherein the decoding circuitry is aligned with the first pillar slice and the second pillar slice, and wherein the decoding circuitry is shared between the first pillar slice and the second pillar slice.

6. The apparatus of claim 1, wherein the decoding circuitry comprises a set of pillar line drivers, and wherein the set of pillar line drivers comprises a number of pillar column drivers and a number of pillar row drivers.

7. The apparatus of claim 6, wherein the number of pillar column drivers is equal to half the number of pillar row drivers, and wherein the number of pillar row drivers is equal to half the number of pillar column drivers, or both.

8. A device comprising: a first pillar tile comprising a plurality of first pillars, each respective pillar of the plurality of first pillars being coupled to one or more respective memory cells of the plurality of first memory cells; a second pillar tile comprising a plurality of second pillars, each respective pillar of the plurality of second pillars being coupled to one or more respective second memory cells of the plurality of second memory cells; Decoding circuitry associated with the first pillar tile and the second pillar tile; and A controller operable to cause the device to: applying a first voltage to a first pillar of the plurality of first pillars included in the first pillar tile using the decoding circuitry, the first pillar being coupled to a first memory cell of the plurality of first memory cells, wherein the first memory cell is operable to be accessed based at least in part on applying the first voltage to the first pillar; and A second voltage is applied to a second pillar of the plurality of second pillars included in the second pillar tile using the decoding circuit system, the second pillar being coupled to a second memory cell of the plurality of second memory cells, wherein the second memory cell is operable to be accessed based at least in part on applying the second voltage to the second pillar.

9. The apparatus of claim 8, wherein the plurality of first pillars comprises a plurality of first pillar columns and a plurality of first pillar rows, and wherein the plurality of second pillars comprises a plurality of second pillar columns and a plurality of second pillar rows.

10. The apparatus of claim 9, wherein the decoding circuitry is further operable to: A corresponding first pillar column of the plurality of first pillar columns in the first pillar tile and a corresponding second pillar column of the plurality of second pillar columns in the second pillar tile are activated, wherein the first pillar tile and the second pillar tile share a pillar column decoder coupled to the decoding circuit system.

11. The apparatus of claim 9, wherein the decoding circuitry is further operable to: Activate a corresponding first pillar row of the plurality of first pillar rows in the first pillar tile and a corresponding second pillar row of the plurality of second pillar rows in the second pillar tile, wherein the first pillar tile and the second pillar tile share a pillar row decoder coupled to the decoding circuit system.

12. The apparatus of claim 8 , wherein the decoding circuitry is positioned below the plurality of first memory cells and the plurality of second memory cells, wherein the decoding circuitry is aligned with the first pillar slice and the second pillar slice, and wherein the decoding circuitry is shared between the first pillar slice and the second pillar slice.

13. The apparatus of claim 8, wherein the decoding circuitry comprises a set of pillar line drivers, and wherein the set of pillar line drivers comprises a number of pillar column drivers and a number of pillar row drivers.

14. The apparatus of claim 13, wherein the number of pillar column drivers is equal to half the number of pillar row drivers, and wherein the number of pillar row drivers is equal to half the number of pillar column drivers, or both.

15. A device comprising: a plurality of first pillar tiles, each first pillar tile comprising a plurality of first pillars, each corresponding pillar in the plurality of first pillars being coupled to one or more corresponding memory cells in the plurality of first memory cells; a plurality of second pillar tiles, each second pillar tile comprising a plurality of second pillars, each corresponding pillar in the plurality of second pillars being coupled to one or more corresponding second memory cells in the plurality of second memory cells; and A decoding circuit system is associated with each first pillar tile and each second pillar tile, and is operable to activate one or more of the plurality of first pillars included in each first pillar tile and one or more of the plurality of second pillars included in each second pillar tile.

16. The apparatus of claim 15, wherein the plurality of first struts comprises a plurality of first strut columns and a plurality of first strut rows, and wherein the second plurality of struts comprises a plurality of second strut columns and a plurality of second strut rows.

17. The apparatus of claim 16, wherein the decoding circuitry is further operable to: A corresponding first pillar column of the plurality of first pillar columns in each first pillar tile and a corresponding second pillar column of the plurality of second pillar columns in each second pillar tile are activated, wherein each first pillar tile and each second pillar tile share a pillar column decoder coupled to the decoding circuit system.

18. The apparatus of claim 16, wherein the decoding circuitry is further operable to: A corresponding first pillar row of the plurality of first pillar rows in each first pillar tile and a corresponding second pillar row of the plurality of second pillar rows in each second pillar tile are activated, wherein each first pillar tile and each second pillar tile share a pillar row decoder coupled to the decoding circuit system.

19. An apparatus according to claim 15, wherein the decoding circuit system is positioned below the plurality of first memory cells and the plurality of second memory cells, wherein the decoding circuit system is aligned with each first pillar tile and each second pillar tile, and wherein the decoding circuit system is shared between each first pillar tile and each second pillar tile.

20. The apparatus of claim 15, wherein the decoding circuitry comprises a set of pillar line drivers, and wherein the set of pillar line drivers comprises a number of pillar column drivers and a number of pillar row drivers.

21. An apparatus comprising: A first pillar tile includes a plurality of first pillars, each first pillar being coupled to one or more corresponding memory cells of the plurality of first memory cells; word line decoding circuitry aligned with edges of the first pillar tile and a second pillar tile adjacent to the first pillar tile, wherein the word line decoding circuitry is shared between the first pillar tile and the second pillar tile, and wherein the word line decoding circuitry is operable to activate one or more first word line plates associated with the first pillar tile and one or more second word line plates associated with the second pillar tile; and Pillar decoding circuitry operable to activate one or more of a plurality of pillars included in the first pillar tile, the pillar decoding circuitry comprising a first portion oriented in a first direction and a second portion oriented in a second direction different from the first direction.

22. The apparatus of claim 21, wherein: the first portion of the pillar decoding circuitry comprising two subsets of pillar decoding circuitry, each of the two subsets being aligned with an opposing edge of the first pillar tile; and The second portion of the pillar decoding circuitry includes two subsets of pillar decoding circuitry, each of the two subsets aligned in the second direction and offset from each other in the first direction.

23. The apparatus of claim 22, wherein the pillar decoding circuitry is positioned below the plurality of first memory cells.

24. The apparatus of claim 21, wherein: the first portion of the pillar decoding circuitry comprising two subsets of pillar decoding circuitry, each of the two subsets being aligned with opposite edges of the first pillar tile in the first direction, wherein the first portion of the pillar decoding circuitry is shared between the first pillar tile and the second pillar tile; and The second portion of the pillar decoding circuit system includes two subsets of the pillar decoding circuit system, each of the two subsets is aligned with an opposite edge of the first pillar tile in the second direction, wherein the second portion of the pillar decoding circuit system is shared between the first pillar tile and a third pillar tile adjacent to the first pillar tile.

25. The apparatus of claim 24, wherein the pillar decoding circuitry is positioned below the plurality of first memory cells and below a plurality of second memory cells coupled to a plurality of second pillars in the second pillar tile.

26. The apparatus of claim 21, wherein the word line decoding circuitry is positioned below the plurality of first memory cells and below a plurality of second memory cells coupled to a plurality of second pillars in the second pillar tile.

27. An apparatus according to claim 26, wherein a first area occupied by the word line decoding circuit system below the plurality of first memory cells is based at least in part on the number of first word line plates associated with the first pillar block, and wherein a second area occupied by the word line decoding circuit system below the plurality of second memory cells is based at least in part on the number of second word line plates associated with the second pillar block.

28. The apparatus of claim 21, wherein a first area occupied by the pillar decoding circuitry of the first pillar tile is larger than a second area occupied by the word line decoding circuitry of the first pillar tile.

29. An apparatus according to claim 21, wherein the pillar decoding circuit system includes a set of pillar line drivers, and wherein the first portion of the pillar decoding circuit system includes a plurality of pillar column drivers and the second portion of the pillar decoding circuit system includes a plurality of pillar row drivers.

30. An apparatus according to claim 21, wherein the word line decoding circuit system includes a plurality of word line decoders, each of the plurality of word line decoders including a corresponding set of word line drivers, wherein each word line driver is operable to activate a corresponding word line plate of the one or more first word line plates associated with the first pillar block, a corresponding word line plate of the one or more second word line plates associated with the second pillar block, or both.

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