Calibration method of nonlinear analog-to-digital conversion circuit and reference voltage generation circuit thereof

Abstract

The invention discloses a calibration method of a nonlinear analog-to-digital conversion circuit and an implementation method of a reference voltage generation circuit of the nonlinear analog-to-digital conversion circuit. The implementation method of the reference voltage generation circuit comprises the following steps: providing at least two calibration rows, wherein each calibration row comprises resistor or capacitor modules which are connected in series; providing a voltage source and a current source outside the image sensor pixel array; the series-connected resistor or capacitor modules corresponding to the at least two calibration rows are connected in series and combined to form a group of variable reference voltages, and the number of the reference voltages is increased, so that the error of the reference voltage generation circuit is reduced, and the calibration precision is improved.

Description

Technical Field

[0001] The invention relates to a calibration method for a nonlinear analog-to-digital conversion circuit and a reference voltage generating circuit thereof. Background Art

[0002] An analog-to-digital converter, also known as an A / D converter, or ADC for short, usually refers to an electronic component that converts analog signals into digital signals. It is currently widely used in industry, medical care, communications and other fields to meet the needs of various data acquisition applications.

[0003] As pixel arrays in image sensors continue to expand in size, traditional chip-level analog-to-digital converters (ADCs) can no longer meet high frame rate requirements. Therefore, high-frame-rate image sensors typically employ column-level ADCs. Column-level ADCs achieve high precision with minimal footprint and power consumption, making them widely used in high-pixel, high-frame-rate image sensors.

[0004] The analog-to-digital converter (ADC) mainly consists of a comparator and a storage unit or a counting unit, and requires a ramp signal (VRAMP) as the comparison level of the comparator. The accuracy of the ramp signal directly affects the output accuracy of the ADC. In addition, the application scenarios of high-frame-rate image sensors require corresponding high-speed ramp signals. Therefore, how to generate high-speed and high-precision ramp signals is a very important research topic.

[0005] Traditionally, the ramp signal is linear, and achieving the same effective accuracy requires a longer time or a faster speed, or at the same speed and time, the effective accuracy that can be achieved is lower.

[0006] Photon shot noise exists in all image sensors and increases with input signal. However, the quantization noise of the ADC does not vary with the input signal. Therefore, when the signal is large, photon shot noise becomes dominant, causing the analog-to-digital converter to exceed the required performance, potentially reducing accuracy. This manifests itself in a ramp signal: the slope for large signals can be greater than that for small signals. This can shorten the ADC conversion time and increase the frame rate for the same effective output accuracy, or improve the ADC's effective output accuracy for the same frame rate. Therefore, nonlinear ADCs that utilize multi-slope nonlinear ramp signals are better suited for high-speed, high-precision image sensor applications.

[0007] However, if a nonlinear ADC with a multi-slope nonlinear ramp signal is used, a calibration step must be added to convert the nonlinear output into a linear output before the digital module can perform subsequent image processing. If the nonlinear ADC is calibrated using a posteriori methods, even if the calibration parameters are calibrated for each chip, it will not be able to cover all complex application environments. This may lead to various image quality issues such as layering and color cast, affecting the stability and accuracy of the nonlinear ADC.

[0008] Typically, the resistors that generate the reference voltage group can be parasitic resistances of metal lines. Arranged in a line, these metal parasitic resistances can produce a linearly varying reference voltage. The number of reference voltages directly impacts calibration accuracy. For example, the smaller number of columns in a low-pixel sensor can't provide enough reference voltages within a single row, leading to larger calibration errors and reduced reliability. Summary of the Invention

[0009] Based on the above problems, the present invention proposes a method for implementing a reference voltage generation circuit for calibrating a nonlinear analog-to-digital conversion circuit, including: providing at least two calibration rows, each calibration row including resistor or capacitor modules connected in series; providing a voltage source and a current source located outside the image sensor pixel array; and connecting the resistor or capacitor modules connected in series corresponding to the at least two calibration rows in series to form a set of varying reference voltages, thereby increasing the number of the reference voltages to reduce the error of the reference voltage generation circuit and improve calibration accuracy.

[0010] Optionally, the first and second ends of the series-connected resistor or capacitor modules corresponding to the at least two calibration rows are respectively connected to one end of the voltage source and one end of the current source; the other end of the current source is grounded.

[0011] Optionally, each calibration row includes a first metal line and a second metal line; the parasitic resistance of the first metal line and the second metal line are the same, so that the output load of the voltage source is consistent.

[0012] Optionally, each of the calibration rows further includes a plurality of calibration row pixel units; each calibration row pixel unit includes a source follower transistor and a row selection transistor; the gate of the source follower transistor is connected to the first metal line at equal intervals so that the different reference voltages are voltages that vary at equal intervals; the gate of each row selection transistor in the same row is connected to the same row control line.

[0013] Optionally, the at least two calibration rows include a first calibration row and a second calibration row; the first end of the first metal wire of the first calibration row is connected to one end of the voltage source; the second end of the first metal wire of the first calibration row is connected to the second end on the same side of the first metal wire of the second calibration row; the first end of the first metal wire of the second calibration row is connected to one end of the current source through a first switch; the first end of the second metal wire of the first calibration row is connected to one end of the voltage source; the second end of the second metal wire of the first calibration row is connected to the second end on the same side of the second metal wire of the second calibration row; the first end of the second metal wire of the second calibration row is connected to one end of the current source through a second switch; when the first switch is disconnected, the reference voltage generating circuit provides the same reference voltage; when the first switch is closed, the reference voltage generating circuit provides different reference voltages.

[0014] Optionally, the at least two calibration rows include a first calibration row, a second calibration row and a third calibration row; the first end of the first metal wire of the first calibration row is connected to one end of the voltage source; the second end of the first metal wire of the first calibration row is connected to the second end on the same side of the first metal wire of the second calibration row; the first end of the first metal wire of the second calibration row is connected to the first end on the same side of the first metal wire of the third calibration row; the second end of the first metal wire of the third calibration row is connected to one end of the current source through a first switch; the first end of the second metal wire of the first calibration row is connected to one end of the voltage source; the second end of the second metal wire of the first calibration row is connected to the second end on the same side of the second metal wire of the second calibration row; the first end of the second metal wire of the second calibration row is connected to the first end on the same side of the second metal wire of the third calibration row; the second end of the second metal wire of the third calibration row is connected to one end of the current source through a second switch; when the first switch is disconnected, the reference voltage generating circuit provides the same reference voltage; when the first switch is closed, the reference voltage generating circuit provides different reference voltages.

[0015] Optionally, the at least two calibration lines constitute a calibration unit; the reference voltage generating circuit includes at least two calibration units; multiple calibration units are connected to the same current source; and multiple calibration units are connected to the same voltage source.

[0016] The present invention also proposes a calibration method for a nonlinear analog-to-digital conversion circuit, comprising: providing a nonlinear analog-to-digital conversion circuit; providing the above-mentioned reference voltage generating circuit; before or during the normal operation of the nonlinear analog-to-digital conversion circuit, using the nonlinear analog-to-digital conversion circuit to test multiple reference voltages generated by the reference voltage generating circuit to obtain calibration parameters of the nonlinear analog-to-digital conversion circuit, which are used to calibrate the output value of the nonlinear analog-to-digital conversion circuit when it is operating normally, so as to improve the stability and accuracy of the nonlinear analog-to-digital conversion circuit.

[0017] Furthermore, each calibration row in the calibration unit is selected in sequence to combine and form a set of varying reference voltages; when one of the calibration rows is selected, the voltage source and the current source provide the same reference voltage through the first metal line and the second metal line connected in series to simulate the reference signal voltage output by the image sensor pixel array for analog-to-digital conversion, and provide different reference voltages to simulate the image signal voltage output by the image sensor pixel array for analog-to-digital conversion, thereby forming a nonlinear output curve using the calibration signal voltage output by the calibration row and the output digital code after analog-to-digital conversion, so as to obtain calibration parameters of the nonlinear analog-to-digital conversion circuit based on the nonlinear output curve.

[0018] Further, when one of the calibration rows is selected, the second switch is turned on and the first switch is turned off, and the voltage source generates a current that flows into the current source through the second metal line of the calibration row, the second metal line of the calibration row, and the second switch, thereby forming the same reference voltage to simulate the reference signal voltage output by the image sensor pixel array for analog-to-digital conversion; the second switch is turned off and the first switch is turned on, and the voltage source generates a current that flows into the current source through the first metal line of the calibration row, the first metal line of the calibration row, and the first switch, thereby forming a reference voltage that changes at equal intervals to simulate the image signal voltage output by the image sensor pixel array for analog-to-digital conversion.

[0019] Compared with the prior art, the reference voltage generating circuit proposed in the present invention includes at least two calibration rows, thereby being able to generate more calibration voltages within the same reference voltage range, thereby improving calibration accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0021] Figure 1 The figure is a schematic structural diagram of an image sensor using the calibration method of the nonlinear analog-to-digital conversion circuit of the present invention.

[0022] Figure 2 Schematic diagram of the circuit of a conventional row pixel unit.

[0023] Figure 3 A schematic diagram of a reference voltage generating circuit.

[0024] Figure 4 A schematic diagram of an embodiment of a voltage source.

[0025] Figure 5 Schematic diagram of an embodiment of a current source.

[0026] Figure 6 FIG. 1 is a schematic diagram of a reference voltage generating circuit according to a first embodiment of the present invention.

[0027] Figure 7 FIG. 1 is a timing diagram of control signals according to the first embodiment of the present invention.

[0028] Figure 8 FIG. 1 is a schematic diagram of a reference voltage generating circuit according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0029] In the following detailed description of preferred embodiments, reference will be made to the accompanying drawings, which form a part of the present invention. The accompanying drawings illustrate, by way of example, specific embodiments that can implement the present invention. The illustrative embodiments are not intended to be exhaustive of all embodiments according to the present invention. It will be understood that other embodiments may be utilized, and structural or logical modifications may be made, without departing from the scope of the present invention. Therefore, the following detailed description is not restrictive, and the scope of the present invention is defined by the appended claims.

[0030] Figure 1 This is a block diagram of an image sensor employing the nonlinear analog-to-digital converter circuit calibration method of the present invention. In addition to a pixel array 101, a row control module 102, a column processing array 103, a voltage and current generating circuit 104, a control signal generating circuit 105, and a digital processing module 106, the image sensor also includes a reference voltage generating circuit 107 for nonlinear ADC calibration.

[0031] The pixel array 101 includes a plurality of regular row pixel units. The circuit diagram of a single pixel unit (the structure is not limited thereto, it is only for the convenience of explanation) is as follows: Figure 2 As shown, the pixel unit has a conventional pixel unit structure, specifically including a reset transistor MRST, a transfer transistor MTX <0> to MTX <m>(where M is an integer greater than or equal to 0), and the photosensitive unit PD corresponding to the transmission transistor one by one <0> To PD <m>, source follower transistor MSF, and row selection transistor MRSEL.

[0032] The voltage and current generation circuit 104 is used to provide voltage and current to the row control module 102 and the column processing array 103. It also includes a ramp signal generation circuit (not shown). Compared to traditional ramp signal generation circuits, to improve the frame rate and accuracy of the image sensor, the ramp signal output by this ramp signal generation circuit is nonlinear. Therefore, the ADC (not shown) in the column processing array 103 can be understood as a nonlinear analog-to-digital conversion circuit.

[0033] The structure of the reference voltage generating circuit 107 is not limited; any circuit capable of generating multiple reference voltage signals is sufficient. The output range of these reference voltage signals can reach the full scale of the nonlinear ADC (i.e., the signal output range of the image sensor pixel array). Before or during normal operation of the nonlinear ADC, these reference voltages are fed to the nonlinear ADC in the column processing array 103 for analog-to-digital conversion, thereby obtaining an ADC conversion curve of linear input and nonlinear output. Based on this conversion curve, the digital processing module 106 calculates calibration parameters for the nonlinear ADC, which are used to calibrate the ADC output during normal operation of the image sensor.

[0034] The calibration method of the nonlinear analog-to-digital conversion circuit of the present invention can operate periodically as needed, and update in real time the changes in the calibration parameters of the nonlinear ADC caused by changes in the working environment of the image sensor or changes in parameter settings, thereby improving the stability and accuracy of the nonlinear analog-to-digital conversion circuit, thereby obtaining excellent image sensor performance.

[0035] The structure and working principle of the reference voltage generating circuit 107 are described in detail below with reference to specific embodiments.

[0036] Figure 3 This is an embodiment of a reference voltage generating circuit that can be used in the nonlinear analog-to-digital conversion circuit calibration method of the present invention. The reference voltage generating circuit includes a calibration row 109, as well as a voltage source 108 and a current source 110. The voltage source 108 and the current source 110 are located outside the pixel array 101. The calibration row 109 can be located inside or outside the pixel array 101, and can be one or more rows, and can be specifically configured as needed. As an example, the dotted box 109 shows the circuit structure of a standard row, which includes a series resistor module 113. Those skilled in the art will understand that the resistor module can also be replaced by a capacitor module. The first end of the series resistor module 113 is connected to the voltage source 108, and the second end is connected to the current source 110.

[0037] When a calibration row 109 is selected, the voltage source 108 and the current source 110 provide the same reference voltage through the series-connected resistor module 113 to simulate the reference signal voltage output by the image sensor pixel array for analog-to-digital conversion, and provide different reference voltages to simulate the image signal voltage output by the image sensor pixel array for analog-to-digital conversion, thereby forming a nonlinear output curve using the calibration signal voltage output by the calibration row and the output digital code after analog-to-digital conversion, so as to obtain calibration parameters of the nonlinear analog-to-digital conversion circuit based on the nonlinear output curve.

[0038] Specifically, the series resistance module 113 includes a first metal wire 111 and a second metal wire 112 connected in parallel. The first end of the first metal wire 111 ( Figure 3 The left end of the middle terminal is connected to the output Vcal of the voltage source 108, and the second end ( Figure 3 The middle right end) is connected to the current source 110 through the first switch sw1. Similarly, the first end of the second metal line 112 ( Figure 3 The left end of the middle terminal is connected to the output Vcal of the voltage source 108, and the second end ( Figure 3 The first metal wire 111 and the second metal wire 112 are connected to the current source 110 through the second switch sw2. The first switch sw1 is controlled by the signal sel1. The second switch sw2 is controlled by the signal sel2. There are many resistors R connected in series on the first metal wire 111 and the second metal wire 112, which can be the resistance of the metal wire itself or an external resistor. Optionally, the resistance value of each R is equal, which is equivalent to dividing the resistance on the metal wire into (N-1) equal parts, where N is the number of columns of pixel units in the image sensor. When R is the resistance of the metal wire itself, the resistance value of a resistor R corresponds to the resistance value of the metal wire corresponding to the width of a pixel unit. Therefore, the current flowing through the metal wire resistance can be used to achieve a uniform voltage change on the metal wire resistance, and then voltage output points are set at equal intervals on the metal wire and provided to the nonlinear ADC for quantization to obtain the calibration parameters of the nonlinear ADC, which are used to calibrate the output value of the nonlinear ADC of the normal pixel unit.

[0039] Each calibration row 109 further includes a plurality of calibration row pixel units 114, wherein each calibration row pixel unit 114 includes a source follower transistor MSF and a row select transistor MRSEL. Figure 2 The calibration row pixel unit 114 only retains the source follower transistor MSF and the row selection transistor MRSEL.

[0040] The number of columns of regular row pixel units in the pixel array 101 is the same as the number of columns of calibration row pixel units in the reference voltage generating circuit 107. The outputs corresponding to each column of the pixel array 101 and the reference voltage generating circuit 107 are connected together, and are pxda <0> To PXDA <n-1>, N is the number of columns of pixel units in the image sensor.

[0041] The gate of each source follower transistor MSF in the same row is connected to the first metal line 111. Optionally, the gates of the source follower transistors MSF are connected to the first metal line 111 at equal intervals to equally divide the resistance of the first metal line 111. The gate of each row select transistor MRSEL is connected to the same row control line, and the control signal RSEL comes from Figure 1 The reference voltage generation circuit 107 is similar to the conventional pixel array 101 except for the input signal source. The controllable gate voltage of the source-follower transistor in the reference voltage generation circuit 107 is used to simulate the entire signal output range of a real pixel photosensitive unit.

[0042] The voltage source 108 can be a simple voltage source or a complex voltage source generating circuit.

[0043] Figure 4 This is only a schematic diagram of an embodiment of the voltage source generating circuit. The working principle is: the current of the current source flows through the variable resistor R2 to generate the output voltage Vr, the sampling circuit samples the voltage Vr to the capacitor C to generate the voltage Vcs, and then passes through the unity gain negative feedback circuit to obtain the output voltage Vcal. Figure 4 The circuit in the dashed box is turned off, and the pull-up transistor swpu is turned on by the control signal pu, pulling the output voltage Vcal to the power supply voltage. The control signal samp is used to control the transistor swsamp. This circuit is relatively common and will not be described in detail.

[0044] The current source 110 may be a simple current source or a complex current source generating circuit.

[0045] Figure 5 This is a schematic diagram of only one embodiment of a current source generation circuit. Its input current, Iin, originates from a nonlinear ramp signal generation circuit and is related to the current source unit within the nonlinear ramp signal generation circuit. This allows the reference voltage generation circuit to follow changes in real time, enabling better matching of the nonlinear ADC's range. Transistor M1 is not adjustable. Transistor M2 is adjustable and can be used to match the analog gain achieved using the output resistance of the nonlinear ramp signal generation circuit, with variations in the amplitude of the nonlinear ramp signal output voltage.

[0046] Figure 3 The reference voltage generation circuit for an inline nonlinear analog-to-digital conversion circuit includes a calibration row 109. This circuit uses the nonlinear analog-to-digital conversion circuit to test multiple reference voltages generated by the reference voltage generation circuit to obtain calibration parameters for the nonlinear analog-to-digital conversion circuit, which are used to calibrate the output value of the nonlinear analog-to-digital conversion circuit during normal operation. Generally, the resistors that generate the reference voltage group can be parasitic resistances of metal wires. The inline arrangement of metal parasitic resistances can generate linearly varying reference voltages. The number of reference voltages directly affects calibration accuracy. For example, the smaller number of columns in a low-pixel sensor cannot provide a sufficient number of reference voltages within a row, resulting in larger calibration errors and reduced reliability.

[0047] To obtain a greater number of calibration voltages within the same reference voltage range, the present invention proposes an improved method for implementing a reference voltage generation circuit for calibrating a nonlinear analog-to-digital conversion circuit, comprising: providing at least two calibration rows, each calibration row including resistor or capacitor modules connected in series; providing a voltage source and a current source located outside the image sensor pixel array; and combining the resistor or capacitor modules connected in series corresponding to the at least two calibration rows to form a set of varying reference voltages, thereby increasing the number of the reference voltages and improving the stability and accuracy of the reference voltage generation circuit.

[0048] Specifically, the present invention Figure 3 The circuit structure is improved and two embodiments are provided.

[0049] Example 1, as Figure 6 As shown, in Figure 3 On the basis of the reference voltage generating circuit of the in-line nonlinear analog-to-digital conversion circuit, the metal line pair corresponding to the first row reference voltage (i.e., the first metal line and the second metal line) is connected to the metal line pair corresponding to the second row reference voltage, that is, the in-line parasitic metal line is changed into a C-shaped parasitic metal line, and the pixel signal lines (pxda) corresponding to the same position in the vertical direction of the two rows are connected together.

[0050] like Figure 6 As shown, the reference voltage generation circuit includes two calibration rows 109, a voltage source 108, and a current source 110. The voltage source 108 and the current source 110 are located outside the pixel array 101, and are connected in series with a resistor module 113. The calibration row 109 can be located inside or outside the pixel array 101.

[0051] The first calibration row 109 (e.g. Figure 6 The first end of the first metal line 111 of the first calibration row 109 is connected to one end of the voltage source 108; the second end of the first metal line 111 of the first calibration row 109 is connected to the second calibration row 109 (such as Figure 6 The first end of the first metal wire 111 of the second calibration row 109 is connected to one end of the current source 110 through the first switch sw1.

[0052] The first end of the second metal wire 112 of the first calibration row 109 is connected to one end of the voltage source 109; the second end of the second metal wire 112 of the first calibration row 109 is connected to the second end of the second metal wire 112 of the second calibration row 109 on the same side; the first end of the second metal wire 112 of the second calibration row 109 is connected to one end of the current source 110 via the second switch sw2.

[0053] Each of the calibration rows 109 further includes a plurality of calibration row pixel units 114 , wherein each calibration row pixel unit 114 includes a source follower transistor MSF and a row select transistor MRSEL.

[0054] The gate of each source follower transistor MSF in the same row is connected to the first metal line 111 .

[0055] Optionally, the gates of the source follower transistors MSF are connected to the first metal lines 111 at equal intervals to equally divide the resistance of the first metal lines 111 .

[0056] The gate of each row selection transistor MRSEL is connected to the same row control line, and the control signal RSEL comes from Figure 1 The row control module 102 in.

[0057] The reference voltage generation circuit 107 is similar to the conventional pixel array 101 except for the different input signal sources. The controllable gate voltage of the source-follower transistor in the reference voltage generation circuit 107 is used to simulate the entire signal output range of a real pixel photosensitive unit.

[0058] In this embodiment, two calibration rows 109 constitute a calibration unit; the reference voltage generating circuit includes at least two calibration units; multiple calibration units can be connected to the same current source 110; and multiple calibration units can be connected to the same voltage source 108.

[0059] During actual circuit operation, each calibration row in the calibration unit can be selected in sequence to combine and form a set of varying reference voltages. When one of the calibration rows is selected, the voltage source and the current source provide the same reference voltage through the first and second metal lines connected in series to simulate the reference signal voltage output by the image sensor pixel array for analog-to-digital conversion, and provide different reference voltages to simulate the image signal voltage output by the image sensor pixel array for analog-to-digital conversion. A nonlinear output curve is thereby formed using the calibration signal voltage output by the calibration row and the output digital code after analog-to-digital conversion, so that calibration parameters of the nonlinear analog-to-digital conversion circuit can be obtained based on the nonlinear output curve.

[0060] When one of the calibration rows is selected, the second switch is turned on and the first switch is turned off, and the voltage source generates a current that flows through the second metal line of the calibration row and the second metal line of the calibration row and the second switch to the current source, thereby forming the same reference voltage to simulate the reference signal voltage output by the image sensor pixel array for analog-to-digital conversion; when the second switch is turned off and the first switch is turned on, the voltage source generates a current that flows through the first metal line of the calibration row and the first metal line of the calibration row and the first switch to the current source, thereby forming a reference voltage that changes at equal intervals to simulate the image signal voltage output by the image sensor pixel array for analog-to-digital conversion.

[0061] Specifically, refer to Figure 6 The C-shaped structure shown in the figure has a control timing diagram as shown in the figure. Figure 7 As shown, according to the Row_addr address, RSEL1 is first set high to select the first calibration row (such as calibration row 0). In the quantized pixel signal voltage stage (signal stage), the second switch sw2 is closed and the first switch sw1 is turned off. At this time, the gate voltage of all SF tubes is Vcal voltage, that is: V_SF <0> =V_SF <1> =V_SF <2> =⋯…=V_SF <n-1>= Vcal. These voltages are quantized by the analog-to-digital converters. During the reference signal voltage quantization phase (reference phase), the first switch sw1 is closed and the second switch sw2 is closed. At this time, the current of Vcal flows into the current source 110 through the parasitic resistance of the first metal line, generating N reference voltages at the gate terminals of the first calibration row SF transistors, satisfying the following: V_SF <0> =Vcal V_SF <1> =Vcal-I*R V_SF <2> =Vcal-2*I*R … … V_SF <n-1>=Vcal-(N-1)*I*R The voltage is quantized by the analog-to-digital converter. After the first calibration row is completed, RSEL1 is set to 0. Then RSEL2 is set to 1 to select the second calibration row. In the quantized pixel signal voltage stage (signal stage), the second switch sw2 is closed and the first switch sw1 is turned off. At this time, the gate voltage of all SF tubes is Vcal voltage, that is: V_SF <n>=V_SF<N+1> =V_SF<N+2> =⋯…=V_SF<2N-1>=Vcal. These voltages are quantized by the analog-to-digital converter. During the quantized pixel signal voltage phase (signal phase), the first switch sw1 is closed and the second switch sw2 is closed. At this time, the current of Vcal flows through the parasitic resistance of the first metal line 111 into the current source 110, generating N reference voltages at the gate terminals of the SF transistors in the second calibration row (e.g., calibration row 1), satisfying the following: V_SF <n>=Vcal-(N-1)*I*RI*r V_SF<N+1> =Vcal-N*I*RI*r V_SF<N+2> =Vcal-(N+1)*I*RI*r … … V_SF<2N-1>=Vcal-(2N-1)*I*RI*r Therefore, the V_SF<2N-1:0> obtained by the C-type is kept consistent with the V_SF of the I-type. <n-1:0>Under the premise of the same reference voltage range, this method can double the reference voltage data volume within the two-line operation time, thereby improving the calibration accuracy.

[0062] Similarly, for Example 2, Figure 8 As shown, if one more calibration row is added, the C-shaped structure can be transformed into an S-shaped structure. The specific connection relationship is as follows Figure 8 The S-shaped V_SF<3N-1:0> is kept consistent with the I-shaped V_SF <n-1:0>Under the premise of the same reference voltage range, this method can triple the reference voltage data volume within the three-line operation time, thereby improving the calibration accuracy.

[0063] It should be noted that the present invention is not only applicable to the calibration of nonlinear analog-to-digital circuits in low-pixel image sensors, and the wiring method is not limited to the inline, C-shaped, and S-shaped structures mentioned herein.

[0064] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and non-restrictive in all respects. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude plural references. Multiple elements recited in a device claim may also be implemented by a single element. Terms such as first and second are used to indicate names and do not imply any particular order. < / n> < / n> < / m> < / m>

Claims

1. A method for implementing a reference voltage generating circuit for calibrating a nonlinear analog-to-digital conversion circuit, characterized in that: include: providing at least two calibration rows, each calibration row comprising resistor or capacitor modules connected in series; Providing a voltage source and a current source located outside the image sensor pixel array; By connecting the series resistor or capacitor modules corresponding to the at least two calibration rows in series to form a set of variable reference voltages, the number of the reference voltages is increased to reduce the error of the reference voltage generating circuit and improve calibration accuracy.

2. The method according to claim 1, wherein The first and second ends of the series-connected resistor or capacitor modules corresponding to the at least two calibration rows are respectively connected to one end of the voltage source and one end of the current source; the other end of the current source is grounded.

3. The method according to claim 2, wherein Each calibration row includes a first metal line and a second metal line; the parasitic resistances of the first metal line and the second metal line are the same, so that the output load of the voltage source is consistent.

4. The method according to claim 3, wherein Each of the calibration rows further comprises a plurality of calibration row pixel units; Each calibration row pixel unit includes a source follower transistor and a row selection transistor; The gates of the source follower transistors are connected to the first metal line at equal intervals, so that the different reference voltages are voltages that vary at equal intervals; The gate of each row selection transistor in the same row is connected to the same row control line.

5. The method according to claim 4, wherein The at least two calibration rows include a first calibration row and a second calibration row; The first end of the first metal line of the first calibration row is connected to one end of the voltage source; the second end of the first metal line of the first calibration row is connected to the second end of the first metal line of the second calibration row on the same side; A first end of the first metal line of the second calibration row is connected to one end of the current source through a first switch; The first end of the second metal line of the first calibration row is connected to one end of the voltage source; the second end of the second metal line of the first calibration row is connected to the second end of the second metal line of the second calibration row on the same side; A first end of the second metal line of the second calibration row is connected to one end of the current source through a second switch; When the first switch is disconnected, the reference voltage generating circuit provides the same reference voltage; When the first switch is closed, the reference voltage generating circuit provides different reference voltages.

6. The method according to claim 4, wherein The at least two calibration rows include a first calibration row, a second calibration row, and a third calibration row; The first end of the first metal line of the first calibration row is connected to one end of the voltage source; the second end of the first metal line of the first calibration row is connected to the second end of the first metal line of the second calibration row on the same side; The first end of the first metal line of the second calibration row is connected to the first end of the first metal line of the third calibration row on the same side; The second end of the first metal line of the third calibration row is connected to one end of the current source through the first switch; The first end of the second metal line of the first calibration row is connected to one end of the voltage source; the second end of the second metal line of the first calibration row is connected to the second end of the second metal line of the second calibration row on the same side; The first end of the second metal line of the second calibration row is connected to the first end of the second metal line of the third calibration row on the same side; A second end of the second metal line of the third calibration row is connected to one end of the current source through a second switch; When the first switch is disconnected, the reference voltage generating circuit provides the same reference voltage; When the first switch is closed, the reference voltage generating circuit provides different reference voltages.

7. The method according to claim 5 or 6, wherein: The at least two calibration lines constitute a calibration unit; the reference voltage generating circuit comprises at least two of the calibration units; and a plurality of the calibration units are connected to the same current source; The plurality of calibration units are connected to the same voltage source.

8. A calibration method for a nonlinear analog-to-digital conversion circuit, characterized in that: include: Providing a nonlinear analog-to-digital conversion circuit; Providing the reference voltage generating circuit as claimed in claim 7; Before or during the normal operation of the nonlinear analog-to-digital conversion circuit, the nonlinear analog-to-digital conversion circuit is used to test multiple reference voltages generated by the reference voltage generating circuit to obtain calibration parameters of the nonlinear analog-to-digital conversion circuit, which are used to calibrate the output value of the nonlinear analog-to-digital conversion circuit during normal operation, so as to improve the stability and accuracy of the nonlinear analog-to-digital conversion circuit.

9. The calibration method according to claim 8, wherein: selecting each calibration row in the calibration unit in sequence to combine and form a set of varying reference voltages; When one of the calibration rows is selected, the voltage source and the current source provide the same reference voltage through the first metal line and the second metal line connected in series to simulate the reference signal voltage output by the image sensor pixel array for analog-to-digital conversion, and provide different reference voltages to simulate the image signal voltage output by the image sensor pixel array for analog-to-digital conversion, thereby forming a nonlinear output curve using the calibration signal voltage output by the calibration row and the output digital code after analog-to-digital conversion, so as to obtain calibration parameters of the nonlinear analog-to-digital conversion circuit based on the nonlinear output curve.

10. The calibration method according to claim 9, wherein: When one of the calibration rows is selected, The second switch is turned on, the first switch is turned off, and the voltage source generates a current that flows through the second metal line of the calibration row and the second metal line of the calibration row and the second switch into the current source, thereby forming a same reference voltage to simulate the reference signal voltage output by the pixel array of the image sensor for analog-to-digital conversion; The second switch is closed and the first switch is opened, and the voltage source generates a current that flows into the current source through the first metal line of the calibration row, the first metal line of the calibration row, and the first switch, thereby forming a reference voltage that changes at equal intervals to simulate the image signal voltage output by the image sensor pixel array for analog-to-digital conversion.

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