Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises a semiconductor layer comprising a main body part, a first extension part and a second extension part which are connected with each other, the first extension part and the second extension part extend in the transverse direction parallel to a substrate, and the main body part extends in the longitudinal direction perpendicular to the substrate; the gate layer extends in the longitudinal direction, and the main body part is in a ring shape extending in the longitudinal direction, surrounds the side wall of the gate layer and is insulated from the gate layer; the first electrode and the second electrode are distributed at intervals in the longitudinal direction, the first electrode is close to the substrate, and the second electrode surrounds the outer side wall of the main body part; the isolation layer is located between the first electrode and the second electrode and surrounds the outer side wall of the main body part; the first extension part extends to an area between the isolation layer and the first electrode and is connected with the first electrode; and the second extension part extends to a region between the isolation layer and the second electrode and is connected with the second electrode.

Description

Technical Field

[0001] The present application relates to but is not limited to semiconductor technology, and in particular to a semiconductor device and a method for manufacturing the same, and electronic equipment. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and numbers of devices contained in a single chip are increasing accordingly, so that any slight difference in process production may affect device performance.

[0003] To minimize product costs, people hope to create as many memory cells as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. Summary of the Invention

[0004] The present application provides a semiconductor device, a method for manufacturing the same, and an electronic device.

[0005] In a first aspect, an embodiment of the present application provides a semiconductor device, comprising: a semiconductor layer, comprising a main body, a first extension portion, and a second extension portion connected to each other, the first extension portion and the second extension portion extending in a transverse direction parallel to a substrate, and the main body extending in a longitudinal direction perpendicular to the substrate; a gate layer extending in the longitudinal direction; the main body is a ring extending in the longitudinal direction and surrounding the side wall of the gate layer and insulated from the gate layer; a first electrode and a second electrode spaced apart in the longitudinal direction, the first electrode being close to the substrate and the second electrode surrounding the outer side wall of the main body; an isolation layer located between the first electrode and the second electrode and surrounding the outer side wall of the main body; the first extension portion extending to the area between the isolation layer and the first electrode and connected to the first electrode; the second extension portion extending to the area between the isolation layer and the second electrode and connected to the second electrode.

[0006] In an exemplary embodiment, it includes a stacked structure arranged on the substrate, the stacked structure including a first conductive layer, a first sacrificial layer, the isolation layer, a second sacrificial layer and a second conductive layer arranged in sequence along a direction away from the substrate; the first electrode is located in the first conductive layer, and the second electrode is located in the second conductive layer; the stacked structure includes a first trough body extending along the longitudinal direction, a second trough body and a third trough body extending along the transverse direction and surrounding the outer side wall of the main body; the main body is located in the first trough body; the second trough body is located between the isolation layer and the first conductive layer, the second trough body is connected to the first trough body, the bottom of the second trough body exposes the first sacrificial layer, the first extension portion is located in the second trough body and connected to the main body; the third trough body is located between the isolation layer and the second conductive layer, the third trough body is connected to the first trough body, the bottom of the third trough body exposes the second sacrificial layer, and the second extension portion is located in the third trough body and connected to the main body.

[0007] In an exemplary embodiment, the thickness of the isolation layer is equal to the length of the channel of the semiconductor layer.

[0008] In an exemplary embodiment, the main body, the first extension and the second extension of the semiconductor layer are made of a metal oxide semiconductor material; the metal in the metal oxide semiconductor material is selected from one or more of the following materials: indium, gallium, zinc, tin and aluminum.

[0009] In an exemplary embodiment, the main body portion, the first extension portion, and the second extension portion of the semiconductor layer are an integrated structure.

[0010] In an exemplary embodiment, the material type of at least one of the first extension portion and the second extension portion is the same as the material type of the main body portion; and the oxygen concentration of the first extension portion and the oxygen concentration of the second extension portion are both lower than the oxygen concentration of the main body portion.

[0011] In an exemplary embodiment, the main body and the first extension are independent of each other and in contact with each other, and the main body and the second extension are independent of each other and in contact with each other; the conductivity of the first extension and the conductivity of the second extension are both higher than the conductivity of the main body.

[0012] In an exemplary embodiment, the stacked structure further includes: a first oxygen absorption layer and a second oxygen absorption layer, wherein the first oxygen absorption layer is located between the first conductive layer and the first extension portion, and the second oxygen absorption layer is located between the second extension portion and the second conductive layer.

[0013] In an exemplary embodiment, the main body of the semiconductor layer is cylindrical, including the annular semiconductor layer and a bottom; the first conductive layer includes a portion of an outer wall surrounding the main body and a portion extending from the outer wall to the bottom of the semiconductor layer.

[0014] In an exemplary embodiment, the main body is made of indium gallium zinc oxide, and the first extension and the second extension are made of indium gallium zinc oxide or indium tin oxide.

[0015] In an exemplary embodiment, the first oxygen absorbing layer is a single layer or a laminated structure; the second oxygen absorbing layer is a single layer or a laminated structure.

[0016] In an exemplary embodiment, the first oxygen absorbing layer and the second oxygen absorbing layer are made of titanium or titanium nitride.

[0017] In an exemplary embodiment, the first oxygen absorption layer includes a stack of a first titanium nitride layer and a first metal titanium layer, and the first titanium nitride layer is located on a side close to the first extension portion and contacts the first extension portion; the second oxygen absorption layer includes a stack of a second titanium nitride layer and a second metal titanium layer, and the second titanium nitride layer is located on a side close to the second extension portion and contacts the second extension portion.

[0018] In a second aspect, an embodiment of the present application also provides a method for preparing a semiconductor device, the method comprising: depositing a first conductive layer, a first sacrificial layer, an isolation layer, a second sacrificial layer, and a second conductive layer in sequence on a substrate; forming a hole that at least passes through the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer and exposes the second conductive layer; etching back the first sacrificial layer and the second sacrificial layer on the sidewalls of the hole to form a first lateral groove and a second lateral groove, respectively; depositing a semiconductor layer on the sidewalls of the hole and in the first lateral groove and the second lateral groove; and forming a gate insulating layer and a gate layer covering the semiconductor layer in sequence in the hole.

[0019] In an exemplary embodiment, the forming of a hole that at least penetrates the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer and exposes the second conductive layer includes: penetrating the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer and the first conductive layer in sequence along a longitudinal direction perpendicular to the substrate to form the hole; or penetrating the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer in sequence along a longitudinal direction perpendicular to the substrate, and removing a portion of the first conductive layer to form the hole, wherein the hole extends into the first conductive layer.

[0020] In an exemplary embodiment, a first oxygen-absorbing layer is deposited before depositing the first sacrificial layer; a second oxygen-absorbing layer is deposited after depositing the second sacrificial layer; the formation of a hole that at least penetrates the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer and exposes the second conductive layer includes: forming the hole by sequentially penetrating the second conductive layer, the second oxygen-absorbing layer, the second sacrificial layer, the isolation layer and the first sacrificial layer in the longitudinal direction; the hole exposes the second conductive layer and the first oxygen-absorbing layer.

[0021] In an exemplary embodiment, the first transverse groove exposes the first oxygen absorption layer so that the semiconductor layer extends into the first transverse groove and contacts the first oxygen absorption layer; the second transverse groove exposes the second oxygen absorption layer so that the semiconductor layer extends into the second transverse groove and contacts the second oxygen absorption layer.

[0022] In an exemplary embodiment, the first oxygen absorbing layer contains titanium atoms and oxygen atoms; the second oxygen absorbing layer contains titanium atoms and oxygen atoms.

[0023] In a third aspect, an embodiment of the present application further provides an electronic device comprising the semiconductor device as described above.

[0024] In an embodiment of the present application, a first extension portion and a second extension portion are provided whose extension direction intersects with the extension direction of the main portion, and the first extension portion is in direct contact with a portion of the main surface of the first electrode, and the second extension portion is in direct contact with a portion of the main surface of the second electrode, so that the contact area between the semiconductor layer and the first electrode and the second electrode is increased, thereby reducing the contact resistance.

[0025] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained through the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide a further understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0027] Figure 1 is a cross-sectional view of a semiconductor device;

[0028] Figure 2 is a cross-sectional view of a semiconductor device in an exemplary embodiment of the present application;

[0029] Figure 3 is a cross-sectional view of a semiconductor device in yet another exemplary embodiment;

[0030] Figure 4 is a cross-sectional view after forming a laminated structure;

[0031] Figure 5A A top view after the first trough is formed;

[0032] Figure 5B for Figure 5A Cross-sectional view along AA direction;

[0033] Figure 6A A top view after the second and third trough bodies are formed;

[0034] Figure 6B for Figure 6A Cross-sectional view along AA direction;

[0035] Figure 7 It is a cross-sectional view of the first trench after forming the first semiconductor layer;

[0036] Figure 8 A cross-sectional view of the first trough body after the second trough body and the third trough body are formed in another embodiment;

[0037] Figure 9 is a cross-sectional view of the first tank body after annealing;

[0038] Figure 10 Schematic diagram of the movement of oxygen in the first extension portion and the first oxygen absorption layer during the annealing process;

[0039] Figure 11 A cross-sectional view of the first tank body after a portion of the first semiconductor layer is removed;

[0040] Figure 12 This is a cross-sectional view of the first trench after forming the second semiconductor layer. DETAILED DESCRIPTION

[0041] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0042] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0043] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0044] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0045] In this specification, unless otherwise specified or limited, the terms "connected" and "connection" should be understood broadly. For example, they can mean contact connection or integral connection; physical connection or signal connection; direct connection or indirect connection through an intermediary component; or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0046] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0047] The phrase "A and B disposed in the same layer" in this disclosure encompasses layers formed of the same material or different materials located on the same film layer. For example, A and B are formed by forming the same film layer from the same material and then undergoing the same patterning process or different patterning processes. A and B disposed in the same layer can be located on the same horizontal plane, but not necessarily on the same film layer, or in different regions of the same film layer, but not necessarily on the same horizontal plane.

[0048] In the embodiments of the present disclosure, "A and B are interconnected integral structures" may include a film layer patterned to form a connection as an integral structure. For example, A and B are formed using the same material in a single film layer and are formed simultaneously through the same patterning process to form a connected structure.

[0049] In the embodiments of the present disclosure, "substrate" means and includes the base material or structure on which materials such as vertical field-effect transistors are formed. The substrate can be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate can be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0050] In the field of integrated circuit technology, increasing product integration often involves minimizing the footprint of individual devices or components. Transistors are crucial components, and vertical transistors can reduce their footprint compared to planar transistors.

[0051] Figure 1 : is a cross-sectional view of a ring channel transistor. Figure 1 As shown, a buffer layer 101 may be formed on a substrate 100 first, and then a stacked structure of a first conductive layer 102, an isolation layer 103, and a second conductive layer 104 may be formed in sequence on the substrate 100. Subsequently, a hole may be opened in the stacked structure to form a groove.

[0052] The trench penetrates the sidewalls of the stacked structure, exposing the first conductive layer 102, and the bottom wall extends deep into the first conductive layer 102, exposing the buffer layer 101. A semiconductor layer 105 is deposited in the trench, attached to the bottom and sidewalls of the trench. The side of the semiconductor layer 105 facing away from the substrate 100 has a depression similar in shape to the trench. Subsequently, a gate insulating layer 106 and a gate layer 107 are sequentially formed in the depression of the semiconductor layer 105. The semiconductor layer 105 surrounds the gate layer 107 to form a ring-shaped channel structure. The first conductive layer 102 surrounds the main body of the semiconductor layer 105 and is in direct contact with the semiconductor layer 105, forming the first electrode of the transistor. The second conductive layer 104 surrounds the main body of the semiconductor layer 105 and is in direct contact with the semiconductor layer 105, forming the second electrode of the transistor, thereby forming a transistor structure in a direction perpendicular to the substrate 100.

[0053] The first electrode and the second electrode each include a major surface (eg, an upper surface and a lower surface) parallel to the substrate and an end surface (eg, a region of the first electrode and the second electrode exposed in the hole).

[0054] Figure 1In the transistor structure shown, the semiconductor layer contacts only the end face of the first electrode or the second electrode. Taking the first electrode as an example, the contact area between the semiconductor layer 105 and the first conductive layer 102 is the thickness of the first conductive layer 102 surrounding the semiconductor layer 105, as shown in the dashed area C. This contact area is relatively small, and further efforts are needed to reduce the contact resistance between the semiconductor layer and the first and second electrodes while simplifying the transistor fabrication process as much as possible.

[0055] Some embodiments of the present application provide a semiconductor device, including: a semiconductor layer, the semiconductor layer including a main body, a first extension portion, and a second extension portion that are interconnected; the first extension portion and the second extension portion extend in a transverse direction parallel to a substrate, and the main body extends in a longitudinal direction perpendicular to the substrate; a gate layer extends in the longitudinal direction, the main body is a ring-shaped portion extending in the longitudinal direction and surrounding the side wall of the gate layer and insulated from the gate layer; a first electrode and a second electrode are spaced apart in the longitudinal direction, the first electrode is close to the substrate, and the second electrode surrounds the outer side wall of the ring-shaped semiconductor layer; an isolation layer is located between the first electrode and the second electrode and surrounds the outer side wall of the ring-shaped semiconductor layer; the first extension portion extends to the area between the isolation layer and the first electrode and is connected to the first electrode; the second extension portion extends to the area between the isolation layer and the second electrode and is connected to the second electrode.

[0056] In the embodiment of the present application, a first extension portion and a second extension portion are provided whose extension direction intersects with the extension direction of the main portion, and the first extension portion is in direct contact with a portion of the main surface of the first electrode, and the second extension portion is in direct contact with a portion of the main surface of the second electrode, so that the contact area between the semiconductor layer and the first electrode and the second electrode is increased, thereby reducing the contact resistance.

[0057] In an exemplary embodiment, the stacked structure includes a stacked structure provided on the substrate, the stacked structure including a first conductive layer, a first sacrificial layer, the isolation layer, a second sacrificial layer, and a second conductive layer sequentially provided in a direction away from the substrate; the first electrode is located in the first conductive layer, which can be understood as being formed by patterning the first conductive layer, and the first conductive layer includes the first electrode; the second electrode is located in the second conductive layer, which can be understood as being formed by patterning the second conductive layer, and the second conductive layer includes the second electrode;

[0058] The stacked structure includes a first trough body extending along the longitudinal direction, a second trough body extending along the transverse direction and surrounding the outer side wall of the semiconductor layer, and a third trough body, the main body is located in the first trough body, the second trough body is located between the isolation layer and the first conductive layer, the second trough body is connected to the first trough body, the bottom of the second trough body exposes the first sacrificial layer, the first extension portion is located in the second trough body and connected to the main body; the third trough body is located between the isolation layer and the second conductive layer, the third trough body is connected to the first trough body, the bottom of the third trough body exposes the second sacrificial layer, the second extension portion is located in the third trough body and connected to the main body.

[0059] In one exemplary embodiment, the first and second extensions serve as contact regions between the first and second electrodes and the channel, and may also be referred to as contact regions. The length of the semiconductor layer between the contact regions in a direction perpendicular to the substrate is the length of the channel. In some embodiments, the thickness of the isolation layer in a direction perpendicular to the substrate is the length of the channel of the semiconductor layer. By using first and second sacrificial layers rather than etching back the isolation layer, it is easier to control the length of the channel and the thickness of the first and second extensions in a direction perpendicular to the substrate. These channel lengths and the thicknesses of the first and second extensions can be accurately controlled during the deposition of the corresponding film layers.

[0060] The semiconductor layer can be a metal oxide semiconductor layer. During fabrication, the semiconductor layer can be deposited at one time to form the first, second, and third trough bodies. The semiconductor layers of the second and third trough bodies can be located on the sidewalls or completely fill the trough bodies. Generally, the metal oxide semiconductor layer in the second and third trough bodies has a higher conductivity than the semiconductor layer in the first trough body, which helps to reduce the contact resistance between the first electrode and the second electrode. In order to reduce the metal oxide semiconductor layer formed in three trough bodies at one time, the present application needs to add an oxygen-absorbing layer to absorb oxygen only from the semiconductor layers of the second and third trough bodies, thereby improving conductivity.

[0061] In an exemplary embodiment, the stacked structure further includes a first oxygen-absorbing layer and a second oxygen-absorbing layer, wherein the first oxygen-absorbing layer is located between the first conductive layer and the first extension portion, and the second oxygen-absorbing layer is located between the second extension portion and the second conductive layer. The first electrode is also located between the first conductive layer and the first oxygen-absorbing layer. It can be understood that the first portion of the first electrode is formed by patterning the first conductive layer, and the second portion of the first electrode is formed by patterning the first oxygen-absorbing layer. The first electrode can be composed of the stacked first portion and the second portion. The second electrode is located between the second conductive layer and the second oxygen-absorbing layer. It can be understood that the third portion of the second electrode is formed by patterning the second oxygen-absorbing layer, and the fourth portion of the second electrode is formed by patterning the second conductive layer. The second electrode can be composed of the stacked third portion and the fourth portion.

[0062] Figure 2 FIG is a cross-sectional view of a semiconductor device in an exemplary embodiment of the present application. Figure 2 As shown, the semiconductor device includes a semiconductor layer 105, a gate layer 107, an isolation layer 103, a first electrode E1 surrounding the outer sidewall of the gate layer 107, and a second electrode E2 surrounding the outer sidewall of the gate layer 107. The semiconductor layer 105 includes a main body, a first extension 151, and a second extension 152 that are interconnected. The main body extends along a second direction Y, and the first and second extensions 151, 152 extend along a first direction X. The first extension 151 is located on the side of the second extension 152 that is closer to the substrate 100. The first direction X can be horizontal, and the second direction Y can be vertical. The first and second extensions 151, 152 are both annular and surround the main body of the semiconductor layer 105. The first and second electrodes E1, E2 are both annular and surround the main body of the semiconductor layer 105.

[0063] In some embodiments, the first electrode E1 may not surround the gate layer 107 . The first electrode E1 is located below the gate layer 107 but does not surround the sidewall of the gate layer.

[0064] The gate layer 107 extends along the second direction Y and is in the shape of a column or line. In the second direction Y, the main body is annular, surrounds the sidewalls of the gate layer 107, and is insulated from the gate layer 107. The first electrode E1 and the second electrode E2 are spaced apart along the second direction Y and located in two regions of the main body, respectively. The upper surface of the first electrode E1 is in direct contact with the bottom of the main body. The first extension 151 is integrally formed with the main body, and the lower surface of the first extension 151 is also in direct contact with the upper surface of the first electrode E1.

[0065] The second electrode E2 is in direct contact with the main body, and the second extension portion 152 and the main body are an integrated structure. The second electrode E2 surrounds the outer wall of the main body of the annular semiconductor layer 105, and the end of the second electrode E2 is in contact with the outer wall of the main body, and the lower surface of the second electrode E2 is in contact with the upper surface of the second extension portion 152.

[0066] The isolation layer 103 is located between the first electrode E1 and the second electrode E2 and surrounds the outer wall of the annular semiconductor layer 105 , specifically the outer wall of the main body of the annular semiconductor layer 105 . The isolation layer 103 is located between the first extension portion 151 and the second extension portion 152 .

[0067] The first extension portion 151 extends to the area between the isolation layer 103 and the upper surface of the first electrode E1, contacting the upper surface of the first electrode E1; the second extension portion 152 extends to the area between the isolation layer 103 and the lower surface of the second electrode E2, contacting the lower surface of the second electrode E2. By providing the first extension portion 151 and the second extension portion 152 on the major surfaces (such as the top or bottom surfaces) of the first and second electrodes, contacting the major surfaces, both the end faces and the major surfaces of the first and second electrodes are in contact with the semiconductor layer, thereby increasing the contact area between the semiconductor layer 105 and the first and second electrodes E1 and E2, and reducing the contact resistance. Figure 2 In the figure, the first direction X is parallel to the substrate 100 and the second direction Y is perpendicular to the substrate 100 for illustration, and the present application does not limit this.

[0068] In some examples, such as Figure 2 As shown, the stacked structure includes a first trough (which can also be understood as a hole) extending along the second direction Y, with the main body located within the first trough. The stacked structure also includes a second trough and a third trough extending along the first direction X and surrounding the outer wall of the semiconductor layer 105. The second trough is located in the first sacrificial layer 111 and between the isolation layer 103 and the first conductive layer 102. The second trough is connected to the first trough, and the bottom of the second trough exposes the end surface of the first sacrificial layer 111. The first extension 151 is located within the second trough and connected to the main body. The third trough is located in the second sacrificial layer 112 and between the isolation layer 103 and the second conductive layer 104. The third trough is connected to the first trough, and the bottom of the third trough exposes the end surface of the second sacrificial layer 112. The second extension 152 is located within the third trough and connected to the main body.

[0069] In some examples, such as Figure 2As shown, the main portion directly contacts the first conductive layer 102 on the side closest to the substrate 100, thereby increasing the contact area between the main portion and the first electrode E1. In other embodiments, the main portion can directly contact the buffer layer 101 on the side closest to the substrate 100, with the first conductive layer 102 surrounding the main portion of the semiconductor layer 105. In this case, the end of the first electrode E1 contacts the main portion, and the upper surface contacts the lower surface of the first extension portion.

[0070] In some examples, the main body, the first extension portion 151 and the second extension portion 152 are made of the same material. For example, the main body, the first extension portion 151 and the second extension portion 152 are different regions of the semiconductor layer 105 formed by a single deposition process.

[0071] In applications where metal oxide semiconductors are used as channels, it is desirable to have good semiconductor properties in the main body and good conductivity in the first and second extensions 151, 152. In some embodiments, this can be achieved by reducing the amount of oxygen in the first and second extensions, while forming the main body, first and second extensions 151, 152 in a single process. This simplifies the process and eliminates the need for two separate processes or additional patterning steps to form the main body, first and second extensions 151, 152. In some examples, this is achieved by adding an oxygen-absorbing layer between the conductive layer and the extensions.

[0072] Figure 3 is a cross-sectional view of a semiconductor device in another exemplary embodiment, Figure 2 On the basis of the structure shown, an oxygen absorbing layer is added to reduce the oxygen concentration in the first extension portion and the second extension portion.

[0073] like Figure 3As shown, the stacked structure may include a first conductive layer 102, a first oxygen-absorbing layer 121, a first sacrificial layer 111, an isolation layer 103, a second sacrificial layer 112, a second oxygen-absorbing layer 122, and a second conductive layer 104, sequentially arranged in a direction away from the substrate 100. The first oxygen-absorbing layer 121 is located between the first conductive layer 102 and the first extension 151, and the second oxygen-absorbing layer 122 is located between the second extension 152 and the second conductive layer 104. A first electrode E1 is located on the side of the semiconductor layer close to the substrate 100 and comprises a stacked first conductive layer 102 and first oxygen-absorbing layer 121. A second electrode E2 comprises a stacked second conductive layer 104 and second oxygen-absorbing layer 122. The first conductive layer 102 and first oxygen-absorbing layer 121 of the second electrode E2 are both arranged around the main body, and the second oxygen-absorbing layer 122 is in direct contact with the main body and the second extension 152. The stacked structure includes a first trough extending along the second direction Y, a second trough extending along the first direction X and surrounding the outer wall of the semiconductor layer, and a third trough. The main body is located within the first trough, the second trough is located between the isolation layer 103 and the first oxygen-absorbing layer 121, the bottom of the second trough is the first sacrificial layer 111, and the second trough is connected to the first trough. The first extension 151 is located within the second trough and connected to the main body. The third trough is located between the isolation layer 103 and the second oxygen-absorbing layer 122, the bottom of the third trough is the second sacrificial layer 112, and the third trough is connected to the first trough. The second extension 152 is located within the third trough and connected to the main body. By providing the first oxygen-absorbing layer 121 between the first conductive layer 102 and the first extension 151, the first oxygen-absorbing layer 121 can absorb oxygen within the first extension 151, thereby reducing the oxygen concentration in the first extension 151 and improving its conductivity. Based on the same principle, the second oxygen absorption layer 122 can reduce the oxygen concentration of the second extension portion 152 and improve the conductivity of the second extension portion 152 .

[0074] In some examples, the main body can be formed in different process steps from the first extension 151 and the second extension 152. This allows the material type of the first and second extensions to be the same as or different from the material type of the channel region. This allows for flexible selection of materials for these two regions, ensuring the semiconductor properties of the channel layer and the conductive properties of the extensions, and eliminating the need for an oxygen gettering layer. For example, if the first and second extensions are made of ITO and the main body is made of IGZO, an oxygen gettering layer may not be required.

[0075] For another example, the first extension and the second extension may be made of the same material type, IGZO, and the channel region may also be made of IGZO. However, the In content ratios in the IGZO in the two regions may be different, and / or the O concentrations in the IGZO in the two regions may be different. The O concentrations in the first and second extensions are less than that in the main body.

[0076] For example, if the In content in the IGZO of the first and second extensions is higher, even if the subsequent channel region annealing treatment has little effect on the conductivity of the extension region, in this case, the oxygen-absorbing layer can be omitted. To further reduce the oxygen content in the IGZO of the first and second extensions, the oxygen-absorbing layer can be provided on this basis.

[0077] In some examples, such as Figure 3 As shown, the main body directly contacts the first oxygen absorbing layer 121 on the side close to the substrate 100. In some examples, the first oxygen absorbing layer 121 directly below the main body may be penetrated, and the main body directly contacts the first conductive layer 102.

[0078] The technical solution of this embodiment is further explained below through the preparation process of the semiconductor device of this embodiment. The "composition process" mentioned in this embodiment includes processes such as depositing a film layer, applying a photoresist, mask exposure, development, etching, and stripping the photoresist, and is a mature preparation process in the relevant technology. The "photolithography process" mentioned in this embodiment includes coating a film layer, mask exposure and development, and is a mature preparation process in the relevant technology. Deposition can adopt known processes such as sputtering, evaporation, and chemical vapor deposition, coating can adopt known coating processes, and etching can adopt known methods, which are not limited here.

[0079] In some examples, such as Figure 2 The manufacturing process of the semiconductor device shown may include the following steps: In this example, the cross-sectional view along the AA direction refers to a cross-sectional view passing through the AA direction and perpendicular to the plane where the substrate is located.

[0080] (11) A buffer layer 101 is deposited on a substrate 100, and then a first conductive film, a first sacrificial film, an isolation layer film, a second sacrificial film, and a second conductive film are sequentially deposited to form a stacked structure including a first conductive layer 102, a first sacrificial layer 111, an isolation layer 103, a second sacrificial layer 112, and a second conductive layer 104 on the buffer layer 101. Figure 4 It is a cross-sectional view after the laminated structure is formed.

[0081] In some examples, the substrate 100 can be a semiconductor substrate, such as a silicon substrate, and different substrate materials can be selected according to the materials of the semiconductor layers to be formed subsequently. The materials of the buffer layer film and the isolation layer film can be different materials, for example, silicon oxide, such as silicon dioxide (SiO2), or other dielectric materials with other etching selectivities can be selected. The materials of the first sacrificial layer film and the second sacrificial film can be silicon nitride, such as silicon nitride (Si3N4). The first conductive film and the second conductive film can be made of metal materials, which can be metal elements or alloys, as well as stacks of multiple metal materials, for example, metal tungsten (W). This application does not limit the materials of the above-mentioned film layers.

[0082] In some examples, the buffer layer 101, the first conductive layer 102, the first sacrificial layer 111, the isolation layer 103, the second sacrificial layer 112, and the second conductive layer 104 may cover the substrate 100. The thickness of different film layers on the substrate 100 in a direction perpendicular to the substrate 100 may be set as needed, and this embodiment is not limited thereto.

[0083] (12) A first opening is etched on the stacked structure in a direction perpendicular to the substrate 100 to form a Figure 5B The first tank K1 is shown.

[0084] In some examples, the outline of the first opening can be defined on the surface of the stacked structure away from the substrate 100 by photolithography, and then the stacked structure is dry-etched in a direction perpendicular to the substrate 100 to remove part of the stacked structure in the first opening to form a first groove K1. Figure 5A This is a top view after the first trough is formed. Figure 5B for Figure 5A Cross-sectional view along the AA direction.

[0085] In some examples, such as Figure 5A As shown, the orthographic projection shape of the first trough body K1 on the substrate 100 can be a rectangle. In other embodiments, the orthographic projection shape of the first trough body K1 on the substrate 100 can be a triangle, a circle, an ellipse, a quadrilateral or polygon of other shapes, or an irregular shape, and this application does not impose any restrictions on this.

[0086] In some examples, such as Figure 5BAs shown, the first opening may stop inside the first conductive layer 102, that is, the first opening may not penetrate the first conductive layer 102. In this case, the bottom wall of the first trough K1 may be the first conductive layer 102, and the side wall of the first trough K1 may include the first conductive layer 102, the first sacrificial layer 111, the isolation layer 103, the second sacrificial layer 112 and the second conductive layer 104. By setting the bottom wall of the first trough K1 to the first conductive layer 102, the area of ​​the first conductive layer 102 exposed in the first opening is larger. After the semiconductor layer is subsequently formed, it helps to increase the contact area between the semiconductor layer of the semiconductor device and the first conductive layer 102, thereby reducing the contact resistance.

[0087] In other embodiments, the first opening can expose the surface of the buffer layer 101, that is, the first opening can pass through the first conductive layer 102. In this case, the bottom wall of the first trough body K1 can be the buffer layer 101, and the side wall of the first trough body K1 can include the first conductive layer 102, the first sacrificial layer 111, the isolation layer 103, the second sacrificial layer 112 and the second conductive layer 104. This embodiment is not limited to this.

[0088] (13) In the first opening, the first sacrificial layer 111 is etched back by lateral selective etching to form a first lateral groove, i.e., a second groove body K2. The second sacrificial layer 112 is etched back by lateral selective etching to form a second lateral groove, i.e., a third groove body K3. Figure 6A This is a top view after the second and third trough bodies are formed. Figure 6B for Figure 6A Cross-sectional view along the AA direction.

[0089] In some examples, the second trough body K2 is annular and communicates with the first trough body K1. The bottom wall of the second trough body K2 is the end of the first sacrificial layer 111, and the side walls of the second trough body K2 are the first conductive layer 102 and the isolation layer 103. By forming the second trough body K2 in communication with the first trough body K1 on the first sacrificial layer 111, the exposed area of ​​the first conductive layer 102 is increased. After the semiconductor layer is subsequently formed, the contact area between the semiconductor layer and the first conductive layer 102 of the semiconductor device is increased, thereby reducing the contact resistance.

[0090] In some examples, the third trough K3 is annular and communicates with the first trough K1. The bottom wall of the third trough K3 is the end of the second sacrificial layer 112, and the sidewalls of the third trough K3 are the isolation layer 103 and the second conductive layer 104. By forming the third trough K3 in communication with the first trough K1 on the second sacrificial layer 112, the exposed area of ​​the second conductive layer 104 is increased. After the semiconductor layer is subsequently formed, the contact area between the semiconductor layer and the second conductive layer 104 of the semiconductor device is increased, thereby reducing contact resistance.

[0091] As can be seen from the above process, no patterning processes such as photolithography and etching are performed during the formation of the second and third troughs. Instead, only the first and second sacrificial layers are etched back using a wet etchant. This reduces production costs. Furthermore, this etch-back process uses the sacrificial layer between the conductive layer and the isolation layer as a window, allowing for relatively accurate control of the distance between the third and second troughs in a direction perpendicular to the substrate, as well as the depth of the troughs.

[0092] In some examples, the orthographic projection of the second slot body K2 on the substrate 100 may at least partially overlap with the orthographic projection of the third slot body K3 on the substrate 100 .

[0093] In some examples, the transverse depth of the second groove body K2 is a first length d1, and the transverse depth of the third groove body K3 is a second length d2, and the first length d1 and the second length d2 are substantially the same. It should be noted that the first length d1 and the second length d2 may be the average, maximum, or minimum values ​​of multiple test points.

[0094] In some examples, the first sacrificial layer and the second sacrificial layer are etched back through a single process, so that in the same cross-section perpendicular to the substrate 100, the first length d1 and the second length d2 are almost equal. In this case, the orthographic projection of the second trough body K2 on the substrate 100 can overlap with the orthographic projection of the third trough body K3 on the substrate 100.

[0095] In some examples, such as Figure 6A As shown, the orthographic projection of the second trough body K2 on the substrate 100 overlaps with the orthographic projection of the third trough body K3 on the substrate 100, and the orthographic projection shapes of the second trough body K2 and the third trough body K3 on the substrate 100 are the same as the orthographic projection shape of the first trough body K1, both being rectangular. In other embodiments, the orthographic projection shapes of the second trough body K2 and the third trough body K3 on the substrate 100 may be triangular, circular, elliptical, other quadrilateral and polygonal shapes, or irregular shapes. The orthographic projection shapes of the first trough body K1, the second trough body K2, and the third trough body K3 may also be different and can be set as needed, and this application does not impose any restrictions on this.

[0096] (14) depositing a first semiconductor thin film on the substrate 100 having the aforementioned pattern formed thereon to form a semiconductor layer 105; Figure 7 This is a cross-sectional view of the first trench after the semiconductor layer is formed.

[0097] In some examples, such as Figure 7As shown, the semiconductor layer 105 includes a main body, a first extension 151, and a second extension 152. The main body extends perpendicular to the substrate 100 and is in close contact with the inner wall of the first trough K1. The first and second extensions 151, 152 extend parallel to the substrate 100. The first extension 151 completely fills the second trough K2, and the second extension 152 completely fills the third trough K3. The side of the semiconductor layer 105 away from the substrate 100 has a first recessed portion similar in shape to the first trough K1.

[0098] In some examples, the first semiconductor film forming the semiconductor layer may be made of a metal oxide semiconductor material, and the material of the semiconductor layer may be selected from at least one of the following materials: indium, gallium, zinc, tin, and aluminum.

[0099] In some examples, the first semiconductor film forming the semiconductor layer can be made of a metal oxide semiconductor material. For example, the metal oxide semiconductor material can include indium gallium zinc oxide (IGZO). When the semiconductor layer is made of IGZO, the leakage current of the semiconductor device is low, which helps ensure a low refresh rate of the dynamic memory. However, this embodiment is not limited to this. In other examples, the materials of the metal oxide may include: IGO, ITO, IZO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO and other materials, which can be adjusted according to actual conditions.

[0100] (15) A first insulating film and a third conductive film are sequentially deposited, and a gate insulating layer 106 and a gate electrode layer 107 are sequentially formed in the first recess of the semiconductor layer 105. The gate insulating layer 106 can be closely attached to the inner wall of the first recess of the semiconductor layer 105. The side of the gate insulating layer 106 away from the substrate 100 has a second recess similar in shape to the first recess. The gate electrode layer 107 is located on the sidewall of the second recess or filled in the second recess of the gate insulating layer 106. A cross-sectional view of the semiconductor device after the gate electrode layer 107 is formed can be referred to. Figure 2 .

[0101] In some examples, the first insulating film may be made of a high-k dielectric material, including but not limited to at least one of the following: silicon oxide and hafnium oxide. The third conductive film may be made of a metal material, for example.

[0102] In some examples, such as Figure 3 The manufacturing process of the semiconductor device shown may include the following steps.

[0103] (21) A buffer layer 101 and a stacked structure are formed on a substrate 100, and a first groove body K1 is formed on the stacked structure. In the first groove body K1, the first sacrificial layer 111 is etched back by lateral selective etching to form a first lateral groove, i.e., a second groove body K2. The second sacrificial layer 112 is etched back by lateral selective etching to form a second lateral groove, i.e., a third groove body K3.

[0104] Figure 8 This is a cross-sectional view of the first trough body after forming the second trough body and the third trough body in another embodiment. The top view after forming the second trough body and the third trough body can refer to the above Figure 6A , which will not be described in detail here. The difference between this step and the aforementioned preparation steps (11) to (13) lies in the film layer included in the laminated structure and the structures of the first tank body K1, the second tank body K2 and the third tank body K3. The rest of the content can refer to the aforementioned preparation steps (11) to (13) and will not be described in detail here.

[0105] In one example, if Figure 8 As shown, in this embodiment, the stacked structure formed on the buffer layer 101 on the side of the buffer layer 101 away from the substrate 100 may include a first conductive layer 102, a first oxygen-absorbing layer 121, a first sacrificial layer 111, an isolation layer 103, a second sacrificial layer 112, a second oxygen-absorbing layer 122, and a second conductive layer 104, arranged in that order. The first conductive layer 102 and the first oxygen-absorbing layer 121 can subsequently be used to form a first electrode, while the second oxygen-absorbing layer 122 and the second conductive layer 104 can subsequently be used to form a second electrode. The stacked two layers help increase the contact area with the semiconductor layer, thereby helping to reduce contact resistance.

[0106] In one example, if Figure 8 As shown, the bottom wall of the first trough body K1 is the first oxygen-absorbing layer 121, and the sidewalls of the first trough body K1 include the first sacrificial layer 111, the isolation layer 103, the second sacrificial layer 112, the second oxygen-absorbing layer 122, and the second conductive layer 104. The bottom wall of the second trough body K2 is the first sacrificial layer 111, and the sidewalls of the second trough body K2 are the first oxygen-absorbing layer 121 and the isolation layer 103. The bottom wall of the third trough body K3 is the second sacrificial layer 112, and the sidewalls of the third trough body K3 are the isolation layer 103 and the second oxygen-absorbing layer 122. The shapes, dimensions, and other parameters of the first trough body K1, the second trough body K2, and the third trough body K3 can refer to the description of the above preparation steps.

[0107] In one example, the material of the first oxygen absorption layer 121 and the second oxygen absorption layer 122 can be a conductive material with high oxygen solubility, such as metal titanium (Ti), titanium nitride, or a stacked material of titanium and titanium nitride, etc., which is not limited in this application.

[0108] (22) A second semiconductor thin film is deposited on the patterned substrate 100 to form a first semiconductor layer 150. The first semiconductor layer 150 is closely attached to the inner wall of the first trench K1. The first semiconductor layer 150 includes a first extension portion 151 that completely fills the second trench K2 and a second extension portion 152 that completely fills the third trench K3. Subsequently, the first semiconductor layer 150 is annealed to increase the doping concentration of the first extension portion 151 and the second extension portion 152. Figure 9 This is a cross-sectional view of the first tank after annealing.

[0109] In one example, the material of the second semiconductor film can be IGZO, such as C-axis aligned crystalline (CAAC) IGZO. CAAC-IGZO has better stability and helps to improve the performance of semiconductor devices. When a semiconductor device with this structure is applied to a memory device, the performance of the memory device can be improved.

[0110] Figure 10 Schematic diagram of the movement of oxygen in the first extension portion and the first oxygen absorption layer during the annealing process. Figure 10 The circle in the first extension portion 151 represents oxygen, and the arrow direction represents the movement direction of oxygen. Figure 10 As shown, in one example, the first oxygen absorber layer 121 may include a stack of a first titanium nitride layer 11 and a first metal titanium layer 12. The first titanium nitride layer 11 is located on a side close to the first extension portion 151. During the annealing process, oxygen in the first extension portion 151 moves into the first oxygen absorber layer 121 and dissolves in the first oxygen absorber layer 121, thereby leaving more oxygen vacancies in the first semiconductor layer 150, thereby increasing the doping concentration of the oxygen vacancies in the first extension portion 151. The principle of oxygen movement between the second extension portion 152 and the second oxygen absorber layer 122 is the same as that between the first extension portion 151 and the first oxygen absorber layer 121, and will not be repeated here.

[0111] (23) On the substrate 100 on which the aforementioned pattern is formed, a portion of the first semiconductor layer 150 is removed, leaving only the first extension portion 151 and the second extension portion 152. Figure 11 This is a cross-sectional view of the first trench after removing part of the first semiconductor layer.

[0112] In one example, the first semiconductor layer 150 can be etched using a chlorine (Cl)-based gas, and then cleaned with isopropyl alcohol (IPA) to remove excess first semiconductor film. Removing the first semiconductor film in this manner does not damage the metal oxide semiconductor material, ensuring that the exposed surfaces of the first extension portion 151 and the second extension portion 152 remain intact, thereby maintaining the performance of the semiconductor device.

[0113] In an exemplary embodiment, the chlorine-based gas may include, for example, boron trichloride (BCl 3 ), chlorine (Cl 2 ), hydrogen chloride (HCl), silicon tetrachloride (Si Cl 4 ), or other gases or plasma.

[0114] (24) A third semiconductor thin film is deposited on the substrate 100 on which the aforementioned pattern is formed, thereby forming a second semiconductor layer 123 . Figure 12 This is a cross-sectional view of the first trench after forming the second semiconductor layer.

[0115] In one example, the material of the third semiconductor film may have different properties from the material of the second semiconductor film. For example, the second semiconductor film and the third semiconductor film may be different in terms of crystallization state, elemental composition and material composition. In an exemplary embodiment, the third semiconductor film may be made of amorphous IGZO, IGZO materials with different In:Ga:Zn ratios, or In2O3, Ga2O3, ZnO and ITO and other materials. This application does not impose any restrictions on this.

[0116] In one example, if Figure 12 As shown, the second semiconductor layer 123 is closely attached to the inner wall of the first groove body K1, and the second semiconductor layer 123 includes a main body portion, which is in direct contact with the first extension portion 151 and the second extension portion 152. The side of the second semiconductor layer 123 away from the substrate 100 has a third recessed portion with a shape similar to that of the first groove body K1.

[0117] In one example, after partially removing the first semiconductor layer 150, the second semiconductor layer 123 is re-formed, so that the main body of the semiconductor layer of the semiconductor device and the first extension portion 151 and the second extension portion 152 are prepared separately. The first extension portion 151 and the second extension portion 152 have been annealed and contain more oxygen vacancies, while the main body has not been annealed and has a relatively low oxygen vacancy concentration. In this embodiment, by forming the main body and the first extension portion 151 and the second extension portion 152 separately, the oxygen vacancy concentration in the first extension portion 151 and the second extension portion 152 can be increased, while the oxygen vacancy concentration in the main body can be reduced, thereby further improving the performance of the semiconductor device.

[0118] (25) A first insulating film and a third conductive film are sequentially deposited, and a gate insulating layer 106 and a gate electrode layer 107 are sequentially formed on the side of the second semiconductor layer 123 away from the substrate 100. The gate insulating layer 106 can be closely attached to the inner wall of the third recess of the second semiconductor layer 123. The side of the gate insulating layer 106 away from the substrate 100 has a fourth recess similar in shape to the third recess, and the gate electrode layer 107 is filled in the fourth recess of the gate insulating layer 106. A cross-sectional view of the semiconductor device after the gate electrode layer 107 is formed can be referred to. Figure 3 .

[0119] In some examples, the materials of the first insulating film and the third conductive film can refer to the description of the aforementioned preparation steps and are not repeated here.

[0120] An embodiment of the present application also provides a method for preparing a semiconductor device, the method comprising: depositing a first conductive layer, a first sacrificial layer, an isolation layer, a second sacrificial layer, and a second conductive layer in sequence on a substrate; forming a hole that at least penetrates the second conductive layer, the second sacrificial layer, the isolation layer, and the first sacrificial layer and exposes the second conductive layer; etching back the first sacrificial layer and the second sacrificial layer on the sidewalls of the hole to form a first lateral groove and a second lateral groove, respectively; depositing a semiconductor layer on the sidewalls of the hole and in the first lateral groove and the second lateral groove; and sequentially forming a gate insulating layer and a gate layer covering the semiconductor layer in the hole.

[0121] In an exemplary embodiment, the forming of a hole that at least penetrates the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer and exposes the second conductive layer includes: penetrating the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer and the first conductive layer in sequence along a longitudinal direction perpendicular to the substrate to form the hole; or penetrating the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer in sequence along a longitudinal direction perpendicular to the substrate, and removing a portion of the first conductive layer to form the hole, wherein the hole extends into the first conductive layer.

[0122] In an exemplary embodiment, a first oxygen absorption layer is deposited before depositing the first sacrificial layer; a second oxygen absorption layer is deposited after depositing the second sacrificial layer; the forming of a hole that at least penetrates the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer and exposes the second conductive layer includes: forming the hole by sequentially penetrating the second conductive layer, the second oxygen absorption layer, the second sacrificial layer, the isolation layer and the first sacrificial layer in the longitudinal direction; the hole exposes the second conductive layer and the first oxygen absorption layer.

[0123] In an exemplary embodiment, the first transverse groove exposes the first oxygen absorbing layer so that the semiconductor layer extends into the first transverse groove and contacts the first oxygen absorbing layer; the second transverse groove exposes the second oxygen absorbing layer so that the semiconductor layer extends into the second transverse groove and contacts the second oxygen absorbing layer.

[0124] In an exemplary embodiment, the first oxygen-absorbing layer includes titanium atoms and oxygen atoms; and the second oxygen-absorbing layer includes titanium atoms and oxygen atoms.

[0125] In an exemplary embodiment, depositing the first oxygen absorption layer before depositing the first sacrificial layer includes: depositing a first oxygen absorption film before depositing the first sacrificial layer to form the first oxygen absorption layer, and the material of the first oxygen absorption film includes titanium or titanium nitride; depositing the second oxygen absorption layer after depositing the second sacrificial layer includes: depositing a second oxygen absorption film after depositing the second sacrificial layer to form the second oxygen absorption layer, and the material of the second oxygen absorption film includes titanium or titanium nitride.

[0126] In an exemplary embodiment, the depositing of the first oxygen absorption layer before depositing the first sacrificial layer includes: before depositing the first sacrificial layer, depositing a metal titanium film and a titanium nitride film in sequence to form a first metal titanium layer and a first titanium nitride layer; the first oxygen absorption layer includes a stack of the first metal titanium layer and the first titanium nitride layer; the depositing of the second oxygen absorption layer after depositing the second sacrificial layer includes: after depositing the second sacrificial layer, depositing a titanium nitride film and a metal titanium film in sequence to form a second titanium nitride layer and a second metal titanium layer; the second oxygen absorption layer includes a stack of the second titanium nitride layer and the second metal titanium layer.

[0127] An embodiment of the present application further provides an electronic device comprising the semiconductor device described above.

[0128] In an exemplary embodiment, an electronic device may include the semiconductor device. The semiconductor device may be a memory cell including transistors. For example, the memory cell may have a structure such as 1T1C or 2T0C. Two or more transistors may be stacked in a direction perpendicular to the substrate, thereby increasing the storage density of the memory device. This is not limited in this application. The semiconductor device may be a memory device including transistors, such as an SRAM.

[0129] In an exemplary embodiment of the present application, the electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a mobile power supply, etc. The storage device may include a memory in a computer, etc., which is not limited here.

[0130] Although the embodiments disclosed in this application are as described above, the contents described are merely embodiments adopted to facilitate understanding of this application and are not intended to limit this application. Any person skilled in the art to which this application belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application. However, the scope of patent protection of this application shall still be based on the scope defined by the attached claims.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor layer comprising a main portion, a first extending portion, and a second extending portion connected to each other, wherein the first extending portion and the second extending portion extend in a transverse direction parallel to a substrate, and the main portion extends in a longitudinal direction perpendicular to the substrate; The gate layer extends in the longitudinal direction; the main body is annular and extends in the longitudinal direction, surrounds the sidewall of the gate layer, and is insulated from the gate layer; A first electrode and a second electrode are spaced apart in a longitudinal direction, wherein the first electrode is close to the substrate and the second electrode surrounds the outer wall of the main body; an isolation layer, located between the first electrode and the second electrode and surrounding an outer wall of the main body; The first extension portion extends to a region between the isolation layer and the first electrode and is connected to the first electrode; The second extension portion extends to a region between the isolation layer and the second electrode and is connected to the second electrode.

2. The semiconductor device according to claim 1, wherein comprising a stacked structure arranged on the substrate, the stacked structure comprising a first conductive layer, a first sacrificial layer, the isolation layer, a second sacrificial layer, and a second conductive layer sequentially arranged in a direction away from the substrate; The first electrode is located in the first conductive layer, and the second electrode is located in the second conductive layer; the stacked structure includes a first slot extending along the longitudinal direction, a second slot extending along the transverse direction and surrounding the outer side wall of the main body, and a third slot; The main body is located in the first tank; The second slot body is located between the isolation layer and the first conductive layer, the second slot body is connected to the first slot body, the first sacrificial layer is exposed at the bottom of the second slot body, and the first extension portion is located in the second slot body and connected to the main body; The third slot body is located between the isolation layer and the second conductive layer, the third slot body is connected to the first slot body, the second sacrificial layer is exposed at the bottom of the third slot body, and the second extension portion is located in the third slot body and connected to the main body.

3. The semiconductor device according to claim 1 or 2, wherein: The thickness of the isolation layer is equal to the length of the channel of the semiconductor layer.

4. The semiconductor device according to claim 1 or 2, wherein: The main body, the first extension and the second extension of the semiconductor layer are made of metal oxide semiconductor material; the metal in the metal oxide semiconductor material is selected from one or more of the following materials: indium, gallium, zinc, tin and aluminum.

5. The semiconductor device according to claim 4, wherein The main portion, the first extension portion, and the second extension portion of the semiconductor layer are an integrated structure. The semiconductor device according to claim 4 , wherein: The material type of at least one of the first extension portion and the second extension portion is the same as the material type of the main body portion; and the oxygen concentration of the first extension portion and the oxygen concentration of the second extension portion are both lower than the oxygen concentration of the main body portion.

7. The semiconductor device according to claim 4, wherein: The main body and the first extension are independent of each other and in contact with each other, and the main body and the second extension are independent of each other and in contact with each other; The conductivity of the first extension portion and the conductivity of the second extension portion are both higher than the conductivity of the main body portion.

8. The semiconductor device according to claim 2, wherein: The stacked structure further includes a first oxygen absorption layer and a second oxygen absorption layer, wherein the first oxygen absorption layer is located between the first conductive layer and the first extension portion, and the second oxygen absorption layer is located between the second extension portion and the second conductive layer.

9. The semiconductor device according to claim 1, wherein The main body of the semiconductor layer is cylindrical, including the annular semiconductor layer and a bottom; the first conductive layer includes a portion surrounding the outer wall of the main body and a portion extending from the outer wall to the bottom of the semiconductor layer.

10. The semiconductor device according to claim 1, wherein The main body is made of indium gallium zinc oxide, and the first extension and the second extension are made of indium gallium zinc oxide or indium tin oxide.

11. The semiconductor device according to claim 8, wherein The materials of the first oxygen absorbing layer and the second oxygen absorbing layer include titanium or titanium nitride.

12. The semiconductor device according to claim 11, wherein The first oxygen absorption layer includes a stack of a first titanium nitride layer and a first metal titanium layer, and the first titanium nitride layer is located on a side close to the first extension portion and contacts the first extension portion; the second oxygen absorption layer includes a stack of a second titanium nitride layer and a second metal titanium layer, and the second titanium nitride layer is located on a side close to the second extension portion and contacts the second extension portion.

13. A method for preparing a semiconductor device, characterized in that: The method comprises: Depositing a first conductive layer, a first sacrificial layer, an isolation layer, a second sacrificial layer, and a second conductive layer in sequence on the substrate; forming a hole that at least penetrates the second conductive layer, the second sacrificial layer, the isolation layer, and the first sacrificial layer and exposes the second conductive layer; Carving back the first sacrificial layer and the second sacrificial layer on the sidewalls of the hole to form a first transverse groove and a second transverse groove, respectively; A semiconductor layer is deposited on the sidewall of the hole and in the first transverse groove and the second transverse groove; and a gate insulating layer and a gate layer covering the semiconductor layer are sequentially formed in the hole.

14. The preparation method according to claim 13, characterized in that The forming of a hole that at least penetrates the second conductive layer, the second sacrificial layer, the isolation layer, and the first sacrificial layer and exposes the second conductive layer includes: sequentially penetrating the second conductive layer, the second sacrificial layer, the isolation layer, the first sacrificial layer, and the first conductive layer in a longitudinal direction perpendicular to the substrate to form the hole; or The second conductive layer, the second sacrificial layer, the isolation layer, and the first sacrificial layer are sequentially penetrated along a longitudinal direction perpendicular to the substrate, and a portion of the first conductive layer is removed to form the hole, which extends into the first conductive layer.

15. The preparation method according to claim 13, characterized in that Depositing a first oxygen absorption layer before depositing the first sacrificial layer; depositing a second oxygen absorption layer after depositing the second sacrificial layer; forming a hole that at least penetrates the second conductive layer, the second sacrificial layer, the isolation layer, and the first sacrificial layer and exposes the second conductive layer, comprises: The hole is formed by sequentially penetrating the second conductive layer, the second oxygen absorption layer, the second sacrificial layer, the isolation layer and the first sacrificial layer in a longitudinal direction; the second conductive layer and the first oxygen absorption layer are exposed through the hole.

16. The preparation method according to claim 15, characterized in that The first transverse groove exposes the first oxygen absorption layer so that the semiconductor layer extends into the first transverse groove and contacts the first oxygen absorption layer; the second transverse groove exposes the second oxygen absorption layer so that the semiconductor layer extends into the second transverse groove and contacts the second oxygen absorption layer.

17. The preparation method according to claim 15, characterized in that The first oxygen absorbing layer contains titanium atoms and oxygen atoms; the second oxygen absorbing layer contains titanium atoms and oxygen atoms.

18. An electronic device, characterized in that: The semiconductor device comprises the semiconductor device according to any one of claims 1 to 12.

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