Semiconductor device and method of manufacturing the same

Abstract

The embodiment of the invention relates to a semiconductor device and a manufacturing method thereof. According to one embodiment, a method of manufacturing a semiconductor device includes a step of forming a first insulating film. The method further includes a step of forming a first layer containing tungsten and nitrogen on the first insulating film. The method further includes a step of reducing the nitrogen concentration in the first layer by annealing the first layer in a state in which the first layer is exposed. The method further includes a step of forming a second layer including tungsten on the first layer after the annealing.

Description

[0001] [Related Applications]

[0002] This application claims the benefit of priority from Japanese Patent Application No. 2024-035254 (filing date: March 7, 2024), the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor device and a method for manufacturing the same. Background Art

[0004] In a semiconductor device including a wiring layer such as an electrode layer, it is desired to reduce the resistance of the wiring layer or to suppress the diffusion of atoms from the wiring layer to other layers. Summary of the Invention

[0005] According to one embodiment, a method for manufacturing a semiconductor device includes forming a first insulating film. The method further includes forming a first layer containing tungsten and nitrogen on the first insulating film. The method further includes annealing the first layer while the first layer is exposed to reduce the nitrogen concentration in the first layer. The method further includes forming a second layer containing tungsten on the annealed first layer.

[0006] According to one embodiment, a semiconductor device capable of forming a wiring layer having appropriate characteristics and a method for manufacturing the same can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a perspective view showing the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0009] Figure 3 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0010] Figure 4 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0011] Figure 5 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0012] Figure 6 (a) Figure 6 (b) is a cross-sectional view showing the structure of a semiconductor device according to a comparative example of the first embodiment.

[0013] Figure 7It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0014] Figure 8 (a) Figure 8 (b) Figure 8 (c) is a cross-sectional view showing details of the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 9 (a) Figure 9 (b) is a graph showing the characteristics of the semiconductor device according to the first embodiment.

[0016] Figure 10 This is another graph related to the characteristics of the semiconductor device according to the first embodiment.

[0017] Figure 11 It is a cross-sectional view showing the structure of a semiconductor device according to a modification of the first embodiment.

[0018] Figure 12 (a) Figure 12 (b) is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment and the structure of a semiconductor device according to a modification of the second embodiment.

[0019] Figure 13 (a) Figure 13 (b) Figure 13 (c) Figure 13 (d) is a cross-sectional view showing the method for manufacturing the semiconductor device according to the second embodiment.

[0020] Figure 14 It is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment.

[0021] Figure 15 It is a cross-sectional view showing the structure of a columnar portion according to a third embodiment.

[0022] Figure 16 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment.

[0023] Figure 17 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment. DETAILED DESCRIPTION

[0024] The following describes embodiments of the present invention with reference to the accompanying drawings. These embodiments do not limit the present invention. The accompanying drawings are schematic or conceptual diagrams, and the ratios of the various components may not necessarily be the same as in the actual device. In the specification and drawings, elements identical to those described above for the accompanying drawings are denoted by the same reference numerals, and detailed descriptions are omitted as appropriate.

[0025] (First embodiment)

[0026] Figure 1 This is a perspective view showing the structure of a semiconductor device according to Embodiment 1. The semiconductor device according to this embodiment includes, for example, a three-dimensional semiconductor memory.

[0027] The semiconductor device of this embodiment includes a core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, a blocking insulating film 5, and an electrode layer 6. The blocking insulating film 5 includes an insulating film 5a and an insulating film 5b. The electrode layer 6 includes a barrier metal layer 6a and an electrode material layer 6b. The electrode layer 6 is an example of a first wiring layer. The barrier metal layer 6a is an example of a first layer. The electrode material layer 6b is an example of a second and third layer, and is an example of a wiring material layer within the first wiring layer.

[0028] Figure 1 In the embodiment, a plurality of electrode layers and a plurality of insulating films are alternately stacked on a substrate, and memory holes Ha are provided in these electrode layers and insulating films. Figure 1 One electrode layer 6 among these electrode layers is shown. These electrode layers function as word lines of a three-dimensional semiconductor memory, for example. Figure 1 The X and Y directions are parallel to and perpendicular to the substrate surface, as well as the Z direction, which is perpendicular to the substrate surface. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0029] A core insulating film 1, a channel semiconductor layer 2, a tunnel insulating film 3, a charge storage layer 4, and an insulating film 5a are formed within the memory hole Ha, constituting a memory cell of a three-dimensional semiconductor memory. The insulating film 5a is formed on the sides of the electrode layer and the insulating film within the memory hole Ha, and the charge storage layer 4 is formed on the sides of the insulating film 5a. The charge storage layer 4 is capable of storing signal charges for the three-dimensional semiconductor memory. The tunnel insulating film 3 is formed on the sides of the charge storage layer 4, and the channel semiconductor layer 2 is formed on the sides of the tunnel insulating film 3. The channel semiconductor layer 2 functions as a channel for the three-dimensional semiconductor memory. The core insulating film 1 is formed on the sides of the channel semiconductor layer 2. The insulating film 5a is an example of a third insulating film. The tunnel insulating film 3 is an example of a fourth insulating film.

[0030] The insulating film 5a is, for example, a SiO2 film (silicon oxide film). The charge storage layer 4 is, for example, a SiN film (silicon nitride film). The tunnel insulating film 3 is, for example, a SiO2 film. The channel semiconductor layer 2 is, for example, a polysilicon layer. The core insulating film 1 is, for example, a SiO2 film.

[0031] The insulating film 5b, barrier metal layer 6a, and electrode material layer 6b are formed between two of the plurality of insulating films, and are sequentially formed on the lower surface of the upper insulating film, the upper surface of the lower insulating film, and the side surfaces of the insulating film 5a. The plurality of insulating films or barrier insulating films 5 are examples of first insulating films. Alternatively, the plurality of insulating films are examples of second insulating films.

[0032] The insulating film 5b is, for example, an Al2O3 film (aluminum oxide film). The barrier metal layer 6a is, for example, a W (tungsten) layer containing N (nitrogen) atoms as impurity atoms. The electrode material layer 6b is, for example, a W layer. Further details about the barrier metal layer 6a and the electrode material layer 6b will be described below.

[0033] Figures 2 to 5 It is a cross-sectional view showing the method for manufacturing the semiconductor device according to the first embodiment.

[0034] First, a substrate 11 is prepared, and a stacked film 12 ( Figure 2 The laminated film 12 is formed by alternately laminating a plurality of sacrificial layers 13 and a plurality of insulating films 14 on a substrate 11. The laminated film 12 can be formed directly on the substrate 11 or formed on the substrate 11 via other layers. The substrate 11 is, for example, a semiconductor substrate such as a Si (silicon) substrate. The sacrificial layer 13 is, for example, a SiN film. The insulating film 14 is, for example, a SiO2 film. The sacrificial layer 13 is an example of the fourth layer. The insulating film 14 is an example of the first and second insulating films.

[0035] Next, a plurality of memory holes Ha ( Figure 2 ). Figure 2 One of these memory holes Ha is shown. Each memory hole Ha of the present embodiment has a circular shape in a plan view and penetrates the build-up film 12 .

[0036] Next, an insulating film 5a, a charge storage layer 4, a tunnel insulating film 3, a channel semiconductor layer 2, and a core insulating film 1 are sequentially formed on the side of the stacked film 12 in each memory hole Ha. Figure 3 The insulating film 5a, the charge storage layer 4, the tunnel insulating film 3, and the channel semiconductor layer 2 are formed to have a tubular shape extending along the Z direction. The core insulating film 1 is formed to have a columnar shape extending along the Z direction.

[0037] Next, a plurality of slits (not shown) are formed in the laminated film 12, and the sacrificial layer 13 is removed from these slits using a solution such as a phosphoric acid solution. As a result, a plurality of recesses Hb ( Figure 4). The recess Hb is an example of a first recess.

[0038] Next, an insulating film 5b, a barrier metal layer 6a, and an electrode material layer 6b are sequentially formed on the surfaces of the insulating films 5a and 14 in each recess Hb. Figure 5 ). As a result, a barrier insulating film 5 including insulating films 5a and 5b is formed. Furthermore, an electrode layer 6 including a barrier metal layer 6a and an electrode material layer 6b is formed in each recess Hb. Furthermore, a laminated film 12 is formed on the substrate 11, alternately including a plurality of electrode layers 6 and a plurality of insulating films 14. In this manner, a replacement step is performed to replace (substitute) the sacrificial layer 13 with the electrode layer 6. The insulating film 14 and the barrier insulating film 5 are examples of a first insulating film.

[0039] Each recess Hb is formed between two adjacent insulating films 14 in the Z direction. Within each recess Hb, the insulating film 5b, barrier metal layer 6a, and electrode material layer 6b are sequentially formed on the lower surface of the upper insulating film 14, the upper surface of the lower insulating film 14, and the side surfaces of the insulating film 5a. As a result, each electrode layer 6 is formed between the insulating films 14 via the insulating film 5b. Meanwhile, within each memory hole Ha after the replacement process, the charge storage layer 4 is provided on the side surfaces of the multiple electrode layers 6 via the insulating film 5a, and the channel semiconductor layer 2 is provided on the side surfaces of the charge storage layer 4 via the tunnel insulating film 3.

[0040] In this way, the semiconductor device ( Figure 5 ). Figure 1 Shown Figure 5 A portion of a semiconductor device is shown.

[0041] Next, refer to Figure 6 and Figure 7 , the first embodiment is compared with the comparative example.

[0042] Figure 6 It is a cross-sectional view showing the structure of a semiconductor device according to a comparative example of the first embodiment.

[0043] Figure 6 (a) shows the structure of the semiconductor device of this comparative example. Figure 6 (a) with Figure 5 Similarly, the charge storage layer 4, the blocking insulating film 5, the electrode layer 6, the insulating film 14, etc. are shown. However, the electrode layer 6 of this comparative example includes a barrier metal layer 6a' instead of the barrier metal layer 6a. Figure 6 (a) also shows the gap Ga formed in the electrode material layer 6b when the electrode material layer 6b is formed. The gap Ga becomes an air gap extending substantially parallel to the XY plane. Figure 6As shown in (a), the electrode material layer 6b of this comparative example includes metal layers 21 and 22 formed in sequence on the side surface, upper surface, and lower surface of the barrier metal layer 6a'.

[0044] Barrier metal layer 6a' is, for example, a TiN film (titanium nitride film). Metal layers 21 and 22 are, for example, W layers. In this comparative example, barrier metal layer 6a' and metal layer 22 are polycrystalline layers, while metal layer 21 is an amorphous layer. Therefore, the resistivity of metal layer 22 is lower than that of metal layer 21.

[0045] In this comparative example, metal layer 21 is formed using WF6 gas and B2H6 gas, and metal layer 22 is formed using WF6 gas and H2 gas (W represents tungsten, F represents fluorine, B represents boron, and H represents hydrogen). Therefore, metal layers 21 and 22 contain F atoms as impurity atoms.

[0046] Figure 6 (b) is a cross-sectional view for explaining the problem of the semiconductor device of this comparative example. In this comparative example, if the thickness of the electrode layer 6 is reduced in order to miniaturize the semiconductor device, it is difficult to form a semiconductor layer in the recess Hb (refer to FIG. Figure 5 ) embedded in the electrode material layer 6b, which easily forms a large gap Ga within the electrode material layer 6b. The concentration of F atoms in the electrode layer 6 increases at the surface of the electrode layer 6, so the F atoms in the electrode layer 6 are present in high concentration on the surface of the electrode layer 6 facing the gap Ga. As a result, the F atoms in the electrode layer 6 are easily diffused through the gap Ga, which may cause semiconductor device defects (such as insulation defects). Therefore, it is desirable to suppress the diffusion of F atoms by using the barrier metal layer 6a'. Figure 6 The arrows shown in (b) indicate how F atoms diffuse from the electrode layer 6 to other layers (eg, the insulating film 14 ).

[0047] Figure 7 It is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0048] like Figure 7 As shown, the electrode layer 6 of this embodiment includes a barrier metal layer 6a. Furthermore, the electrode material layer 6b of this embodiment includes metal layers 25 and 26 formed sequentially on the side, top, and bottom surfaces of the barrier metal layer 6a. The barrier metal layer 6a is an example of the first layer. The metal layer 25 is an example of the third layer. The metal layer 26 is an example of the second layer.

[0049] The barrier metal layer 6a of this embodiment contains W (tungsten) atoms and N (nitrogen) atoms. As described above, the barrier metal layer 6a is, for example, a W layer containing N atoms as impurity atoms. That is, the barrier metal layer 6a contains, for example, W as a main component. In addition, the W layer containing N atoms as impurity atoms is expressed as a W(N) layer. As described below, when the composition ratio of W atoms to N atoms in the WN film is 6:4, the ratio k of the number of N atoms n2 in the W(N) layer of this embodiment to the sum of the number of W atoms n1 and the number of N atoms n2 is less than 40% (that is, k=n2 / (n1+n2)<0.40). In addition, the ratio of the number of W atoms in the barrier metal layer 6a of this embodiment to the number of all atoms is greater than 60%. In this embodiment, the barrier metal layer 6a is a crystalline layer, for example, a polycrystalline layer.

[0050] The metal layer 25 is, for example, a W layer. The metal layer 26 is, for example, a W layer. The metal layers 25 and 26 may or may not contain N atoms as impurity atoms. However, even when the metal layer 26 contains N atoms as impurity atoms, the N concentration in the barrier metal layer 6a of this embodiment is higher than the N concentration in the metal layer 26. The N concentration in the metal layer 26 is, for example, 7.0×10 19 ~2.0×20 20 atoms / cm 3 Similarly, even when metal layer 25 contains nitrogen atoms as impurity atoms, the nitrogen concentration in barrier metal layer 6a of this embodiment is higher than the nitrogen concentration in metal layer 25. In this embodiment, metal layer 26 is a polycrystalline layer, and metal layer 25 is an amorphous layer. Therefore, the resistivity of metal layer 26 is lower than that of metal layer 25.

[0051] For example, as described below, a WN film is formed by CVD (Chemical Vapor Deposition), and the barrier metal layer 6a is formed by annealing the WN film to a W(N) layer. In this embodiment, the WN film is annealed (H2 annealing) using a specific gas, such as H2 (hydrogen). The specific gas can be, for example, Ar (argon) or N2 (nitrogen). The annealing is performed at a temperature higher than 400°C, ideally at a temperature higher than 500°C. In this embodiment, the WN film, which is an amorphous layer, is crystallized by the annealing and becomes a crystalline layer, i.e., a W(N) layer (barrier metal layer 6a). The annealing is performed at a temperature higher than 400°C and lower than 1050°C, for example. The duration of the annealing is, for example, 1 hour, but it can also be other times. In this embodiment, a W(N) layer (barrier metal layer 6a) having a k ratio less than 40% is formed from a WN film having a k ratio of 40%. The N concentration in this W(N) layer is lower than the N concentration in the WN film. This WN film is an example of the first layer.

[0052] The WN film used to form the barrier metal layer 6a is formed using, for example, a source gas containing W and a reducing gas containing N. The source gas is, for example, WF6 gas. The reducing gas is, for example, NH3 (ammonia gas). In this case, the WN film or the W(N) layer (barrier metal layer 6a) formed from the WN film may contain F atoms and H atoms as impurity atoms. The source gas may also contain halogens other than F, for example, Cl (chlorine). For example, when WOCl4 gas and NH3 gas are used to form the WN film, the WN film or the W(N) layer may contain Cl atoms, O atoms, and H atoms as impurity atoms (O represents oxygen). In addition, the WN film used to form the barrier metal layer 6a may also be formed by methods other than CVD. The WN film used to form the barrier metal layer 6a may also be formed by, for example, ALD (Atomic Layer Deposition).

[0053] The metal layer 25 is formed, for example, using a source gas containing W and F and a reducing gas containing B and H. The source gas is, for example, WF6 gas. The reducing gas is, for example, B2H6 gas. In this case, the metal layer 25 may contain F atoms, B atoms, and H atoms as impurity atoms. The source gas may also contain halogens other than F, for example, Cl. An example of such a source gas is WOCl4 gas. In this case, the metal layer 25 may contain Cl atoms and O atoms as impurity atoms. On the other hand, the reducing gas may also contain Si instead of B. An example of such a reducing gas is SiH4 gas or Si2H6 gas. In this case, the metal layer 25 may contain Si atoms and H atoms as impurity atoms.

[0054] Metal layer 26 is formed, for example, using a source gas containing W and F and a reducing gas containing H. The source gas is, for example, WF6 gas. The reducing gas is, for example, H2 gas. In this case, metal layer 26 may contain F atoms and H atoms as impurity atoms. The source gas may also contain halogens other than F, for example, Cl. An example of such a source gas is WOCl4 gas. In this case, metal layer 26 may contain Cl atoms and O atoms as impurity atoms.

[0055] According to the present embodiment, by forming the electrode layer 6 using a W(N) layer (barrier metal layer 6a), the metal layer 25 can be made thinner compared to the case where the barrier metal layer is a TiN film. Thus, by thinning the metal layer 25 as a high-resistance layer, the resistance of the electrode layer 6 can be reduced. In addition, the W(N) layer is more effective in suppressing the diffusion of F atoms than the WN film. Therefore, according to the present embodiment, by forming the electrode layer 6 using a W(N) layer, the diffusion of F atoms can be effectively suppressed. For example, the F (fluorine) concentration of the insulating film 14 when the W(N) layer is used is less than 1 / 3 of the F concentration of the insulating film 14 when the W(N) layer is not used. Thus, it can be seen that the W(N) layer suppresses the diffusion of F atoms. This also applies to halogen atoms other than F atoms. Further details on this content will be described below.

[0056] Figure 8 1 is a cross-sectional view showing details of the method for manufacturing a semiconductor device according to the first embodiment. Figure 8 Shows the formation Figure 7 The process of the structure shown.

[0057] When forming the electrode layer 6 in each recess Hb, first, a barrier metal layer 6c ( Figure 8 (a)). The barrier metal layer 6c is, for example, a WN film. The barrier metal layer 6c of this embodiment is formed by CVD using WF6 gas and NH3 gas. The composition ratio of W atoms to N atoms in the barrier metal layer 6c is 6:4. Therefore, the ratio k of the number of N atoms n2 in the barrier metal layer 6c to the sum of the number of W atoms n1 and the number of N atoms n2 is 40% (that is, k = n2 / (n1 + n2) = 0.40). The barrier metal layer 6c is an example of the first layer.

[0058] Next, the barrier metal layer 6c is annealed ( Figure 8(b)). For example, the annealing is performed at a temperature higher than 400°C using a specific gas (such as H2 gas, Ar gas, or N2 gas). For example, the annealing is performed at a temperature higher than 500°C and lower than 1050°C. As a result, the barrier metal layer 6c becomes the barrier metal layer 6a. The barrier metal layer 6a is, for example, a W(N) layer, that is, a W layer containing N atoms as impurity atoms. In this embodiment, the WN film (barrier metal layer 6c) as an amorphous layer is crystallized by the annealing and becomes a crystalline layer, namely, a W(N) layer (barrier metal layer 6a). In this embodiment, a barrier metal layer 6a with a ratio k of less than 40% is formed from a barrier metal layer 6c with a ratio k of 40%, and the N concentration in the barrier metal layer 6a is lower than the N concentration in the barrier metal layer 6c. The barrier metal layer 6a after annealing may also have an N (nitrogen) concentration gradient. Figure 8 In (b), the barrier metal layer 6 c is annealed while the barrier metal layer 6 c is exposed in the recessed portion Hb.

[0059] Next, a metal layer 25 ( Figure 8 (c)). Metal layer 25 is, for example, a W layer containing W as a main component, and is formed using WF6 gas and B2H6 gas. In this embodiment, metal layer 25 is formed as an amorphous layer, for example, at a temperature below 300°C (preferably below 200°C). Metal layer 25 in this embodiment is formed as the initial film of electrode material layer 6b. Furthermore, the N concentration in barrier metal layer 6a in this embodiment is higher than the N concentration in metal layer 25.

[0060] Next, a metal layer 26 ( Figure 8 (c)). The metal layer 26 is, for example, a W layer containing W as a main component, and is formed using WF6 gas and H2 gas. The metal layer 26 of this embodiment is formed as a polycrystalline layer at, for example, 450°C. In this embodiment, the metal layer 26 is formed at a temperature higher than the temperature at which the metal layer 25 is formed. The metal layer 26 can also be formed to contain gap Ga. The metal layer 26 is, for example, a LFW (Low-Fluorine Tungsten) layer or a CVD-W (Chemical-Vapor-Deposition Tungsten) layer. The metal layer 26 of this embodiment forms the electrode material layer 6b together with the metal layer 25. In addition, the N concentration in the barrier metal layer 6a of this embodiment is higher than the N concentration in the metal layer 26. The metal layer 26 has an N concentration of, for example, 7.0×10 19 ~2.0×20 20 atoms / cm 3In addition, the N concentration is, for example, a value measured by SIMS (Secondary Ion Mass Spectrometry) analysis.

[0061] In this embodiment, the metal layer 25 may be transformed from an amorphous layer to a polycrystalline layer during or after the formation of the metal layer 26. In this case, the metal layer 25 is crystallized by annealing at, for example, 600° C. or higher, preferably 750° C. or higher, thereby transforming from an amorphous layer to a polycrystalline layer.

[0062] Figure 9 This is a graph related to the characteristics of the semiconductor device according to the first embodiment.

[0063] Figure 9 (a) shows the results of XPS (X-ray Photoelectron Spectroscopy) analysis of the barrier metal layer 6a. The horizontal axis represents the annealing temperature of the barrier metal layer 6c. The vertical axis represents the intensity associated with nitrogen atoms within the barrier metal layer 6a (N intensity). As the nitrogen concentration within the barrier metal layer 6a decreases, the N intensity decreases. Figure 9 (a) shows the XPS analysis results of the W (N) layer when annealing is performed using H 2 gas or Ar (argon) gas as the specific gas.

[0064] according to Figure 9 (a) It can be seen that the N concentration in the barrier metal layer 6a will decrease regardless of whether H2 gas or Ar gas is used for annealing. Furthermore, it can be seen that the N concentration in the barrier metal layer 6a is even lower if H2 gas is used for annealing. Therefore, it is ideal that the barrier metal layer 6c of this embodiment is annealed using H2 gas. In addition, according to Figure 9 (a) It can be seen that the N intensity associated with the W (N) layer annealed using H2 gas begins to decrease at 400°C, and the N intensity at 500°C is significantly lower than that at 400°C. Therefore, the barrier metal layer 6c of this embodiment is annealed at a temperature higher than 400°C, and ideally at a temperature higher than 500°C.

[0065] exist Figure 9 In (a), the N intensity of the barrier metal layer 6a annealed at 500°C or higher is higher than the N intensity of the LFW layer (metal layer 26). In this case, the N concentration in the barrier metal layer 6a is higher than the N concentration in the LFW layer. As described above, the ratio k of the barrier metal layer 6a of this embodiment is less than 40%, and is preferably 10% or less. The ratio k of the barrier metal layer 6a of this embodiment is, for example, 5% or less. Figure 9As shown in (a), the N concentration in the barrier metal layer 6a can be significantly reduced by annealing at a temperature above 500°C using H2 gas, so a barrier metal layer 6a with a ratio k of less than 10% or less than 5% can be achieved, for example, by annealing at a temperature above 500°C using H2 gas.

[0066] Figure 9 (b) shows the X-ray scattering results related to the barrier metal layer 6a. The horizontal axis represents the scattering angle (2θ), and the vertical axis represents the scattering intensity. Figure 9 (b) shows the X-ray scattering results when the barrier metal layer 6 c is annealed at 300° C., 400° C., 500° C., 580° C., or 650° C. using H 2 gas. Figure 9 (b) also shows the X-ray scattering results of the LFW layer (metal layer 26) as a comparative example.

[0067] according to Figure 9 (b) It can be seen that when the annealing temperature is 500°C or higher, a scattering peak of X-ray scattering can be observed. Therefore, it can be seen that the barrier metal layer 6a of this embodiment is a crystalline layer, and the tungsten contained in the barrier metal layer 6a of this embodiment has a crystalline structure with a (110) plane orientation. In addition, according to Figure 9 (b) It can be seen that the LFW layer (metal layer 26) of this embodiment is also a crystalline layer.

[0068] Figure 10 This is another graph related to the characteristics of the semiconductor device according to the first embodiment.

[0069] Figure 10 The XPS analysis results for the barrier metal layer 6a are shown. The horizontal axis represents the annealing temperature of the barrier metal layer 6c. The vertical axis represents the intensity associated with the F atoms in the barrier metal layer 6a (F intensity). As the F concentration in the barrier metal layer 6a decreases, the F intensity decreases. Figure 10 The XPS analysis results are shown when annealing is performed using H 2 gas or Ar gas as the specific gas.

[0070] according to Figure 10 It can be seen that if H2 gas is used for annealing, the F concentration in the barrier metal layer 6a can be reduced to approximately the same level as the F concentration in the LFW layer (metal layer 26) by annealing at 500°C. Therefore, annealing at 500°C or higher is effective not only in reducing the N concentration in the barrier metal layer 6a, but also in reducing the F concentration in the barrier metal layer 6a.

[0071] Figure 11 It is a cross-sectional view showing the structure of a semiconductor device according to a modification of the first embodiment.

[0072] The semiconductor device of this variation ( Figure 11) is similar to the semiconductor device of the first embodiment ( Figure 7 ) has the same structure. However, the electrode material layer 6b of the first embodiment includes the metal layers 25 and 26, whereas the electrode material layer 6b of this variation includes only the metal layer 26. The semiconductor device of this variation can be used, for example Figure 8 (a)~ Figure 8 The method shown in (c) is manufactured by omitting the step of forming the metal layer 25 .

[0073] As described above, each electrode layer 6 in this embodiment includes a barrier metal layer 6a serving as a W(N) layer and an electrode material layer 6b (metal layers 25 and 26) serving as a W layer. Therefore, this embodiment enables the formation of an electrode layer 6 having suitable characteristics. For example, the resistance of the electrode layer 6 can be reduced, or the diffusion of F atoms from the electrode layer 6 to other layers can be suppressed.

[0074] (Second embodiment)

[0075] Figure 12 sectional views showing the structure of the semiconductor device according to the second embodiment and the structure of a semiconductor device according to a modification of the second embodiment.

[0076] Figure 12 (a) shows a semiconductor device according to a second embodiment. The semiconductor device of this embodiment includes an interlayer insulating film 31 formed on the substrate 11, and a wiring layer 32 formed within the interlayer insulating film 31. The wiring layer 32 is, for example, one of a plurality of wiring layers forming the multilayer wiring structure of the semiconductor device of this embodiment, and includes one or more wirings. Figure 12 (a) shows one of these wirings. The wiring layer 32 may also be a plug layer including one or more contact plugs or one or more via plugs. The interlayer insulating film 31 is an example of a first insulating film. The wiring layer 32 is an example of a first wiring layer.

[0077] Figure 12 The wiring layer 32 shown in (a) includes a barrier metal layer 32a and a wiring material layer 32b formed in this order within an interlayer insulating film 31. The barrier metal layer 32a is formed on the side surfaces and top surface of the interlayer insulating film 31. The wiring material layer 32b includes a metal layer 42 formed on the side surfaces and top surface of the barrier metal layer 32a. Figure 12 (a) also shows a gap Gb formed in the metal layer 42 when the metal layer 42 is formed. The gap Gb is an air gap extending substantially parallel to the Z direction. The barrier metal layer 32a is an example of the first layer. The metal layer 42 is an example of the second layer.

[0078] The barrier metal layer 32a of this embodiment corresponds to the barrier metal layer 6a of the first embodiment and is formed using the same method as the barrier metal layer 6a of the first embodiment. Therefore, the barrier metal layer 32a is, for example, a W(N) layer and has the same N concentration as the barrier metal layer 6a.

[0079] The metal layer 42 of this embodiment corresponds to the metal layer 26 of the first embodiment and is formed by the same method as the metal layer 26 of the first embodiment. Therefore, the metal layer 42 is, for example, a W layer and has the same N concentration as the metal layer 26.

[0080] In addition, the wiring layer 32 of this embodiment does not include a metal layer corresponding to the metal layer 26 of the first embodiment. Therefore, the wiring layer 32 of this embodiment has Figure 11 The electrode layer 6 of the modified example of the first embodiment shown has the same structure.

[0081] Figure 12 (b) shows a semiconductor device according to a variation of the second embodiment. Figure 12 The structure of the semiconductor device of the second embodiment shown in (a) is the same. However, the wiring material layer 32b of this variation includes a metal layer 41 between the barrier metal layer 32a and the metal layer 42. The metal layer 41 is an example of a third layer.

[0082] The metal layer 41 of this variation corresponds to the metal layer 25 of the first embodiment and is formed by the same method as the metal layer 25 of the first embodiment. Therefore, the metal layer 41 is, for example, a W layer and has the same N concentration as the metal layer 25.

[0083] Figure 13 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to the second embodiment.

[0084] First, an interlayer insulating film 31 is formed on the substrate 11, and a wiring trench Hc ( Figure 13 (a) The interlayer insulating film 31 may be formed directly on the substrate 11 or may be formed on the substrate 11 via another layer. The wiring trench Hc is an example of a first recess.

[0085] Next, a barrier metal layer 32c ( Figure 13(b)). The barrier metal layer 32c is, for example, a WN film. The barrier metal layer 32c of this embodiment is formed by CVD using WF6 gas and NH3 gas, and the composition ratio of W atoms to N atoms in the barrier metal layer 32c is 6:4. Therefore, the ratio k of the number n2 of N atoms in the barrier metal layer 32c to the sum of the number n1 of W atoms and the number n2 of N atoms is 40% (that is, k = n2 / (n1+n2) = 0.40). The barrier metal layer 32c is an example of the first layer. In addition, the illustration of the barrier metal layer 32c formed outside the wiring trench Hc is omitted.

[0086] Next, the barrier metal layer 32c is annealed ( Figure 13 (c)). For example, the annealing is performed at a temperature higher than 400°C using a specific gas (for example, H2 gas). For example, the annealing is performed at a temperature higher than 500°C and lower than 1050°C. As a result, the barrier metal layer 32c is transformed into the barrier metal layer 32a. The barrier metal layer 32a is, for example, a W(N) layer, that is, a W layer containing N atoms as impurity atoms. In the present embodiment, the WN film (barrier metal layer 32c), which is an amorphous layer, is crystallized by the annealing and becomes a crystalline layer, that is, a W(N) layer (barrier metal layer 32a). In the present embodiment, a barrier metal layer 32a having a ratio k of 40% is formed to have a ratio k less than 40%, and the N concentration in the barrier metal layer 32a is lower than the N concentration in the barrier metal layer 32c.

[0087] Next, a metal layer 42 (wiring material layer 32b) is formed on the side and upper surface of the barrier metal layer 32a in the wiring trench Hc ( Figure 13 (c)). The metal layer 42 is, for example, a W layer containing W as a main component, and is formed using WF6 gas and H2 gas. The metal layer 42 of this embodiment is formed as a polycrystalline layer at 450°C, for example. The metal layer 42 may also be formed to include gaps Gb. The metal layer 42 is, for example, an LFW layer or a CVD-W layer. The N concentration in the barrier metal layer 32a of this embodiment is higher than the N concentration in the metal layer 42. The metal layer 42 has an N concentration of, for example, 7.0×10 19 ~2.0×20 20 atoms / cm 3 In addition, the metal layer 42 formed outside the wiring groove Hc is omitted from the illustration.

[0088] Then, the barrier metal layer 32a and the metal layer 42 formed outside the wiring trench Hc are removed by, for example, CMP (Chemical Mechanical Polishing). As a result, the wiring layer 32 including the barrier metal layer 32a and the metal layer 42 is formed in the wiring trench Hc.

[0089] In this way, manufacturing Figure 12 (a) shows a semiconductor device of the second embodiment. Figure 12 In the semiconductor device of the modified example of the second embodiment shown in (b), the metal layer 41 is formed after the barrier metal layer 32a is formed and before the metal layer 42 is formed. The method for forming the metal layer 41 is the same as that of the Figure 8 The method for forming the metal layer 25 in the step (c) is the same.

[0090] As described above, the wiring layer 32 of this embodiment includes the barrier metal layer 32a, which is a W(N) layer, and the wiring material layer 32b, which is a W layer. Therefore, according to this embodiment, a wiring layer 32 having suitable characteristics can be formed. For example, similar to the electrode layer 6 of the first embodiment, the resistance of the wiring layer 32 can be reduced, or the diffusion of F atoms from the wiring layer 32 to other layers can be suppressed.

[0091] (Third embodiment)

[0092] Figure 14 This is a cross-sectional view showing the structure of a semiconductor device according to a third embodiment. The semiconductor device of this embodiment is, for example, a three-dimensional semiconductor memory device, and is manufactured by bonding an array wafer including an array region 101 to a circuit wafer including a circuit region 102. The relationship between this embodiment and the first and second embodiments will be described below.

[0093] Array region 101 includes a memory cell array 111 including a plurality of memory cells, an insulating film 112 overlying memory cell array 111, and an interlayer insulating film 113 under memory cell array 111. Insulating film 112 is, for example, a silicon oxide film or a silicon nitride film. Interlayer insulating film 113 is, for example, a silicon oxide film or a laminated film including a silicon oxide film and other insulating films.

[0094] The circuit region 102 is disposed under the array region 101 . Figure 14 The interface (bonding surface) S between the array region 101 and the circuit region 102 is shown. The circuit region 102 includes an interlayer insulating film 114 beneath an interlayer insulating film 113, and a substrate 115 beneath the interlayer insulating film 114. The interlayer insulating film 114 is, for example, a silicon oxide film or a laminated film comprising a silicon oxide film and other insulating films. The substrate 115 is, for example, a semiconductor substrate such as a silicon substrate.

[0095] Figure 14 The X and Y directions are parallel to and perpendicular to the surface of the substrate 115, and the Z direction is perpendicular to the surface of the substrate 115. In this specification, the +Z direction is considered the upward direction, and the -Z direction is considered the downward direction. The -Z direction may or may not coincide with the direction of gravity.

[0096] The array region 101 includes a plurality of word lines WL and source lines SL as a plurality of electrode layers within the memory cell array 111 . Figure 14 The figure shows a stepped structure 121 of the memory cell array 111. Each word line WL is electrically connected to a word wiring layer 123 via a contact plug 122. Each pillar CL, which passes through the word lines WL, is electrically connected to a bit line BL via a via plug 124 and to a source line SL. The source line SL includes a lower layer SL1, which is a semiconductor layer, and an upper layer SL2, which is a metal layer.

[0097] The circuit region 102 includes a plurality of transistors 131. Each transistor 131 includes a gate electrode 132 provided on a substrate 115 via a gate insulating film, and a source diffusion layer and a drain diffusion layer (not shown) provided within the substrate 115. The circuit region 102 further includes a plurality of contact plugs 133 provided on the gate electrodes 132, source diffusion layers, or drain diffusion layers of these transistors 131, and a wiring layer 134 provided on these contact plugs 133 and including a plurality of wiring lines.

[0098] Furthermore, circuit region 102 includes a wiring layer 135 disposed on wiring layer 134 and including a plurality of wiring lines, and a wiring layer 136 disposed on wiring layer 135 and also including a plurality of wiring lines. Circuit region 102 further includes a plurality of via plugs 137 disposed on wiring layer 136, and a plurality of metal pads 138 disposed on these via plugs 137. Metal pads 138 are, for example, a metal layer comprising a Cu (copper) layer. Circuit region 102 functions as a control circuit (logic circuit) that controls the operation of array region 101. This control circuit is comprised of transistors 131 and the like and is electrically connected to metal pads 138.

[0099] Array region 101 includes a plurality of metal pads 141 disposed on metal pads 138, and a plurality of via plugs 142 disposed on metal pads 141. Metal pads 141 are, for example, a metal layer including a Cu layer. Array region 101 further includes a wiring layer 143 disposed on via plugs 142 and including a plurality of wiring lines, and a wiring layer 144 disposed on wiring layer 143 and including a plurality of wiring lines. The bit lines BL are included in wiring layer 144. The control circuit is electrically connected to memory cell array 111 via metal pads 141, 138, etc., and controls the operation of memory cell array 111 via metal pads 141, 138, etc.

[0100] Array region 101 also includes a plurality of via plugs 145 disposed on wiring layer 144, metal pads 146 disposed on these via plugs 145 and insulating film 112, and a passivation insulating film 147 disposed on metal pads 146 and insulating film 112. Metal pads 146 are, for example, a metal layer including a Cu layer, and function as external connection pads (bonding pads) for the semiconductor device of this embodiment. Passivation insulating film 147 is, for example, a laminated film including a silicon oxide film and a silicon nitride film, and has openings P that expose the top surfaces of metal pads 146. Metal pads 146 can be electrically connected to a mounting substrate or other devices via bonding wires, solder balls, metal bumps, or the like through openings P.

[0101] Figure 15 It is a cross-sectional view showing the structure of a columnar portion CL according to the third embodiment. Figure 15 Shown Figure 14 One of the multiple columnar portions CL shown.

[0102] like Figure 15 As shown, the memory cell array 111 includes layers alternately stacked on an interlayer insulating film 113 (see Figure 14 ) and a plurality of word lines WL and a plurality of insulating films 151. The word lines WL are, for example, a metal layer including a W layer, etc. The insulating film 151 is, for example, a silicon oxide film.

[0103] The columnar portion CL includes, in this order, a blocking insulating film 152, a charge storage layer 153, a tunnel insulating film 154, a channel semiconductor layer 155, and a core insulating film 156. The charge storage layer 153 is, for example, an insulating film such as a silicon nitride film, and is formed on the sides of the word line WL and the insulating film 151 via the blocking insulating film 152. The channel semiconductor layer 155 is, for example, a polysilicon layer, and is formed on the sides of the charge storage layer 153 via the tunnel insulating film 154. The blocking insulating film 152, the tunnel insulating film 154, and the core insulating film 156 are, for example, silicon oxide films.

[0104] Figure 16 and Figure 17 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to a third embodiment.

[0105] Figure 16 The array wafer W1 and the circuit wafer W2 are shown. Specifically, Figure 16 One of the plurality of array regions 101 included in the array wafer W1 and one of the plurality of circuit regions 102 included in the circuit wafer W2 are shown.

[0106] Figure 16 The direction of the array wafer W1 is Figure 14The direction of the array region 101 is opposite. In this embodiment, a plurality of semiconductor devices are manufactured by bonding the array wafer W1 and the circuit wafer W2 together. Figure 16 1 shows the array wafer W1 before being reversed for bonding. Figure 14 Array region 101 is shown after being reversed for lamination and after lamination and dicing.

[0107] Figure 16 Also shown are the upper surface S1 of the array wafer W1 and the upper surface S2 of the circuit wafer W2. The array wafer W1 includes a substrate 116 provided under an insulating film 112. The substrate 116 is, for example, a semiconductor substrate such as a silicon substrate.

[0108] In this embodiment, first, Figure 16 As shown, a memory cell array 111, an insulating film 112, an interlayer insulating film 113, a stepped structure portion 121, a metal pad 141, etc. are formed on the substrate 116 of the array wafer W1, and an interlayer insulating film 114, a transistor 131, a metal pad 138, etc. are formed on the substrate 115 of the circuit wafer W2. For example, a dielectric plug 145, a wiring layer 144, a wiring layer 143, a dielectric plug 142, and a metal pad 141 are sequentially formed on the substrate 116. In addition, a contact plug 133, a wiring layer 134, a wiring layer 135, a wiring layer 136, a dielectric plug 137, and a metal pad 138 are sequentially formed on the substrate 115. Next, as shown in FIG. Figure 17 As shown, the array wafer W1 and the circuit wafer W2 are bonded together using mechanical pressure. This bonds the interlayer insulating film 113 to the interlayer insulating film 114. Next, the array wafer W1 and the circuit wafer W2 are annealed. This bonds the metal pad 141 to the metal pad 138.

[0109] Then, the substrate 115 is thinned by CMP, and after the substrate 116 is removed by CMP, the array wafer W1 and the circuit wafer W2 are cut into a plurality of chips. Figure 14 Furthermore, the metal pad 146 and the passivation insulating film 147 are formed on the insulating film 112 after, for example, the substrate 115 is thinned and the substrate 116 is removed.

[0110] also, Figure 14 The interface between interlayer insulating film 113 and interlayer insulating film 114, and the interface between metal pad 141 and metal pad 138 are shown. However, these interfaces are generally no longer observable after the annealing. However, the locations of these interfaces can be estimated by, for example, detecting the inclination of the side surface of metal pad 141 or the side surface of metal pad 138, or the positional offset between the side surfaces of metal pad 141 and metal pad 138.

[0111] Next, the relationship between this embodiment and the first and second embodiments will be described.

[0112] Each word line WL of this embodiment can also be formed by, for example, the same method as the electrode layer 6 of the first embodiment. This can reduce the resistance of the word line WL or suppress the diffusion of F atoms from the word line WL to other layers. In this case, the substrate 116, insulating film 151, blocking insulating film 152, charge storage layer 153, tunnel insulating film 154, channel semiconductor layer 155, and core insulating film 156 of this embodiment correspond to the substrate 11, insulating film 14, blocking insulating film 5, charge storage layer 4, tunnel insulating film 3, channel semiconductor layer 2, and core insulating film 1 of the first embodiment, respectively. However, since the substrate 116 of this embodiment is removed after the array wafer W1 and the circuit wafer W2 are bonded together, it does not remain in the manufactured semiconductor device.

[0113] In addition, at least any one of the wiring layers 134, 135, 136, 143, and 144 of this embodiment can also be formed by, for example, the same method as the wiring layer 32 of the second embodiment. This can reduce the resistance of the wiring layer or suppress the diffusion of F atoms from the wiring layer to other layers. In this case, the substrate 116 or substrate 115 of this embodiment corresponds to the substrate 11 of the second embodiment, and the interlayer insulating film 113 or interlayer insulating film 114 of this embodiment corresponds to the interlayer insulating film 31 of the second embodiment. However, since the substrate 116 of this embodiment is removed after the array wafer W1 and the circuit wafer W2 are bonded together, it will not remain in the manufactured semiconductor device.

[0114] As described above, according to this embodiment, similarly to the first and second embodiments, a wiring layer having appropriate characteristics can be formed.

[0115] While several embodiments of the present invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their variations are intended to be within the scope and spirit of the invention and are also intended to be within the scope of the invention set forth in the claims and their equivalents.

[0116] Explanation of symbols

[0117] 1: Core insulation film

[0118] 2: Channel semiconductor layer

[0119] 3: Tunnel insulating film

[0120] 4: Charge storage layer

[0121] 5: Barrier insulating film

[0122] 5a: Insulating film

[0123] 5b: Insulating film

[0124] 6: Electrode layer

[0125] 6a: Barrier metal layer

[0126] 6a': barrier metal layer

[0127] 6b: Electrode material layer

[0128] 6c: Barrier metal layer

[0129] 11: substrate

[0130] 12: Laminated film

[0131] 13: Sacrificial layer

[0132] 14: Insulation film

[0133] 21:Metal layer

[0134] 22:Metal layer

[0135] 23:Metal layer

[0136] 24:Metal layer

[0137] 25:Metal layer

[0138] 26:Metal layer

[0139] 31: Interlayer insulating film

[0140] 32: Wiring layer

[0141] 32a: Barrier metal layer

[0142] 32b: Wiring layer

[0143] 32c: barrier metal layer

[0144] 41:Metal layer

[0145] 42:Metal layer

[0146] 101: Array area

[0147] 102: Circuit area

[0148] 111: memory cell array

[0149] 112: Insulation film

[0150] 113: Interlayer insulating film

[0151] 114: Interlayer insulating film

[0152] 115: substrate

[0153] 116: substrate

[0154] 121: Step structure

[0155] 122: Contact plug

[0156] 123: word wiring layer

[0157] 124:Interface plug

[0158] 131: Transistor

[0159] 132: Gate electrode

[0160] 133: Contact plug

[0161] 134: Wiring layer

[0162] 135: Wiring layer

[0163] 136: Wiring layer

[0164] 137:Intermediate plug

[0165] 138:Metal pad

[0166] 141:Metal pad

[0167] 142:Intermediate plug

[0168] 143: Wiring layer

[0169] 144: Wiring layer

[0170] 145:Intermediate plug

[0171] 146:Metal pad

[0172] 147: Passivation insulating film

[0173] 151: Insulation film

[0174] 152: blocking insulating film

[0175] 153: Charge storage layer

[0176] 154: tunnel insulating film

[0177] 155: channel semiconductor layer

[0178] 156: core insulating film.

Claims

1. A method for manufacturing a semiconductor device, comprising: forming a first insulating film; forming a first layer including tungsten and nitrogen on the first insulating film; annealing the first layer while the first layer is exposed, thereby reducing the nitrogen concentration in the first layer; and A second layer containing tungsten is formed on the annealed first layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein The annealing is performed at a temperature higher than 400° C. and lower than 1050° C.

3. The method for manufacturing a semiconductor device according to claim 1, wherein The annealing is performed using hydrogen (H2) gas.

4. The method for manufacturing a semiconductor device according to claim 1, wherein The annealing is performed using argon (Ar) gas or nitrogen (N2) gas.

5. The method for manufacturing a semiconductor device according to claim 1, wherein The first layer before the annealing is a tungsten nitride (WN) film. The method for manufacturing a semiconductor device according to claim 1 , wherein The first layer is formed by chemical vapor deposition.

7. The method for manufacturing a semiconductor device according to claim 1, wherein The first layer is crystallized by the annealing.

8. The method for manufacturing a semiconductor device according to claim 1, wherein The tungsten contained in the first layer after the annealing has a crystal structure having a (110) plane.

9. The method for manufacturing a semiconductor device according to claim 1, wherein The first layer and the second layer are formed in such a manner that the nitrogen concentration in the first layer after the annealing is higher than the nitrogen concentration in the second layer, and in such a manner that the ratio of the number of nitrogen atoms in the first layer after the annealing to the sum of the number of tungsten atoms and the number of nitrogen atoms is less than 40%.

10. The method for manufacturing a semiconductor device according to claim 1, further comprising: forming a laminated film including a plurality of fourth layers and a plurality of second insulating films alternately; forming a charge storage layer on the side surfaces of the plurality of fourth layers via a third insulating film; forming a semiconductor layer on the side of the charge storage layer via a fourth insulating film; removing the plurality of fourth layers to form a plurality of first recesses in the laminated film; as well as forming a plurality of electrode layers in the plurality of first recesses; The first layer and the second layer are one electrode layer among the plurality of electrode layers.

11. A semiconductor device comprising: a first insulating film; and The first wiring layer includes: a first layer and a second layer, wherein the first layer is provided on the first insulating film and contains tungsten and nitrogen; and the second layer is provided on the first layer and contains tungsten. The nitrogen concentration in the first layer is higher than the nitrogen concentration in the second layer, The tungsten contained in the first layer has a crystal structure having a (110) plane.

12. The semiconductor device according to claim 11, wherein The first layer contains tungsten as a main component and nitrogen atoms as impurity atoms.

13. The semiconductor device according to claim 11, wherein The ratio of the number of nitrogen atoms in the first layer to the sum of the number of tungsten atoms and the number of nitrogen atoms is less than 40%.

14. The semiconductor device according to claim 11, wherein The nitrogen concentration in the second layer is: 7.0×10 19 ~2.0×20 20 atoms / cm 3 .

15. The semiconductor device according to claim 11, wherein The second layer further contains fluorine or chlorine.

16. The semiconductor device according to claim 11, wherein The first layer is a barrier metal layer, and the second layer is a wiring material layer.

17. The semiconductor device according to claim 11, wherein The first wiring layer further includes a third layer provided between the first layer and the second layer and including tungsten.

18. The semiconductor device according to claim 17, wherein The third layer further contains boron or silicon.

19. A semiconductor device comprising: A laminated film alternately including a plurality of electrode layers and a plurality of second insulating films; a charge storage layer provided on the side surfaces of the plurality of electrode layers via a third insulating film; and a semiconductor layer provided on a side of the charge storage layer via a fourth insulating film; One of the plurality of electrode layers includes a first layer and a second layer, wherein the first layer includes tungsten and nitrogen, and the second layer is provided on the first layer and includes tungsten. The nitrogen concentration in the first layer is higher than the nitrogen concentration in the second layer, The tungsten contained in the first layer has a crystal structure having a (110) plane.

20. The semiconductor device according to claim 19, wherein The one electrode layer among the plurality of electrode layers further includes a third layer provided between the first layer and the second layer and including tungsten.

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