Semiconductor device having improved channel structure and method of manufacturing the same

Abstract

The invention provides a semiconductor device with an improved channel structure and a method of manufacturing the semiconductor device. The semiconductor device includes: a substrate; a channel part on the substrate, wherein the channel part comprises a plurality of composite channel layers which are stacked at intervals along the vertical direction; the source / drain parts are respectively positioned on two sides of the channel part in the first direction; and a gate stack extending in a second direction intersecting the first direction and surrounding respective peripheries of the plurality of composite channel layers, in which each composite channel layer includes a first semiconductor layer and a second semiconductor layer surrounding a periphery of the first semiconductor layer, the first semiconductor layer includes an intrinsic semiconductor and the second semiconductor layer includes a heavily doped semiconductor.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device with an improved channel structure and a method for manufacturing the semiconductor device. Background Art

[0002] The rapid development of the Internet and related technologies has placed increasing demands on chip performance. The industry has proposed miniaturization to reduce the area of ​​a single device on the chip. As a result, field-effect transistors have evolved from the earliest planar logic devices to the era of three-dimensional logic devices such as FinFET (Fin Field-Effect Transistor) and GAA Nanosheet (Gate-All-Around Around Nanosheet).

[0003] In the process of realizing the concept of the present disclosure, the inventors discovered that the GAA Nanosheet in the related art suffers from the technical problem of a gradual decrease in the current switching ratio due to the miniaturization of the channel size. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device.

[0005] One aspect of the present disclosure provides a semiconductor device, comprising:

[0006] A substrate; a channel portion on the substrate, comprising a plurality of composite channel layers spaced apart and stacked along a vertical direction; source / drain portions, respectively located on both sides of the channel portion in a first direction; and a gate stack, extending in a second direction intersecting with the first direction and surrounding the periphery of each of the plurality of composite channel layers, wherein each composite channel layer comprises a first semiconductor layer and a second semiconductor layer surrounding the periphery of the first semiconductor layer, the first semiconductor layer comprises an intrinsic semiconductor and the second semiconductor layer comprises a heavily doped semiconductor.

[0007] According to an embodiment of the present disclosure, the doping concentration of the second semiconductor layer is 1×10 17 cm -3 ~5×10 21 cm -3 .

[0008] According to an embodiment of the present disclosure, the first semiconductor layer and the second semiconductor layer each include Si, SiGe, Ge, GaN, or GaAs.

[0009] According to an embodiment of the present disclosure, the source / drain is n-doped and the second semiconductor layer is heavily n-doped; or the source / drain is p-doped and the second semiconductor layer is heavily p-doped.

[0010] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising: forming a film layer on a substrate, the film layer comprising a plurality of alternatingly stacked first semiconductor layers and a plurality of sacrificial layers, wherein the first semiconductor layer comprises an intrinsic semiconductor; etching the film layer to obtain a fin extending along a first direction; forming a sacrificial gate extending in a second direction intersecting the first direction and intersecting the fin, and forming sidewalls on both sides of the sacrificial gate in the first direction; etching the fin using the sacrificial gate and the sidewall as a mask to expose the sidewalls of the film layer in the first direction; forming a source / drain portion on the sidewall; removing the sacrificial gate and the plurality of sacrificial layers on the inner side of the sidewall to release the first semiconductor layer, and forming a second semiconductor layer on the periphery of the first semiconductor layer to obtain multiple composite channel layers, wherein the second semiconductor layer comprises a heavily doped semiconductor; and forming a gate stack on the inner side of the sidewall.

[0011] According to an embodiment of the present disclosure, the second semiconductor layer is formed by atomic layer deposition or selective epitaxy.

[0012] According to an embodiment of the present disclosure, the above method further includes: forming a gate oxide layer around the periphery of the plurality of composite channel layers.

[0013] According to an embodiment of the present disclosure, the doping concentration of the second semiconductor layer is 1×10 17 cm -3 ~5×10 21 cm -3 .

[0014] According to an embodiment of the present disclosure, the first semiconductor layer and the second semiconductor layer each include Si, SiGe, Ge, GaN, or GaAs.

[0015] According to an embodiment of the present disclosure, the source / drain is n-doped and the second semiconductor layer is heavily n-doped; or the source / drain is p-doped and the second semiconductor layer is heavily p-doped.

[0016] According to an embodiment of the present disclosure, a channel portion is composed of a plurality of composite channel layers stacked and spaced apart from each other, and each composite channel layer includes a first semiconductor layer and a second semiconductor layer surrounding the periphery of the first semiconductor layer, the first semiconductor layer includes an intrinsic semiconductor and the second semiconductor layer includes a heavily doped semiconductor, whereby each composite channel layer can be regarded as a double channel. Since the heavily doped second semiconductor layer can form a junctionless device with the source / drain portion, it has a smaller threshold voltage than the case of a first semiconductor layer with only an intrinsic semiconductor (conventional GAA Nanosheet device), and can be turned on preferentially and transport majority carriers. At the same time, the second semiconductor layer will also provide carriers to the first semiconductor layer after it is turned on, so as to increase the carrier concentration and electron mobility of the first semiconductor layer, thereby increasing the on-state current (I on) That is, the current switching ratio is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0018] Figure 1A A cross-sectional view along a first direction of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0019] Figure 1B A cross-sectional view of a semiconductor device in a second direction according to an embodiment of the present disclosure is schematically shown.

[0020] Figure 1C A perspective view of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0021] Figure 2 The flowchart schematically shows a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0022] Figure 3A to Figure 10B Schematically shows Figure 2 A cross-sectional view of the structure obtained after executing part of the process in the method shown. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0024] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0026] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and for the purpose of clarity, certain details are magnified and certain details may be omitted. The shapes of the various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0027] In the process of realizing the inventive concept of the present disclosure, the inventors found that as the channel size of the logic semiconductor device continues to shrink, a series of short channel effects will appear, including the on-state current I on This is because at small sizes, the scattering effect on the carriers in the channel is enhanced, thereby reducing the mobility. At the same time, the gate's control over the carriers in the channel depends on its distance from the channel. Therefore, when the size is reduced, the gate's ability to regulate the carriers becomes weaker, and it is difficult to completely suppress the leakage current in the off state, and it is difficult to increase the current in the on state, resulting in a current switching ratio I on / I off In addition, the bottom leakage problem of GAA nanosheet devices will further affect the stability of device threshold voltage and switching speed and other performance.

[0028] In view of this, an embodiment of the present disclosure provides a semiconductor device, comprising: a substrate; a channel portion on the substrate, comprising a plurality of composite channel layers stacked and spaced apart from each other in a vertical direction; a source / drain portion, respectively located on both sides of the channel portion in a first direction; and a gate stack, extending in a second direction intersecting with the first direction and surrounding the periphery of each of the plurality of composite channel layers, wherein each composite channel layer comprises a first semiconductor layer and a second semiconductor layer surrounding the periphery of the first semiconductor layer, the first semiconductor layer comprises an intrinsic semiconductor and the second semiconductor layer comprises a heavily doped semiconductor.

[0029] The following will be passed Figure 1A to Figure 1C The cross-section and overall structure of the semiconductor device in different directions are shown respectively.

[0030] Figure 1A A cross-sectional view along a first direction of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0031] Figure 1BA cross-sectional view of a semiconductor device in a second direction according to an embodiment of the present disclosure is schematically shown.

[0032] Figure 1C A perspective view of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0033] like Figure 1A to Figure 1C As shown, the semiconductor device 100 of this embodiment may include a substrate 110, a channel portion 130 on the substrate 110, and channels 130 located in the channel portion 130 in a first direction (eg, Figure 1A The source / drain portions 120 on both sides of the horizontal direction in the paper) and in a second direction (eg, perpendicular to) the first direction (eg, Figure 1B The gate stack 140, the gate oxide layer 150 and the spacer 160 extend in the horizontal direction (in the middle paper). Taking the SOI substrate as an example, the substrate 110 includes a base substrate 111 and a buried oxide layer 112, and the channel portion 130 includes a composite channel layer 131, a composite channel layer 132, a composite channel layer 133, and a composite channel layer 134, and the multiple composite channel layers are spaced apart and stacked in a vertical direction. For the composite channel layer 131, it includes a first semiconductor layer 131 (1) and a second semiconductor layer 131 (2) surrounding the periphery of the first semiconductor layer 131 (1), and the other composite channel layers 132, 133, and 134 also have the same structure; the gate stack 140 extends in a second direction (y) intersecting with the first direction (x) and surrounds the periphery of each of the multiple composite channel layers. A gate oxide layer 150 is further included between the gate stack 140 and the multiple composite channel layers for isolating the multiple composite channel layers from the gate stack, and the sidewalls of the gate stack also include sidewalls 160.

[0034] According to an embodiment of the present disclosure, the first semiconductor layer and the second semiconductor layer are made of the same intrinsic material, that is, the second semiconductor layer is obtained by heavily doping the material selected for the first semiconductor layer.

[0035] According to the embodiments of the present disclosure, the material of the sidewall spacer can be selected according to environmental requirements, the material of the oxide layer can be other high dielectric constant materials such as silicon dioxide, and the material of the gate stack can be polysilicon or various metals.

[0036] According to the embodiments of the present disclosure, when a semiconductor device is operating, when a suitable voltage is applied to the gate electrode layer in the gate stack, an electric field is generated in the gate dielectric layer, which in turn affects the distribution of carriers in the composite channel layer. In the on-state, the electric field attracts carriers (electrons or holes) into the composite channel layer, forming a conductive channel that enables electrical conduction between the source and drain. Because the heavily doped second semiconductor layer can quickly provide additional carriers to the first semiconductor layer, the magnitude of the on-state current can be increased.

[0037] Among them, the current switching ratio is at least 10% higher than that of other GAA Nanosheet devices in related technologies, for example, from 10 5 Increase to 10 7 .

[0038] According to the embodiments of the present disclosure, the above-mentioned semiconductor device is mainly used in the field of small size, and the length of the gate stack is 10nm~100nm, and the width is 20nm~1μm.

[0039] Figure 1A-1B The number of the plurality of composite channel layers is merely illustrative, and in practice there may be more or less composite channel layers, which is not limited here. In addition to SOI substrates, other substrates may also be used, and therefore, the present disclosure is not limited thereto.

[0040] According to an embodiment of the present disclosure, a channel portion is composed of a plurality of composite channel layers stacked and spaced apart from each other, and each composite channel layer includes a first semiconductor layer and a second semiconductor layer surrounding the periphery of the first semiconductor layer, the first semiconductor layer includes an intrinsic semiconductor and the second semiconductor layer includes a heavily doped semiconductor, whereby each composite channel layer can be regarded as a double channel. Since the heavily doped second semiconductor layer can form a junctionless device with the source / drain portion, it has a smaller threshold voltage than the case of a first semiconductor layer with only an intrinsic semiconductor (conventional GAA Nanosheet device), and can be turned on preferentially and transport majority carriers. At the same time, the second semiconductor layer will also provide carriers to the first semiconductor layer after it is turned on, so as to increase the carrier concentration and electron mobility of the first semiconductor layer, thereby increasing the on-state current (I on ) That is, the current switching ratio is improved.

[0041] According to an embodiment of the present disclosure, the doping concentration of the second semiconductor layer is 1×10 17 cm -3 ~5×10 21 cm -3 .

[0042] According to the embodiments of the present disclosure, the doping concentration and doping material of the second semiconductor layer can be set according to the application scenario of the semiconductor device to achieve the technical effect of increasing the on-state current.

[0043] According to an embodiment of the present disclosure, the first semiconductor layer and the second semiconductor layer each include Si, SiGe, Ge, GaN, or GaAs.

[0044] According to the embodiments of the present disclosure, a first semiconductor layer and a second semiconductor layer made of semiconductor materials with different characteristics may be selected according to the application scenario of the semiconductor device.

[0045] According to an embodiment of the present disclosure, the source / drain is n-doped and the second semiconductor layer is heavily n-doped; or the source / drain is p-doped and the second semiconductor layer is heavily p-doped.

[0046] When the source / drain portion is doped with n-type and the second semiconductor layer is heavily doped with n-type, the above-mentioned semiconductor material is an n-type field effect transistor; when the source / drain portion is doped with p-type and the second semiconductor layer is heavily doped with p-type, the above-mentioned semiconductor material is a p-type field effect transistor.

[0047] Figure 2 The flowchart schematically shows a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0048] Figure 3A to Figure 10B Schematically shows Figure 2 A cross-sectional view of the structure obtained after executing part of the process in the method shown.

[0049] like Figure 2 As shown, the method 200 includes operations S210 to S270.

[0050] In operation S210 , a film layer is formed on a substrate, wherein the film layer includes a plurality of first semiconductor layers and a plurality of sacrificial layers that are alternately stacked, wherein the first semiconductor layer includes an intrinsic semiconductor.

[0051] According to an embodiment of the present disclosure, the material of the first semiconductor layer is an intrinsic semiconductor without impurities, and the film layer can be formed by a chemical vapor deposition process.

[0052] refer to Figure 3A and Figure 3B , an SOI substrate 110 can be provided. The SOI substrate 110 may include a base substrate 111 and a buried oxide layer 112 on the base substrate 111. The base substrate 111 may include a semiconductor material such as silicon (Si), and the buried oxide layer 112 may include an oxide (such as silicon oxide). The buried oxide layer 112 may further include an SOI layer. The SOI layer may include the same semiconductor material as the base substrate 111, such as silicon, or a different semiconductor material from the base substrate 111, such as germanium (Ge) or SiGe. In this example, the SOI layer also serves as one of the first semiconductor layers in the film layer (the lowest first semiconductor layer in the film layer).

[0053] On the SOI substrate 110, a film layer 310 can be formed, for example, by an epitaxial growth process. The film layer 310 includes alternating stacks of first semiconductor layers 311 (as described above, the bottommost first semiconductor layer 311 can be formed from the SOI layer of the SOI substrate 110) and sacrificial layers 312. The sacrificial layers 312 can define the location of a gate stack to be formed later, and the first semiconductor layer 311 (together with a second semiconductor layer to be formed later) can define a channel portion. For example, the first semiconductor layer 311 can include a semiconductor material such as silicon, while the sacrificial layers 312 can include a semiconductor material having an etch selectivity relative to the first semiconductor layer 311, such as SiGe.

[0054] In operation S220 , the film layer is etched to obtain a fin extending along a first direction.

[0055] refer to Figure 4A and Figure 4B , a layer of photoresist (not shown) can be coated on the surface of the film layer, for example, along the first direction ( Figure 4A In the horizontal direction of the paper, Figure 4B A strip extending perpendicular to the paper.

[0056] For convenience, a possible hard mask structure, such as a stacked oxide / nitride layer hard mask, is not shown here. Furthermore, the example using photoresist is not limited thereto. Each layer is then sequentially etched using an anisotropic etch, such as vertical reactive ion etching (RIE). In this example, the etching may stop at the buried oxide layer 112. This forms a protruding structure 310' (which may be referred to as a "fin") extending along the first direction. The etch mask may then be removed.

[0057] In operation S230 , a sacrificial gate extending in a second direction intersecting the first direction to intersect the fin is formed, and spacers are formed on both sides of the sacrificial gate in the first direction.

[0058] refer to Figure 5A and Figure 5B , a second direction (eg, perpendicular to the first direction) may be formed on the SOI substrate 110. Figure 5A in a direction perpendicular to the paper, or Figure 5B A sacrificial gate 320 is shown, extending (in the horizontal direction within the paper) to intersect the fin 310'. For example, the sacrificial gate 320 may include an oxide layer and polysilicon on the oxide layer. Similarly, for convenience, a hard mask that may exist on the sacrificial gate 320 is not shown. Spacers 160 may be formed on the sidewalls of the sacrificial gate 320 through a spacer formation process. For example, the spacers 160 may include nitride.

[0059] In operation S240 , the fin is etched using the sacrificial gate and the spacer as masks to expose the sidewalls of the film layer in the first direction.

[0060] refer to Figure 6A and Figure 6B The sacrificial gate 320 and the spacer 160 are used as etching masks to perform anisotropic etching on the fin 310 ′, such as RIE in the vertical direction, to form a channel portion 130 that is self-aligned to the sacrificial gate 320 .

[0061] In operation S250 , source / drain portions are formed on the sidewalls.

[0062] refer to Figure 7A and Figure 7B The source / drain portion 120 may be formed on the exposed sidewalls of the first semiconductor layer 311 (and the sacrificial layer 312 ) by, for example, selective epitaxial growth.

[0063] In operation S260, the sacrificial gate and the multiple sacrificial layers are removed from the inner side of the spacer to release the first semiconductor layer, and a second semiconductor layer is formed around the first semiconductor layer to obtain multiple composite channel layers.

[0064] refer to Figure 8A and Figure 8B The sacrificial gate 320 can be removed by selective etching to expose the first semiconductor layer 311 and the sacrificial layer 312 in the space between the spacers 160. At the same time, the sidewalls of the sacrificial layer 312 in the second direction can be exposed. Thereafter, the sacrificial layer 312 can be removed by, for example, selective etching to release the first semiconductor layer 311.

[0065] refer to Figure 9A and Figure 9B , a second semiconductor layer 313 can be formed on the surface of the released first semiconductor layer 311 by selective epitaxy. The second semiconductor layer 313 can include a suitable semiconductor material, for example, the same semiconductor material as the first semiconductor layer 311, such as Si, and can be heavily doped, with the same doping type as the source / drain portion 120, and a doping concentration of, for example, 1×10 17 cm -3 ~5×10 21 cm -3 Thus, the composite channel layer 330 according to the embodiment of the present disclosure is obtained, including the first semiconductor layer 311 and the second semiconductor layer 313 surrounding the outer periphery of the first semiconductor layer 311 .

[0066] In operation S270 , a gate stack is formed inside the spacer.

[0067] refer to Figure 10A and Figure 10BA gate dielectric layer, a work function layer, and a gate electrode layer can be sequentially formed to obtain the final gate stack 140. For example, the gate dielectric layer can include a high-k gate dielectric such as hafnium oxide (HfO2). The work function layer can include a metal nitride such as TiN and have a suitable work function, for example, an n-type work function for an n-type FET and a p-type work function for a p-type FET. The gate electrode layer can include a conductive material, for example, a metal such as tungsten (W).

[0068] In addition, a gate oxide layer 150 may be formed between the gate dielectric layer and the composite channel layer 330 .

[0069] It should be noted that the semiconductor device part in the embodiment of the present disclosure corresponds to the method part of manufacturing the semiconductor device in the embodiment of the present disclosure. The description of the method part of manufacturing the semiconductor device specifically refers to the semiconductor device part and will not be repeated here.

[0070] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or part of the code, which contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the boxes can also occur in an order different from that marked in the accompanying drawings. For example, two boxes shown in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, as well as the combination of boxes in the block diagram or flowchart, can be implemented using a dedicated hardware-based system that performs the specified functions or operations, or can be implemented using a combination of dedicated hardware and computer instructions. It will be understood by those skilled in the art that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure may be combined and / or coupled in various ways, and all of these combinations and / or couplings fall within the scope of the present disclosure.

[0071] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device having an improved channel structure, comprising: substrate; The channel portion on the substrate includes a plurality of composite channel layers spaced apart and stacked in a vertical direction; source / drain portions, respectively located on both sides of the channel portion in the first direction; as well as a gate stack extending in a second direction intersecting the first direction and surrounding a periphery of each of the plurality of composite channel layers; Each composite channel layer includes a first semiconductor layer and a second semiconductor layer surrounding the first semiconductor layer. The first semiconductor layer includes an intrinsic semiconductor and the second semiconductor layer includes a heavily doped semiconductor.

2. The semiconductor device according to claim 1, wherein The doping concentration of the second semiconductor layer is 1×10 17 cm -3 ~5×10 21 cm -3 .

3. The semiconductor device according to claim 1, wherein The first semiconductor layer and the second semiconductor layer each include Si, SiGe, Ge, GaN or GaAs.

4. The semiconductor device according to claim 1, wherein The source / drain portion is n-type doped, and the second semiconductor layer is heavily n-type doped; or The source / drain portion is p-type doped, and the second semiconductor layer is heavily p-type doped.

5. A method for manufacturing a semiconductor device having an improved channel structure, comprising: forming a film layer on a substrate, the film layer comprising a plurality of first semiconductor layers and a plurality of sacrificial layers stacked alternately, wherein the first semiconductor layer comprises an intrinsic semiconductor; Etching the film layer to obtain a fin extending along a first direction; forming a sacrificial gate extending in a second direction intersecting the first direction so as to intersect the fin, and forming sidewalls on both sides of the sacrificial gate in the first direction; Etching the fin using the sacrificial gate and the sidewall as a mask to expose the sidewall of the film layer in the first direction; forming a source / drain portion on the sidewall; removing the sacrificial gate and the multi-layer sacrificial layer on the inner side of the spacer to release the first semiconductor layer, and forming a second semiconductor layer on the periphery of the first semiconductor layer to obtain a plurality of composite channel layers, wherein the second semiconductor layer includes a heavily doped semiconductor; and A gate stack is formed inside the spacer.

6. The method according to claim 5, wherein: The second semiconductor layer is formed by atomic layer deposition or selective epitaxy.

7. The method according to claim 5, further comprising: A gate oxide layer is formed around the plurality of composite channel layers.

8. The method according to claim 5, wherein The doping concentration of the second semiconductor layer is 1×10 17 cm -3 ~5×10 21 cm -3 .

9. The method according to claim 5, wherein: The first semiconductor layer and the second semiconductor layer each include Si, SiGe, Ge, GaN or GaAs.

10. The method according to claim 5, wherein The source / drain portion is n-type doped, and the second semiconductor layer is heavily n-type doped; or The source / drain portion is p-type doped, and the second semiconductor layer is heavily p-type doped.

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