Semiconductor device and forming method thereof

Abstract

A method for forming a semiconductor device is provided. The method includes forming a fin structure including a fin stack portion, the fin stack portion including first semiconductor portions and second semiconductor portions alternately stacked; forming a dummy gate structure including a dummy gate stack across a channel region of the fin structure; forming source / drain features over the source / drain regions of the fin structure on opposite sides of the dummy gate structure; removing the dummy gate stack to form a gate trench exposing sidewalls of the first semiconductor portion and the second semiconductor portion; selectively removing the first semiconductor portion to release the second semiconductor layer portion in the channel region as a channel member; depositing a dielectric material to fill gaps between the channel members; selectively growing a semiconductor cap on a sidewall of the channel member; removing the deposited dielectric material; and forming a gate stack to surround the semiconductor cap and the channel feature and to fill the gap. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This shrinking process generally provides benefits by increasing production efficiency and reducing associated costs. However, such shrinking has also increased the complexity of processing and manufacturing ICs. Summary of the Invention

[0003] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a fin structure above a substrate, the fin structure comprising a fin stack portion of a first semiconductor portion and a second semiconductor portion alternately stacked; forming a dummy gate structure comprising a dummy gate stack and a gate spacer located on the sidewalls of the dummy gate stack, the dummy gate stack spanning a channel region of the fin structure; forming a source / drain component above a source / drain region of the fin structure on opposite sides of the dummy gate structure; removing the dummy gate stack to form a gate trench exposing the sidewalls of the first semiconductor portion and the second semiconductor portion; selectively removing the first semiconductor portion to release the second semiconductor portion in the channel region as a channel component; depositing a dielectric material to fill a gap between the channel components; selectively growing a semiconductor cap on the sidewalls of the channel component; removing the deposited dielectric material in the gap; and forming a gate stack to surround the semiconductor cap and the channel component, wherein the gate stack fills the gap.

[0004] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a fin structure above a substrate, the fin structure comprising a fin stack portion of a first semiconductor portion and a second semiconductor portion alternately stacked; forming a dummy gate structure, the dummy gate structure comprising a dummy gate stack spanning a channel region of the fin structure and a gate spacer located on a sidewall of the dummy gate stack; forming a source / drain component above a source / drain region of the fin structure on opposite sides of the dummy gate structure; removing the dummy gate stack to form a gate trench exposing the sidewalls of the first semiconductor portion and the second semiconductor portion; selectively growing a semiconductor cap on the sidewall of the second semiconductor portion; selectively removing the first semiconductor portion to release the second semiconductor portion in the channel region as a channel component; and forming a gate stack to surround the channel component, wherein the gate stack fills the gap between the channel components.

[0005] Still other embodiments of the present application provide a semiconductor device comprising: a plurality of suspended channel nanostructures located above a substrate and having a length dimension in a first direction and a width dimension in a second direction transverse to the first direction, each of the plurality of channel nanostructures comprising a channel member and a semiconductor cap located on opposite sidewalls of the channel member along the second direction; and a gate stack surrounding a channel region of each of the plurality of channel nanostructures and filling gaps between the channel nanostructures, wherein the sidewalls of the gate stack along the first direction are surrounded by internal spacers. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the disclosed embodiments will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1 is a flow chart of a method for fabricating a gate-all-around (GAA) device according to some embodiments of the present disclosure.

[0008] Figures 2 to 15F The GAA device according to some embodiments of the present disclosure is shown in FIG. Figure 1 Various views during the manufacturing process of the method.

[0009] Figure 16 is a flow chart of a method for fabricating a gate-all-around (GAA) device according to some embodiments of the present disclosure.

[0010] 17A to 27D The GAA device according to some embodiments of the present disclosure is shown in FIG. Figure 16 Various views during the manufacturing process of the method. DETAILED DESCRIPTION

[0011] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact with each other, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not, by itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another (or more) elements or components as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0013] Some non-planar transistor architectures, such as vertical field-effect transistors (VFETs) and nanosheet field-effect transistors (NSFETs), employ semiconductor channels with various gate-all-around (GAA) technologies to achieve increased device density, greater power efficiency, and some improved performance over lateral devices. In NSFET embodiments, the gate stack wraps around the entire perimeter of each nanosheet, enabling more complete depletion in the channel region and reducing short-channel effects due to steeper subthreshold swing (SS) and smaller drain-induced barrier lowering (DIBL). The wrapped gate structure and source / drain contacts used in nanosheet-based devices also enable better management of leakage current and parasitic capacitance in the active region, even as drive current increases.

[0014] In a GAA configuration, a nanosheet-based FET consists of a source structure, a drain structure, and a stacked nanosheet channel between the source and drain structures. A gate surrounds the stacked nanosheet channel and regulates the flow of electrons through the nanosheet channel between the source and drain structures. A GAA nanosheet FET is fabricated by forming alternating layers of channel nanosheets and sacrificial nanosheets. The sacrificial nanosheets are released from the channel nanosheet before the FET device is completed.

[0015] However, silicon channel-based nanosheet GAA devices (in which the silicon channel is typically formed (released) by removing adjacent SiGe nanosheets in a process called "sheet formation" (SHF)) often face challenges due to the reduction in channel width during the removal of the sacrificial nanosheet in the replacement metal gate process. The etching of the sacrificial nanosheet also removes the channel nanosheet material, resulting in a dumbbell-shaped channel profile. This shape inevitably increases the parasitic capacitance (C eff ) and reduces the direct current (DC), thereby degrading the overall performance of the nanosheet GAA device.

[0016] The embodiments of the present disclosure increase the channel width by selectively depositing semiconductor caps on the sidewalls of the channel during the gate replacement process to enhance device performance. These semiconductor caps are designed to either compensate for the width loss of the channel nanosheets caused by the etching process used to remove the sacrificial nanosheets or serve as sacrificial components consumed during the etching process, thereby preventing the etching of the channel nanosheets. As a result, the improvement of the dumbbell-shaped channel profile can reduce the C eff And increase DC, thereby enhancing the performance of the entire nanosheet GAA device.

[0017] The GAA transistor structure described below can be patterned by any suitable method. For example, the structure can be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, the double patterning or multiple patterning process combines photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above the substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0018] Figure 1 is a flow chart of a method 100 of forming a GAA device 200 according to some embodiments of the present disclosure. Figures 2 to 15F 1 is a diagram of a GAA device 200 at various stages of the method 100 according to some embodiments. Figures 2 to 15F Some embodiments of method 100 are described. Method 100 is merely an example and is not intended to limit the disclosed embodiments beyond what is explicitly recited in the claims. Additional operations may be provided before, during, and after method 100, and some of the described operations may be replaced, eliminated, or moved around for additional embodiments of the method.

[0019] refer to Figure 1 and Figure 2The method 100 includes operation 102, in which an initial structure of a GAA device 200 is provided. The initial structure includes a substrate 202, a stack 204 of alternating epitaxial semiconductor layers above the substrate 202, and a hard mask layer 209 above the stack. Figure 2 is a cross-sectional view of the GAA device 200 after forming a stack 204 of alternating epitaxial semiconductor layers over a substrate 202 and subsequently forming a hard mask layer 209 over the stack 204 .

[0020] The substrate 202 may be any suitable substrate and may be processed to have various components. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon substrate. In some embodiments, the substrate 202 includes various layers, including conductive or insulating layers formed on the semiconductor substrate. The substrate 202 may include various doping configurations. For example, different doping profiles (e.g., n-well, p-well) may be formed on the substrate 202 in regions designed for different device types (e.g., n-type FET, p-type FET). Suitable doping may include ion implantation and / or diffusion processes of dopants. The substrate 202 typically has isolation components (e.g., shallow trench isolation (STI) components) between regions providing different device types. The substrate 202 includes other semiconductors, such as germanium or diamond. Alternatively, the substrate 202 includes: compound semiconductors, such as silicon carbide (SiC), gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, GaInAsP, and / or other suitable materials. Furthermore, substrate 202 may optionally include an epitaxial layer, may be strained for enhanced performance, may include a silicon-on-insulator structure, and / or have other suitable enhancement features.

[0021] A stack 204 of alternating epitaxial semiconductor layers is blanket deposited on the substrate 202. The stack 204 includes alternating sacrificial semiconductor layers 206 and channel semiconductor layers 208, wherein each channel semiconductor layer 208 is disposed between the sacrificial semiconductor layers 206. In some embodiments, the sacrificial semiconductor layers 206 include a first semiconductor material and the channel semiconductor layers 208 include a second semiconductor material different from the first semiconductor material. The materials of the sacrificial semiconductor layers 206 and the channel semiconductor layers 208 can be selected based on providing different etching selectivities. For example, in some embodiments, the first semiconductor material can include germanium (Ge) or silicon germanium (SiGe), and the second semiconductor material can include silicon (Si). In some optional embodiments, the first semiconductor material includes SiGe having a first Ge content, and the second semiconductor material includes SiGe having a second Ge content lower than the first Ge content. In various embodiments, the sacrificial semiconductor layers 206 and the channel semiconductor layers 208 are substantially free of dopants (i.e., having a Ge content of less than about 1×10 17 cm -3 extrinsic dopant concentration).

[0022] In some embodiments, the sacrificial semiconductor layer 206 may be removed later in the process, thereby leaving behind the channel nanostructures (eg, Figure 13A Therefore, the thickness of the sacrificial semiconductor layer 206 determines the thickness of the adjacent channel nanostructures (e.g., Figure 13A 262). In some embodiments, the thickness of the sacrificial semiconductor layer 206 can be in a range from about 8 nm to about 15 nm. The thickness of the channel semiconductor layer 208 is selected based on, for example, manufacturing considerations, transistor performance considerations, etc. In some embodiments, the thickness of the channel semiconductor layer 208 can be in a range from about 4 nm to about 10 nm.

[0023] The number of the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 depends on the channel nanostructure in the GAA device 200 (eg, Figure 13A In some embodiments, the number of channel semiconductor layers 208 is, for example, from 2 to 10 to form a stack of 2 to 10 vertically spaced channel nanostructures. In some embodiments, and as Figure 2 As shown in , the stack 204 includes four (4) layers of sacrificial semiconductor layers 206 and three (3) layers of channel semiconductor layers 208 .

[0024] The sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are epitaxially grown layer by layer from the top surface of the substrate 202. In some embodiments, the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 are grown by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process such as a metal organic CVD (MOCVD) process, or other suitable epitaxial growth process. The epitaxial growth produces the sacrificial semiconductor layer 206 and the channel semiconductor layer 208 having the same crystal orientation as the substrate 202.

[0025] A hard mask layer 209 is formed above the topmost surface of the stack 204. In some embodiments, the hard mask layer 209 includes a dielectric material such as, for example, silicon nitride (SiN), silicon carbonitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or a combination thereof. In some embodiments, the hard mask layer 209 is formed by chemical CVD, plasma enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes. In some embodiments, the hard mask layer 209 may have a dual-layer structure including a pad oxide layer and a pad nitride layer formed above the pad oxide layer. In some embodiments, the pad oxide layer includes silicon oxide, which may be formed by thermal oxidation. The pad nitride layer includes SiN, which may be formed by CVD, PECVD, PVD, ALD, or other suitable deposition processes. The hard mask layer 209 is used to protect portions of the substrate 202 and the stack 204, and to define patterns (e.g., fins) as described below.

[0026] refer to Figure 1 and Figures 3A to 3B In accordance with some embodiments, method 100 proceeds to operation 104 where a fin structure 210 is formed from the stack 204 . Figure 3A and Figure 3B is a cross-sectional view of the GAA device 200 after forming the fin structure 210. It should be noted that although Figure 3A A single fin structure 210 is shown in FIG, but any number of fin structures 210 may be formed.

[0027] In some embodiments, portions of the stack 204 and the substrate 202 are patterned to form a fin structure 210. The fin structure 210 extends vertically from the substrate 202 along the Z direction and has a length dimension along the X direction and a width dimension along the Y direction. The width of the fin structure 210 can be in a range from about 10 nm to about 90 nm. The fin structure 210 includes a base portion 210B (e.g., a fin portion / protrusion) and a fin stack portion 210S. The base portion 210B is formed by the substrate 202, while the fin stack portion 210S is formed by the stack 204 and includes a portion of the sacrificial semiconductor layer 206 (referred to herein as the sacrificial semiconductor portion 206P) and a portion of the channel semiconductor layer 208 (referred to herein as the channel semiconductor portion 208P).

[0028] In some embodiments, the fin structure 210 can be formed using a photolithography and etching process. During the photolithography process, a photoresist layer is first applied to the hard mask layer 209 by, for example, spin coating. The photoresist layer is then exposed according to a mask of a pattern and developed to form a pattern in the photoresist layer. The photoresist layer with a pattern can be used as an etching mask to pattern other layers. In some embodiments, the patterned photoresist layer is implemented using an extreme ultraviolet (EUV) photolithography process. The patterned photoresist layer is then used to protect an area of ​​the substrate 202 and the sacrificial semiconductor layer 206 channel semiconductor layer 208 formed thereon, while the etching process forms the fin structure 210. In some embodiments, the etching process can be a dry etching process such as plasma etching or reactive ion etching (RIE), a wet etching process, or a combination thereof.

[0029] In various other embodiments, the fin structure 210 can be formed using a suitable process including a double patterning or multiple patterning process. Typically, the double patterning or multiple patterning process combines photolithography and a self-aligned process, thereby allowing the creation of patterns having, for example, a pitch that is smaller than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. Mandrels are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining mandrels are then used as an etch mask to pattern the stack 204 and substrate 202 to provide the fin structure 210.

[0030] Subsequently, an isolation feature 216 may be formed near and around the base portion 210B of the fin structure 210. The isolation feature 216 is disposed between the fin structure 210 and another fin structure 210 (not shown). The isolation feature 216 may also be referred to as a shallow trench isolation (STI) feature. In an exemplary process, a dielectric layer is first deposited over the substrate 202, and the trenches between the fin structure 210 and the adjacent fin structure 210 are filled with a dielectric material. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials. In various instances, the dielectric layer may be deposited by a CVD process, a sub-atmospheric pressure CVD (SACVD) process, a flowable CVD process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, spin coating, and / or other suitable processes. The deposited dielectric material is then planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed by a dry etching process, a wet etching process, and / or a combination thereof to form isolation features 216. In some embodiments, the top surface of isolation features 216 is substantially coplanar with or lower than the bottom surface of bottom-most sacrificial semiconductor portion 206P. In some embodiments, and as Figure 3A As shown in FIG, the fin stack portion 210S and the base portion 210B of the fin structure 210 rise above the isolation feature 216. The portion of the base portion 210B located above the isolation feature 216 may have a height H1 that is equal to or greater than the thickness T1 of the channel semiconductor portion 208P. Figure 3A and Figure 3B As shown in FIG, the hard mask layer 209 is formed of a dielectric material having a high etch selectivity compared to the isolation features 216 and remains in the structure after the formation of the isolation features 216. The remaining portion of the hard mask layer 209 is referred to as a hard mask portion 209P.

[0031] refer to Figure 1 and Figures 4A to 4B In accordance with some embodiments, method 100 proceeds to operation 106 where a dummy gate structure 220 is formed over hard mask portion 209P and fin structure 210 . Figure 4A and Figure 4B is a cross-sectional view of the GAA device 200 after forming a dummy gate structure 220. The dummy gate structure 220 is formed across the hard mask portion 209P and the fin structure 210, along sidewalls of the hard mask portion 209P and the fin structure 210, and over a top surface of the hard mask portion 209P.

[0032] The dummy gate structure 220 includes a dummy gate stack (222, 224) and a gate spacer 226. According to an embodiment of the present disclosure, the dummy gate stack (222, 224) will be replaced with a metal gate stack.

[0033] In some embodiments, the dummy gate stack (222, 224) includes a dummy gate dielectric 222 and a dummy gate electrode 224 on the dummy gate dielectric 222. In some embodiments, the dummy gate stack (222, 224) may further include a dummy gate cap (not shown) on top of the dummy gate electrode 224.

[0034] In some embodiments, the dummy gate dielectric 222 may be made of silicon oxide, silicon nitride, or silicon oxynitride. The dummy gate electrode 224 may be made of silicon such as polycrystalline silicon or amorphous silicon. In some embodiments, the dummy gate stack (222, 224) may be formed by first conformally depositing a dummy gate dielectric layer over the hard mask portion 209P, the fin structure 210, and the isolation component 216. Then, a dummy gate electrode layer is blanket deposited on the dummy gate dielectric layer so that the hard mask portion 209P and the fin structure 210 are completely embedded in the dummy gate electrode layer. In some embodiments, the thickness of the dummy gate dielectric layer may be in the range of from about 1 nm to about 5 nm. In some embodiments, the thickness of the dummy gate electrode layer may be in the range of from about 100 nm to about 200 nm. In some embodiments, the dummy gate electrode layer is subjected to a planarization operation. The dummy gate dielectric layer and the dummy gate electrode layer may be deposited using CVD, PECVD, PVD, ALD, or other suitable deposition processes. Subsequently, the dummy gate dielectric layer and the dummy gate electrode layer are patterned using photolithography and etching processes. For example, a photoresist layer (not shown) is applied over the dummy gate electrode layer and patterned by photolithographic exposure and development. The pattern in the photoresist layer is sequentially transferred to the dummy gate electrode layer and the dummy gate dielectric layer by at least one anisotropic etching process, thereby forming a dummy gate stack (222, 224), which includes the remaining portion of the dummy gate dielectric layer and the dummy gate electrode layer. The anisotropic etching process can be a dry etching process, such as RIE, a wet etching process, or a combination thereof. If not completely consumed, the remaining photoresist layer after forming the dummy gate stack (222, 224) is removed by, for example, ashing.

[0035] The gate spacer 226 is disposed on the sidewalls of the dummy gate stack (222, 224). In some embodiments, the gate spacer 226 may include a dielectric material such as, for example, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, the gate spacer 226 is made of silicon nitride. In some embodiments, the gate spacer 226 may be formed by first depositing a conformal gate spacer material layer on the exposed surfaces of the dummy gate stack (222, 224), the hard mask portion 209P, the fin structure 210, and the isolation feature 216; and then etching the gate spacer material layer to remove horizontal portions of the gate spacer material layer. In some embodiments, the gate spacer material layer may be deposited, for example, by CVD, PECVD, or ALD. In some embodiments, the gate spacer material layer may be etched by dry etching, such as, for example, plasma etching or RIE. The vertical portions of the gate spacer material layer present on the sidewalls of the dummy gate stack (222, 224) constitute the gate spacer 226.

[0036] refer to Figure 1 and Figures 5A to 5B In accordance with some embodiments, method 100 proceeds to operation 108 where source / drain trenches 228 are formed in the fin structure 210 . Figure 5A and Figure 5B is a cross-sectional view of the GAA device 200 after forming the source / drain trenches 228 .

[0037] In some embodiments, the hard mask portion 209P, the sacrificial semiconductor portion 206P, and the channel semiconductor portion 208P in the source / drain region are etched using the dummy gate structure 220 as an etching mask to form the source / drain trench 228. Etching can be performed by a dry etching process such as plasma etching or RIE. Exemplary dry etching processes can be implemented with oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof. Alternatively, etching can be performed by a wet etching process using an etchant such as ammonium hydroxide, a mixture of hydrogen peroxide and water (APM), tetramethylammonium hydroxide (TMAH), or ammonium hydroxide (NH4OH). Figure 5B As shown in FIG, sidewalls of the hard mask portion 209P, the sacrificial semiconductor portion 206P, and the channel semiconductor portion 208P are exposed in the source / drain trench 228. In some embodiments, the substrate 202 may also be partially etched. Thus, the bottom surface of the source / drain trench 228 may be flush with or lower than the top surface of the base portion 210B.

[0038] refer to Figure 1 and Figures 6A to 6B According to some embodiments, method 100 proceeds to operation 110 where an inner spacer 230 is formed. Figure 6A and Figure 6B is a cross-sectional view of the GAA device 200 after forming the inner spacer 230 .

[0039] In some embodiments, and as Figure 6B As shown in FIG, the inner spacer 230 has substantially the same lateral dimensions as the gate spacer 226 and contacts the sidewalls of the sacrificial semiconductor portion 206P. In operation 110, the sacrificial semiconductor portion 206P exposed in the source / drain trench 228 is laterally recessed to form an inner spacer recess in the fin stack portion 210S of the fin structure 210. In some embodiments, the lateral etching process can be performed using an isotropic etching process that etches the semiconductor material (e.g., SiGe) and other exposed elements of the sacrificial semiconductor portion 206P in the fin structure 210 selective to the semiconductor material (e.g., Si) of the channel semiconductor portion 208P. In some embodiments, the amount of sacrificial semiconductor portion 206P etched is controlled such that the lateral etching distance is no greater than the width of the gate spacer 226. In some embodiments, an isotropic wet etching process can be performed using an etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution. Optionally, the lateral ends of the sacrificial semiconductor portion 206P exposed in the source / drain trenches 228 can first be selectively oxidized to increase the etch selectivity between the sacrificial semiconductor portion 206P and the channel semiconductor portion 208P. In some embodiments, the oxidation process can be performed by exposing the structure to a wet oxidation process, a dry oxidation process, or a combination thereof.

[0040] After forming the inner spacer recess, a layer of inner spacer material is deposited over the structure (including in the inner spacer recess). The inner spacer material may include silicon oxide, silicon nitride, silicon oxycarbide, silicon oxycarbonitride, silicon carbonitride, metal nitride, or any suitable dielectric material. The inner spacer material layer may be formed by CVD, ALD, or any other suitable conformal deposition process. In some embodiments, the inner spacer material layer may be formed to have a thickness such that the inner spacer recess is completely filled with the inner spacer material layer.

[0041] Then, an etching process, such as an anisotropic etching process, is performed to remove portions of the inner spacer material layer disposed outside the inner spacer recess in the fin structure 210. The remaining portions of the inner spacer material layer (i.e., the portions disposed within the inner spacer recess) form the inner spacer 230. In some embodiments, the anisotropic etching process may be a wet etching process including an etchant such as, for example, buffered hydrofluoric acid (BHF), hydrofluoric acid (HF), hydrofluoric acid nitric acid (HNA), phosphoric acid, HF diluted with ethylene glycol (HFEG), hydrochloric acid (HCl), or any combination thereof. In some embodiments, the anisotropic etching process may be a dry etching process including an oxygen-containing gas, hydrogen, nitrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas (e.g., CF3I), other suitable gases and / or plasmas, and / or combinations thereof.

[0042] refer to Figure 1 and 7A to 7B In accordance with some embodiments, method 100 proceeds to operation 112 where source / drain features 232 are formed in source / drain trenches 228 . Figure 7A and Figure 7B 2 is a cross-sectional view of the GAA device 200 after forming source / drain features 232. The source / drain features 232 are disposed on opposite sides of the dummy gate structure 220, the sacrificial semiconductor portion 206P, and the channel semiconductor portion 208P such that the source / drain features 232 are in contact with the channel semiconductor portion 208P but are separated from the sacrificial semiconductor portion 206P by the inner spacer 230.

[0043] The source / drain features 232 are epitaxially grown in the source / drain trenches 228. The epitaxial process may include CVD deposition (e.g., vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), low pressure CVD (LPCVD), plasma-enhanced CVD (PECVD)), molecular beam epitaxy (MBE), other suitable selective epitaxial growth (SEG) processes, or a combination thereof. Due to the fact that the substrate 202 in the source / drain trenches 228 is covered by the isolation features 216, there are no nucleation sites at the bottom during the source / drain epitaxial growth. Therefore, the source / drain features 232 grow laterally from the exposed sidewalls of the channel semiconductor portion 208P and the base portion 210B in the fin structure 210.

[0044] The source / drain features 232 may include any suitable material for an n-type or p-type FET device. For example, when forming an n-type FET device, the source / drain features 232 may include a material that applies tensile strain in the channel region, such as Si, SiC, SiCP, SiP, etc., and may be doped in situ during the epitaxial growth process by introducing n-type dopants (such as phosphorus (P) or arsenic (As)), or ex situ using an implantation process (i.e., a junction implantation process). Similarly, when forming a p-type FET device, the source / drain features 232 may include a material that applies compressive strain in the channel region, such as Si, SiGe, SiGeB, Ge, GeSn, etc., and may be doped in situ during the epitaxial growth process by introducing p-type dopants (such as boron (B), aluminum (Al), gallium (Ga), and indium (In)), or ex situ using an implantation process (i.e., a junction implantation process). The epitaxial source / drain features 232 may have a surface that is raised from the corresponding surface of the channel semiconductor portion 208P and may have a small facet. In some embodiments, the source / drain feature 232 is a p-type source / drain feature and includes boron-doped SiGe. In some embodiments, the source / drain feature 232 is an n-type source / drain feature and includes phosphorus-doped Si.

[0045] Figures 7C to 7E This is a plan view of the channel and source / drain regions along the XY plane. Figure 7C In some embodiments, the epitaxial growth of the source / drain features 232 is controlled such that the lateral epitaxial growth forms the source / drain features 232 having the same width as the channel semiconductor portion 208P. Figure 7C As shown in FIG, the sidewalls of the source / drain features 232 are aligned with the sidewalls of the channel semiconductor portion 208P along the Y direction. Figure 7D In some other embodiments, the lateral epitaxial growth forms the source / drain features 232 having a width greater than the width of the channel semiconductor portion 208P. In such an example, the sidewalls of the source / drain features 232 extend laterally outwardly beyond the sidewalls of the channel semiconductor portion 208P in the Y direction, as shown in FIG. Figure 7D As shown in .

[0046] In some embodiments, a thermal annealing process is performed after the epitaxial growth and doping of the source / drain features 232. This process causes dopants to be implanted into the portion of the channel semiconductor portion 208P that is in contact with the source / drain features 232. This annealing process effectively extends the source / drain features 232 into the end portion of the channel semiconductor portion 208P, reducing the parasitic resistance of the nanosheet FET device. In other embodiments, the thermal annealing process is performed in a later process (such as after forming the high-k gate dielectric layer) so that the same annealing process can be used for two purposes simultaneously: driving dopants into the channel semiconductor portion 208P; and improving the reliability of the high-k gate dielectric. In some embodiments, and as Figure 7B and Figure 7E As shown in FIG, after annealing, the sidewalls of the source / drain features 232 are aligned with the inner sidewalls of the gate spacers 226. In some other embodiments, the thermal annealing process is omitted, and the sidewalls of the source / drain features 232 are aligned with the outer sidewalls of the gate spacers 226 ( Figure 7C and Figure 7D ).

[0047] refer to Figure 1 and Figures 8A to 8B In accordance with some embodiments, the method 100 proceeds to operation 114 where an interlayer dielectric (ILD) layer 234 is formed over the source / drain features 232 and the isolation features 216 . Figure 8A and Figure 8B is a cross-sectional view of the GAA device 200 after forming the ILD layer 234 .

[0048] In some embodiments, the ILD layer 234 may include a low-k dielectric material having a dielectric constant lower than that of silicon dioxide (approximately 3.9). The low-k dielectric material may include silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), fluorinated silicate glass (FSG), silicon oxycarbide (SiO x C y ), spin-on glass (SOG), or a combination thereof. The ILD layer 234 may include a multilayer structure having a variety of dielectric materials and may be formed by CVD, flowable CVD (FCVD), spin coating, or other suitable deposition processes. In some embodiments, forming the ILD layer 234 further includes performing a CMP process to planarize the top surface of the ILD layer 234, thereby exposing the dummy gate electrode 224. The top surface of the ILD layer 234 may be coplanar with the top surfaces of the dummy gate electrode 224 and the gate spacer 226.

[0049] refer to Figure 1 and Figures 9A to 9BAccording to some embodiments, the method 100 proceeds to operation 116 where the dummy gate stack ( 222 , 224 ) including the dummy gate dielectric 222 and the dummy gate electrode 224 is removed. Figure 9A and Figure 9B is a cross-sectional view of the GAA device 200 after removing the dummy gate stack ( 222 , 224 ).

[0050] The etching process selectively removes the dummy gate dielectric 222 and the dummy gate electrode 224, thereby forming a gate trench 240 that exposes the hard mask portion 209P, the sacrificial semiconductor portion 206P, and the channel semiconductor portion 208P in the channel region of the fin structure 210. The ILD layer 234 protects the source / drain features 232 during the etching process. The etching process can be a dry etching process, a wet etching process, or a combination thereof. The etching process can be adjusted so that the dummy gate dielectric 222 and the dummy gate electrode 224 are removed without (or to a minimal extent) etching other components in the GAA device 200 (including the ILD layer 234, the source / drain features 232, the gate spacers 226, and the hard mask portion 209P). For example, in an embodiment where the dummy gate electrode 224 is composed of polysilicon and the ILD layer 234 is composed of silicon oxide, a wet etchant such as a TMAH solution can be used to selectively remove the dummy gate electrode 224. Thereafter, the dummy gate dielectric 222 is removed using plasma dry etching and / or wet etching.

[0051] In some embodiments, after removing the dummy gate stack ( 222 , 224 ), a base mask layer 218 may be formed on the isolation feature 216 to surround the exposed portion ( s ) of the base portion 210B above the isolation structure 216 . Figure 10 ). The base mask layer 218 prevents subsequent epitaxial growth of semiconductor material from the base portion 210B. Therefore, no semiconductor cap ( Figure 14A 260), thereby preventing the I off The formation of the base mask layer 218 is optional.

[0052] refer to Figure 1 and Figures 11A to 11B According to some embodiments, method 100 proceeds to operation 118 where sacrificial semiconductor portion 206P is removed. Figure 11A and Figure 11B is a cross-sectional view of the GAA device 200 after removing the sacrificial semiconductor portion 206P.

[0053] The selective removal of the sacrificial semiconductor portion 206P releases the channel semiconductor portion 208P to form the channel member 208A. In some embodiments, the channel member 208A is a nanosheet. In some embodiments, the sacrificial semiconductor portion 206P can be removed by a selective etching process using an etchant that is selective for the material of the sacrificial semiconductor portion 206P, thereby removing the sacrificial semiconductor portion 206P without substantially attacking the channel semiconductor portion 208P. In some embodiments, the etching process is an isotropic etching process, which can be a dry etching process or a wet etching process. In some embodiments, the selective etching process can include oxidizing the sacrificial semiconductor portion 206P using a suitable oxidizing agent, such as ozone. The oxidized sacrificial semiconductor portion 206P can then be selectively removed. In some embodiments, when the channel semiconductor portion 208P comprises Si and the sacrificial semiconductor portion 206P comprises SiGe, the sacrificial semiconductor portion 206P can be selectively removed by applying HCl gas or a gas mixture of CF4, SF6, and CHF3 at a temperature of approximately 500° C. to approximately 700° C. The inner spacers 230 serve as an etch stop layer to protect the source / drain features 232 during the removal of the sacrificial semiconductor portion 206P. After the removal of the sacrificial semiconductor portion 206P, the channel semiconductor portion 208P forms a plurality of channel members 208A.

[0054] In some embodiments, after exposing the channel member 208A by removing the sacrificial semiconductor portion 206P, a trimming operation can be performed to reduce the thickness of the channel member 208A, thereby improving the gate fill window. The trimming operation can utilize any suitable etching process, such as dry etching, wet etching, or a combination thereof. After the trimming operation, the channel member 208A can have a width W2 ranging from about 10 nm to about 90 nm (e.g., from about 10 nm to about 40 nm) and a thickness T2 ranging from about 4 nm to about 7 nm.

[0055] like Figure 11A and Figure 11B As shown in FIG, gaps 242 (e.g., empty spaces) are formed between adjacent channel members 208A, between the topmost channel member 208A and the hard mask layer 209, and between the bottommost channel member 208A and the base portion 210B due to the removal of the sacrificial semiconductor portion 206P and the nanosheet trimming. The gaps 242 define the spacing S between adjacent channel members 208A. In some embodiments, the spacing between adjacent channel members 208A (also referred to as the sheet-to-sheet spacing) can be in the range of from about 8 nm to about 15 nm.

[0056] However, the etching process used to remove the sacrificial semiconductor portion 20A6 and to trim the channel member 208A also recesses the channel member 208A in the Y direction, causing a width loss in the channel member 208 A. This width loss results in a dumbbell-shaped channel member 208A. Figure 11C is a plan view of the channel and source / drain regions along the XY plane. Figure 11C As shown in FIG, the channel width loss causes the sidewalls of the channel member 208A to be recessed from the sidewalls of the inner spacer 230 in the Y direction. The channel member 208A has a width W2 ( W1 ) less than the width W2 of the hard mask portion 209P (ie, the width of the channel semiconductor portion 208P). Figure 11A In some embodiments, the width W1 of the channel semiconductor portion 208P in the channel region of the fin structure 210 may be in a range from 12.5 nm to 45 nm, and the width W2 of the channel member 208A may be reduced to 10 nm to 40 nm after the nanosheet formation and nanosheet trimming processes.

[0057] refer to Figure 1 and FIG. 12A to FIG. 12B According to some embodiments, method 100 proceeds to operation 120 where a sacrificial plug 250 is formed to fill gap 242 . Figure 12A and Figure 12B is a cross-sectional view of the GAA device 200 after forming a sacrificial plug 250 to fill the gap 242 .

[0058] A sacrificial material layer is conformally deposited over the channel member 208A and the hard mask portion 209P exposed by the gate trench 240 and the gap 242. In some embodiments, the thickness of the sacrificial layer is controlled so that the portion of the sacrificial layer located in the gap 242 merges. Thus, the sacrificial material layer completely fills the gap 242. The sacrificial material layer may include a material that can be selectively etched relative to the hard mask portion 209P. In some embodiments, the sacrificial material layer may include a metal oxide, such as aluminum oxide (AlO). x ) or zirconium oxide. The sacrificial layer can be formed by a suitable deposition process, such as PVD, CVD, ALD, or other suitable conformal deposition methods. Next, an etching process, such as an anisotropic etching process, is performed to remove the portion of the sacrificial layer disposed outside the gap 242 from the structure. The remaining portion of the sacrificial material layer remains in the gap 242 to form a sacrificial plug 250.

[0059] refer to Figure 1 and 13A to 13B According to some embodiments, the method proceeds to operation 122 where a semiconductor cap 260 is positioned on opposing sidewalls of the channel member 208A and the base portion 210B. 13A to 13BFIG2 is a cross-sectional view of the GAA device 200 after semiconductor caps 260 are formed on opposite sidewalls of the channel member 208A and the base portion 210B. Each channel member 208A and its corresponding semiconductor cap 260 on the sidewall form a channel nanostructure 262. The base portion 210B and its semiconductor cap 260 on the sidewall form a mesa structure 264.

[0060] Semiconductor cap 260 is incorporated to offset the width reduction that occurs during the formation of channel member 208A. In some embodiments, the material of semiconductor cap 260 is selected so that there are no significant differences in chemical or material properties between semiconductor cap 260 and channel member 208A. In some embodiments, semiconductor cap 260 is composed of the same semiconductor material as channel member 208A. For example, in some embodiments, where channel member 208A is made of Si, semiconductor cap 260 is also composed of Si. An interface may or may not exist between channel member 208A and their corresponding semiconductor cap 260.

[0061] The semiconductor cap 260 may be formed by epitaxial growth, during which the semiconductor cap 260 is epitaxially grown from semiconductor surfaces (including the sidewalls of the channel member 208A and the base portion 210B), but is not epitaxially grown from dielectric surfaces (such as the surfaces of the hard mask portion 209A, the gate spacers 226, the inner spacers 230, the ILD layer 234, and the sacrificial plug 250). Therefore, the semiconductor cap 260 grows only on the opposite sidewalls of the channel member 208A and the base portion 210B along the Y direction, while the epitaxial growth of the semiconductor cap 260 on the top and bottom surfaces of the channel member 208A and the top surface of the base portion 210B is blocked by the hard mask portion 209P and the sacrificial plug 250.

[0062] The thickness of the semiconductor cap 260 is controlled by the duration of the epitaxial growth process. The semiconductor cap 260 can be formed to have various thicknesses. Figures 13C to 13F is a plan view of the channel and source / drain regions showing different thicknesses of the semiconductor cap 260 formed by epitaxial growth according to some embodiments. Figure 13C As shown in FIG, the semiconductor cap 260 is formed to match the width lost by the channel member 208A during the sheet forming process. Thus, the semiconductor cap 260 has sidewalls that align with the sidewalls of the inner spacer 230 in the Y direction. The sidewalls can be curved or straight. In some other embodiments, and as shown in FIG. Figure 13D As shown in FIG, the semiconductor cap 260 is formed to have a thickness less than the width lost by the channel member 208A during the sheet forming process. Therefore, the semiconductor cap 260 has a dumbbell shape with recessed sidewalls relative to the sidewalls of the inner spacer 230 in the Y direction. In still other embodiments, and as Figure 13E and Figure 13F As shown in FIG, the semiconductor cap 260 is formed to have a thickness greater than the width lost by the channel member 208A during the sheet forming process, so that the sidewalls of the semiconductor cap 260 protrude beyond the sidewalls of the inner spacer 230 in the Y direction. In some embodiments, each protruding portion of the semiconductor cap 260 has a flat surface, such as Figure 13E In other embodiments, as shown in Figure 13F As shown in FIG, each protruding portion of the semiconductor cap 260 may have a curved surface because the semiconductor material is not grown on the dielectric surface of the gate spacer 226. In some embodiments, each protruding portion of the semiconductor cap 260 may have a thickness D1 less than 5 nm.

[0063] The thickness of the semiconductor cap 260 on the sidewalls of the channel member 208A may be the same as or different from the thickness of the semiconductor cap 260 on the sidewalls of the base portion 210B. Figure 13A As shown in FIG, in the example where the height of base portion 210B is the same as the thickness of channel member 208A, the thickness T3′ of semiconductor cap 260 on base portion 210B is the same as the thickness T3 of semiconductor cap 260 on channel member 208B. Figure 13G As shown in , in the example where the height of base portion 210B is greater than the thickness of channel member 208A, the thickness T3' of semiconductor cap 260 on base portion 210B exceeds the thickness T3 of semiconductor cap 260 on channel member 208B due to the additional surface area available for epitaxial growth.

[0064] refer to Figure 1 and FIG. 14A to FIG. 14B According to some embodiments, method 100 proceeds to operation 124 where sacrificial plug 250 is removed. Figure 14A and Figure 14B is a cross-sectional view of the GAA device 200 after the sacrificial plug 250 is removed.

[0065] The sacrificial plug 250 can be removed by an isotropic etching process. The isotropic etching process can be a dry etching process such as RIE or a wet etching process that etches the sacrificial plug 250 selectively to the channel member 208A, the base portion 210B, the semiconductor cap 260, and the hard mask portion 209P. After removing the sacrificial plug 250, the gap 242 reappears, exposing the top and bottom surfaces of the channel member 208A and the top surface of the base portion 210B in the Z direction.

[0066] refer to Figure 1 and FIG. 15A to FIG. 15B In accordance with some embodiments, method 100 proceeds to operation 126 where a gate stack 270 is formed in gate trench 240 and gap 242 . Figure 15A and Figure 15B 2 is a cross-sectional view of the GAA device 200 after forming a gate stack 270. The gate stack 270 is disposed above and between the channel nanostructures 262 and above the mesa structure 264. In some embodiments, the gate stack 270 includes an interface layer 272, a gate dielectric layer 274, a work function layer 276, and a gate electrode layer 278.

[0067] An interfacial layer 272 is formed on the exposed surfaces of the channel nanostructures 262 and the mesa structures 264. The interfacial layer 272 promotes adhesion of the gate dielectric layer 274 to the channel nanostructures 262. In some embodiments, the interfacial layer 272 may include a dielectric material such as silicon oxide. In some embodiments, the interfacial layer 272 may be formed by chemical oxidation or thermal oxidation of surface portions of the channel nanostructures 262 and the mesa structures 264. For example, in some embodiments, the interfacial layer 272 is formed using ozonated deionized water including ozone. For example, in some embodiments, the interfacial layer 272 is formed using ozonated deionized water including ozone. The thickness of the interfacial layer 272 ranges from about 0.5 nm to about 1.5 nm. In some embodiments, the interfacial layer 272 is about 1 nm thick, achieved by oxidizing about 1 nm of the channel nanostructures 262. Figures 15C to 15E is a plan view of the channel and source / drain regions showing an interface layer 272 formed in the semiconductor cap 260. In an example where the channel nanostructures 262 have sidewalls aligned with the sidewalls of the inner spacers 230, the interface layer 272 extends between the inner spacers 230 in the X direction and has sidewalls aligned with the sidewalls of the inner spacers 230 in the Y direction, as shown. Figure 15C When the channel nanostructure 262 is dumbbell-shaped, the interface layer 272 is U-shaped, laterally surrounding the gate dielectric layer 274, as shown in FIG. Figure 15D If the channel nanostructures 262 protrude beyond the sidewalls of the inner spacers 230 in the Y direction, the interface layer 272 extends between the gate spacers 226 in the X direction, with the sidewalls contacting the gate spacers 226, as shown in FIG. Figure 15E Described in.

[0068] Thereafter, a gate dielectric layer 274 is conformally deposited over the interfacial layer 272 and the hard mask portion 209P. The gate dielectric layer 274 encapsulates the channel nanostructures 262 and the hard mask portion 209P and is located on the sidewalls of the gate trench 240. In some embodiments, the gate dielectric layer 274 may include a high-k dielectric material having a dielectric constant greater than that of silicon dioxide. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and a hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy. The gate dielectric layer 274 may be formed by CVD, ALD, or other suitable conformal deposition methods. In some embodiments, the gate dielectric layer 274 is formed using a conformal deposition process such as ALD to ensure that the high-k gate dielectric layer 274 has a uniform thickness around each of the channel nanostructures 262. The gate dielectric layer 274 can be formed to have a thickness ranging from about 1 nm to about 2.5 nm. In some embodiments, the gate dielectric layer 274 can be formed to have a thickness of about 1.5 nm.

[0069] Subsequently, a work function layer 276 is deposited over the gate dielectric layer 274. For n-type FETs, the work function layer 276 may include an n-type work function layer suitable for adjusting the threshold voltage for the n-type FET. Suitable n-type work function materials include, but are not limited to, aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum silicide (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaSi), hafnium carbide (HfC), and combinations thereof. For p-type FETs, the work function layer 276 may include a p-type work function layer suitable for adjusting the threshold voltage for the p-type FET. In some embodiments, the p-type work function layer includes tungsten (W), molybdenum (Mo), tungsten nitride (WN), tungsten carbon nitride (WCN), tantalum silicon nitride (TaSiN), or tantalum nitride (TaN). The work function layer can be formed by a conformal deposition process, such as, for example, ALD or CVD. In some embodiments, the work function layer 276 may be formed to have a thickness ranging from about 1.5 nm to about 2.5 nm.

[0070] Thereafter, a gate electrode layer 278 is formed on the work function layer 276 to fill any remaining volume in the gate trench 240 and the gap 242. The gate electrode layer 278 may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. The gate electrode layer 278 may be formed by any suitable deposition process, such as CVD, PECVD, PVD, or electrochemical plating.

[0071] Next, excess portions of the gate dielectric layer 274, the work function layer 276, and the gate electrode layer 278 deposited on the top surfaces of the ILD layer 234 and the gate spacers 226 are removed in a planarization process such as a CMP process to form a gate stack 270. The top surface of the gate stack 270 may be coplanar with the top surfaces of the ILD layer 234 and the gate spacers 226. In some embodiments, and as Figure 15F As shown in FIG, portions of the gate spacers 226 and the ILD layer 234 are also removed during the CMP process to reduce the thickness of the gate electrode layer 278 over the hard mask portion 209P, thereby helping to reduce RC delay.

[0072] The gate stack 270 thus formed surrounds the channel nanostructures 262 and fills the gaps 242 between the channel nanostructures 262, the gaps 242 between the hard mask portion 209P and the topmost channel nanostructure 262, and the gaps 242 between the bottommost channel nanostructure 262 and the mesa structure 264. Between the channel nanostructures 262, a gate electrode layer 278 is circumferentially surrounded (in the cross-sectional view) by a work function layer 276, which in turn is circumferentially surrounded by a gate dielectric layer 274. In the portion of the gate stack 270 formed above the hard mask portion 209P, a gate electrode layer 278 is formed above the work function layer 276, wherein the work function layer 276 wraps around the gate electrode layer 278, and the gate dielectric layer 274 wraps around the work function layer 276.

[0073] Additional processing may be performed to complete the fabrication of the GAA device 200. For example, a gate contact (not shown for simplicity) and source / drain contacts may be formed to electrically couple to the gate stack 270 and the source / drain features 232, respectively. An interconnect structure may then be formed over the source / drain contacts and the gate contact. The interconnect structure may include multiple dielectric layers surrounding metal features (including conductive traces and conductive vias) that form electrical connections between devices on the substrate 202, such as the GAA device 200.

[0074] Embodiments of the present disclosure offer advantages. By incorporating a semiconductor cap to compensate for the loss in sheet width, the dumbbell-shaped channel profile can be improved from over 2 nm to 1 nm or less, or eliminated entirely. This increase in channel width helps reduce the overlap between the source / drain components and the metal gate, thereby reducing parasitic capacitance. Furthermore, the increased channel width enhances current flow, thereby improving device performance.

[0075] Figure 16 is a flow chart of a method 300 of forming a GAA device 400 according to some embodiments of the present disclosure. 17A to 27D 3. FIG. 3 is a diagram of a GAA device 400 at various stages of the method 300 according to some embodiments. 17A to 27D Some embodiments of method 300 are described. Method 300 is merely an example and is not intended to limit the disclosed embodiments beyond what is explicitly recited in the claims. Additional operations may be provided before, during, and after method 300, and some of the described operations may be replaced, eliminated, or moved around for additional embodiments of the method.

[0076] In operation 302, the method 300 forms an initial structure of a GAA device 400. The initial structure includes a substrate 202, a stack 204 of alternating sacrificial semiconductor layers 206 and channel semiconductor layers 208 above the substrate 202, and a hard mask layer 209 above the topmost surface of the stack 204. Figure 2 shown in the above reference Figure 2 Already discussed.

[0077] refer to Figure 16 According to some embodiments, the method 300 proceeds to operation 304, where the fin structure 210 is formed from the stack 204. This operation is described above with reference to Figure 1 and Figures 3A to 3B Already described.

[0078] refer to Figure 16 and 17A to 17B In accordance with some embodiments, method 300 proceeds to operation 306 where hard mask portion 209P is removed. Figure 17A and Figure 17B is a cross-sectional view of the GAA device 400 after removing the hard mask portion 209P.

[0079] The hard mask portion 209P is removed from the topmost surface of the fin structure 210. The removal of the hard mask portion 209P may be performed using an anisotropic etching process. The etching process may be a dry etching process such as RIE, a wet etching process, or a combination thereof.

[0080] refer to Figure 16 and 18A to 18B According to some embodiments, the method 300 proceeds to operation 308 where a dummy gate structure 220 is formed over the fin structure 210 . Figure 18A and Figure 18B is a cross-sectional view of the GAA device 400 after forming the dummy gate structure 220. The dummy gate structure 220 is formed across the fin structure 210, along the sidewalls of the fin structure 210, and over the top surface of the fin structure 210.

[0081] The dummy gate structure 220 includes a dummy gate stack (222, 224) and a gate spacer 226. According to an embodiment of the present disclosure, the dummy gate stack (222, 224) will be replaced with a metal gate stack.

[0082] In some embodiments, the dummy gate stack (222, 224) includes a dummy gate dielectric 222 and a dummy gate electrode 224 on the dummy gate dielectric 222. In some embodiments, the dummy gate stack (222, 224) may further include a dummy gate cap (not shown) on top of the dummy gate electrode 224.

[0083] In some embodiments, the dummy gate dielectric 222 may be made of silicon oxide, silicon nitride, or silicon oxynitride. The dummy gate electrode 224 may be made of silicon such as polycrystalline silicon or amorphous silicon. In some embodiments, the dummy gate stack (222, 224) may be formed by first conformally depositing a dummy gate dielectric layer over the fin structure 210 and the isolation component 216. Then, a dummy gate electrode layer is blanket deposited on the dummy gate dielectric layer so that the fin structure 210 is completely embedded in the dummy gate electrode layer. In some embodiments, the thickness of the dummy gate dielectric layer may be in the range of from about 1 nm to about 5 nm. In some embodiments, the thickness of the dummy gate electrode layer may be in the range of from about 100 nm to about 200 nm. In some embodiments, the dummy gate electrode layer is subjected to a planarization operation. The dummy gate dielectric layer and the dummy gate electrode layer may be deposited using CVD, PECVD, PVD, ALD, or other suitable deposition processes. Subsequently, the dummy gate dielectric layer and the dummy gate electrode layer are patterned using photolithography and etching processes. For example, a photoresist layer (not shown) is applied over the sacrificial electrode layer and patterned by photolithographic exposure and development. The pattern in the photoresist layer is sequentially transferred to the sacrificial electrode layer and the sacrificial dielectric layer by at least one anisotropic etching process, thereby forming a dummy gate stack (222, 224). The anisotropic etching process can be a dry etching process (e.g., RIE), a wet etching process, or a combination thereof. If not completely consumed, the remaining photoresist layer after forming the dummy gate stack (222, 224) is removed by, for example, ashing.

[0084] The gate spacer 226 is disposed along the sidewalls of the dummy gate stack (222, 224). In some embodiments, the gate spacer 226 may include a dielectric material such as, for example, an oxide, a nitride, an oxynitride, or a combination thereof. In some embodiments, the gate spacer 226 is made of silicon nitride. In some embodiments, the gate spacer 226 may be formed by first depositing a conformal gate spacer material layer on the exposed surfaces of the dummy gate stack (222, 224), the fin structure 210, and the isolation feature 216; and then etching the gate spacer material layer to remove horizontal portions of the gate spacer material layer. In some embodiments, the gate spacer material layer may be deposited, for example, by CVD, PECVD, or ALD. In some embodiments, the gate spacer material layer may be etched by dry etching, such as, for example, plasma etching or RIE. The vertical portions of the gate spacer material layer present on the sidewalls of the dummy gate stack (222, 224) constitute the gate spacer 226.

[0085] refer to Figure 16 and Figures 19A to 19B In accordance with some embodiments, method 300 proceeds to operation 310 where source / drain trenches 228 are formed in fin structure 210 . Figure 19A and Figure 19B is a cross-sectional view of the GAA device 400 after forming the source / drain trenches 228 .

[0086] In some embodiments, the sacrificial semiconductor portion 206P and the channel semiconductor portion 208P of the fin structure 210 in the source / drain region are etched using the dummy gate structure 220 as an etching mask to form a source / drain trench 228. The etching can be performed by a dry etching process such as plasma etching or RIE. Exemplary dry etching processes can be implemented with oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBr3), iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. Alternatively, the etching can be performed by a wet etching process using an etchant such as APM, TMAH or NH4OH. Figure 19B As shown in FIG, sidewalls of the sacrificial semiconductor portion 206P and the channel semiconductor portion 208P are exposed in the source / drain trench 228. In some embodiments, the substrate 202 may also be partially etched. Thus, the bottom surface of the source / drain trench 228 may be flush with or lower than the top surface of the base portion 210B.

[0087] refer to Figure 16 and FIG. 20A to FIG. 20BAccording to some embodiments, the method 300 proceeds to operation 312 where the inner spacer 230 is formed. Figure 20A and Figure 20B 2 is a cross-sectional view of the GAA device 400 after forming the inner spacer 230. The inner spacer 230 has substantially the same lateral dimensions as the gate spacer 226 and contacts the sidewalls of the sacrificial semiconductor portion 206P. Figure 1 and Figures 6A to 6B Already described.

[0088] refer to Figure 16 and Figures 21A to 21B In accordance with some embodiments, method 300 proceeds to operation 314 where source / drain features 232 are formed in source / drain trenches 228 . Figure 21A and Figure 21B 2 is a cross-sectional view of the GAA device 400 after forming the source / drain features 232. The source / drain features 232 are disposed on opposite sides of the dummy gate structure 220, the sacrificial semiconductor portion 206P, and the channel semiconductor portion 208P such that the source / drain features 232 are in contact with the channel semiconductor portion 208P but are separated from the sacrificial semiconductor portion 206P by the inner spacer 230. This operation is described above with reference to Figure 1 and 7A to 7B Already described.

[0089] refer to Figure 16 and FIG. 22A to FIG. 22B In accordance with some embodiments, the method 300 proceeds to operation 316 where an interlayer dielectric (ILD) layer 234 is formed over the source / drain features 232 and the isolation features 216 . Figure 22A and Figure 22B is a cross-sectional view of the GAA device 400 after forming the ILD layer 234. This operation is described above with reference to Figure 1 and Figures 8A to 8B Already described.

[0090] refer to Figure 16 and FIG. 23A to FIG. 23B According to some embodiments, the method 300 proceeds to operation 318 where the dummy gate stack ( 222 , 224 ) including the dummy gate dielectric 222 and the dummy gate electrode 224 is removed. Figure 23A and Figure 23B 2 is a cross-sectional view of the GAA device 400 after removing the dummy gate stack (222, 224). The removal of the dummy gate stack (222, 224) forms a gate trench 240 that exposes the sacrificial semiconductor portion 206P and the channel semiconductor portion 208P in the channel region of the fin structure 210. This operation is described above with reference to Figure 1 and Figures 9A to 9B Already described.

[0091] In some embodiments, after removing the dummy gate stack ( 222 , 224 ), a base mask layer 218 may be formed on the isolation feature 216 to surround the exposed portion ( s ) of the base portion 210B above the isolation feature 216 . Figure 24 ). Base mask layer 218 prevents subsequent epitaxial growth of semiconductor material from base portion 210B. Therefore, no semiconductor cap (eg, Figure 25A 560), thereby preventing the I off The formation of the base mask layer 218 is optional.

[0092] refer to Figure 16 and FIG. 25A to FIG. 25B In accordance with some embodiments, method 300 proceeds to operation 320 where a semiconductor cap 560 is formed on opposing sidewalls of channel semiconductor portion 208P and base portion 210B. Figure 25A and Figure 25B is a cross-sectional view of the GAA device 400 after forming a semiconductor cap 560 on opposing sidewalls of the channel semiconductor portion 208P and the base portion 210B.

[0093] The semiconductor cap 560 is designed to be consumed during the subsequent channel nanosheet formation process, thereby serving as a sacrificial component to prevent the width of the channel semiconductor portion 208P from being lost. The semiconductor cap 560 is composed of the same semiconductor material as the channel semiconductor portion 208P. For example, in some embodiments, when the channel semiconductor portion 208P is made of Si, the semiconductor cap 560 is also composed of Si. An interface may or may not exist between the channel members 208A and their corresponding semiconductor caps 560.

[0094] The semiconductor cap 560 can be formed by selectively depositing a semiconductor material on the sidewalls of the channel semiconductor portion 208P and the base portion 210B exposed by the gate trench 240 using ALD, CVD, PVD, or other suitable methods. The thickness T3 of the semiconductor cap 560 can be in a range from about 0.5 nm to about 4 nm. In some embodiments, the thickness T3 of the semiconductor cap 560 is about 0.75 nm, about 1 nm, about 1.5 nm, about 2 nm, about 2.5 nm, about 3 nm, or about 3.5 nm. The topmost sacrificial semiconductor portion 206P within the fin structure 210 helps prevent the growth of the semiconductor cap on the topmost surface of the fin structure 210.

[0095] refer to Figure 16 and Figures 26A to 26B According to some embodiments, method 300 proceeds to operation 322 where sacrificial semiconductor portion 206P is removed. Figure 26A and Figure 26B is a cross-sectional view of the GAA device 400 after removing the sacrificial semiconductor portion 206P.

[0096] The selective removal of the sacrificial semiconductor portion 206P releases the channel semiconductor portion 208P to form the channel member 208A. In some embodiments, the sacrificial semiconductor portion 206P can be removed by a selective etching process using an etchant that is selective for the material of the sacrificial semiconductor portion 206P, thereby removing the sacrificial semiconductor portion 206P without substantially attacking the channel semiconductor portion 208P and the semiconductor cap 560. In some embodiments, the etching process is an isotropic etching process, which can be a dry etching process or a wet etching process. In some embodiments, the selective etching process can include oxidizing the sacrificial semiconductor portion 206P using a suitable oxidizing agent, such as ozone. The oxidized sacrificial semiconductor portion 206P can then be selectively removed. In some embodiments, when the channel semiconductor portion 208P and the semiconductor cap 560 comprise Si and the sacrificial semiconductor portion 206P comprises SiGe, the sacrificial semiconductor portion 206P can be selectively removed by applying HCl gas at a temperature of approximately 500° C. to approximately 700° C., or by applying a gas mixture of CF4, SF6, and CHF3. The inner spacer 230 acts as an etch stop layer to protect the source / drain features 232 during the etching process. The etching process also removes the semiconductor cap 560. In some embodiments, the semiconductor cap 560 is completely consumed. The resulting channel member 208A (also now referred to as the channel nanostructure 562) retains the original width W1 of the channel semiconductor portion 208P. In some embodiments, the channel nanostructure 562 is a nanosheet.

[0097] Figure 26C and Figure 26D is a plan view of the channel and source / drain regions showing the channel nanostructure 562 formed after the etching process. In some embodiments, the semiconductor cap 560 formed on the sidewalls of the base portion 210B is completely consumed by the etching process. The resulting channel nanostructure 562 is formed only of the channel member 208A, wherein the sidewalls are aligned with the sidewalls of the inner spacer 230 along the Y direction, as shown in FIG. Figure 26C As shown in . Therefore, the channel nanostructure 562 has a width W1 that is the same as the width of the channel semiconductor portion 208P. In other embodiments, the semiconductor cap 560 formed on the sidewall of the base portion 210B is partially consumed by the etching process. Figure 26D As shown in FIG, the resulting channel nanostructure 562 includes the channel member 208A and the remaining portion of the semiconductor cap 560. The sidewalls of the channel nanostructure 562 extend beyond the sidewalls of the inner spacer 230 in the Y direction.

[0098] In some embodiments, the semiconductor caps 560 formed on the sidewalls of the base portion 210B are also completely consumed by the etching process. The remaining portion of the base portion 210B is referred to herein as a mesa structure 564. In instances where the semiconductor caps 560 on the sidewalls of the base portion 210B have a thickness greater than that of the semiconductor caps 560 on the sidewalls of the channel member 208A, the semiconductor caps 560 formed on the sidewalls of the base portion 210B may be partially consumed during the etching process. The mesa structure 564 may remain as a remaining portion of the semiconductor caps 560.

[0099] In some embodiments, after removing the sacrificial semiconductor portion 206P, a trimming operation can be performed to reduce the thickness of the channel nanostructure 562 to improve the gate fill window. The trimming operation can utilize any suitable etching process, such as dry etching, wet etching, or a combination thereof. After the trimming operation, the channel nanostructure 562 can have a width W3 ranging from about 10 nm to about 90 nm (e.g., from about 12.5 nm to about 45 nm) and a thickness T4 ranging from about 4 nm to about 7 nm.

[0100] Due to the removal of the sacrificial semiconductor portion 206P and the nanosheet trimming, gaps 242 (e.g., empty spaces) are formed between adjacent channel nanostructures 562 and between the bottommost channel nanostructure 562 and the base portion 210B. The gaps 242 define the spacing S between adjacent channel nanostructures 562. In some embodiments, the spacing between adjacent channel nanostructures 562 (also referred to as the sheet-to-sheet spacing) can be in the range of from about 8 nm to about 15 nm.

[0101] refer to Figure 16 and FIG. 27A to FIG. 27B In accordance with some embodiments, the method 300 proceeds to operation 324 where a gate stack 270 is formed in the gate trench 240 and the gap 242 . Figure 27A and Figure 27B is a cross-sectional view of the GAA device 400 after forming a gate stack 270. The gate stack 270 is disposed above and between the channel nanostructures 562 and above the mesa structure 564. In some embodiments, the gate stack 270 includes an interface layer 272, a gate dielectric layer 274, a work function layer 276, and a gate electrode layer 278.

[0102] An interfacial layer 272 is formed on the exposed surfaces of the channel nanostructures 562 and the top surfaces of the mesa structures 564. The interfacial layer 272 promotes adhesion of the gate dielectric layer 274 to the channel nanostructures 562. In some embodiments, the interfacial layer 272 may include a dielectric material such as silicon oxide. In some embodiments, the interfacial layer 272 may be formed by chemical oxidation or thermal oxidation of surface portions of the channel nanostructures 562 and the mesa structures 564. For example, in some embodiments, the interfacial layer 272 is formed using ozonated deionized water containing ozone. The thickness of the interfacial layer 272 ranges from approximately 0.5 nm to approximately 1.5 nm. In some embodiments, the interfacial layer 272 is approximately 1 nm thick, achieved by oxidizing approximately 1 nm of the channel nanostructures 562. The sidewalls of the interfacial layer 272 are aligned with the sidewalls of the inner spacer 230.

[0103] A gate dielectric layer 274 is conformally deposited over the interfacial layer 272. The gate dielectric layer 274 wraps around the channel nanostructures 262 and is located on the sidewalls of the gate trench 240. In some embodiments, the gate dielectric layer 274 may include a high-k dielectric material having a dielectric constant greater than that of silicon dioxide. Examples of high-k dielectric materials include, but are not limited to, hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide (ZrO2), aluminum oxide (Al2O3), titanium oxide (TiO2), and a hafnium oxide-aluminum oxide (HfO2-Al2O3) alloy. The gate dielectric layer 274 may be formed by CVD, ALD, or other suitable conformal deposition methods. In some embodiments, the gate dielectric layer 274 is formed using a conformal deposition process such as ALD to ensure that the high-k gate dielectric layer 274 has a uniform thickness around each of the channel nanostructures 562. The gate dielectric layer 274 can be formed to have a thickness ranging from about 1 nm to about 2.5 nm. In some embodiments, the gate dielectric layer 274 can be formed to have a thickness of about 1.5 nm.

[0104] Figure 27C and Figure 27D is a plan view of the channel and source / drain regions showing the formed interfacial layer 272. In the example where the channel nanostructures 562 have sidewalls aligned with the sidewalls of the inner spacers 230, the interfacial layer 272 extends between the inner spacers 230 in the X direction and has sidewalls aligned with the sidewalls of the inner spacers 230 in the Y direction, as shown. Figure 27C If the channel nanostructures 562 protrude beyond the sidewalls of the inner spacers 230 in the Y direction, the interface layer 272 extends between the gate spacers 226 in the X direction, with the sidewalls contacting the gate spacers 226, as shown in FIG. Figure 27D Described in.

[0105] Subsequently, a work function layer 276 is deposited over the gate dielectric layer 274. For n-type FETs, the work function layer 276 may include an n-type work function layer suitable for adjusting the threshold voltage for the n-type FET. Suitable n-type work function materials include, but are not limited to, aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum carbide (TaAlC), tantalum aluminum silicide (TaSiAl), tantalum silicon carbide (TaSiC), tantalum silicide (TaSi), hafnium carbide (HfC), and combinations thereof. For p-type FETs, the work function layer 276 may include a p-type work function layer suitable for adjusting the threshold voltage for the p-type FET. In some embodiments, the p-type work function layer includes tungsten (W), molybdenum (Mo), tungsten nitride (WN), tungsten carbon nitride (WCN), tantalum silicon nitride (TaSiN), or tantalum nitride (TaN). The work function layer can be formed by a conformal deposition process, such as, for example, ALD or CVD. In some embodiments, the work function layer 276 may be formed to have a thickness ranging from about 1.5 nm to about 2.5 nm.

[0106] Thereafter, a gate electrode layer 278 is formed on the work function layer 276 to fill any remaining volume in the gate trench 240 and the gap 242. The gate electrode layer 278 may include a conductive material such as tungsten, cobalt, ruthenium, iridium, molybdenum, copper, aluminum, or a combination thereof. The gate electrode layer 278 may be formed by any suitable deposition process, such as CVD, PECVD, PVD, or electrochemical plating.

[0107] Next, excess portions of the gate dielectric layer 274, work function layer 276, and gate electrode layer 278 deposited on the top surfaces of the ILD layer 234 and gate spacers 226 are removed in a planarization process, such as a CMP process, to form a gate stack 270. The top surface of the gate stack 270 may be coplanar with the top surfaces of the ILD layer 234 and gate spacers 226. The gate stack 270 surrounds the channel nanostructures 562. Between the channel nanostructures 562, the gate electrode layer 278 is circumferentially surrounded by the work function layer 276 (in the cross-sectional view), which in turn is circumferentially surrounded by the gate dielectric layer 274. In the portion of the gate stack 270 formed above the topmost channel nanostructure 562, a gate electrode layer 278 is formed above the work function layer 276. The work function layer 276 wraps around the gate electrode layer 278. The gate dielectric layer 274 also wraps around the work function layer 276.

[0108] Additional processing may be performed to complete the fabrication of the GAA device 400. For example, a gate contact (not shown for simplicity) and source / drain contacts may be formed to electrically couple to the gate stack 270 and the source / drain features 232, respectively. An interconnect structure may then be formed over the source / drain contacts and the gate contact. The interconnect structure may include multiple dielectric layers surrounding metal features (including conductive traces and conductive vias) that form electrical connections between devices on the substrate 202, such as the GAA device 400.

[0109] Embodiments of the present disclosure offer advantages. By using a semiconductor cap as a sacrificial component to prevent loss of width in the channel semiconductor portion, the dumbbell-shaped channel profile can be improved from over 2 nm to 1 nm or less, or eliminated entirely. This increase in channel width helps reduce the overlap between the source / drain components and the metal gate, thereby reducing parasitic capacitance. Furthermore, the increased channel width enhances current flow. Consequently, device performance can be improved.

[0110] One aspect of the present disclosure relates to a method for forming a semiconductor device. The method includes forming a fin structure above a substrate. The fin structure includes a fin stack portion comprising alternating first and second semiconductor portions. Next, forming a dummy gate structure including a dummy gate stack and gate spacers on sidewalls of the dummy gate stack. The dummy gate stack spans a channel region of the fin structure. Next, forming source / drain components above source / drain regions of the fin structure on opposite sides of the dummy gate structure. Next, removing the dummy gate stack to form a gate trench that exposes the sidewalls of the first and second semiconductor portions. Next, selectively removing the first semiconductor portion to release the second semiconductor portion in the channel region as a channel member. Next, depositing a dielectric material to fill a gap between the channel members. Next, depositing a semiconductor cap on the sidewalls of the channel member. Next, removing the deposited dielectric material in the gap, followed by forming a gate stack to surround the semiconductor cap and the channel member. The gate stack fills the gap.

[0111] Another aspect of the present specification relates to a method for forming a semiconductor device. The method includes forming a fin structure above a substrate. The fin structure includes a fin stack portion of a first semiconductor portion and a second semiconductor portion alternately stacked. Next, a dummy gate structure including a dummy gate stack is formed across a channel region of the fin structure and gate spacers on sidewalls of the dummy gate stack. Next, source / drain components are formed above source / drain regions of the fin structure on opposite sides of the dummy gate structure. Next, the dummy gate stack is removed to form a gate trench that exposes the sidewalls of the first semiconductor portion and the second semiconductor portion. Next, a semiconductor cap is selectively grown on the sidewalls of the second semiconductor portion. Next, the first semiconductor portion is selectively removed to release the second semiconductor portion in the channel region as a channel component, followed by forming a gate stack to surround the channel component, wherein the gate stack fills the gap between the channel components.

[0112] Yet another aspect of the present disclosure relates to a semiconductor device. The semiconductor device includes a plurality of suspended channel nanostructures located above a substrate and having a length dimension in a first direction and a width dimension in a second direction transverse to the first direction. Each of the plurality of channel nanostructures includes a channel member and a semiconductor cap located on opposite sidewalls of the channel member along the second direction. The semiconductor device also includes a gate structure including a gate stack surrounding a channel region of each of the plurality of channel nanostructures and filling gaps between the channel nanostructures. The sidewalls of the gate stack along the first direction are surrounded by internal spacers.

[0113] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a fin structure above a substrate, the fin structure comprising a fin stack portion of a first semiconductor portion and a second semiconductor portion alternately stacked; forming a dummy gate structure comprising a dummy gate stack and a gate spacer located on the sidewalls of the dummy gate stack, the dummy gate stack spanning a channel region of the fin structure; forming a source / drain component above a source / drain region of the fin structure on opposite sides of the dummy gate structure; removing the dummy gate stack to form a gate trench exposing the sidewalls of the first semiconductor portion and the second semiconductor portion; selectively removing the first semiconductor portion to release the second semiconductor portion in the channel region as a channel component; depositing a dielectric material to fill a gap between the channel components; selectively growing a semiconductor cap on the sidewalls of the channel component; removing the deposited dielectric material in the gap; and forming a gate stack to surround the semiconductor cap and the channel component, wherein the gate stack fills the gap.

[0114] In some embodiments, the method further includes forming a hard mask portion over the fin stack portion, wherein, after removing the first semiconductor portion, the hard mask portion contacts a topmost channel member of the channel member, and the gate stack surrounds a portion of the hard mask portion and fills a gap between the topmost channel member and the hard mask portion. In some embodiments, the method further includes recessing the source / drain region of the fin structure to expose sidewalls of the first and second semiconductor portions in the channel region after forming the dummy gate structure; selectively recessing the exposed sidewalls of the first semiconductor portion to form an inner spacer recess; and forming an inner spacer in the inner spacer recess, wherein the source / drain feature contacts the inner spacer. In some embodiments, the sidewalls of the semiconductor cap exposed by the gate trench are recessed relative to sidewalls of the inner spacer. In some embodiments, the sidewalls of the semiconductor cap exposed by the gate trench protrude beyond sidewalls of the inner spacer. In some embodiments, the sidewalls of the semiconductor cap exposed by the gate trench are aligned with sidewalls of the inner spacer. In some embodiments, the semiconductor cap has a flat surface or a curved surface. In some embodiments, the dielectric material comprises aluminum oxide. In some embodiments, the fin structure further comprises a base portion located below the fin stack portion, wherein selectively growing the semiconductor cap on the sidewalls of the channel member also forms another semiconductor cap on the sidewalls of the base portion. In some embodiments, the another semiconductor cap on the sidewalls of the base portion has a thickness equal to or greater than a thickness of the semiconductor cap on the sidewalls of the channel member.

[0115] Other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a fin structure above a substrate, the fin structure comprising a fin stack portion of a first semiconductor portion and a second semiconductor portion alternately stacked; forming a dummy gate structure, the dummy gate structure comprising a dummy gate stack spanning a channel region of the fin structure and a gate spacer located on a sidewall of the dummy gate stack; forming a source / drain component above a source / drain region of the fin structure on opposite sides of the dummy gate structure; removing the dummy gate stack to form a gate trench exposing the sidewalls of the first semiconductor portion and the second semiconductor portion; selectively growing a semiconductor cap on the sidewall of the second semiconductor portion; selectively removing the first semiconductor portion to release the second semiconductor portion in the channel region as a channel component; and forming a gate stack to surround the channel component, wherein the gate stack fills the gap between the channel components.

[0116] In some embodiments, the method further comprises: after forming the dummy gate structure, recessing the source / drain region of the fin structure to expose sidewalls of the first semiconductor portion and the second semiconductor portion in the channel region; selectively recessing the exposed sidewalls of the first semiconductor portion to form an inner spacer recess; and forming an inner spacer in the inner spacer recess, wherein the source / drain component contacts the inner spacer. In some embodiments, selectively removing the first semiconductor portion is performed by an isotropic etching process. In some embodiments, the semiconductor cap is completely removed by the isotropic etching process. In some embodiments, the semiconductor cap is partially removed by the isotropic etching process, wherein the gate stack surrounds the remaining portion of the semiconductor cap and the channel member.

[0117] Still other embodiments of the present application provide a semiconductor device comprising: a plurality of suspended channel nanostructures located above a substrate and having a length dimension in a first direction and a width dimension in a second direction transverse to the first direction, each of the plurality of channel nanostructures comprising a channel member and a semiconductor cap located on opposite sidewalls of the channel member along the second direction; and a gate stack surrounding a channel region of each of the plurality of channel nanostructures and filling gaps between the channel nanostructures, wherein the sidewalls of the gate stack along the first direction are surrounded by internal spacers.

[0118] In some embodiments, the sidewalls of the semiconductor cap are aligned with the sidewalls of the inner spacer along the second direction. In some embodiments, the sidewalls of the semiconductor cap are recessed relative to the sidewalls of the inner spacer along the second direction. In some embodiments, the sidewalls of the semiconductor cap protrude beyond the sidewalls of the inner spacer along the second direction. In some embodiments, the semiconductor device further comprises: a hard mask portion located above a topmost channel nanostructure of the plurality of channel nanostructures, the gate stack surrounding the topmost channel nanostructure and filling a gap between the hard mask portion and the topmost channel nanostructure.

[0119] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art will appreciate that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent constructions do not depart from the spirit and scope of the embodiments of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a fin structure over a substrate, the fin structure including a fin stack portion of alternately stacked first semiconductor portions and second semiconductor portions; forming a dummy gate structure including a dummy gate stack and gate spacers on sidewalls of the dummy gate stack, wherein the dummy gate stack spans a channel region of the fin structure; forming source / drain features over source / drain regions of the fin structure on opposite sides of the dummy gate structure; removing the dummy gate stack to form a gate trench exposing sidewalls of the first semiconductor portion and the second semiconductor portion; selectively removing the first semiconductor portion to release the second semiconductor portion in the channel region as a channel member; depositing a dielectric material to fill gaps between the channel members; selectively growing a semiconductor cap on the sidewalls of the channel member; removing the deposited dielectric material in the gap; as well as A gate stack is formed to surround the semiconductor cap and the channel member, wherein the gate stack fills the gap.

2. The method according to claim 1, further comprising: A hard mask portion is formed over the fin stack portion, wherein, after removing the first semiconductor portion, the hard mask portion contacts a topmost channel member of the channel members, and the gate stack surrounds a portion of the hard mask portion and fills a gap between the topmost channel member and the hard mask portion.

3. The method according to claim 1, further comprising: After forming the dummy gate structure, recessing the source / drain region of the fin structure to expose sidewalls of the first semiconductor portion and the second semiconductor portion in the channel region; selectively recessing the exposed sidewalls of the first semiconductor portion to form inner spacer recesses; as well as An inner spacer is formed in the inner spacer groove, wherein the source / drain feature contacts the inner spacer.

4. The method according to claim 3, wherein: The sidewalls of the semiconductor cap exposed by the gate trench are recessed relative to sidewalls of the inner spacer.

5. The method according to claim 3, wherein: The sidewalls of the semiconductor cap exposed by the gate trench protrude beyond sidewalls of the inner spacer.

6. The method according to claim 3, wherein: The sidewalls of the semiconductor cap exposed by the gate trench are aligned with sidewalls of the inner spacer.

7. The method according to claim 1, wherein The semiconductor cap has a flat surface or a curved surface.

8. The method according to claim 1, wherein The dielectric material includes aluminum oxide.

9. A method for forming a semiconductor device, comprising: forming a fin structure over a substrate, the fin structure including a fin stack portion of alternately stacked first semiconductor portions and second semiconductor portions; forming a dummy gate structure, the dummy gate structure comprising a dummy gate stack spanning a channel region of the fin structure and a gate spacer located on a sidewall of the dummy gate stack; forming source / drain features over source / drain regions of the fin structure on opposite sides of the dummy gate structure; removing the dummy gate stack to form a gate trench exposing sidewalls of the first semiconductor portion and the second semiconductor portion; selectively growing a semiconductor cap on the sidewalls of the second semiconductor portion; selectively removing the first semiconductor portion to release the second semiconductor portion in the channel region as a channel member; as well as A gate stack is formed to surround the channel members, wherein the gate stack fills gaps between the channel members.

10. A semiconductor device comprising: a plurality of suspended channel nanostructures positioned above the substrate and having a length dimension in a first direction and a width dimension in a second direction transverse to the first direction, each of the plurality of channel nanostructures comprising a channel member and a semiconductor cap positioned on opposite sidewalls of the channel member along the second direction; as well as A gate stack surrounds the channel region of each of the plurality of channel nanostructures and fills gaps between the channel nanostructures, wherein a sidewall of the gate stack along the first direction is surrounded by an inner spacer.

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