Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device and a method for manufacturing a semiconductor device are provided. The semiconductor device may include: a lower interlayer insulating layer; an insulating pattern on the lower interlayer insulating layer; an active pattern on the lower interlayer insulating layer and spaced apart from the insulating pattern; a dummy active pattern on the active pattern; a field insulating layer on sidewalls of the insulating pattern, sidewalls of the active pattern, and sidewalls of the dummy active pattern; a first nanosheet on the insulating pattern; a second nanosheet on the dummy active pattern; a gate electrode on the insulating pattern and the dummy active pattern, and on the first nanosheet and the second nanosheet; a first source / drain region on one side of the gate electrode and on the insulating pattern; a second source / drain region on the one side of the gate electrode and on the dummy active pattern; a bottom source / drain contact electrically connected to the first source / drain region; and an upper source / drain contact electrically connected to the second source / drain region.

Description

[0001] This application claims priority from Korean Patent Application No. 10-2024-0031779 filed on March 6, 2024, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a semiconductor device and a method of manufacturing a semiconductor device, and more particularly to a semiconductor device including, for example, an MBCFET. TM A semiconductor device (multi-bridge channel field effect transistor) and a method for manufacturing the semiconductor device. Background Art

[0003] As one of scaling technologies for increasing the density of integrated circuit devices, a multi-gate transistor has been proposed in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate and a gate is formed on a surface of the silicon body.

[0004] These multi-gate transistors utilize a three-dimensional channel and are easily scaled down. Furthermore, current control capability can be improved without increasing the gate length of the multi-gate transistor. Furthermore, short channel effects (SCE), in which the potential of the channel region is affected by the drain voltage, can be effectively suppressed. Summary of the Invention

[0005] Aspects of the present disclosure provide a semiconductor device and a method of manufacturing the semiconductor device that take into account the structural stability of source / drain regions to which bottom source / drain contacts are connected.

[0006] Aspects of the present disclosure are not limited to those mentioned above, and other aspects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0007] According to some embodiments of the present disclosure, a semiconductor device may include: a lower interlayer insulating layer; an insulating pattern extending along a first horizontal direction on an upper surface of the lower interlayer insulating layer; an active pattern extending along the first horizontal direction on an upper surface of the lower interlayer insulating layer, the active pattern being spaced apart from the insulating pattern in a second horizontal direction different from the first horizontal direction, the active pattern comprising a material different from that of the insulating pattern; a dummy active pattern extending along the first horizontal direction on an upper surface of the active pattern and contacting the upper surface of the active pattern; a field insulating layer on an upper surface of the lower interlayer insulating layer and on sidewalls of the insulating pattern, the active pattern, and the dummy active pattern; a first plurality of nanosheets stacked in a vertical direction and spaced apart from each other on an upper surface of the insulating pattern; a second plurality of nanosheets on an upper surface of the dummy active pattern stacked in a vertical direction on the surface and spaced apart from each other; a gate electrode extending in a second horizontal direction on the insulating pattern and the dummy active pattern, the gate electrode at least partially surrounding each of the first plurality of nanosheets and the second plurality of nanosheets; a first source / drain region on one side of the gate electrode and on the insulating pattern, the first source / drain region contacting the insulating pattern; a second source / drain region on the one side of the gate electrode and on the dummy active pattern, the second source / drain region contacting the dummy active pattern; a bottom source / drain contact extending in a vertical direction in the lower interlayer insulating layer and the insulating pattern, the bottom source / drain contact electrically connected to the first source / drain region; and an upper source / drain contact on the second source / drain region, the upper source / drain contact electrically connected to the second source / drain region.

[0008] According to some embodiments of the present disclosure, a semiconductor device may include: a lower interlayer insulating layer; an insulating pattern extending along a first horizontal direction on an upper surface of the lower interlayer insulating layer; an active pattern extending along the first horizontal direction on an upper surface of the lower interlayer insulating layer, the active pattern being spaced apart from the insulating pattern in a second horizontal direction different from the first horizontal direction, the active pattern including a material different from that of the insulating pattern; a dummy active pattern extending along the first horizontal direction on an upper surface of the active pattern and contacting an upper surface of the active pattern, the dummy active pattern including silicon germanium (SiGe); and a field insulating layer on an upper surface of the lower interlayer insulating layer and on sidewalls of the insulating pattern, the active pattern, and the dummy active pattern. In which, relative to the upper surface of the lower interlayer insulating layer, the upper surface of the field insulating layer is higher than the upper surface of the insulating pattern and the upper surface of the dummy active pattern in the vertical direction; the gate electrode extends along the second horizontal direction on the insulating pattern and the dummy active pattern; the first source / drain region is on one side of the gate electrode and on the insulating pattern; the second source / drain region is on the said side of the gate electrode and on the dummy active pattern; the bottom source / drain contact extends in the vertical direction in the lower interlayer insulating layer and the insulating pattern, the bottom source / drain contact is electrically connected to the first source / drain region; and the upper source / drain contact is on the second source / drain region, the upper source / drain contact is electrically connected to the second source / drain region.

[0009] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device may include: forming a first semiconductor layer including silicon germanium (SiGe) on an upper surface of a substrate; alternately stacking a second semiconductor layer including silicon (Si) and a third semiconductor layer including silicon germanium (SiGe) on an upper surface of the first semiconductor layer; etching a portion of the substrate and a portion of the first to third semiconductor layers to form a first active pattern and a second active pattern extending along a first horizontal direction on a lower surface of the first semiconductor layer, wherein the second active pattern is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; forming a field insulating layer on the substrate and on sidewalls of the first active pattern, sidewalls of the second active pattern, and sidewalls of the first semiconductor layer; forming a dummy gate extending along a second horizontal direction on an upper surface of the field insulating layer and on an upper surface of an uppermost second semiconductor layer among the second semiconductor layers; forming a first source / drain region on one side of the dummy gate and on the first active pattern, and and forming a second source / drain region on the side of the dummy gate and on the second active pattern, wherein a first portion of the first semiconductor layer in contact with the lower surface of the first source / drain region is defined as a first dummy active pattern, and wherein a second portion of the first semiconductor layer in contact with the lower surface of the second source / drain region is defined as a second dummy active pattern; etching the dummy gate and the third semiconductor layer to form a gate trench; forming a gate electrode in the gate trench; forming an upper source / drain contact on the second source / drain region, and the upper source / drain contact is electrically connected to the second source / drain region; etching the substrate; forming a protective layer on the lower surface of the second active pattern; etching the first active pattern and the first dummy active pattern; forming an insulating pattern on the lower surface of the first source / drain region, the insulating pattern extending in a first horizontal direction; and forming a bottom source / drain contact, the bottom source / drain contact extending in a vertical direction in the insulating pattern and electrically connected to the first source / drain region. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the attached drawings.

[0011] Figure 1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present disclosure.

[0012] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'.

[0013] Figure 3 It is along Figure 1 A cross-sectional view taken along line BB'.

[0014] Figure 4 It is along Figure 1 A cross-sectional view taken along line CC'.

[0015] Figure 5 It is along Figure 1 A cross-sectional view taken along line D-D'.

[0016] Figures 6 to 41 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0017] Figures 42 to 44 are cross-sectional views for explaining semiconductor devices according to some other embodiments of the present disclosure.

[0018] Figures 45 to 47 are cross-sectional views for explaining semiconductor devices according to some other embodiments of the present disclosure.

[0019] Figure 48 and Figure 49 are cross-sectional views for explaining semiconductor devices according to some other embodiments of the present disclosure. DETAILED DESCRIPTION

[0020] In the following, reference will be made to Figures 1 to 5 Semiconductor devices according to some embodiments of the present disclosure are described.

[0021] Figure 1 is a layout diagram for explaining a semiconductor device according to some embodiments of the present disclosure. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA'. Figure 3 It is along Figure 1 A cross-sectional view taken along line BB'. Figure 4 It is along Figure 1 A cross-sectional view taken along line CC'. Figure 5 It is along Figure 1 A cross-sectional view taken along line D-D'.

[0022] Reference Figures 1 to 5The semiconductor device according to some embodiments of the present disclosure includes a lower interlayer insulating layer 100, an insulating pattern 101, a second active pattern F2, a second dummy active pattern DF2, a field insulating layer 105, a first plurality of nanosheets NW1 to a fourth plurality of nanosheets NW4, a first gate electrode G1 and a second gate electrode G2, a first gate spacer 111 and a second gate spacer 112, a first gate insulating layer 121 and a second gate insulating layer 122, a first capping pattern 131 and a second capping pattern 132, a first source / drain region SD1 and a second source / drain region SD2, a first etch stop layer 140, a first upper interlayer insulating layer 150, an upper source / drain contact UCA, a bottom source / drain contact BCA, an upper silicide layer USL, a bottom silicide layer BSL, a gate contact CB, a second etch stop layer 160, a second upper interlayer insulating layer 170, and a first via V1 and a second via V2.

[0023] The lower interlayer insulating layer 100 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. The low-k material may include, for example, tetraethyl fluoride orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxydi-tert-butyloxysiloxane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ (Tongran Silazane), FSG (fluorosilicate glass), polyimide nanofoam such as polypropylene oxide, CDO (carbon-doped silicon oxide), OSG (organosilicate glass), SiLK, amorphous fluorinated carbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but the present disclosure is not limited thereto.

[0024] Hereinafter, each of the first horizontal direction DR1 and the second horizontal direction DR2 may be defined as a direction parallel to the upper surface of the lower interlayer insulating layer 100. The second horizontal direction DR2 may be defined as a direction different from the first horizontal direction DR1. The vertical direction DR3 may be defined as a direction perpendicular to each of the first horizontal direction DR1 and the second horizontal direction DR2. In other words, the vertical direction DR3 may be defined as a direction perpendicular to the upper surface of the lower interlayer insulating layer 100.

[0025] The insulating pattern 101 may extend along a first horizontal direction DR1 on the upper surface of the lower interlayer insulating layer 100. The insulating pattern 101 may protrude from the upper surface of the lower interlayer insulating layer 100 in a vertical direction DR3. The lower surface of the insulating pattern 101 may contact the upper surface of the lower interlayer insulating layer 100. The insulating pattern 101 may include an insulating material. For example, the insulating pattern 101 may include the same material as the lower interlayer insulating layer 100.

[0026] The second active pattern F2 may extend along the first horizontal direction DR1 on the upper surface of the lower interlayer insulating layer 100. The second active pattern F2 may be spaced apart from the insulating pattern 101 in the second horizontal direction DR2. The second active pattern F2 may protrude from the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3. The second active pattern F2 may be in contact with the upper surface of the lower interlayer insulating layer 100. For example, the uppermost surface of the second active pattern F2 may be formed lower than the uppermost surface of the insulating pattern 101 (for example, when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). For example, the lower surface of the second active pattern F2 may be formed on the same plane as the lower surface of the insulating pattern 101 (i.e., may be coplanar with the lower surface of the insulating pattern 101). For example, the second active pattern F2 may overlap with the insulating pattern 101 in the second horizontal direction DR2. As used herein, "element A overlaps element B in direction X" (or similar language) means that there is at least one straight line extending along direction X and intersecting both elements A and B. The second active pattern F2 may include a material different from that of the lower interlayer insulating layer 100 and the insulating pattern 101, respectively. For example, the second active pattern F2 may include silicon (Si).

[0027] The second dummy active pattern DF2 may extend along the first horizontal direction DR1 on the upper surface of the second active pattern F2. The lower surface of the second dummy active pattern DF2 may contact the upper surface of the second active pattern F2. For example, the profiles of the two sidewalls of the second dummy active pattern DF2 in the second horizontal direction DR2 may be formed continuously with the profiles of the two sidewalls of the second active pattern F2 in the second horizontal direction DR2. In other words, the opposing sidewalls of the second dummy active pattern DF2 in the second horizontal direction DR2 may be collinear with the opposing sidewalls of the second active pattern F2 in the second horizontal direction DR2 along the vertical direction DR3. For example, the uppermost surface of the second dummy active pattern DF2 may be formed on the same plane as the uppermost surface of the insulating pattern 101. For example, the second dummy active pattern DF2 may overlap the insulating pattern 101 in the second horizontal direction DR2. For example, the second dummy active pattern DF2 may include silicon germanium (SiGe).

[0028] A first plurality of nanosheets NW1 may be disposed on the upper surface of the insulating pattern 101. The first plurality of nanosheets NW1 may be disposed at the intersection of the insulating pattern 101 and the first gate electrode G1. The lower surface of the lowest nanosheet in the first plurality of nanosheets NW1 may be in contact with the upper surface of the insulating pattern 101. A second plurality of nanosheets NW2 may be disposed on the upper surface of the insulating pattern 101. The second plurality of nanosheets NW2 may be disposed at the intersection of the insulating pattern 101 and the second gate electrode G2. The second plurality of nanosheets NW2 may be spaced apart from the first plurality of nanosheets NW1 in the first horizontal direction DR1. The lower surface of the lowest nanosheet in the second plurality of nanosheets NW2 may be in contact with the upper surface of the insulating pattern 101.

[0029] A third plurality of nanosheets NW3 may be disposed on the upper surface of the second dummy active pattern DF2. The third plurality of nanosheets NW3 may be disposed at the intersection of the second dummy active pattern DF2 and the first gate electrode G1. The third plurality of nanosheets NW3 may be spaced apart from the first plurality of nanosheets NW1 in the second horizontal direction DR2. The lower surface of the lowest nanosheet in the third plurality of nanosheets NW3 may be in contact with the upper surface of the second dummy active pattern DF2. A fourth plurality of nanosheets NW4 may be disposed on the upper surface of the second dummy active pattern DF2. The fourth plurality of nanosheets NW4 may be disposed at the intersection of the second dummy active pattern DF2 and the second gate electrode G2. The fourth plurality of nanosheets NW4 may be spaced apart from the third plurality of nanosheets NW3 in the first horizontal direction DR1. The fourth plurality of nanosheets NW4 may be spaced apart from the second plurality of nanosheets NW2 in the second horizontal direction DR2. The lower surface of the lowest nanosheet in the fourth plurality of nanosheets NW4 may be in contact with the upper surface of the second dummy active pattern DF2.

[0030] Each of the first to fourth plurality of nanosheets (NW1 to NW4) may include a plurality of nanosheets stacked and spaced apart from each other in the vertical direction DR3. Figures 2 to 4In the figure, each of the first to fourth pluralities of nanosheets (NW1 to NW4) is illustrated as including four nanosheets stacked and spaced apart in the vertical direction DR3, but this is for ease of explanation and the present disclosure is not limited thereto. In some other embodiments, each of the first to fourth pluralities of nanosheets (NW1 to NW4) may include three nanosheets stacked and spaced apart in the vertical direction DR3. In some other embodiments, each of the first to fourth pluralities of nanosheets (NW1 to NW4) may include five or more nanosheets stacked and spaced apart in the vertical direction DR3. For example, each of the first to fourth pluralities of nanosheets (NW1 to NW4) may include silicon (Si). However, the present disclosure is not limited thereto. In some other embodiments, each of the first to fourth pluralities of nanosheets (NW1 to NW4) may include silicon germanium (SiGe).

[0031] A field insulating layer 105 may be disposed on the upper surface of the lower interlayer insulating layer 100. The field insulating layer 105 may surround the sidewalls of each of the insulating pattern 101, the second active pattern F2, and the second dummy active pattern DF2. The field insulating layer 105 may contact the sidewalls of each of the insulating pattern 101, the second active pattern F2, and the second dummy active pattern DF2. For example, the field insulating layer 105 may contact the sidewalls (e.g., the lower portions of the sidewalls) of the lowermost nanosheet of each of the first and third pluralities of nanosheets NW1 and NW3 in the second horizontal direction DR2. Although not shown, the field insulating layer 105 may contact the sidewalls (e.g., the lower portions of the sidewalls) of the lowermost nanosheet of each of the second and fourth pluralities of nanosheets NW2 and NW4 in the second horizontal direction DR2.

[0032] For example, the upper surface of the field insulating layer 105 may be formed to be higher than each of the upper surfaces of the insulating pattern 101 and the upper surface of the second dummy active pattern DF2 (e.g., when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). For example, the upper surface of the field insulating layer 105 may be formed to be higher than each of the lower surface of the lowermost nanosheet in the first plurality of nanosheets NW1 and the lower surface of the lowermost nanosheet in the third plurality of nanosheets NW3 (e.g., when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). In addition, the upper surface of the field insulating layer 105 may be formed to be lower than each of the upper surface of the lowermost nanosheet in the first plurality of nanosheets NW1 and the upper surface of the lowermost nanosheet in the third plurality of nanosheets NW3 (e.g., when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). Although not shown, the upper surface of the field insulating layer 105 may be formed to be higher than each of the lower surface of the lowermost nanosheet in the second plurality of nanosheets NW2 and the lower surface of the lowermost nanosheet in the fourth plurality of nanosheets NW4 (for example, when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). Furthermore, the upper surface of the field insulating layer 105 may be formed to be lower than each of the upper surface of the lowermost nanosheet in the second plurality of nanosheets NW2 and the upper surface of the lowermost nanosheet in the fourth plurality of nanosheets NW4 (for example, when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). The field insulating layer 105 may include, for example, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof.

[0033] The first gate electrode G1 may extend along the second horizontal direction DR2 over the insulating pattern 101, the second dummy active pattern DF2, and the field insulating layer 105. The first gate electrode G1 may surround each of the first and third pluralities of nanosheets NW1 and NW3. It will be understood that, as used herein, "element A surrounds element B" (or similar language) means that element A at least partially surrounds element B, but does not necessarily mean that element A completely surrounds element B. The second gate electrode G2 may extend along the second horizontal direction DR2 over the insulating pattern 101, the second dummy active pattern DF2, and the field insulating layer 105. The second gate electrode G2 may surround each of the second and fourth pluralities of nanosheets NW2 and NW4. The second gate electrode G2 may be spaced apart from the first gate electrode G1 in the first horizontal direction DR1.

[0034] Each of the first gate electrode G1 and the second gate electrode G2 may include, for example, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), carbonitride (WN), or the like. Tantalum (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof. Each of the first gate electrode G1 and the second gate electrode G2 may include a conductive metal oxide, a conductive metal oxynitride, or the like, and may further include oxidized forms of the above materials.

[0035] The first gate spacer 111 may extend along two (i.e., opposing) sidewalls of the first gate electrode G1 in a second horizontal direction DR2 on the upper surface of the uppermost nanosheet in the first plurality of nanosheets NW1 and the upper surface of the uppermost nanosheet in the third plurality of nanosheets NW3. The second gate spacer 112 may extend along two (i.e., opposing) sidewalls of the second gate electrode G2 in the second horizontal direction DR2 on the upper surface of the uppermost nanosheet in the second plurality of nanosheets NW2 and the upper surface of the uppermost nanosheet in the fourth plurality of nanosheets NW4. Each of the first and second gate spacers 111 and 112 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. However, the present disclosure is not limited thereto.

[0036] The first source / drain regions SD1 may be provided on both sides (i.e., opposite sides) of each of the first gate electrode G1 and the second gate electrode G2 on the insulating pattern 101. For example, the first source / drain regions SD1 may include a plurality of first source / drain regions SD1 spaced apart from each other in the first horizontal direction DR1, with the first gate electrode G1 and the second gate electrode G2 respectively located between adjacent first source / drain regions SD1 among the plurality of first source / drain regions SD1 (e.g., see FIG. 1 ). Figure 2). For example, the first source / drain region SD1 may be disposed between the first gate electrode G1 and the second gate electrode G2 on the insulating pattern 101. For example, a lower surface of the first source / drain region SD1 may be in contact with the insulating pattern 101. For example, the lower surface of the first source / drain region SD1 may be formed to be lower than each of the lower surface of the lowermost nanosheet in the first plurality of nanosheets NW1 and the lower surface of the lowermost nanosheet in the second plurality of nanosheets NW2 (for example, when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). For example, the lower surface of the first source / drain region SD1 may be formed to be lower than the upper surface of the field insulating layer 105 (for example, when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). For example, at least a portion of a sidewall of the first source / drain region SD1 in the second horizontal direction DR2 may be in contact with the field insulating layer 105.

[0037] The second source / drain regions SD2 may be provided on both sides (i.e., opposite sides) of each of the first gate electrode G1 and the second gate electrode G2 on the second dummy active pattern DF2. For example, the second source / drain regions SD2 may include a plurality of second source / drain regions SD2 spaced apart from each other in the first horizontal direction DR1, with the first gate electrode G1 and the second gate electrode G2 respectively located between adjacent second source / drain regions SD2 among the plurality of second source / drain regions SD2 (e.g., see FIG. 2 ). Figure 3 ). For example, the second source / drain region SD2 may be disposed between the first gate electrode G1 and the second gate electrode G2 on the second dummy active pattern DF2. For example, a lower surface of the second source / drain region SD2 may be in contact with the second dummy active pattern DF2. For example, the lower surface of the second source / drain region SD2 may be formed to be lower than each of the lower surface of the lowermost nanosheet in the third plurality of nanosheets NW3 and the lower surface of the lowermost nanosheet in the fourth plurality of nanosheets NW4 (e.g., when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). For example, the lower surface of the second source / drain region SD2 may be formed to be higher than the lower surface of the second dummy active pattern DF2 (e.g., when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). For example, the lower surface of the second source / drain region SD2 may be formed to be lower than the upper surface of the field insulating layer 105 (e.g., when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). For example, at least a portion of a sidewall of the second source / drain region SD2 in the second horizontal direction DR2 may be in contact with the field insulating layer 105 .

[0038] The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the field insulating layer 105. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the first gate spacer 111. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the first plurality of nanosheets NW1. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the third plurality of nanosheets NW3. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the first source / drain region SD1. The first gate insulating layer 121 may be disposed between the first gate electrode G1 and the second source / drain region SD2.

[0039] Although not specifically shown, the second gate insulating layer 122 may be disposed between the second gate electrode G2 and the field insulating layer 105. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the second gate spacer 112. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the second plurality of nanosheets NW2. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the fourth plurality of nanosheets NW4. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the first source / drain region SD1. The second gate insulating layer 122 may be disposed between the second gate electrode G2 and the second source / drain region SD2.

[0040] For example, each of the first gate insulating layer 121 and the second gate insulating layer 122 may not contact the insulating pattern 101 and the second dummy active pattern DF2, respectively. For example, each of the first gate insulating layer 121 and the second gate insulating layer 122 may contact the first source / drain region SD1 and the second source / drain region SD2, respectively. However, the present disclosure is not limited thereto. In some other embodiments, an internal spacer may be disposed between each of the first gate insulating layer 121 and the second gate insulating layer 122 and the first source / drain region SD1. Furthermore, an internal spacer may be disposed between each of the first gate insulating layer 121 and the second gate insulating layer 122 and the second source / drain region SD2. The internal spacer may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0041] Each of the first gate insulating layer 121 and the second gate insulating layer 122 may include at least one of a high-k material having a higher dielectric constant than silicon oxide, silicon oxynitride, or silicon nitride. The high-k material may include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0042] According to some other embodiments, the semiconductor device may include a negative capacitor (NC) field effect transistor (FET). For example, each of the first gate insulating layer 121 and the second gate insulating layer 122 may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0043] A ferroelectric material layer may have a negative capacitance, while a paraelectric material layer may have a positive capacitance. For example, if two or more capacitors are connected in series and each capacitor has a positive capacitance, the total capacitance will be reduced compared to the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of the two or more capacitors connected in series has a negative value, the total capacitance may have a positive value and may be greater than the absolute value of each individual capacitor.

[0044] When a ferroelectric material layer having a negative capacitance and a paraelectric material layer having a positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric material layers can be increased. By utilizing the increased total capacitance, a transistor including the ferroelectric material layer can have a subthreshold swing (SS) of less than 60 mV / decade at room temperature.

[0045] The ferroelectric material layer may have ferroelectric properties. For example, the ferroelectric material layer may include at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. For example, hafnium zirconium oxide may be a material in which zirconium (Zr) is doped into hafnium oxide. In another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0046] The ferroelectric material layer may further include a dopant. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant included in the ferroelectric material layer may vary depending on which ferroelectric material the ferroelectric material layer includes.

[0047] If the ferroelectric material layer includes hafnium oxide, the dopant included in the ferroelectric material layer may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0048] If the dopant is aluminum (Al), the ferroelectric material layer may contain 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0049] If the dopant is silicon (Si), the ferroelectric material layer may contain 2 at% to 10 at% of silicon. If the dopant is yttrium (Y), the ferroelectric material layer may contain 2 at% to 10 at% of yttrium. If the dopant is gadolinium (Gd), the ferroelectric material layer may contain 1 at% to 7 at% of Gd. If the dopant is zirconium (Zr), the ferroelectric material layer may contain 50 at% to 80 at% of Zr.

[0050] The paraelectric material layer may have paraelectric properties. The paraelectric material layer may include, for example, at least one of silicon oxide and a metal oxide having a high dielectric constant. The metal oxide included in the paraelectric material layer may include, for example, at least one of hafnium oxide, zirconium oxide, and aluminum oxide, but is not limited thereto.

[0051] The ferroelectric material layer and the paraelectric material layer may include the same material. The ferroelectric material layer may have ferroelectric properties, while the paraelectric material layer may not have ferroelectric properties. For example, if the ferroelectric material layer and the paraelectric material layer include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material layer is different from the crystal structure of the hafnium oxide included in the paraelectric material layer.

[0052] The ferroelectric material layer may have a thickness with ferroelectric properties. The thickness of the ferroelectric material layer may be, for example, 0.5 nm to 10 nm, but is not limited thereto. Since each ferroelectric material may have a different critical thickness at which it exhibits ferroelectric properties, the thickness of the ferroelectric material layer may vary depending on the ferroelectric material.

[0053] As an example, each of the first gate insulating layer 121 and the second gate insulating layer 122 may include a single ferroelectric material layer. In another example, each of the first gate insulating layer 121 and the second gate insulating layer 122 may include a plurality of ferroelectric material layers spaced apart from each other. Each of the first gate insulating layer 121 and the second gate insulating layer 122 may have a laminated structure in which a plurality of ferroelectric material layers and a plurality of paraelectric material layers are alternately stacked.

[0054] The first etch stop layer 140 may be disposed on the sidewalls of each of the first gate spacer 111 and the second gate spacer 112 in the first horizontal direction DR1. The first etch stop layer 140 may be disposed on the upper surface of the field insulation layer 105. The first etch stop layer 140 may be disposed on the upper surface of each of the first source / drain region SD1 and the second source / drain region SD2. The first etch stop layer 140 may be disposed on the sidewalls of each of the first source / drain region SD1 and the second source / drain region SD2 in the second horizontal direction DR2. For example, the first etch stop layer 140 may be formed conformally. The first etch stop layer 140 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0055] The first capping pattern 131 may extend along the second horizontal direction DR2 over each of the first gate spacer 111, the first gate insulating layer 121, and the first gate electrode G1. The second capping pattern 132 may extend along the second horizontal direction DR2 over each of the second gate spacer 112, the second gate insulating layer 122, and the second gate electrode G2. For example, the lower surface of each of the first capping pattern 131 and the second capping pattern 132 may contact the first etch stop layer 140. However, the present disclosure is not limited to this. In some other embodiments, the sidewalls of each of the first capping pattern 131 and the second capping pattern 132 may also contact the first etch stop layer 140. Each of the first capping pattern 131 and the second capping pattern 132 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. However, the present disclosure is not limited to this.

[0056] The first upper interlayer insulating layer 150 may be disposed on the first etch stop layer 140. The first upper interlayer insulating layer 150 may be disposed on the sidewalls of each of the first capping pattern 131 and the second capping pattern 132. The first upper interlayer insulating layer 150 may be on each of the first source / drain region SD1 and the second source / drain region SD2 on the field insulating layer 105 (e.g., may cover each of the first source / drain region SD1 and the second source / drain region SD2 on the field insulating layer 105). For example, the upper surface of the first upper interlayer insulating layer 150 may be formed on the same plane as the upper surface of each of the first capping pattern 131 and the second capping pattern 132. The first upper interlayer insulating layer 150 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0057] The upper source / drain contact UCA may be disposed between the first gate electrode G1 and the second gate electrode G2. The upper source / drain contact UCA may be disposed on an upper surface of the second source / drain region SD2. The upper source / drain contact UCA may extend into the interior of the second source / drain region SD2 by penetrating the first upper interlayer insulating layer 150 and the first etch stop layer 140 in the vertical direction DR3 (i.e., extending in the first upper interlayer insulating layer 150 and the first etch stop layer 140 along the vertical direction DR3). The upper source / drain contact UCA may be electrically connected to the second source / drain region SD2. Figure 3 and Figure 5 , the upper source / drain contact UCA is shown as being formed as a single layer, but the present disclosure is not limited thereto. In some other embodiments, the upper source / drain contact UCA may be formed of multiple layers. For example, the upper surface of the upper source / drain contact UCA may be formed on the same plane as the upper surface of the first upper interlayer insulating layer 150. However, the present disclosure is not limited thereto. In some other embodiments, the upper surface of the upper source / drain contact UCA may be formed to be higher than the upper surface of the first upper interlayer insulating layer 150 (for example, when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). The upper source / drain contact UCA may include a conductive material.

[0058] The upper silicide layer USL may be disposed between the upper source / drain contact UCA and the second source / drain region SD2. The upper silicide layer USL may be disposed along an interface between the upper source / drain contact UCA and the second source / drain region SD2. The upper silicide layer USL may include, for example, a metal silicide material.

[0059] The gate contact CB may be disposed on top of the first gate electrode G1. The gate contact CB may be connected to the first gate electrode G1 by penetrating the first capping pattern 131 in the vertical direction DR3. As used herein, "element A connected to element B" (or similar language) means that element A is physically and / or electrically connected to element B. Figure 4 , the gate contact CB is shown as being formed as a single layer, but the present disclosure is not limited thereto. In some other embodiments, the gate contact CB may be formed from multiple layers. For example, the upper surface of the gate contact CB may be formed on the same plane as the upper surface of the upper source / drain contact UCA and the upper surface of the first upper interlayer insulating layer 150, but the present disclosure is not limited thereto. The gate contact CB may include a conductive material.

[0060] A bottom source / drain contact BCA may be disposed between the first gate electrode G1 and the second gate electrode G2 (e.g., when viewed in plan view). The bottom source / drain contact BCA may be disposed at the bottom of the first source / drain region SD1. The bottom source / drain contact BCA may be electrically connected to the first source / drain region SD1 by penetrating the lower interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3. For example, the sidewalls of the bottom source / drain contact BCA may be surrounded by the lower interlayer insulating layer 100 and the insulating pattern 101. For example, the sidewalls of the bottom source / drain contact BCA may be in contact with each of the lower interlayer insulating layer 100 and the insulating pattern 101.

[0061] For example, the width of the bottom source / drain contact BCA in the second horizontal direction DR2 can be smaller than the width of the insulating pattern 101 in the second horizontal direction DR2. For example, the upper surface of the bottom source / drain contact BCA can be formed on the same plane as the lower surface of the first source / drain region SD1, but the present disclosure is not limited to this. For example, the bottom source / drain contact BCA can be formed as a single layer. However, the present disclosure is not limited to this. In some other embodiments, the bottom source / drain contact BCA can be formed from multiple layers.

[0062] The bottom silicide layer BSL may be disposed between the bottom source / drain contact BCA and the first source / drain region SD1. The bottom silicide layer BSL may be disposed along an interface between the bottom source / drain contact BCA and the first source / drain region SD1. The bottom silicide layer BSL may include, for example, a metal silicide material.

[0063] The second etch stop layer 160 may be disposed on an upper surface of each of the upper source / drain contact UCA, the first and second capping patterns 131 and 132, and the first upper interlayer insulating layer 150. Figures 2 to 5 , the second etch stop layer 160 is shown as being formed as a single layer, but the present disclosure is not limited thereto. In some other embodiments, the second etch stop layer 160 may be formed of multiple layers. The second etch stop layer 160 may include, for example, at least one of aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, silicon oxide, silicon nitride, silicon oxynitride, and a low-k material. A second upper interlayer insulating layer 170 may be disposed on the second etch stop layer 160. The second upper interlayer insulating layer 170 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low-k material.

[0064] The first via hole V1 may be connected to the upper source / drain contact UCA by penetrating the second upper interlayer insulating layer 170 and the second etch stop layer 160 in the vertical direction DR3. The second via hole V2 may be connected to the gate contact CB by penetrating the second upper interlayer insulating layer 170 and the second etch stop layer 160 in the vertical direction DR3. Figures 3 to 5 In the embodiment, each of the first via V1 and the second via V2 is shown as being formed as a single layer, but the present disclosure is not limited thereto. In some other embodiments, each of the first via V1 and the second via V2 may be formed of multiple layers. Each of the first via V1 and the second via V2 may include a conductive material.

[0065] In the following, reference is made to Figures 6 to 41 , a method of manufacturing a semiconductor device according to some embodiments of the present disclosure will be described.

[0066] Figures 6 to 41 is a diagram of an intermediate stage for explaining a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0067] Reference Figure 6 and Figure 7 A substrate 10 may be provided. The substrate 10 may be a silicon substrate or an SOI (silicon on insulator) substrate. In some other embodiments, the substrate 10 may include silicon germanium, SGOI (silicon germanium on insulator), indium antimonide, lead telluride compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the present disclosure is not limited thereto.

[0068] Subsequently, a laminate structure 20 may be formed on the upper surface of the substrate 10. For example, the laminate structure 20 may include a first semiconductor layer 21, a second semiconductor layer 22, and a third semiconductor layer 23. The first semiconductor layer 21 may be formed on the upper surface of the substrate 10. The first semiconductor layer 21 may be in contact with the upper surface of the substrate 10. For example, the first semiconductor layer 21 may include silicon germanium (SiGe). Subsequently, the second semiconductor layers 22 and the third semiconductor layers 23 may be alternately stacked on the upper surface of the first semiconductor layer 21. For example, a plurality of second semiconductor layers 22 and a plurality of third semiconductor layers 23 may be alternately stacked on the upper surface of the first semiconductor layer 21. The lowermost second semiconductor layer 22 may be in contact with the upper surface of the first semiconductor layer 21. For example, the second semiconductor layer 22 may be formed on top of the laminate structure 20. In other words, the uppermost second semiconductor layer 22 may be formed at the top of the laminate structure 20. For example, the second semiconductor layer 22 may include silicon (Si). For example, the third semiconductor layer 23 may include silicon germanium (SiGe). For example, the concentration of germanium (Ge) in the first semiconductor layer 21 may be higher than that in the third semiconductor layer 23. Here, the concentration of germanium (Ge) indicates an atomic ratio of germanium (Ge) contained in silicon germanium (SiGe).

[0069] Subsequently, a portion of the laminate structure 20 may be etched. While etching the laminate structure 20, a portion of the substrate 10 may also be etched. In other words, a portion of the substrate 10 and portions of the first to third semiconductor layers 21, 22, and 23 may be etched. Through such an etching process, a first active pattern F1 and a second active pattern F2 may each be defined on the bottom of the laminate structure 20 on the upper surface of the substrate 10. Each of the first active pattern F1 and the second active pattern F2 may protrude from the upper surface of the substrate 10 in the vertical direction DR3. Each of the first active pattern F1 and the second active pattern F2 may extend in the first horizontal direction DR1. For example, each of the first active pattern F1 and the second active pattern F2 may extend along the first horizontal direction DR1 on the lower surface of the first semiconductor layer 21. The second active pattern F2 may be spaced apart from the first active pattern F1 in the second horizontal direction DR2. For example, a profile of a sidewall of each of the first and second active patterns F1 and F2 in the second horizontal direction DR2 may be formed continuously with a profile of a sidewall of the remaining laminate structure 20 in the second horizontal direction DR2 (eg, continuously in the vertical direction D3 ).

[0070] Thereafter, a field insulation layer 105 may be formed on the upper surface of the substrate 10. The field insulation layer 105 may surround the sidewalls of the first active pattern F1, the sidewalls of the second active pattern F2, and the sidewalls of the first semiconductor layer 21, respectively. The field insulation layer 105 may contact each of the sidewalls of the first active pattern F1, the sidewalls of the second active pattern F2, and the sidewalls of the first semiconductor layer 21. For example, the field insulation layer 105 may surround a portion of the sidewalls of the lowermost second semiconductor layer 22. The field insulation layer 105 may contact a portion of the sidewalls of the bottom (i.e., lowermost) second semiconductor layer 22. For example, the upper surface of the field insulation layer 105 may be formed to be higher than the upper surface of the first semiconductor layer 21 (e.g., when measured in the vertical direction DR3 relative to the upper surface of the substrate 10). For example, the upper surface of the field insulation layer 105 may be formed to be higher than the bottom surface of the lowermost second semiconductor layer 22 (e.g., when measured in the vertical direction DR3 relative to the upper surface of the substrate 10). For example, an upper surface of the field insulation layer 105 may be formed to be lower than an upper surface of the lowermost second semiconductor layer 22 (eg, when measured in the vertical direction DR3 with respect to the upper surface of the substrate 10 ).

[0071] Subsequently, a pad oxide layer 30 may be formed on the upper surface of the field insulating layer 105, on the exposed sidewalls and upper surface of the second semiconductor layer 22, and on the exposed sidewalls of the third semiconductor layer 23 (e.g., the pad oxide layer 30 may be formed to cover the upper surface of the field insulating layer 105, the exposed sidewalls and upper surface of the second semiconductor layer 22, and the exposed sidewalls of the third semiconductor layer 23). For example, the pad oxide layer 30 may not contact each of the first active pattern F1, the second active pattern F2, and the first semiconductor layer 21. For example, the pad oxide layer 30 may be formed conformally. The pad oxide layer 30 may include, for example, silicon oxide (SiO2). Reference Figure 8 and Figure 9 First and second dummy gates DG1 and DG2, as well as first and second dummy capping patterns DC1 and DC2, may be formed on the pad oxide layer 30 on the laminate structure 20 and the field insulation layer 105, extending along the second horizontal direction DR2. For example, the first and second dummy gates DG1 and DG2 may be formed on the upper surface of the field insulation layer 105 and the upper surface of the uppermost second semiconductor layer 22. For example, the second dummy gate DG2 may be spaced apart from the first dummy gate DG1 in the first horizontal direction DR1. The first dummy capping pattern DC1 may be disposed on the first dummy gate DG1. The second dummy capping pattern DC2 may be disposed on the second dummy gate DG2. Simultaneously with the formation of the first and second dummy gates DG1 and DG2 and the first and second dummy capping patterns DC1 and DC2, the remaining pad oxide layer 30 on the substrate 10, except for the portion overlapping the first and second dummy gates DG1 and DG2 in the vertical direction DR3, may be removed.

[0072] Subsequently, a spacer material layer SM may be formed on the sidewalls of each of the first and second dummy gates DG1 and DG2, on the sidewalls and upper surface of each of the first and second dummy capping patterns DC1 and DC2, on the sidewalls and upper surface of the exposed laminate structure 20, and on the upper surface of the field insulating layer 105 (e.g., the spacer material layer SM may be formed to cover the sidewalls of each of the first and second dummy gates DG1 and DG2, on the sidewalls and upper surface of each of the first and second dummy capping patterns DC1 and DC2, on the sidewalls and upper surface of the exposed laminate structure 20, and on the upper surface of the field insulating layer 105). For example, the spacer material layer SM may be conformally formed. The spacer material layer SM may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0073] Reference Figures 10 to 13 The laminate structure 20 may be etched using the first and second dummy gates DG1 and DG2 and the first and second dummy capping patterns DC1 and DC2 as masks (see FIG. Figure 8 and Figure 9 ) to form a first source / drain trench ST1 and a second source / drain trench ST2. The first source / drain trench ST1 may be formed between the first dummy gate DG1 and the second dummy gate DG2 on the first active pattern F1. The second source / drain trench ST2 may be formed between the first dummy gate DG1 and the second dummy gate DG2 on the second active pattern F2.

[0074] For example, each of the first source / drain trench ST1 and the second source / drain trench ST2 may extend to the first semiconductor layer 21 (see Figure 8 and Figure 9 ). In other words, the bottom surface of each of the first source / drain trench ST1 and the second source / drain trench ST2 may be formed by the first semiconductor layer 21 (see Figure 8 and Figure 9 After forming the first source / drain trench ST1, the first semiconductor layer 21 (see FIG. 2 ) remaining on the upper surface of the first active pattern F1 Figure 8 and Figure 9 ) may be defined as a first dummy active pattern DF1. In other words, after forming the first source / drain trench ST1, the first semiconductor layer 21 (see Figure 8 and Figure 9 ) remaining on the upper surface of the first active pattern F1 may be defined as a first dummy active pattern DF1. In addition, after forming the second source / drain trench ST2, the first semiconductor layer 21 (see FIG. 2 ) remaining on the upper surface of the second active pattern F2 may be defined as a first dummy active pattern DF1. Figure 8 and Figure 9 ) may be defined as the second dummy active pattern DF2. In other words, after forming the second source / drain trench ST2, the first semiconductor layer 21 (see Figure 8 and Figure 9 ) remaining on the upper surface of the second active pattern F2 can be defined as a second dummy active pattern DF2. That is, after the first and second source / drain trenches ST1 and ST2 are respectively formed, each of the first and second dummy active patterns DF1 and DF2 can be exposed. For example, the bottom surface of each of the first and second source / drain trenches ST1 and ST2 can be formed to be lower than the upper surface of the field insulation layer 105 (for example, when measured in the vertical direction DR3 relative to the upper surface of the substrate 10).

[0075] For example, while forming the first source / drain trench ST1 and the second source / drain trench ST2, a spacer material layer SM (see FIG. 2 ) is formed on the upper surface of each of the first dummy capping pattern DC1 and the second dummy capping pattern DC2. Figure 8 and Figure 9 ) and a portion of each of the first and second dummy cap patterns DC1 and DC2 may be etched away. The spacer material layer SM (see FIG. 5 ) remaining on the sidewalls of each of the first and second dummy cap patterns DC1 and DC2 and the first and second dummy gates DG1 and DG2 may be etched away. Figure 8 and Figure 9 ) may be defined as a first gate spacer 111 and a second gate spacer 112 .

[0076] For example, after forming the first source / drain trench ST1, the second semiconductor layer 22 (see FIG. 2 ) remains at the bottom of the first dummy gate DG1 on the first dummy active pattern DF1. Figure 8 and Figure 9 ) may be defined as a first plurality of nanosheets NW1. After forming the first source / drain trench ST1, the second semiconductor layer 22 (see FIG. 2 ) remains at the bottom of the second dummy gate DG2 on the first dummy active pattern DF1. Figure 8 and Figure 9 ) may be defined as a second plurality of nanosheets NW2. After forming the second source / drain trench ST2, the second semiconductor layer 22 (see FIG. 2 ) remaining at the bottom of the first dummy gate DG1 on the second dummy active pattern DF2 is Figure 8 and Figure 9 ) may be defined as a third plurality of nanosheets NW3. After forming the second source / drain trench ST2, the second semiconductor layer 22 (see FIG. 2 ) remains at the bottom of the second dummy gate DG2 on the second dummy active pattern DF2. Figure 8 and Figure 9 ) can be defined as the fourth plurality of nanosheets NW4.

[0077] Reference Figures 14 to 16 , can be in the first source / drain trench ST1 (see Figure 10 ) forms a first source / drain region SD1 inside the second source / drain trench ST2 (see Figure 11 ) is formed inside the second source / drain region SD2. For example, the lower surface of the first source / drain region SD1 may be in contact with the first dummy active pattern DF1. In addition, the lower surface of the second source / drain region SD2 may be in contact with the second dummy active pattern DF2.

[0078] Subsequently, a first dummy capping pattern DC1 and a second dummy capping pattern DC2 (see FIG. 1 ) may be formed on the upper surface of the exposed field insulating layer 105, on the sidewall of each of the exposed first and second gate spacers 111 and 112, and on the exposed first and second dummy capping patterns DC1 and DC2. Figure 10 and Figure 11 ) and on the surface of each of the exposed first source / drain regions SD1 and the second source / drain regions SD2. Subsequently, a first upper interlayer insulating layer 150 may be formed on the first etch stop layer 140. Thereafter, a planarization process may be performed to expose the upper surface of each of the first and second dummy gates DG1 and DG2.

[0079] Reference Figures 17 to 19 , the first dummy gate DG1 and the second dummy gate DG2 can be etched separately (see Figure 14 and Figure 15 ), pad oxide layer 30 (see Figure 14 and Figure 15 ) and the third semiconductor layer 23 (see Figure 14 and Figure 15 The first dummy gate DG1 (see Figure 14 and Figure 15 ), pad oxide layer 30 (see Figure 14 and Figure 15 ) and the third semiconductor layer 23 (see Figure 14 and Figure 15 ) The etched portion can be defined as the first gate trench GT1. In addition, the second dummy gate DG2 (see Figure 14 and Figure 15 ), pad oxide layer 30 (see Figure 14 and Figure 15 ) and the third semiconductor layer 23 (see Figure 14 and Figure 15 ) The etched portion can be defined as a second gate trench GT2.

[0080] Reference Figures 20 to 22 , can be in the first gate trench GT1 (see Figure 17 and Figure 18 ) are sequentially formed inside the first gate insulating layer 121, the first gate electrode G1 and the first capping pattern 131. In addition, the second gate trench GT2 (see Figure 17 and Figure 18 ) are sequentially formed inside each of the plurality of nanosheets NW1 and the third plurality of nanosheets NW3. The second gate electrode G2 may surround each of the second plurality of nanosheets NW2 and the fourth plurality of nanosheets NW4.

[0081] Reference Figures 23 to 26 , an upper source / drain contact UCA may be formed on the second source / drain region SD2. The upper source / drain contact UCA may extend into the interior of the second source / drain region SD2 by penetrating the first upper interlayer insulating layer 150 and the first etch stop layer 140 in the vertical direction DR3. Furthermore, an upper silicide layer USL may be formed between the second source / drain region SD2 and the upper source / drain contact UCA. Furthermore, a gate contact CB connected to the first gate electrode G1 may be formed by penetrating the first cap pattern 131 in the vertical direction DR3.

[0082] Subsequently, a second etch stop layer 160 and a second upper interlayer insulating layer 170 may be sequentially formed on the upper surface of each of the first upper interlayer insulating layer 150, the first and second capping patterns 131 and 132, and the upper source / drain contact UCA. A first via hole V1 connected to the upper source / drain contact UCA may be formed by penetrating the second etch stop layer 160 and the second upper interlayer insulating layer 170 in the vertical direction DR3. In addition, a second via hole V2 connected to the gate contact CB may be formed by penetrating the second etch stop layer 160 and the second upper interlayer insulating layer 170 in the vertical direction DR3.

[0083] Reference Figures 27 to 30 , the substrate 10 can be etched (see Figures 23 to 26 As a result, the lower surface of the field insulating layer 105, the lower surface of the first active pattern F1, and the lower surface of the second active pattern F2 may be exposed. For example, the substrate 10 may be etched by a planarization process (see FIG. Figures 23 to 26 ).

[0084] Reference Figures 31 to 34 , a protective layer 40 may be formed on the lower surface of the second active pattern F2. For example, the protective layer 40 may be formed on the lower surface of the field insulating layer 105 adjacent to the second active pattern F2. For example, the protective layer 40 is not formed on the first active pattern F1 (see FIG. Figures 27 to 30 ) and the lower surface of the field insulating layer 105 and the first active pattern F1 (see Figures 27 to 30 ) on the lower surface adjacent to the first active pattern F1 (see FIG. 1 ). For example, the protective layer 40 may include a material different from that of the field insulating layer 105. For example, the protective layer 40 may include a material different from that of the first active pattern F1 (see FIG. 1 ). Figures 27 to 30 ) and the first dummy active pattern DF1 each have an etching selectivity. For example, the protective layer 40 may include any one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxynitride (SiON), and silicon oxycarbon nitride (SiOCN), but the present disclosure is not limited thereto. Subsequently, the first active pattern F1 (see Figures 27 to 30). As a result, the first dummy active pattern DF1 may be exposed.

[0085] Reference Figures 35 to 37 , the first dummy active pattern DF1 may be etched (see Figures 31 to 34 As a result, a lower surface of a lowermost nanosheet among the first plurality of nanosheets NW1 , a lower surface of a lowermost nanosheet among the second plurality of nanosheets NW2 , and a lower surface of the first source / drain region SD1 may be exposed, respectively.

[0086] Reference Figures 38 to 41 , the protective layer 40 can be removed (see Figure 36 and Figure 37 ). Subsequently, the first active pattern F1 (see Figures 27 to 30 ) and the first dummy active pattern DF1 (see Figures 31 to 34 ). ) An insulating pattern 101 is formed on each etched portion of the second dummy active pattern DF2. For example, the insulating pattern 101 may be formed on the lower surface of the first source / drain region SD1. The insulating pattern 101 may extend in the first horizontal direction DR1. For example, the insulating pattern 101 may be in contact with the lower surface of the lowest nanosheet in the first plurality of nanosheets NW1, the lower surface of the lowest nanosheet in the second plurality of nanosheets NW2, and the lower surface of the first source / drain region SD1, respectively. In addition, the sidewalls of the insulating pattern 101 may be in contact with the field insulating layer 105. For example, the uppermost surface of the insulating pattern 101 may be formed on the same plane as the uppermost surface of the second dummy active pattern DF2. For example, the lower surface of the insulating pattern 101 may be formed on the same plane as the lower surface of the second active pattern F2 and the lower surface of the field insulating layer 105.

[0087] In addition, a lower interlayer insulating layer 100 may be formed on the lower surface of the insulating pattern 101, the lower surface of the second active pattern F2, and the lower surface of the field insulating layer 105, respectively. The lower interlayer insulating layer 100 may be in contact with the lower surface of the insulating pattern 101, the lower surface of the second active pattern F2, and the lower surface of the field insulating layer 105, respectively. For example, the lower interlayer insulating layer 100 may include the same material as the insulating pattern 101. For example, the insulating pattern 101 and the lower interlayer insulating layer 100 may be formed by the same manufacturing process.

[0088] Reference Figures 2 to 5, a bottom source / drain contact BCA may be formed by penetrating the lower interlayer insulating layer 100 and the insulating pattern 101 in the vertical direction DR3 to be electrically connected to the first source / drain region SD1. For example, the sidewalls of the bottom source / drain contact BCA may be surrounded by the lower interlayer insulating layer 100 and the insulating pattern 101. For example, the upper surface of the bottom source / drain contact BCA may be formed on the same plane as the upper surface of the insulating pattern 101. However, the present disclosure is not limited thereto. In some other embodiments, at least a portion of the bottom source / drain contact BCA may extend into the interior of the first source / drain region SD1. In addition, a bottom silicide layer BSL may be formed between the bottom source / drain contact BCA and the first source / drain region SD1. Through this manufacturing process, a Figures 2 to 5 The semiconductor device shown in .

[0089] Methods for manufacturing semiconductor devices according to some embodiments of the present disclosure may include forming first and second dummy active patterns DF1 and DF2 on first and second active patterns F1 and F2. During a process in which the first active pattern F1, comprised of silicon (Si), is etched in a region where a bottom source / drain contact BCA is formed, the first dummy active pattern DF1, comprised of silicon germanium (SiGe), can prevent the first source / drain region SD1 from being etched. Consequently, the methods for manufacturing semiconductor devices according to some embodiments of the present disclosure can ensure the structural stability of the first source / drain region SD1 to which the bottom source / drain contact BCA is connected.

[0090] In the semiconductor devices according to some embodiments of the present disclosure manufactured using the above-described method, an insulating pattern 101 comprising an insulating material is disposed at the bottom of the first source / drain region SD1 to which the bottom source / drain contact BCA is connected. A second active pattern F2 comprising silicon (Si) and a second dummy active pattern DF2 comprising silicon germanium (SiGe) may be disposed at the bottom of the second source / drain region SD2 to which the upper source / drain contact UCA is connected. Furthermore, the upper surface of the insulating pattern 101 and the upper surface of the second dummy active pattern DF2 may each be in contact with the lowermost nanosheet. Furthermore, the upper surface of the field insulating layer 105 may be formed to be higher than each of the upper surfaces of the insulating pattern 101 and the second dummy active pattern DF2.

[0091] In the following, reference will be made to Figures 42 to 44 The semiconductor devices according to some other embodiments of the present disclosure are described. The description will focus on Figures 1 to 5 The differences in the semiconductor devices are shown in FIG.

[0092] Figures 42 to 44 are cross-sectional views for explaining semiconductor devices according to some other embodiments of the present disclosure.

[0093] Reference Figures 42 to 44 In the semiconductor device according to some other embodiments of the present disclosure, the protection layer 40 may be disposed on the lower surface of the second active pattern F2 .

[0094] For example, the protective layer 40 may be disposed on the lower surface of the second active pattern F2 and the lower surface of the field insulation layer 105 adjacent to the second active pattern F2. The lower interlayer insulation layer 100 may be on the protective layer 40 on the lower surface of the second active pattern F2 and the lower surface of the field insulation layer 105 adjacent to the second active pattern F2 (e.g., the lower interlayer insulation layer 100 may cover the protective layer 40). In other words, the protective layer 40 may be disposed between the lower interlayer insulation layer 100 and the lower surface of the second active pattern F2. Alternatively, the protective layer 40 may be disposed between the lower interlayer insulation layer 100 and the lower surface of the field insulation layer 105.

[0095] For example, the protective layer 40 is not provided on the lower surface of the insulating pattern 101. That is, the protective layer 40 may not be in contact with the lower surface of the insulating pattern 101. For example, the protective layer 40 may include a material different from each of the field insulating layer 105 and the lower interlayer insulating layer 100. In addition, the protective layer 40 may include a material different from each of the second active pattern F2 and the second dummy active pattern DF2. For example, the protective layer 40 may include any one of silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxynitride (SiON), and silicon oxycarbon nitride (SiOCN), but the present disclosure is not limited thereto.

[0096] In the following, reference is made to Figures 45 to 47 , a semiconductor device according to some other embodiments of the present disclosure will be described. The description will focus on Figures 1 to 5 The differences in the semiconductor devices are shown in FIG.

[0097] Figures 45 to 47 are cross-sectional views for explaining semiconductor devices according to some other embodiments of the present disclosure.

[0098] Reference Figures 45 to 47 In the semiconductor device according to some other embodiments of the present disclosure, a lower surface of each of the first source / drain region SD31 and the second source / drain region SD32 may be formed on the same plane as a lower surface of the lowermost nanosheet.

[0099] For example, the lower surface of the first source / drain region SD31 may be formed on the same plane as the lower surface of the lowermost nanosheet in the first plurality of nanosheets NW1 and the lower surface of the lowermost nanosheet in the second plurality of nanosheets NW2. In addition, the lower surface of the second source / drain region SD32 may be formed on the same plane as the lower surface of the lowermost nanosheet in the third plurality of nanosheets NW3 and the lower surface of the lowermost nanosheet in the fourth plurality of nanosheets NW4.

[0100] In the following, reference is made to Figure 48 and Figure 49 , a semiconductor device according to some other embodiments of the present disclosure will be described. The description will focus on Figures 1 to 5 The differences in the semiconductor devices are shown in FIG.

[0101] Figure 48 and Figure 49 are cross-sectional views for explaining semiconductor devices according to some other embodiments of the present disclosure.

[0102] Reference Figure 48 and Figure 49 In the semiconductor device according to some other embodiments of the present disclosure, at least a portion of the bottom source / drain contact BCA4 may extend into the interior of the first source / drain region SD1 .

[0103] For example, the upper surface of the bottom source / drain contact BCA4 can be formed to be higher than the lower surface of the first source / drain region SD1 (for example, when measured relative to the upper surface of the lower interlayer insulating layer 100 in the vertical direction DR3). For example, at least a portion of the bottom source / drain contact BCA4 can be surrounded by the first source / drain region SD1. At least a portion of the bottom source / drain contact BCA4 can overlap with the first source / drain region SD1 in each of the first horizontal direction DR1 and the second horizontal direction DR2. For example, a bottom silicide layer BSL4 can be disposed between the bottom source / drain contact BCA4 and the first source / drain region SD1. The bottom silicide layer BSL4 can be disposed along the interface between the bottom source / drain contact BCA4 and the first source / drain region SD1.

[0104] Although the exemplary embodiments of the present disclosure have been described above with reference to the accompanying drawings, it will be understood that the present disclosure is not limited to the above embodiments and can be manufactured in various forms. Moreover, those skilled in the art who have ordinary knowledge in the art will recognize that the present disclosure can be implemented in other specific forms without changing the technical concept or essential features of the present disclosure. Therefore, it should be understood that the above embodiments are illustrative and non-restrictive in all aspects.

[0105] As used herein, the terms "comprise," "include," "have," and any other variations thereof illustrate the presence of narrated features, steps, operations, elements, components, and / or groups, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. Additionally, it will be understood that although the terms "first," "second," "third," and the like may be used herein to describe various elements, these elements should not be limited by these terms. On the contrary, these terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of this disclosure.

Claims

1. A semiconductor device comprising: lower interlayer insulating layer; an insulating pattern extending along a first horizontal direction on an upper surface of the lower interlayer insulating layer; an active pattern extending along a first horizontal direction on an upper surface of the lower interlayer insulating layer, the active pattern being spaced apart from the insulating pattern in a second horizontal direction different from the first horizontal direction, the active pattern comprising a material different from that of the insulating pattern; a dummy active pattern extending along a first horizontal direction on an upper surface of the active pattern and contacting the upper surface of the active pattern; a field insulating layer on an upper surface of the lower interlayer insulating layer and on sidewalls of the insulating pattern, the active pattern, and the dummy active pattern; a first plurality of nanosheets stacked in a vertical direction on an upper surface of the insulating pattern and spaced apart from each other; a second plurality of nanosheets stacked in a vertical direction on the upper surface of the dummy active pattern and spaced apart from each other; a gate electrode extending along a second horizontal direction on the insulating pattern and the dummy active pattern, the gate electrode at least partially surrounding each of the first plurality of nanosheets and the second plurality of nanosheets; a first source / drain region on one side of the gate electrode and on the insulating pattern, the first source / drain region being in contact with the insulating pattern; a second source / drain region on the one side of the gate electrode and on the dummy active pattern, the second source / drain region being in contact with the dummy active pattern; a bottom source / drain contact extending in a vertical direction in the lower interlayer insulating layer and the insulating pattern, the bottom source / drain contact being electrically connected to the first source / drain region; as well as An upper source / drain contact is on the second source / drain region, the upper source / drain contact being electrically connected to the second source / drain region.

2. The semiconductor device according to claim 1, wherein The dummy active pattern includes silicon germanium.

3. The semiconductor device according to claim 1, wherein An uppermost surface of the insulation pattern is coplanar with an uppermost surface of the dummy active pattern.

4. The semiconductor device according to claim 1, wherein With respect to an upper surface of the lower interlayer insulating layer, an upper surface of the field insulating layer is higher than upper surfaces of the insulating patterns and upper surfaces of the dummy active patterns in a vertical direction.

5. The semiconductor device according to claim 1, wherein A lower surface of a lowermost nanosheet among the first plurality of nanosheets is in contact with an upper surface of the insulating pattern, and The lower surface of the lowest nanosheet in the second plurality of nanosheets contacts the upper surface of the dummy active pattern. The semiconductor device according to claim 1 , wherein: The field insulating layer contacts opposite sidewalls of a lowermost nanosheet of the first plurality of nanosheets and opposite sidewalls of a lowermost nanosheet of the second plurality of nanosheets in the second horizontal direction.

7. The semiconductor device according to claim 1, wherein The insulation pattern overlaps the dummy active pattern in the second horizontal direction.

8. The semiconductor device according to claim 1, wherein Lower surfaces of the insulating patterns and lower surfaces of the active patterns contact the lower interlayer insulating layer.

9. The semiconductor device according to claim 1, further comprising: a protective layer between the lower interlayer insulating layer and the lower surface of the active pattern, the protective layer including a material different from that of the lower interlayer insulating layer, The lower surface of the insulating pattern contacts the lower interlayer insulating layer.

10. The semiconductor device according to claim 1, wherein A lower surface of the first source / drain region is coplanar with a lower surface of a lowermost nanosheet of the first plurality of nanosheets, and The lower surface of the second source / drain region is coplanar with the lower surface of the lowermost nanosheet in the second plurality of nanosheets.

11. The semiconductor device according to claim 1, wherein At least a portion of the bottom source / drain contact extends into the first source / drain region.

12. A semiconductor device comprising: lower interlayer insulating layer; an insulating pattern extending along a first horizontal direction on an upper surface of the lower interlayer insulating layer; an active pattern extending along a first horizontal direction on an upper surface of the lower interlayer insulating layer, the active pattern being spaced apart from the insulating pattern in a second horizontal direction different from the first horizontal direction, the active pattern comprising a material different from that of the insulating pattern; a dummy active pattern extending along a first horizontal direction on an upper surface of the active pattern and contacting the upper surface of the active pattern, the dummy active pattern comprising silicon germanium; a field insulating layer on an upper surface of the lower interlayer insulating layer and on sidewalls of the insulating pattern, the active pattern, and the dummy active pattern, wherein the upper surface of the field insulating layer is higher than the upper surfaces of the insulating pattern and the dummy active pattern in a vertical direction relative to the upper surface of the lower interlayer insulating layer; a gate electrode extending along a second horizontal direction on the insulating pattern and the dummy active pattern; a first source / drain region on one side of the gate electrode and on the insulating pattern; a second source / drain region on the one side of the gate electrode and on the dummy active pattern; a bottom source / drain contact extending in a vertical direction in the lower interlayer insulating layer and the insulating pattern, the bottom source / drain contact being electrically connected to the first source / drain region; and An upper source / drain contact is on the second source / drain region, the upper source / drain contact being electrically connected to the second source / drain region.

13. The semiconductor device according to claim 12, further comprising: a first plurality of nanosheets stacked in a vertical direction on an upper surface of the insulating pattern and spaced apart from each other; as well as a second plurality of nanosheets stacked vertically on the upper surface of the dummy active pattern and spaced apart from each other; wherein the gate electrode at least partially surrounds each of the first plurality of nanosheets and the second plurality of nanosheets.

14. The semiconductor device according to claim 12, wherein The lower surface of the first source / drain region is in contact with the insulating pattern, and The lower surface of the second source / drain region contacts the dummy active pattern.

15. The semiconductor device according to claim 12, wherein The insulation pattern overlaps the dummy active pattern in the second horizontal direction.

16. A method of manufacturing a semiconductor device, comprising: forming a first semiconductor layer including silicon germanium on an upper surface of the substrate; alternately stacking a second semiconductor layer including silicon and a third semiconductor layer including silicon germanium on an upper surface of the first semiconductor layer; Etching a portion of the substrate and portions of the first semiconductor layer to the third semiconductor layer to form a first active pattern and a second active pattern extending in a first horizontal direction on a lower surface of the first semiconductor layer, wherein the second active pattern is spaced apart from the first active pattern in a second horizontal direction different from the first horizontal direction; forming a field insulating layer on the substrate and on sidewalls of the first active pattern, the second active pattern, and the first semiconductor layer; forming a dummy gate extending along a second horizontal direction on an upper surface of the field insulating layer and an upper surface of an uppermost second semiconductor layer among the second semiconductor layers; forming a first source / drain region on one side of the dummy gate and on the first active pattern, and forming a second source / drain region on the one side of the dummy gate and on the second active pattern, wherein a first portion of the first semiconductor layer in contact with a lower surface of the first source / drain region is defined as the first dummy active pattern, and wherein a second portion of the first semiconductor layer in contact with a lower surface of the second source / drain region is defined as the second dummy active pattern; etching the dummy gate and the third semiconductor layer to form a gate trench; forming a gate electrode in the gate trench; forming an upper source / drain contact on the second source / drain region, with the upper source / drain contact electrically connected to the second source / drain region; etching the substrate; forming a protective layer on a lower surface of the second active pattern; etching a first active pattern and a first dummy active pattern; forming an insulating pattern on a lower surface of the first source / drain region, the insulating pattern extending in a first horizontal direction; and A bottom source / drain contact is formed, extending in a vertical direction in the insulating pattern and electrically connected to the first source / drain region.

17. The method according to claim 16, wherein A concentration of germanium included in the first semiconductor layer is greater than a concentration of germanium included in each of the third semiconductor layers.

18. The method according to claim 16, wherein The step of forming the field insulating layer includes forming an upper surface of the field insulating layer that is higher than an upper surface of the first semiconductor layer in a vertical direction relative to an upper surface of the substrate.

19. The method according to claim 16, wherein The step of forming the insulating pattern includes forming an uppermost surface of the insulating pattern coplanar with an uppermost surface of the second dummy active pattern.

20. The method of claim 16, further comprising: The protection layer is removed after etching the first active pattern and the first dummy active pattern.

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