Semiconductor device and preparation method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof. The method comprises the following steps: forming a gate layer on a substrate; forming a first mask layer on the gate layer; etching the grid electrode layer by using the first mask layer to form a grid electrode; performing ion doping on the substrate so as to form source / drain regions on two sides of the grid electrode; the first mask layer is removed; and forming a grid side wall covering the side surface of the grid.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, the number of stacked layers of three-dimensional memory continues to increase, and the size of the memory array (Array) on the chip continues to decrease. Therefore, the size of the peripheral circuit (CMOS) that matches the size of the memory array also needs to be reduced accordingly. The size of the page buffer (PB) occupies a large area in the peripheral circuit. Therefore, how to reduce the size of the page buffer is particularly important. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.

[0004] To achieve the above objectives, the technical solution of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a method for preparing a semiconductor device, the method comprising: forming a gate layer on a substrate; forming a first mask layer on the gate layer; etching the gate layer using the first mask layer to form a gate; ion doping the substrate to form source / drain regions on both sides of the gate; removing the first mask layer; and forming gate sidewalls covering the sides of the gate.

[0006] In some embodiments, the method further includes forming a conductive contact layer on the source / drain region and a gate conductive layer on the gate.

[0007] In some embodiments, the method further includes: forming an interlayer dielectric layer covering the semiconductor device; etching the interlayer dielectric layer using a contact hole mask to form a contact hole that penetrates the interlayer dielectric layer and extends to the conductive contact layer; and etching the interlayer dielectric layer using a first wiring layer mask to enlarge the opening at the top of the contact hole to form a wiring opening.

[0008] In some embodiments, the method further includes: filling the contact hole to form a conductive structure in a portion of the contact hole excluding the wiring opening, and forming a first wiring layer in the wiring opening.

[0009] In some embodiments, the substrate includes a first region and a second region; the etching of the gate layer using the first mask layer to form a gate includes: etching the gate layer using the first mask layer to form a first gate in the first region and forming a second gate in the second region; wherein the gate oxide layer thickness of the first region is greater than the gate oxide layer thickness of the second region.

[0010] In some embodiments, after removing the first mask layer, the method further includes: performing ion doping on the substrate located in the second region to form source / drain regions on both sides of the second gate.

[0011] In some embodiments, the method further includes: forming a second wiring layer on the first wiring layer, the second wiring layer being electrically connected to the first wiring layer; and the first wiring layer serving as a jumper between the conductive structure and the second wiring layer.

[0012] In some embodiments, the gate layer has a thickness ranging from 700 angstroms to 1200 angstroms.

[0013] In some embodiments, the height of the conductive structure ranges from 1500 angstroms to 4000 angstroms.

[0014] In some embodiments, a width of the bottom of the conductive structure ranges from 35 nanometers to 45 nanometers.

[0015] In some embodiments, a width of the first wiring layer ranges from 60 nanometers to 180 nanometers.

[0016] In some embodiments, a thickness of the gate spacer along a first direction ranges from 38 nanometers to 47 nanometers, where the first direction is a direction from close to the gate to far away from the gate.

[0017] In a second aspect, an embodiment of the present disclosure provides a semiconductor device, comprising: a substrate; a transistor disposed on the substrate; a gate of the transistor having a thickness ranging from 700 angstroms to 1200 angstroms.

[0018] In some embodiments, the transistor further includes: a conductive contact layer disposed on the source / drain region of the transistor; and a gate conductive layer disposed on the gate.

[0019] In some embodiments, the method further includes: a conductive structure electrically connected to the conductive contact layer; and a first wiring layer electrically connected to the conductive structure.

[0020] In some embodiments, the method further includes: a second wiring layer electrically connected to the first wiring layer; and the first wiring layer serving as a jumper between the conductive structure and the second wiring layer.

[0021] In some embodiments, the height of the conductive structure ranges from 1500 angstroms to 4000 angstroms.

[0022] In some embodiments, a width of the bottom of the conductive structure ranges from 35 nanometers to 45 nanometers.

[0023] In some embodiments, a width of the first wiring layer ranges from 60 nanometers to 180 nanometers.

[0024] In some embodiments, the transistor further includes a gate sidewall covering a side of the gate; the gate sidewall has a thickness ranging from 38 nanometers to 47 nanometers along a first direction, and the first direction is a direction from close to the gate to away from the gate.

[0025] In a third aspect, an embodiment of the present disclosure provides a semiconductor device comprising: a transistor; a conductive structure electrically connected to the transistor; a first wiring layer and a second wiring layer, wherein the first wiring layer serves as a jumper between the conductive structure and the second wiring layer.

[0026] In some embodiments, the method further includes: a first contact located between the first wiring layer and the second wiring layer, wherein the first contact and the first wiring layer together serve as a jumper between the conductive structure and the second wiring layer.

[0027] In some embodiments, the transistor comprises a high-voltage transistor; a gate of the high-voltage transistor has a thickness ranging from 700 angstroms to 1200 angstroms.

[0028] In some embodiments, the height of the conductive structure ranges from 1500 angstroms to 4000 angstroms.

[0029] In some embodiments, a width of the bottom of the conductive structure ranges from 35 nanometers to 45 nanometers.

[0030] In some embodiments, a width of the first wiring layer ranges from 60 nanometers to 180 nanometers.

[0031] The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device. The method includes: forming a gate layer on a substrate; forming a first mask layer on the gate layer; etching the gate layer using the first mask layer to form a gate; ion doping the substrate to form source / drain regions on both sides of the gate; removing the first mask layer; and forming gate sidewalls covering the sides of the gate. The present disclosure removes the first mask layer after forming the source / drain regions on both sides of the gate, allowing the first mask layer to be used as a protective layer for the gate. This reduces the gate thickness, thereby effectively reducing the size of the peripheral circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic structural diagram of a memory device in an embodiment of the present disclosure;

[0033] Figure 2 A schematic diagram of the steps of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure;

[0034] Figures 3a to 3j A cross-sectional view of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure;

[0035] Figure 4 A cross-sectional view of a conductive structure and a first wiring layer provided in an embodiment of the present disclosure;

[0036] Figure 5 Top views of two semiconductor devices provided by embodiments of the present disclosure;

[0037] Figure 6 A schematic structural diagram of a semiconductor device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] The following will clearly and completely describe the technical solutions in the embodiments of the present disclosure in conjunction with the embodiments of the present disclosure and the accompanying drawings. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0039] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0040] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0041] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to, or coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to, or directly coupled to" another element or layer, there may be no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. However, when the second element, component, region, layer, or part is discussed, it does not necessarily mean that the first element, component, region, layer, or part exists in the present disclosure.

[0042] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0043] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0044] In order to fully understand the present disclosure, detailed steps and detailed structures will be presented in the following description to illustrate the technical solution of the present disclosure. The preferred embodiments of the present disclosure are described in detail below. However, in addition to these detailed descriptions, the present disclosure may also have other implementation methods.

[0045] Figure 1 This is a schematic diagram of the structure of a memory device in an embodiment of the present disclosure. Figure 1 The memory device 100 includes a first semiconductor structure 120 and a second semiconductor structure 140, wherein a bonding surface 101 is included between the first semiconductor structure 120 and the second semiconductor structure 140, and an external pad (not shown in the figure) can be formed on the bonding surface for electrically connecting the first semiconductor structure 120 and the second semiconductor structure 140.

[0046] The first semiconductor structure 120 includes a CMOS substrate 121 suitable for peripheral circuits (CMOS), and a plurality of CMOS transistors (including high-voltage transistors and low-voltage transistors) are formed on the CMOS substrate 121, wherein PMOS transistors and NMOS transistors are collectively referred to as CMOS transistors. A CMOS interconnect structure 122 is formed on the CMOS transistors, and the CMOS interconnect structure 122 includes a pad, a via contact (Vertical Interconnect Access, VIA) and a CMOS wiring layer 123. The CMOS interconnect structure 122 is electrically connected to the gate, source or drain of the CMOS transistor through a conductive structure (contact). The CMOS interconnect structure 122 may also include one or more dielectric layers, in which a CMOS wiring layer and a via contact may be formed.

[0047] The second semiconductor structure 140 includes an array substrate 141. A memory cell array is formed on the array substrate 141. An array interconnect structure 142 is formed on the memory cell array. The array interconnect structure 142 includes an array wiring layer 143. The array wiring layer 143 is electrically connected to the CMOS wiring layer 123 to achieve electrical connection between the first semiconductor structure 120 and the second semiconductor structure 140.

[0048] refer to Figure 1 Because the CMOS wiring layer 123 extends laterally in the first and second directions and is relatively large, wiring connections between semiconductor structures is difficult. Furthermore, the presence of the high-voltage transistor 124 and the low-voltage transistor 125 in the first semiconductor structure, along with the difficulty in reducing the gate height of the high-voltage transistor 124 and the height of the interlayer dielectric layer, and the close correlation between the sizes of the memory cell array and peripheral circuits, make it particularly important to reduce the size of the peripheral circuits while simultaneously reducing the difficulty of connecting semiconductor devices.

[0049] In view of this, an embodiment of the present disclosure provides a method for manufacturing a semiconductor device. Figure 2 A schematic diagram of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. Figure 2 , the preparation method comprises the following steps:

[0050] Step 201, forming a gate layer on a substrate;

[0051] Step 202, forming a first mask layer on the gate layer;

[0052] Step 203, etching the gate layer using the first mask layer to form a gate;

[0053] Step 204 , ion doping the substrate to form source / drain regions on both sides of the gate;

[0054] Step 205, removing the first mask layer;

[0055] Step 206 , forming a gate spacer covering the side surfaces of the gate.

[0056] Figures 3a to 3j This is a cross-sectional view of a semiconductor device during the manufacturing process provided by an embodiment of the present disclosure. It should be noted that: Figures 3a to 3j This is a complete schematic diagram reflecting the implementation process of the semiconductor device manufacturing method. The unmarked parts in some drawings can be shared with each other. Figure 2 as well as Figures 3a to 3j , the preparation method of the semiconductor device provided by the embodiment of the present disclosure is described in detail.

[0057] It should be noted that, for ease of description in the disclosed embodiments, the first and second directions are represented as two orthogonal directions in the substrate plane, that is, two lateral surfaces extending laterally in the substrate plane; the third direction is a direction perpendicular to the substrate plane. For example, the first direction is represented as the X direction in the drawings; the second direction is represented as the Y direction in the drawings; and the third direction is represented as the Z direction in the drawings.

[0058] refer to Figure 3aThe embodiment of the present disclosure provides a substrate 301. The material of the substrate 301 may include a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate, or a germanium-on-insulator (GOI) substrate. A shallow trench isolation structure 302 has been formed in the substrate 301. The shallow trench isolation structure 302 can be used to define an active area or to isolate transistors. The substrate 301 may include a first region 310 and a second region 320. The shallow trench isolation structure 302 can electrically isolate the transistor located in the first region 310 from the transistor located in the second region 320. The first region 310 is used to form a high voltage (HV) transistor, and the second region 320 is used to form a low voltage (LV) transistor and / or a low-low voltage (LLV) transistor.

[0059] The steps of forming the shallow trench isolation structure 302 include: forming a shallow trench mask layer on the substrate 301, and etching the substrate 301 using the shallow trench mask layer to form a shallow trench. The material of the shallow trench mask layer may include one or more of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide. The shallow trench may be formed using a plasma dry etching process, a gas reaction dry etching process, or a wet etching process. Furthermore, an isolation material is deposited in the shallow trench to form the shallow trench isolation structure 302. The shallow trench isolation structure 302 may be formed by a physical vapor deposition (PVD) process, a chemical vapor deposition (CVD) process, or an atomic layer deposition (ALD) process. Afterwards, the shallow trench mask layer may be removed by dry or wet etching.

[0060] In some embodiments, the substrate includes a first region and a second region;

[0061] Etching the gate layer using the first mask layer to form the gate includes:

[0062] Etching the gate layer using the first mask layer to form a first gate in the first region and a second gate in the second region;

[0063] The thickness of the gate oxide layer in the first region is greater than the thickness of the gate oxide layer in the second region.

[0064] In some embodiments, continue to refer to Figure 3aA gate oxide layer 303 is formed on the substrate 301 to separate the gate and the channel of the transistor. The gate oxide layer 303 can be a silicon oxide layer formed by a thermal oxidation method or an in-situ steam generation method. In the process of forming the gate oxide layer 303, the thickness of the gate oxide layer 303 located in the first region 310 can be greater than the thickness of the gate oxide layer 303 located in the second region by properly utilizing a mask. The thickness of the gate oxide layer 303 located in the first region 310 is greater than the thickness of the gate oxide layer 303 located in the second region. The larger gate oxide layer thickness enables the transistor formed in the first region 310 to have a stronger pressure bearing capacity, and the smaller gate oxide layer thickness enables ions in the second region 320 to pass through the gate oxide layer to form a source / drain when the ion implantation energy is low.

[0065] In some embodiments, the gate layer has a thickness ranging from 700 angstroms to 1200 angstroms.

[0066] In some embodiments, reference Figure 3b A gate layer is formed on the gate oxide layer 303, and a first mask layer 304 is formed on the gate layer. The gate layer is etched using the first mask layer 304 to form a first gate 311 in the first region 310 and a second gate 321 in the second region 320. The gate layer may be made of polysilicon or doped polysilicon. In some embodiments, the thickness h1 of the gate layer (first gate 311) in the first region ranges from 700 angstroms to 1200 angstroms. Preferably, the thickness h1 of the gate layer (first gate 311) in the first region may be 850 angstroms.

[0067] In some embodiments, reference Figure 3c , ion doping is performed on the substrate 301 located in the first region 310 to form first source / drain regions 312 on both sides of the first gate 311, wherein the first mask layer 304 serves as a protective layer for the first gate 311 and the second gate 321, and can protect the first gate 311 and the second gate 321 in the subsequent ion doping step to prevent ions from breaking through the first gate 311 while avoiding ions from being injected into the channel. Therefore, under the protection of the first mask layer 304, the thickness of the first gate 311 can be reduced without affecting the device performance.

[0068] In some embodiments, after removing the first mask layer, the method further includes:

[0069] Ion doping is performed on the substrate located in the second region to form source / drain regions on both sides of the second gate.

[0070] refer to Figure 3dAfter forming the first source / drain regions 312 on both sides of the first gate 311, the first mask layer 304 can be removed by dry or wet etching to increase the process window for ion doping of the substrate in the second region 320. Furthermore, an LDD process is performed on the substrate 301 in the second region 320 to form second source / drain regions 322 on both sides of the second gate 321.

[0071] In some embodiments, the thickness of the gate spacer along a first direction ranges from 38 nanometers to 47 nanometers, where the first direction is from close to the gate to far away from the gate.

[0072] Further, refer to Figure 3e , forming gate spacers covering the sides of the gate, including: forming a first gate spacer 313 covering the sides of the first gate 311 and a second gate spacer 323 covering the sides of the second gate 321 through a spacer process. The first gate spacer 313 and the second gate spacer 323 can be a single-layer structure or a multi-layer structure as shown in the figure. The thickness of the first gate spacer 313 and the second gate spacer 323 along the first direction ranges from 38 to 47 nanometers. Preferably, the thickness of the first gate spacer 313 and the second gate spacer 323 along the first direction can be 43 nanometers.

[0073] In some embodiments, the first source / drain region 312 and the second source / drain region 322 may serve as the source / drain of the first gate 311 and the source / drain of the second gate 321 , respectively.

[0074] In other embodiments, the first source / drain region 312 may be a lightly doped source / drain region, and ion implantation may be performed on the first source / drain region 312 using the first gate sidewall 313 to form a heavily doped source / drain region (not shown). The heavily doped source / drain region located in the first source / drain region 312 and the second source / drain region 322 may serve as the source / drain of the first gate 311 and the source / drain of the second gate 321, respectively. The heavily doped source / drain region located in the first source / drain region 312 helps lower the potential barrier during metal extraction to achieve ohmic contact. It should be noted that the first mask layer 304 may be removed after forming the heavily doped source / drain region located in the first source / drain region 312 to prevent ions from penetrating the first gate 311 when forming the heavily doped source / drain region located in the first source / drain region 312.

[0075] In some embodiments, the method further includes forming a conductive contact layer on the source / drain regions and a gate conductive layer on the gate.

[0076] In some embodiments, reference Figure 3fA first conductive contact layer 314 and a second conductive contact layer 324 are formed on the first source / drain region 312 and the second source / drain region 322, and a first gate conductive layer 315 and a second gate conductive layer 325 are formed on the first gate 311 and the second gate 321. The conductive contact layer and the gate conductive layer may be formed by depositing a conductive material or by metallization, and may include metal silicide.

[0077] In some embodiments, the method further comprises:

[0078] forming an interlayer dielectric layer (ILD) covering the semiconductor device;

[0079] Etching the interlayer dielectric layer using the contact hole mask to form a contact hole that penetrates the interlayer dielectric layer and extends to the conductive contact layer;

[0080] The interlayer dielectric layer is etched using the first wiring layer mask to enlarge the opening at the top of the contact hole to form a wiring opening.

[0081] In some embodiments, continue to refer to Figure 3f , forming an interlayer dielectric layer 305 covering the substrate 301, wherein the thickness H of the interlayer dielectric layer 305 can be 2000 angstroms. Figure 3g A contact hole mask layer (not shown) having a first opening and a second opening is formed on the interlayer dielectric layer 305. The projections of the first opening and the second opening on the substrate 301 at least partially overlap with the first conductive contact layer 314 and the second conductive contact layer 324, respectively. The interlayer dielectric layer 305 is etched using the contact hole mask layer, with the conductive contact layers 314 and 324 serving as etch stop layers, to form a contact hole 306 that penetrates the interlayer dielectric layer 305 and extends to the first conductive contact layer 314 and the second conductive contact layer 324. It should be noted that the interlayer dielectric layer 305 can be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof.

[0082] Further, refer to Figure 3h The contact hole mask layer is removed, and a first wiring layer mask (not shown) having a third opening and a fourth opening is formed on the interlayer dielectric layer 305. The projections of the third opening and the fourth opening on the substrate 301 overlap with the first opening and the second opening, respectively, and are larger than the first opening and the second opening, respectively. The interlayer dielectric layer 305 is etched using the first wiring layer mask to enlarge the opening at the top of the contact hole to form a wiring opening 306b. The contact hole with the enlarged top opening includes the wiring opening 306b and a portion 306a excluding the wiring opening. Here, the wiring opening 306b is used to form the first wiring layer (Metal 1), and the portion 306a excluding the wiring opening is used to form the conductive structure (Contact).

[0083] In some embodiments, the method further includes filling the contact hole to form a conductive structure in a portion of the contact hole excluding the wiring opening, and forming a first wiring layer in the wiring opening.

[0084] In this way, the conductive structure and the first wiring layer can be simultaneously formed through only one filling step, without the need to form the conductive structure and the first wiring layer separately, thereby effectively reducing the number of process steps and process costs.

[0085] It should be noted that since the wiring opening is formed by expanding the top of the contact hole on the basis of forming the contact hole, when forming the interlayer dielectric layer, the deposition thickness of the interlayer dielectric layer needs to refer to the conductive structure to be formed and the size of the first wiring layer in the third direction.

[0086] In some embodiments, the height of the conductive structure ranges from 1500 angstroms to 4000 angstroms. The height of the conductive structure is the length of the conductive structure in the third direction.

[0087] In some embodiments, reference Figure 3i Contact hole 306 is filled with a conductive material, and a conductive structure 3061 is formed in portion 306a of contact hole 306 excluding the wiring opening, and a first wiring layer 3062 is formed in wiring opening 306b. In some embodiments, height h2 of conductive structure 3061 ranges from 1500 angstroms to 4000 angstroms. Preferably, height h2 of conductive structure 3061 can be 2000 angstroms.

[0088] In some embodiments, the bottom of the conductive structure has a width ranging from 35 nm to 45 nm.

[0089] Figure 4 A cross-sectional view of the conductive structure and the first wiring layer provided in an embodiment of the present disclosure. Figure 4 , the width L1 of the bottom of the conductive structure 3061 ranges from 35 nm to 45 nm, while in other embodiments the conductive structure size (bottom width) is generally greater than 50 nm. Figure 4 As shown, the width L2 of the top of the conductive structure 3061 ranges from 50 nanometers to 60 nanometers, and the width L3 of the first wiring layer 3062 ranges from 60 nanometers to 180 nanometers. Preferably, the width L3 of the first wiring layer 3062 can be 120 nanometers. Due to the relatively small thickness of the interlayer dielectric layer, the size of the conductive structure 3061 formed by the semiconductor device fabrication method provided by the embodiment of the present disclosure can be significantly reduced, thereby improving routing flexibility in subsequent process steps. Furthermore, the size of the first wiring layer 3062 is significantly reduced, and it can be formed in the same step as the conductive structure 3061, reducing process steps and process costs.

[0090] In some embodiments, the method further includes: forming a second wiring layer (Metal2) on the first wiring layer, the second wiring layer being electrically connected to the first wiring layer; and the first wiring layer serving as a jumper between the conductive structure and the second wiring layer.

[0091] In some embodiments, reference Figure 3j , a second wiring layer 3063 is formed on the first wiring layer 3062. The second wiring layer 3063 can be formed by depositing a second dielectric layer on the interlayer dielectric layer 305, etching the second dielectric layer using a photomask to form a second wiring opening, and filling the second wiring opening with a conductive material. The first wiring layer 3062 serves as a jumper between the conductive structure 3061 and the second wiring layer 3063, and routing is started from the second wiring layer 3063 to achieve electrical connection between the transistor and the memory array. In the embodiment of the present disclosure, by using the first wiring layer 3062 as a jumper and routing from the second wiring layer 3063, the height of the conductive structure can be reduced while preventing the performance of the high-voltage transistor from being affected by the routing. The second wiring layer 3063 includes a first routing extending along a first direction and a second routing extending along a second direction. The first routing and the second routing can achieve electrical connection between the peripheral circuit and the memory array. It should be noted that the material of the second interlayer dielectric layer can be the same as that of the interlayer dielectric layer 305.

[0092] Continue to refer Figure 3j The transistor formed in the first area 310 can be jumped to the second wiring layer 3063 through the first wiring layer 3062, and the wiring is routed through the second wiring layer 3063 to achieve electrical connection between the transistor and the storage array, so as to increase the distance between the wiring and the transistor in the first area 310, so that the transistor in the first area 310 has a stronger pressure-bearing capacity.

[0093] In other embodiments, the transistors formed in the second region 320 can be routed through the first wiring layer 3062 or the second wiring layer 3063 to achieve electrical connection between the transistors and the memory array, thereby increasing the flexibility of back-end-of-line (BEOL) interconnection of the transistors in the second region 320.

[0094] In some embodiments, the width of the first wiring layer ranges from 60 nanometers to 180 nanometers.

[0095] Figure 5 The top view of two semiconductor devices provided in the embodiment of the present disclosure. Figure 5In some embodiments, a semiconductor device 500a includes a wiring layer 501a, a first gate 502a located in a first region (HV), a second gate 503a located in a second region (LV / LLV), and conductive structures 5041a to 5043a located on both sides of the first gate 502a and the second gate 503a. The conductive structure 5042a is a common conductive structure. The wiring layer 501a extends laterally along a plane defined by a first direction and a second direction. In other words, the wiring layer 501a includes traces extending along the first direction and traces extending along the second direction. The projected size of the wiring layer 501a on the plane defined by the first and second directions is much larger than the projected size of the conductive structures on the plane defined by the first and second directions. It should be noted that the wiring layer 501a is Metal 1. In other embodiments, semiconductor device 500b includes a first wiring layer 501b, a first gate 502b located in a first region (HV), a second gate 503b located in a second region (LV / LLV), and conductive structures 5041b to 5043b located on either side of the first gate 502b and the second gate 503b. Conductive structure 5042b is a common conductive structure. Compared to semiconductor device 500a, in semiconductor device 500b, since the first wiring layer 501b does not need to serve as a routing line but only as a jumper between the conductive structure 3061 and the second wiring layer 3063, the size of the first wiring layer 501b can be significantly reduced.

[0096] Figure 6 This is a schematic diagram of the structure of a semiconductor device provided by an embodiment of the present disclosure. The semiconductor device 600 includes:

[0097] substrate 601;

[0098] A transistor 602 is provided on the substrate;

[0099] The gate of transistor 602 has a thickness in the range of 700 angstroms to 1200 angstroms.

[0100] In some embodiments, the transistor 602 includes a high-voltage transistor 602 a and a low-voltage / low-low-voltage transistor 602 b , wherein the gate thickness of the high-voltage transistor 602 a may be 850 angstroms.

[0101] In some embodiments, the transistor further comprises:

[0102] A conductive contact layer 603 is disposed on the source / drain regions of the transistor 602;

[0103] The gate conductive layer 604 is disposed on the gate of the transistor 602 .

[0104] In some embodiments, further comprising:

[0105] Conductive structure 605, electrically connected to the conductive contact layer 603;

[0106] The first wiring layer 606 is electrically connected to the conductive structure 605 .

[0107] In some embodiments, further comprising:

[0108] The second wiring layer 607 is electrically connected to the first wiring layer 606 ; the first wiring layer 606 serves as a jumper between the conductive structure 605 and the second wiring layer 607 .

[0109] In some embodiments, first wiring layer 606 serves as a jumper between conductive structure 605 and second wiring layer 607, with routing initiated from second wiring layer 607 to achieve electrical connection between the transistor and the memory array. In the disclosed embodiments, by using first wiring layer 606 as a jumper and routing from second wiring layer 607, the height of conductive structure 605 can be reduced while preventing the performance of the high-voltage transistor in transistor 602 from being affected by the routing. Second wiring layer 607 includes a first routing extending along a first direction and a second routing extending along a second direction. The first and second routings can achieve electrical connection between peripheral circuits and the memory array.

[0110] In some embodiments, the height of the conductive structure 605 ranges from 1500 angstroms to 4000 angstroms.

[0111] In some embodiments, the height of the conductive structure 605 may be 2000 angstroms, where the height of the conductive structure 605 is the length of the conductive structure 605 in the third direction.

[0112] In some embodiments, the width of the bottom of the conductive structure 605 ranges from 35 nm to 45 nm.

[0113] In some embodiments, the first wiring layer 606 has a width ranging from 60 nm to 180 nm.

[0114] In some embodiments, the width of the first wiring layer 606 is 120 nanometers.

[0115] In some embodiments, since the first wiring layer 606 does not need to be used as a routing line, but only needs to be used as a jumper between the conductive structure 605 and the second wiring layer 607, the height of the conductive structure 605 will not be affected by the distance between the high-voltage transistor in the transistor 602 and the first wiring layer 606. The size of the conductive structure 605 can be greatly reduced, which can improve the routing flexibility in subsequent process steps and help reduce the size of peripheral circuits.

[0116] In some embodiments, the transistor 602 further includes a gate spacer 608 covering a side surface of the gate;

[0117] The thickness of the gate spacer 608 along a first direction ranges from 38 nm to 47 nm, where the first direction is from close to the gate to far away from the gate.

[0118] In some embodiments, the thickness of the gate spacer 608 along the first direction is 43 nm.

[0119] The present disclosure also provides a semiconductor device 600, referring to Figure 6 , comprising: a transistor 602;

[0120] a conductive structure 605 electrically connected to the transistor 602;

[0121] The first wiring layer 606 and the second wiring layer 607 , the first wiring layer 606 serves as a jumper between the conductive structure 605 and the second wiring layer 607 .

[0122] In some embodiments, first wiring layer 606 is used as a jumper between conductive structure 605 and second wiring layer 607, with routing initiated from second wiring layer 607 to achieve electrical connection between the transistor and the memory array. In the disclosed embodiments, by using first wiring layer 606 as a jumper and routing from second wiring layer 607, the height of conductive structure 605 can be reduced while preventing the performance of the high-voltage transistor in transistor 602 from being affected by the routing. Second wiring layer 607 includes a first routing extending along a first direction and a second routing extending along a second direction. The first and second routings can achieve electrical connection between peripheral circuits and the memory array.

[0123] In some embodiments, the invention further includes: a first contact 609 located between the first wiring layer 606 and the second wiring layer 607 , and the first contact 609 and the first wiring layer 606 together serve as a jumper between the conductive structure 605 and the second wiring layer 607 .

[0124] In some embodiments, transistor 602 includes a high-voltage transistor 602a;

[0125] The gate of the high voltage transistor 602a has a thickness ranging from 700 angstroms to 1200 angstroms.

[0126] In some embodiments, transistor 602 also includes a low voltage / low-low voltage transistor 602b, wherein the high voltage transistor 602a can achieve back-end process interconnection through the second wiring layer 607, and the low voltage / low-low voltage transistor 602b can achieve back-end process interconnection through the first wiring layer 606 or the second wiring layer 607.

[0127] In some embodiments, the height of the conductive structure 605 ranges from 1500 angstroms to 4000 angstroms.

[0128] In some embodiments, the height of the conductive structure 605 may be 2000 angstroms, where the height of the conductive structure 605 is the length of the conductive structure 605 in the third direction.

[0129] In some embodiments, the first wiring layer 606 has a width ranging from 60 nm to 180 nm.

[0130] In some embodiments, the width of the bottom of the conductive structure 605 ranges from 35 nm to 45 nm.

[0131] In some embodiments, the first wiring layer 606 has a width ranging from 60 nm to 180 nm.

[0132] In some embodiments, the width of the first wiring layer 606 is 120 nanometers.

[0133] In some embodiments, since the first wiring layer 606 does not need to be used as a routing line, but only needs to be used as a jumper between the conductive structure 605 and the second wiring layer 607, the height of the conductive structure 605 will not be affected by the distance between the high-voltage transistor 602a and the first wiring layer 606. The size of the conductive structure 605 can be greatly reduced, which can improve the routing flexibility in subsequent process steps and help reduce the size of peripheral circuits.

[0134] It should be noted that the above description of the semiconductor device is similar to the description of the semiconductor device manufacturing method embodiment, and has similar beneficial effects as the semiconductor device manufacturing method embodiment. For any technical details not disclosed in the semiconductor device embodiment of the present disclosure, please refer to the description of the semiconductor device manufacturing method embodiment of the present disclosure for understanding.

[0135] The present disclosure provides a method for fabricating a semiconductor device and the semiconductor device. The method includes: forming a gate layer on a substrate; forming a first mask layer on the gate layer; etching the gate layer using the first mask layer to form a gate; ion doping the substrate to form source / drain regions on both sides of the gate; removing the first mask layer; and forming gate sidewalls covering the sides of the gate. The present disclosure removes the first mask layer after forming the source / drain regions on both sides of the gate. This allows the first mask layer to serve as a protective layer for the gate, thereby reducing the gate thickness and effectively reducing the size of the peripheral circuitry.

[0136] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0137] The above description is only a preferred embodiment of the present disclosure and does not limit the patent scope of the present disclosure. All equivalent structural transformations made by using the contents of the present disclosure and the drawings under the inventive concept of the present disclosure, or direct / indirect application in other related technical fields are included in the patent protection scope of the present disclosure.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises: forming a gate layer on the substrate; forming a first mask layer on the gate layer; etching the gate layer using the first mask layer to form a gate; performing ion doping on the substrate to form source / drain regions on both sides of the gate; removing the first mask layer; A gate sidewall is formed to cover the side surface of the gate.

2. The method according to claim 1, characterized in that The method further comprises: A conductive contact layer is formed on the source / drain region and a gate conductive layer is formed on the gate.

3. The method according to claim 2, characterized in that The method further comprises: forming an interlayer dielectric layer covering the semiconductor device; Etching the interlayer dielectric layer using a contact hole mask to form a contact hole that penetrates the interlayer dielectric layer and extends to the conductive contact layer; The interlayer dielectric layer is etched using a first wiring layer mask to enlarge the opening at the top of the contact hole to form a wiring opening.

4. The method according to claim 3, characterized in that The method further comprises: The contact hole is filled to form a conductive structure in a portion of the contact hole excluding the wiring opening, and a first wiring layer is formed in the wiring opening.

5. The method according to claim 1, wherein The substrate includes a first region and a second region; The etching the gate layer by using the first mask layer to form a gate includes: Etching the gate layer using the first mask layer to form a first gate in the first region and a second gate in the second region; The thickness of the gate oxide layer in the first region is greater than the thickness of the gate oxide layer in the second region.

6. The method according to claim 5, characterized in that After removing the first mask layer, the method further includes: Ion doping is performed on the substrate located in the second region to form source / drain regions on both sides of the second gate.

7. The method according to claim 4, characterized in that The method further comprises: A second wiring layer is formed on the first wiring layer, and the second wiring layer is electrically connected to the first wiring layer; the first wiring layer serves as a jumper between the conductive structure and the second wiring layer.

8. The method according to claim 1, characterized in that The gate layer has a thickness ranging from 700 angstroms to 1200 angstroms.

9. The method according to claim 4, characterized in that The height of the conductive structure ranges from 1500 angstroms to 4000 angstroms.

10. The method according to claim 4, characterized in that The bottom of the conductive structure has a width ranging from 35 nanometers to 45 nanometers.

11. The method according to claim 4, characterized in that The width of the first wiring layer ranges from 60 nanometers to 180 nanometers.

12. The method according to claim 1, characterized in that The thickness of the gate spacer along a first direction ranges from 38 nanometers to 47 nanometers, and the first direction is a direction from close to the gate to far away from the gate.

13. A semiconductor device, characterized in that: include: substrate; a transistor, disposed on the substrate; The thickness of the gate of the transistor ranges from 700 angstroms to 1200 angstroms.

14. The semiconductor device according to claim 13, wherein: The transistor further includes: A conductive contact layer is provided on the source / drain region of the transistor; The gate conductive layer is disposed on the gate.

15. The semiconductor device according to claim 14, wherein: Also includes: a conductive structure electrically connected to the conductive contact layer; The first wiring layer is electrically connected to the conductive structure.

16. The semiconductor device according to claim 15, wherein: Also includes: a second wiring layer electrically connected to the first wiring layer; The first wiring layer serves as a jumper between the conductive structure and the second wiring layer.

17. The semiconductor device according to claim 15, wherein: The height of the conductive structure ranges from 1500 angstroms to 4000 angstroms.

18. The semiconductor device according to claim 15, wherein The bottom of the conductive structure has a width ranging from 35 nanometers to 45 nanometers.

19. The semiconductor device according to claim 15, wherein The width of the first wiring layer ranges from 60 nanometers to 180 nanometers.

20. The semiconductor device according to claim 13, wherein The transistor further includes a gate sidewall covering a side of the gate; The thickness of the gate spacer along a first direction ranges from 38 nanometers to 47 nanometers, and the first direction is a direction from close to the gate to far away from the gate.

21. A semiconductor device, characterized in that: include: transistor; a conductive structure electrically connected to the transistor; a first wiring layer and a second wiring layer, wherein the first wiring layer serves as a jumper between the conductive structure and the second wiring layer.

22. The semiconductor device according to claim 21, wherein Also includes: A first contact is located between the first wiring layer and the second wiring layer, and the first contact and the first wiring layer together serve as a jumper between the conductive structure and the second wiring layer.

23. The semiconductor device according to claim 21, wherein The transistor comprises a high voltage transistor; The thickness of the gate of the high-voltage transistor ranges from 700 angstroms to 1200 angstroms.

24. The semiconductor device according to claim 21, wherein The height of the conductive structure ranges from 1500 angstroms to 4000 angstroms.

25. The semiconductor device according to claim 21, wherein The bottom of the conductive structure has a width ranging from 35 nanometers to 45 nanometers.

26. The semiconductor device according to claim 21, wherein The width of the first wiring layer ranges from 60 nanometers to 180 nanometers.

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