Semiconductor element and manufacturing method thereof
By forming pores and groove structures in semiconductor elements, the problems of large size and difficulty in wearing display driver integrated circuits in the existing technology are solved, and a more miniaturized and high-performance display driver integrated circuit is achieved, which is suitable for augmented reality and virtual reality technologies.
Patent Information
- Application Number
- CN202410319922.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-03-04
- Filing Date
- 2024-03-20
- Publication Date
- 2025-09-09
AI Technical Summary
The wire connection design of the display driver integrated circuit in existing head-mounted display devices results in large product size, occupies space, and increases the difficulty of wearing. It cannot meet the application requirements of augmented reality and virtual reality technologies.
By forming a metal gate and spacers on the substrate, using an etching process to form pores on both sides of the metal gate, and forming grooves on the low-impedance metal layer, the grooves are sealed with a buffer layer to form pores, thereby reducing the gate-source and gate-drain capacitances and improving the slew rate of the display driver integrated circuit.
It effectively reduces the size of semiconductor components, reduces the difficulty of wearing, and improves the performance of display driver integrated circuits, making it suitable for the application of augmented reality and virtual reality technologies.
Smart Images
Figure CN120614867A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor element and a manufacturing method thereof, and in particular to a semiconductor element with pores formed between a high-dielectric-constant dielectric layer and a low-resistance metal layer and a manufacturing method thereof. Background Art
[0002] With the advancement of science and technology, technologies such as augmented reality (AR) and virtual reality (VR) are gradually maturing. In the foreseeable future, AR and VR will be widely used in human life, for example in education, logistics, medical care, and the military.
[0003] Currently, augmented reality and virtual reality are mainly realized by head-mounted displays. Among them, current head-mounted displays usually connect display driver integrated circuits (DDICs) containing high-voltage components, medium-voltage components, and / or low-voltage components to a display module via very long wires or metal interconnects. This design usually results in a large product, which not only takes up space but also increases the difficulty of wearing. Therefore, how to improve the current manufacturing process to provide a display that can be used in AR or VR environments is an important issue. Summary of the Invention
[0004] An embodiment of the present invention discloses a method for manufacturing a semiconductor device, which mainly forms a metal gate on a substrate and an interlayer dielectric layer surrounding the metal gate, removes a portion of the metal gate to form a first groove, and then forms a buffer layer on the metal gate and seals the first groove to form a first air hole.
[0005] Another embodiment of the present invention discloses a semiconductor device comprising a metal gate disposed on a substrate, a spacer disposed adjacent to the metal gate, an interlayer dielectric layer surrounding the metal gate, a first air hole disposed on one side of the metal gate and between the spacer and the metal gate, and a second air hole disposed on the other side of the metal gate and between the spacer and the metal gate. The metal gate further comprises a high-k dielectric layer disposed on the substrate, a work function metal layer disposed on the high-k dielectric layer, and a low-resistance metal layer disposed on the work function metal layer. BRIEF DESCRIPTION OF THE DRAWINGS
[0006] Figures 1 to 5 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0007] Explanation of symbols
[0008] 12: Base
[0009] 14: Fin structure
[0010] 16: Shallow Trench Isolation
[0011] 18: Gate structure
[0012] 20: Gate structure
[0013] 24: Gate dielectric layer
[0014] 26: Gate material layer
[0015] 28: gap wall
[0016] 30: Source / drain region
[0017] 32: epitaxial layer
[0018] 34: Interlayer dielectric layer
[0019] 36: Gate dielectric layer
[0020] 38: buffer layer
[0021] 40: pores
[0022] 42: Hard mask
[0023] 46: High dielectric constant dielectric layer
[0024] 48: Work function metal layer
[0025] 50: low impedance metal layer
[0026] 52:Metal gate
[0027] 56: Groove
[0028] 60: Contact plug
[0029] 62: Silicide metal layer
[0030] 102: Plane area
[0031] 104: Non-planar area DETAILED DESCRIPTION
[0032] Although specific configurations and arrangements are discussed herein, it should be understood that this is done for illustrative purposes only. Those skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.
[0033] It should be noted that references in the specification to "one embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," etc. indicate that the described embodiments may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such terms do not necessarily refer to the same embodiment. In addition, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, it is within the knowledge of those skilled in the relevant art to implement such feature, structure, or characteristic in conjunction with other embodiments, whether or not explicitly described.
[0034] Generally, terms can be understood at least in part based on usage in context. For example, as used herein, the term "one or more" (depending at least in part on the context) can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a plural combination of features, structures or characteristics. Similarly, terms such as "a", "an" or "the" can again be understood to express singular usage or to convey plural usage, depending at least in part on the context. In addition, the term "based on" can be understood as not necessarily intended to convey an exclusive set of factors, and can instead allow for the presence of additional factors that are not necessarily explicitly described and depend at least in part on the context.
[0035] It should be readily understood that the meanings of “on,” “over,” and “above” in the disclosure of this case should be interpreted in the broadest manner, so that “on” means not only “directly” on something, but also includes being on something with intervening features or layers therebetween, and that “on” or “above” means not only being on or above something, but also includes having no intervening features or layers (i.e., directly on something).
[0036] Furthermore, for ease of description, as illustrated in the accompanying drawings, spatially relative terms such as "below," "beneath," "lower," "above," "higher," etc. may be used to describe the relationship of one element or feature to another element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
[0037] As used herein, the term "substrate" refers to the material onto which a layer of material is subsequently added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. Additionally, the substrate can include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer.
[0038] As used herein, the term "layer" refers to a portion of a material that includes an area having a thickness. A layer may extend over the entire underlying or superstructure, or may have an extent that is less than the extent of the underlying or superstructure. In addition, a layer may be an area of a uniform or non-uniform continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes between the top and bottom surfaces. A layer may extend horizontally, vertically and / or along a tapered surface. A substrate may be a layer that may include one or more layers and / or may have one or more layers above and / or below it. A layer may contain multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (in which contacts, interconnects and / or vias are formed) and one or more dielectric layers.
[0039] Please refer to Figures 1 to 5 , Figures 1 to 5 FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 1 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate, wherein the substrate 12 preferably has a planar region 102 and a non-planar region 104, wherein the planar region 102 can be used to prepare high-voltage components and / or medium-voltage components based on planar field-effect transistors in subsequent manufacturing processes, while the non-planar region 104 is preferably used to prepare low-voltage components based on non-planar component structures such as fin field-effect transistor (Fin FET) components.
[0040] Then, a plurality of fin structures 14 can be formed on the substrate 12 in the non-planar region 104. According to one embodiment of the present invention, the fin structure 14 is preferably obtained by a sidewall image transfer (SIT) technique, and the procedure generally includes: providing a layout pattern to a computer system, and defining the corresponding pattern in a photomask through appropriate calculations. Subsequently, a plurality of equidistant and equal-width patterned sacrificial layers can be formed on the substrate through photolithography and etching processes, so that their individual appearances are strip-shaped. Thereafter, deposition and etching processes are sequentially performed to form spacers on each sidewall of the patterned sacrificial layer. The patterned sacrificial layer is then removed, and an etching process is performed under the coverage of the spacers, so that the pattern formed by the spacers is transferred to the substrate, and then a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.
[0041] In addition, the fin structure 14 may be formed by first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask into the substrate 12 to form the fin structure 14. Alternatively, the fin structure may be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then using an epitaxial process to grow a semiconductor layer, such as silicon germanium, on the substrate 12 exposed by the patterned hard mask layer. This semiconductor layer may serve as the corresponding fin structure 14. These embodiments of forming the fin structure 14 are all within the scope of the present invention.
[0042] A shallow trench isolation (STI) 16 is then formed to separate the planar region 102 from the non-planar region 104. In this embodiment, the STI 16 is formed by first using a flowable chemical vapor deposition (FCVD) process to form a silicon oxide layer within the substrate 12 surrounding the transistor region. A chemical mechanical polishing (CMP) process is then used in conjunction with an etching process to partially remove the silicon oxide layer, leaving the remaining silicon oxide layer slightly above the substrate 12 surface in the planar region 102 to form the STI 16. In this embodiment, the top surface of the STI 16 is slightly higher than the substrate 12 surface in the planar region 102 and is aligned with the top surface of the fin structure 14 in the non-planar region 104. However, this is not limiting. According to other embodiments of the present invention, the top surface of the STI 16 may alternatively be aligned with or slightly above the substrate 12 surface in the planar region 102. These variations are within the scope of the present invention.
[0043] Next, gate structures 18 and 20 or dummy gates are formed on the substrate 12 in the planar region 102 and the non-planar region 104, respectively. In this embodiment, the gate structures 18 and 20 can be fabricated using a gate-first process, a gate-last process (a high-k first process), or a gate-last process (a high-k last process) based on fabrication process requirements. Taking the post-high-k dielectric layer fabrication process of the present embodiment as an example, a gate dielectric layer 24 or dielectric layer, a gate material layer 26 composed of polysilicon, and a selective hard mask (not shown) can be sequentially formed on the substrate 12. A pattern transfer process is then performed using a patterned photoresist (not shown) as a mask. A portion of the gate material layer 26 is removed by a single etching or successive etching steps. The patterned photoresist is then stripped to form gate structures 18 and 20 each composed of the patterned gate material layer 26 on the substrate 12. It should be noted that in the present embodiment, the gate dielectric layer 24 in the non-planar region 104 can be patterned together with the gate material layer 26 to form the gate structure 20, but this is not limited to this. According to other embodiments of the present invention, when patterning the gate material layer 26, only the gate material layer 26 in the non-planar region 104 can be patterned without patterning the gate dielectric layer 24, so that the gate dielectric layer 24 covers the entire surface of the substrate 12. This variation is also within the scope of the present invention.
[0044] Then, at least one spacer 28 is formed on the sidewalls of the gate structures 18 and 20, respectively, and a source / drain region 30 and / or an epitaxial layer 32 are formed in the substrate 12 on both sides of the spacer 28. In the present embodiment, the spacer 28 can be a single spacer or a composite spacer, for example, it can include an offset spacer and a main spacer in detail. The offset spacer and the main spacer can include the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride and silicon carbide. The source / drain region 30 can include different dopants depending on the conductivity type of the transistor to be prepared, for example, it can include P-type dopants or N-type dopants.
[0045] In a preferred embodiment of the present invention, the epitaxial layer 32 can be made of different materials depending on the type of metal oxide semiconductor (MOS) transistor. For example, if the MOS transistor is a P-type transistor (PMOS), the epitaxial layer 32 can optionally include silicon germanium (SiGe), silicon germanium boron (SiGeB), or silicon germanium tin (SiGeSn). In another embodiment of the present invention, if the MOS transistor is an N-type transistor (NMOS), the epitaxial layer 32 can optionally include silicon carbide (SiC), silicon carbon phosphide (SiCP), or silicon phosphide (SiP). Furthermore, the selective epitaxial fabrication process can be performed using a single layer or multiple layers, and the heterogeneous atoms (e.g., germanium atoms or carbon atoms) can also be varied in a gradual manner. However, it is preferred that the surface of the epitaxial layer 32 be lighter or free of germanium atoms to facilitate the subsequent formation of the metal silicide layer.
[0046] According to one embodiment of the present invention, the source / drain region 30 can be selectively formed on a portion or all of the epitaxial layer 32. In one embodiment, the formation of the source / drain region 30 can also be performed in-situ during the selective epitaxial growth process. For example, when the metal oxide semiconductor conductor is a PMOS, a germanium silicide epitaxial layer, a germanium boron silicide epitaxial layer, or a germanium tin silicide epitaxial layer is formed, which can be accompanied by the implantation of P-type dopants; or when the metal oxide semiconductor conductor is an NMOS, a carbon silicide epitaxial layer, a carbon phosphorus silicide epitaxial layer, or a phosphorus silicide epitaxial layer is formed, which can be accompanied by the implantation of N-type dopants. This can omit the subsequent use of additional ion implantation steps to form the source / drain region 30 of the P-type / N-type transistor. In another embodiment, the dopants in the source / drain region 30 can also be formed in a gradual manner.
[0047] A contact etch stop layer (not shown) is then optionally formed to cover the surfaces of the gate structures 18, 20 and the shallow trench isolation 16, and an interlayer dielectric layer 34 is then formed on the gate structures 18, 20. A planarization process is then performed, such as using chemical mechanical polishing (CMP) to remove portions of the interlayer dielectric layer 34 and the contact etch stop layer and expose the gate material layer 26 made of polysilicon material, so that the upper surface of the gate material layer 26 is flush with the upper surface of the interlayer dielectric layer 34.
[0048] like Figure 2As shown, a replacement metal gate (RMG) process is then performed to convert each gate structure 18 , 20 into a metal gate. For example, a selective dry etching or wet etching process can be performed first, such as using an etching solution such as ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 26 in the gate structures 18 , 20 and even the gate dielectric layer 24 in the non-planar region 104 , thereby forming a recess (not shown) in the interlayer dielectric layer 34 .
[0049] Next, another optional dielectric layer (not shown) or gate dielectric layer 36, a high-k dielectric layer 46, a work function metal layer 48, and a low-resistance metal layer 50 are sequentially formed in each groove. A planarization process is then performed, such as using CMP to remove portions of the low-resistance metal layer 50, the work function metal layer 48, and the high-k dielectric layer 46 to form metal gates 52. Taking the gate structure fabricated using the high-k dielectric layer last fabrication process in this embodiment as an example, each metal gate 52 preferably includes a dielectric layer or gate dielectric layer 36, a U-shaped high-k dielectric layer 46, a U-shaped work function metal layer 48, and a low-resistance metal layer 50.
[0050] In this embodiment, the gate dielectric layer 24 and the gate dielectric layer 36 may include the same material or different materials. For example, both may include silicon oxide. The high-k dielectric layer 46 includes a dielectric material having a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (SrTiO3), and strontium bismuth tantalum oxide (SrTiO3). tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (barium strontium titanate, Ba x Sr 1- x TiO3, BST), or a combination thereof.
[0051] The work function metal layer 48 is preferably used to adjust the work function of the metal gate so that it is suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as, but not limited to, titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide). If the transistor is a P-type transistor, the work function metal layer 48 can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC). Another barrier layer (not shown) may be included between the work function metal layer 48 and the low resistance metal layer 50. The barrier layer may be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low resistance metal layer 50 may be made of low resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof.
[0052] Next, a portion of the high-k dielectric layer 46, a portion of the work function metal layer 48, and a portion of the low-resistance metal layer 50 can be removed to form a groove (not shown). It should be noted that in this stage, due to the different material selection ratios when etching away portions of the high-k dielectric layer 46, a portion of the work function metal layer 48, and a portion of the low-resistance metal layer 50 to form the groove, the top surface of the low-resistance metal layer 50 is preferably slightly higher than the top surfaces of the high-k dielectric layer 46 and the work function metal layer 48.
[0053] More specifically, when the present embodiment removes a portion of the high-k dielectric layer 46, a portion of the work function metal layer 48 and a portion of the low-resistance metal layer 50 by etching, it is preferable to adjust the selection ratio between the materials to remove more of the high-k dielectric layer 46 and the work function metal layer 48 and less of the low-resistance metal layer 50, so that the top surface of the work function metal layer 48 is at least lower than the top surface of the low-resistance metal layer 50.
[0054] It is noteworthy that although the etching process performed in this stage simultaneously removes portions of the high-k dielectric layer 46, the work function metal layer 48, and the low-resistance metal layer 50 in both the planar region 102 and the non-planar region 104, since the actual length of the gate structure 18 in the planar region 102 (i.e., the distance extending along the X direction in the figure) is much longer than the length of the gate structure 20 in the non-planar region 104, the top surface of the remaining work function metal layer 48 in the planar region 102 is not only lower than the top surface of the low-resistance metal layer 50, but also lower than the top surface of the high-k dielectric layer 46. Simultaneously, a groove 56 is formed on one side of the low-resistance metal layer 50 and another groove 56 is formed on the other side of the low-resistance metal layer 50. In detail, each groove 56 is preferably disposed within the work function metal layer 48 or is preferably formed by the sidewalls of the high-k dielectric layer 46, the top surface of the work function metal layer 48, and the sidewalls of the low-resistance metal layer 50.
[0055] After etching part of the high-k dielectric layer 46, part of the work function metal layer 48 and part of the low-resistance metal layer 50 in the non-planar area 104, no grooves are generated between the high-k dielectric layer 46 and the low-resistance metal layer 50. Therefore, the top surface of the remaining work function metal layer 48 is lower than the top surface of the low-resistance metal layer 50, and the top surface of the work function metal layer 48 is better aligned with the top surface of the high-k dielectric layer 46.
[0056] Taking the gate structure 18 in the planar region 102 as an example, the etching process for removing part of the high-k dielectric layer 46, part of the work function metal layer 48, and part of the low-resistance metal layer 50 in this stage is preferably performed by selecting etching gases such as chlorine (Cl2) and / or boron trichloride (BCl3) without forming any patterned mask and removing the most work function metal layer 48, the second most high-k dielectric layer 46, and the least low-resistance metal layer 50 without consuming the sides such as the spacers 28, so that the three are formed into three different heights, wherein the top surface of the remaining work function metal layer 48 is preferably slightly lower than the top surface of the remaining high-k dielectric layer 46, and the top surface of the remaining high-k dielectric layer 46 is slightly lower than the top surface 50 of the remaining low-resistance metal layer.
[0057] like Figure 3As shown, a buffer layer 38 is then formed to seal the grooves 56 on both sides of the low-resistance metal layer 50, thereby forming an air hole 40 on one side of the low-resistance metal layer 50 (as shown on the left), and another air hole 40 on the other side of the low-resistance metal layer 50 (as shown on the right). It should be noted that since there is a height difference between the high-k dielectric layer 46 and the work function metal layer 48 in the planar region 102, but there is no height difference between the high-k dielectric layer 46 and the work function metal layer 48 in the non-planar region 104, after the buffer layer 38 is covered on the interlayer dielectric layer 34 and the gate structures 18 and 20 in the planar region 102 and the non-planar region 104, the air hole 40 is only formed in the original groove 56 in the planar region 102, while the buffer layer 38 in the non-planar region 104 is directly disposed on the surface of the high-k dielectric layer 46 and the work function metal layer 48. In this embodiment, the buffer layer 38 preferably comprises silicon nitride, and its thickness is preferably between 90 and 110 angstroms, or most preferably about 100 angstroms.
[0058] like Figure 4 As shown, a hard mask 42 is then formed on the buffer layer 38 in the planar region 102 and the non-planar region 104. In this embodiment, the hard mask 42 may comprise the same material as or a different material from the buffer layer 38. The hard mask 42 preferably comprises silicon nitride and has a thickness preferably between 800 and 1000 angstroms, or most preferably about 920 angstroms. However, in other embodiments, the hard mask 42 may be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride.
[0059] like Figure 5 As shown, a planarization process may then be performed, such as using CMP to remove a portion of the hard mask 42 so that the top surface of the hard mask 42 is flush with the top surface of the interlayer dielectric layer 34 on both sides. A contact plug formation process may then be performed to form contact plugs 60 that are electrically connected to the source / drain regions 30 adjacent to the gate structures 18 and 20, respectively. In this embodiment, the contact plugs 60 may be formed by first removing a portion of the interlayer dielectric layer 34 to form contact holes (not shown), and then sequentially depositing a barrier layer (not shown) and a metal layer (not shown) on the substrate 12 to fill the contact holes. A planarization process, such as CMP, is then performed to remove a portion of the metal layer, a portion of the barrier layer, and even a portion of the interlayer dielectric layer 34 to form the contact plugs 60 in the contact holes. The top surface of the contact plugs 60 is preferably flush with the top surface of the interlayer dielectric layer 34. In this embodiment, the barrier layer is preferably selected from the group consisting of titanium, tantalum, titanium nitride, tantalum nitride, and tungsten nitride, and the metal layer is preferably selected from the group consisting of aluminum, titanium, tantalum, tungsten, niobium, molybdenum, and copper.
[0060] It should be noted that, in this embodiment, after depositing the barrier layer and the metal layer in the contact hole, a metal silicide process may be simultaneously performed according to process requirements. For example, a thermal annealing process may be performed to allow a portion of the barrier layer to react with the substrate to form a metal silicide layer 62 between the substrate 12 and the contact plug 60. A back-end metal interconnect fabrication process may then be performed according to process requirements. For example, an inter-metal dielectric (IMD) layer (not shown) may be first formed on the interlayer dielectric layer 34. A photolithography and etching process may be performed to remove a portion of the IMD layer and expose the contact plug 60 to form a contact hole (not shown). The contact hole is then filled with metal or a conductive material and planarized to form a metal interconnect consisting of a contact hole conductor and a trench conductor. A stop layer may then be formed on the metal interconnect. In this embodiment, the intermetallic dielectric layer preferably comprises silicon oxide or an ultra-low-k dielectric layer, such as a porous dielectric material, for example, but not limited to, silicon oxycarbide (SiOC) or silicon oxycarbide hydrogen (SiOCH). The metal interconnect preferably comprises copper, and the stop layer comprises, but is not limited to, nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN). This completes the fabrication of a semiconductor device according to one embodiment of the present invention.
[0061] Please refer to Figure 5 , Figure 5 The following also discloses a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. Figure 5 As shown, the semiconductor element in the planar region 102 mainly includes a metal gate 52 disposed on the substrate 12, a spacer 28 surrounding the metal gate 52, an interlayer dielectric layer 34 surrounding the metal gate 52, an air hole 40 disposed on one side of the metal gate 52 such as the left side and disposed between the spacer 28 and the metal gate 52, another air hole 40 disposed on the other side of the metal gate 52 such as the right side and disposed between the spacer 28 and the metal gate 52, a buffer layer 38 disposed on the air hole 40 and the metal gate 52 and a hard mask 42 disposed on the buffer layer 38, wherein the metal gate 52 includes a high dielectric constant dielectric layer 46 disposed on the substrate 12, a work function metal layer 48 disposed on the high dielectric constant dielectric layer 46 and a low resistance metal layer 50 disposed on the work function metal layer 48.
[0062] From a detailed perspective, the top surface of the work function metal layer 48 is preferably lower than the top surface of the high dielectric constant dielectric layer 46 and the top surface of the low impedance metal layer 50, and the top surface of the high dielectric constant dielectric layer 46 is lower than the top surface of the low impedance metal layer 50. Each pore 40 is arranged between the high dielectric constant dielectric layer 46 and the low impedance metal layer 50, or more specifically, is surrounded by the high dielectric constant dielectric layer 46, the work function metal layer 48, the low impedance metal layer 50 and the buffer layer 38. Although the top surface of each pore 40 is roughly aligned with the top surface of the low impedance metal layer 50, it can be slightly higher or slightly lower than the top surface of the low impedance metal layer 50 or even slightly lower than the top surface of the high dielectric constant dielectric layer 46 according to product requirements. These variations are all within the scope of the present invention.
[0063] In summary, the present invention primarily discloses a semiconductor device comprising planar and non-planar transistors for use in a display driver integrated circuit (DDIC). The semiconductor device is fabricated by first forming a metal gate on a substrate and surrounding the metal gate with an interlayer dielectric layer. A portion of the high-k dielectric layer, a portion of the work function metal layer, and a portion of the low-resistance metal layer in the metal gate are then removed. Different selectivity ratios are then used to create a height difference between the remaining high-k dielectric layer, the work function metal layer, and a portion of the low-resistance metal layer. Grooves are then formed on both sides of the low-resistance metal layer. A buffer layer is then formed on the metal gate to seal the grooves and form pores. According to a preferred embodiment of the present invention, the pores formed within the planar metal gate can help reduce the gate-source capacitance (Cgs) and the gate-drain capacitance (Cgd), thereby improving the overall slew rate of the display driver integrated circuit.
[0064] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.
Claims
1. A method for manufacturing a semiconductor device, characterized in that: Include: forming a metal gate on the substrate and an interlayer dielectric layer surrounding the metal gate; removing a portion of the metal gate to form a first groove; and A buffer layer is formed on the metal gate and the first groove is sealed to form a first air hole.
2. The method of claim 1, further comprising: forming a gate structure on the substrate; forming the interlayer dielectric layer to surround the gate structure; Converting the gate structure into the metal gate, wherein the metal gate comprises a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer; Removing the low-resistance metal layer, the work function metal layer, and the high-k dielectric layer to form the first groove on one side of the low-resistance metal layer and the second groove on the other side of the low-resistance metal layer; forming the buffer layer to seal the first groove and the second groove to form the first air hole and the second air hole; and A hard mask is formed on the buffer layer. 3 . The method of claim 2 , wherein a top surface of the work function metal layer is lower than a top surface of the high-k dielectric layer. The method according to claim 2 , wherein a top surface of the work function metal layer is lower than a top surface of the low resistance metal layer. The method of claim 2 , wherein a top surface of the high-k dielectric layer is lower than a top surface of the low-resistance metal layer. 6 . The method of claim 2 , wherein the first air hole is disposed between the high-k dielectric layer and the low-resistance metal layer. 7 . The method of claim 2 , wherein the second air hole is disposed between the high-k dielectric layer and the low-resistance metal layer.
8. A semiconductor device, characterized in that: Include: A metal gate is provided on the substrate; A spacer is provided beside the metal gate; an interlayer dielectric layer surrounding the metal gate; and The first air hole is arranged on one side of the metal gate and between the spacer and the metal gate.
9. The semiconductor device according to claim 8, further comprising: The second air hole is arranged on the other side of the metal gate and between the spacer and the metal gate.
10. The semiconductor device as claimed in claim 9, wherein the metal gate further comprises: a high-k dielectric layer disposed on the substrate; a work function metal layer disposed on the high-k dielectric layer; and The low-resistance metal layer is disposed on the work function metal layer. The semiconductor device as claimed in claim 10 , wherein a top surface of the work function metal layer is lower than a top surface of the high-k dielectric layer. 12 . The semiconductor device as claimed in claim 10 , wherein a top surface of the work function metal layer is lower than a top surface of the low resistance metal layer. 13 . The semiconductor device as claimed in claim 10 , wherein a top surface of the high-k dielectric layer is lower than a top surface of the low-resistance metal layer.
14. The semiconductor device according to claim 10, further comprising: a buffer layer disposed on the first air hole, the low-resistance metal layer, and the second air hole; and A hard mask is disposed on the buffer layer. 15 . The semiconductor device as claimed in claim 10 , wherein the first air hole is disposed between the high-k dielectric layer and the low-resistance metal layer. 16 . The semiconductor device as claimed in claim 10 , wherein the second air hole is disposed between the high-k dielectric layer and the low-resistance metal layer.