Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device which can be applied to the technical field of semiconductors. The period comprises: a substrate; the first field effect transistor and the second field effect transistor are respectively stacked on the substrate and are in mirror symmetry about a first plane extending in the vertical direction and the first horizontal direction; each of the first field effect transistor and the second field effect transistor comprises a first source / drain part, a channel part and a second source / drain part which are stacked on the substrate in sequence, and gate stacks located on the two opposite sides of the channel part in the first horizontal direction, and the gate stacks comprise a first gate stack and a second gate stack; the first gate stack is located on the side, close to the first plane, of the channel part, the second gate stack is located on the side, away from the first plane, of the channel part, and the second gate stack is at least partially surrounded by the channel part in the first horizontal direction.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a multi-threshold voltage controlled semiconductor device and a manufacturing method thereof. Background Art

[0002] In the manufacturing of complementary metal oxide semiconductors and high-density logic and memory chips at the 2 nm level and smaller, vertical channel semiconductor devices are widely used because they have higher integration freedom in the vertical direction.

[0003] In the process of realizing the concept of the present disclosure, the inventors found that the use of gate metal work function layer thickness control in related art is difficult to apply to vertical channel semiconductor devices. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor device and a method for manufacturing the same.

[0005] One aspect of the present disclosure provides a semiconductor device and a method for manufacturing the same, including:

[0006] A substrate; and a first field effect transistor and a second field effect transistor, respectively stacked on the substrate and mirror-symmetrical about a first plane extending in a vertical direction and a first horizontal direction, wherein the first field effect transistor and the second field effect transistor each include: a first source / drain portion, a channel portion, and a second source / drain portion stacked in sequence on the substrate, and a gate stack located on opposite sides of the channel portion in the first horizontal direction, the gate stack including a first gate stack and a second gate stack, the first gate stack being located on a side of the channel portion close to the first plane, the second gate stack being located on a side of the channel portion away from the first plane, and the second gate stack being at least partially surrounded by the channel portion in the first horizontal direction.

[0007] According to an embodiment of the present disclosure, the channel portion includes a first portion located between the first gate stack and the second gate stack, a second portion located between the second gate stack and the first source / drain portion, and a third portion located between the second gate stack and the second source / drain portion.

[0008] According to an embodiment of the present disclosure, the first portion of the channel portion extends in a vertical direction, and the second portion and the third portion extend in a second horizontal direction intersecting the first horizontal direction.

[0009] According to an embodiment of the present disclosure, the channel portions of the first field effect transistor and the second field effect transistor are U-shaped, and the openings thereof are opposite or inversely spaced.

[0010] According to an embodiment of the present disclosure, ends of the second portion and the third portion of the channel portion in the first horizontal direction are vertically aligned with sidewalls of the second gate stack in the first horizontal direction.

[0011] According to an embodiment of the present disclosure, the first gate stacks of the first field effect transistor and the second field effect transistor are opposite to each other, or the second gate stacks are opposite to each other.

[0012] According to an embodiment of the present disclosure, multi-threshold voltage control of a semiconductor device is achieved when different operating voltages are applied to the first gate stack and the second gate stack.

[0013] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising:

[0014] A first film layer and a core shaft are formed on the substrate in sequence, wherein the first film layer includes a first source / drain layer, a sacrificial gate on the first source / drain layer, and a second source / drain layer on the sacrificial gate, the core shaft includes a first sacrificial layer and an insulating layer located on the first sacrificial layer, and the core shaft is recessed inward relative to the first film layer in a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; a second sacrificial layer and a third sacrificial layer are formed on the upper surface of the first film layer and the outer surface of the core shaft, wherein the third sacrificial layer is recessed inward relative to the second sacrificial layer in a first horizontal direction and a second horizontal direction; the second sacrificial layer and the first film layer are vertically etched until the etched first film layer, the etched second sacrificial layer and the third sacrificial layer are aligned in the vertical direction; the sacrificial gate is horizontally etched so that the etched sacrificial gate is recessed inward relative to the first source / drain layer and the second source / drain layer in a first horizontal direction and a second horizontal direction; the periphery of the first film layer, the periphery of the second sacrificial layer and the periphery of the third sacrificial layer are sequentially Form a channel layer and an isolation layer; grind the upper surface of the isolation layer, the upper surface of the channel layer, and the upper surface of the insulating layer until the upper surface of the first sacrificial layer is exposed; remove the first sacrificial layer and etch the first film layer to form a groove between the isolation layer and the upper surface of the substrate, and the groove is aligned with the first sacrificial layer in the vertical direction; remove the isolation layer to expose the channel layer, and deposit a gate stack on the outside of the channel layer, on the upper surface of the second source / drain layer, and in the groove; remove part of the gate stack, and only retain an outer gate stack between the first source / drain layer and the second source / drain layer on a side away from the groove relative to the channel layer and an inner gate stack on a side close to the groove relative to the channel layer to obtain a ring-shaped double-gate device; etch away both ends of the ring-shaped double-gate device to obtain a first field-effect transistor and a second field-effect transistor, wherein the inner gate stack after etching is used as the first gate stack of the first field-effect transistor and the second field-effect transistor, and the outer gate stack after etching is used as the second gate stack of the first field-effect transistor and the second field-effect transistor.

[0015] According to an embodiment of the present disclosure, a first film layer and a core shaft are sequentially formed on a substrate, including: forming a first film layer and a second film layer stacked on the first film layer on the substrate, wherein the second film layer includes a first sacrificial layer and an insulating layer located on the first sacrificial layer; and vertically etching the second film layer to obtain the core shaft.

[0016] According to an embodiment of the present disclosure, the insulating layer is made of the same material as the second and third sacrificial layers and different from the first sacrificial layer, so that the etching rate of the insulating layer is greater than that of the first sacrificial layer.

[0017] According to an embodiment of the present disclosure, the two first field effect transistors and the second field effect transistors on the substrate that are mirror-symmetrical about the first plane both include two first gate stacks and a second gate stack separated by a channel portion, so that multi-threshold voltage control of the semiconductor device can be achieved by adjusting the respective operating voltages of the first gate stack and the second gate stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0019] Figure 1A A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0020] Figure 1B A perspective view of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0021] Figure 2 The flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0022] Figures 3 to 18 Schematically shows Figure 2 A cross-sectional view of the structure obtained after executing part of the process in the method shown. DETAILED DESCRIPTION

[0023] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0024] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0025] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0026] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and for the purpose of clarity, certain details are magnified and certain details may be omitted. The shapes of the various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.

[0027] In the process of realizing the inventive concept of the present disclosure, the inventors discovered that vertical channel semiconductor devices can increase the design space of the gate and source / drain, thereby reducing the area occupied by the device. It is relatively easy to achieve vertical stacking between multi-layer devices and further increase the integration density through corresponding design wiring methods, thus having more integration freedom in the vertical direction.

[0028] Multi-threshold voltage (Multi-VT) control of semiconductor devices is a key technology for achieving high-performance, low-power circuits. Therefore, Multi-threshold technology offers certain advantages for complementary metal oxide semiconductors (CMOS) and high-density logic and memory chips. However, for vertical channel devices, the gate metal work function layer thickness control techniques employed in related technologies are difficult to adapt to the three-dimensional structure of the vertical channel and the diverse channel materials.

[0029] In view of this, an embodiment of the present disclosure provides a semiconductor device, including:

[0030] A substrate; and a first field effect transistor and a second field effect transistor, respectively stacked on the substrate and mirror-symmetrical about a first plane extending in a vertical direction and a first horizontal direction, wherein the first field effect transistor and the second field effect transistor each include: a first source / drain portion, a channel portion, and a second source / drain portion stacked in sequence on the substrate, and a gate stack located on opposite sides of the channel portion in the first horizontal direction, the gate stack including a first gate stack and a second gate stack, the first gate stack being located on a side of the channel portion close to the first plane, the second gate stack being located on a side of the channel portion away from the first plane, and the second gate stack being at least partially surrounded by the channel portion in the first horizontal direction.

[0031] Figure 1A A cross-sectional view of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0032] Figure 1B A perspective view of a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0033] like Figure 1A and Figure 1B As shown, the semiconductor device includes a substrate 110 and a first field effect transistor 120 and a second field effect transistor 130 located on the substrate 110. The first field effect transistor 120 and the second field effect transistor 130 are connected in a vertical direction ( Figure 1A y direction in the first horizontal direction ( Figure 1A The first plane extending in the z direction in the horizontal direction ( ) is mirror-symmetrical. The first field effect transistor 120 and the second field effect transistor 130 each include: a first source / drain portion 121, a channel portion 122, and a second source / drain portion 123 stacked in sequence on the substrate 110, and a first source / drain portion 121 located in the first horizontal direction ( Figure 1A The gate stacks are arranged on opposite sides of the channel portion 122 (in the z direction), and the gate stacks include a first gate stack 124 and a second gate stack 125. The first gate stack 124 is located on a side of the channel portion 122 close to the first plane, and the second gate stack 125 is located on a side of the channel portion 122 away from the first plane. The second gate stack 125 is at least partially surrounded by the channel portion 122 in the first horizontal direction.

[0034] According to embodiments of the present disclosure, the substrate 110 may comprise bulk silicon (Bulk-Si) or silicon-on-insulator (SOI), without limitation herein. The substrate also includes shallow trench isolation (STI) (not shown) to define the active area of ​​the current device, thereby isolating adjacent devices. The STI may comprise an oxide (e.g., silicon oxide). In addition to STI, a LOCOS (local oxidation of silicon) process may also be employed, without limitation herein. The first gate stack 124 and the second gate stack 125 each include a gate metal layer and a gate dielectric layer.

[0035] According to an embodiment of the present disclosure, the channel portion 122 includes one of the following: single crystal silicon, SiGe (silicon germanium), III-V material, and oxide.

[0036] According to an embodiment of the present disclosure, the channel portion 122 includes a first portion located between the first gate stack 124 and the second gate stack 125, a second portion located between the second gate stack 124 and the first source / drain portion 121, and a third portion located between the second gate stack 124 and the second source / drain portion 123. The first portion of the channel portion 122 extends in a vertical direction, and the second and third portions extend in a second horizontal direction that intersects the first horizontal direction. The channel portions 122 of the first field-effect transistor 120 and the second field-effect transistor 130 are each U-shaped, with their openings facing each other or in opposite directions. The ends of the second and third portions of the channel portion 122 in the first horizontal direction are vertically aligned with the sidewalls of the second gate stack 124 in the first horizontal direction. The first gate stacks 124 of the first field-effect transistor 120 and the second field-effect transistor 130 are each facing each other, or the second gate stacks 125 of the first field-effect transistor 120 and the second field-effect transistor 130 are each facing each other.

[0037] According to an embodiment of the present disclosure, when different operating voltages are applied to the first gate stack and the second gate stack, multi-threshold voltage regulation of the semiconductor device is achieved. According to an embodiment of the present disclosure, the two first field effect transistors and the second field effect transistor on the substrate that are mirror-symmetrical about the first plane each include two first gate stacks and second gate stacks separated by a channel portion, so that multi-threshold voltage regulation of the semiconductor device can be achieved by adjusting the respective operating voltages of the first gate stack and the second gate stack. The channel areas and lengths controlled by the first gate stack and the second gate stack are different, so that more comprehensive and multi-directional voltage regulation of the device can be achieved. In addition, the gate in one of the gate stacks can be set as a back gate, so that back gate regulation of the device can be achieved and the threshold voltage can be controlled.

[0038] Figure 2 The flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure is schematically shown.

[0039] Figures 3 to 18 Schematically shows Figure 2 A cross-sectional view of the structure obtained after executing part of the process in the method shown.

[0040] like Figure 2 As shown, the method includes operations S201 to S210.

[0041] In operation S201 , a first film layer and a mandrel are sequentially formed on a substrate.

[0042] like Figure 3~Figure 4As shown, an epitaxial process can be used to form a first film layer 320 and a second film layer 330 stacked on the first film layer 320 on the substrate 310, wherein the first film layer 320 includes a first source / drain layer 321, a sacrificial gate 322 on the first source / drain layer 321, and a second source / drain layer 323 on the sacrificial gate 322, and the second film layer 330 can be a Si / GeSi / Si stack, and the second film layer 330 includes a first sacrificial layer 331 and an insulating layer 332 located on the first sacrificial layer 331.

[0043] like Figure 5 As shown, the second film layer 330 is vertically etched, so that the etched second film layer 330 is recessed inward relative to the first film layer 320 in both a first horizontal direction and a second horizontal direction intersecting the first horizontal direction, thereby forming a mandrel 330'. For convenience, a hard mask structure that may be used in the patterning process is not shown in the figure.

[0044] In operation S202 , a second sacrificial layer and a third sacrificial layer are formed on an upper surface of the first film layer and an outer surface of the mandrel.

[0045] like Figure 6 As shown, a second sacrificial layer 340 and a third sacrificial layer 350 are deposited on the upper surface of the first film layer 320 and the outer surface of the core shaft 330'. The materials of the second sacrificial layer 340 and the third sacrificial layer 350 can both be silicon dioxide, and the third sacrificial layer 350 is recessed inward relative to the second sacrificial layer 340 in both the first horizontal direction and the second horizontal direction.

[0046] In operation S203 , the second sacrificial layer and the first film layer are vertically etched until the etched first film layer, the etched second sacrificial layer, and the third sacrificial layer are aligned in a vertical direction.

[0047] like Figure 7 As shown, a dry etching process can be used to vertically etch the second sacrificial layer 340 and the first film layer 320 until the etched first film layer 320, the etched second sacrificial layer 340, and the third sacrificial layer 350 are vertically aligned. The insulating layer 332 is made of the same material as the second sacrificial layer 340 and the third sacrificial layer 350, but different from the material of the first sacrificial layer 331, so that the etching rate of the insulating layer 332 is greater than that of the first sacrificial layer 331.

[0048] In operation S204 , the sacrificial gate is horizontally etched so that the etched sacrificial gate is recessed inward relative to the first source / drain layer and the second source / drain layer in both the first horizontal direction and the second horizontal direction.

[0049] like Figure 8As shown, the sacrificial gate 322 is horizontally etched. After etching, the sacrificial gate 322 is recessed inward relative to the first source / drain layer 321 and the second source / drain layer 323 in both the first horizontal direction and the second horizontal direction.

[0050] In operation S205 , a channel layer and an isolation layer are sequentially formed on the periphery of the first film layer, the periphery of the second sacrificial layer, and the periphery of the third sacrificial layer.

[0051] like Figure 9 and Figure 10 As shown, a channel layer 360 is deposited on the periphery of the previously obtained structure, and an isolation layer 370 is deposited on the channel layer 360 .

[0052] According to an embodiment of the present disclosure, when Si or SiGe or III-V material is selected as the channel layer 360, it can be formed by an epitaxial process; when oxide is selected as the channel layer 360, it can be formed by atomic layer deposition or physical vapor deposition.

[0053] In operation S206 , the upper surface of the isolation layer, the upper surface of the channel layer, and the upper surface of the insulating layer are polished until the upper surface of the first sacrificial layer is exposed.

[0054] like Figure 11 As shown, chemical mechanical polishing process can be used to Figure 10 The structure shown is ground from top to bottom until the upper surface of the first sacrificial layer 331 is exposed.

[0055] In operation S207 , the first sacrificial layer is removed and the first film layer is etched to form a groove between the isolation layer and the upper surface of the substrate, and the groove is aligned with the first sacrificial layer in a vertical direction.

[0056] like Figure 12 As shown, the first sacrificial layer 331 is removed, and the first film layer 320 is etched according to the shape of the first sacrificial layer 331, so that a groove is formed between the isolation layer 370 and the upper surface of the substrate.

[0057] In operation S208 , the isolation layer is removed to expose the channel layer, and a gate stack is deposited outside the channel layer, on the upper surface of the second source / drain layer, and in the groove.

[0058] like Figure 13 As shown, the sacrificial gate 322 is removed, and the channel layer 360 is exposed in the groove.

[0059] like Figure 14 As shown, in Figure 13 An outer isolation layer 390 is deposited on the upper surface of the structure and within the recesses.

[0060] like Figure 15 As shown, chemical mechanical polishing process can be used to Figure 14 The structure shown is ground from top to bottom until the upper surface of the second source / drain layer 323 is exposed.

[0061] like Figure 16 As shown, the isolation layer 370 may be removed by a wet etching process, so that the channel layer 360 is entirely exposed.

[0062] like Figure 17 As shown, a gate stack 380 is deposited outside the channel layer 360 , on the upper surface of the second source / drain layer 323 and in the groove. The gate stack 380 includes a gate dielectric layer 381 and a gate metal layer 382 .

[0063] In operation S209, part of the gate stack is removed, and only the outer gate stack between the first source / drain layer and the second source / drain layer, which is away from the groove relative to the channel layer, and the inner gate stack, which is close to the groove relative to the channel layer, are retained to obtain a ring-shaped dual-gate device.

[0064] like Figure 18 As shown, the gate stack 380 portion is etched away except for the outer gate stack 380 (1) between the first source / drain layer 321 and the second source / drain layer 323 on the side away from the groove relative to the channel layer 360 and the inner gate stack 380 (2) on the side close to the groove relative to the channel layer 360, to obtain a ring-shaped dual-gate device.

[0065] In operation S210 , two ends of the annular dual-gate device are etched away to obtain a first field effect transistor and a second field effect transistor.

[0066] According to an embodiment of the present disclosure, the inner gate stack after etching is used as the first gate stack of the first field effect transistor and the second field effect transistor, the outer gate stack after etching is used as the second gate stack of the first field effect transistor and the second field effect transistor, the first source / drain layer is used as the first source / drain portion of the first field effect transistor and the second field effect transistor, and the second source / drain layer is used as the second source / drain portion of the first field effect transistor and the second field effect transistor.

[0067] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0068] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A semiconductor device comprising: substrate; as well as A first field effect transistor and a second field effect transistor, respectively stacked on the substrate and mirror-symmetrical about a first plane extending in a vertical direction and a first horizontal direction, wherein the first field effect transistor and the second field effect transistor each include: A first source / drain portion, a channel portion, and a second source / drain portion are sequentially stacked on the substrate, and a gate stack is located on opposite sides of the channel portion in the first horizontal direction, the gate stack includes a first gate stack and a second gate stack, the first gate stack is located on a side of the channel portion close to the first plane, the second gate stack is located on a side of the channel portion away from the first plane, and the second gate stack is at least partially surrounded by the channel portion in the first horizontal direction.

2. The device according to claim 1, wherein The channel portion includes a first portion located between the first gate stack and the second gate stack, a second portion located between the second gate stack and the first source / drain portion, and a third portion located between the second gate stack and the second source / drain portion.

3. The device according to claim 1, wherein The first portion of the channel portion extends along the vertical direction, and the second portion and the third portion extend along a second horizontal direction intersecting the first horizontal direction.

4. The device according to claim 1, wherein The channel portions of the first field effect transistor and the second field effect transistor are U-shaped, and their openings are opposite or in opposite directions.

5. The device according to claim 1, wherein Ends of the second portion and the third portion of the channel portion in the first horizontal direction are vertically aligned with sidewalls of the second gate stack in the first horizontal direction.

6. The device according to claim 1, wherein The first gate stacks of the first field effect transistor and the second field effect transistor are opposite to each other or the second gate stacks are opposite to each other.

7. The device according to claim 1, wherein When different operating voltages are applied to the first gate stack and the second gate stack, multi-threshold voltage control of the semiconductor device is achieved.

8. A method for manufacturing a semiconductor device, comprising: A first film layer and a mandrel are sequentially formed on a substrate, wherein the first film layer includes a first source / drain layer, a sacrificial gate on the first source / drain layer, and a second source / drain layer on the sacrificial gate; the mandrel includes the first sacrificial layer and an insulating layer located on the first sacrificial layer; and the mandrel is recessed inward relative to the first film layer in both a first horizontal direction and a second horizontal direction intersecting the first horizontal direction; forming a second sacrificial layer and a third sacrificial layer on the upper surface of the first film layer and the outer surface of the mandrel, wherein the third sacrificial layer is recessed inward relative to the second sacrificial layer in both the first horizontal direction and the second horizontal direction; performing vertical etching on the second sacrificial layer and the first film layer until the etched first film layer, the etched second sacrificial layer, and the third sacrificial layer are aligned in a vertical direction; performing horizontal etching on the sacrificial gate so that the etched sacrificial gate is recessed inward relative to the first source / drain layer and the second source / drain layer in both the first horizontal direction and the second horizontal direction; forming a channel layer and an isolation layer in sequence on the periphery of the first film layer, the periphery of the second sacrificial layer and the periphery of the third sacrificial layer; Grinding the upper surface of the isolation layer, the upper surface of the channel layer, and the upper surface of the insulating layer until the upper surface of the first sacrificial layer is exposed; removing the first sacrificial layer and etching the first film layer so as to form a groove between the isolation layer and the upper surface of the substrate, wherein the groove is aligned with the first sacrificial layer in a vertical direction; removing the isolation layer to expose the channel layer, and depositing a gate stack outside the channel layer, on the upper surface of the second source / drain layer, and in the groove; Removing part of the gate stack and retaining only an outer gate stack between the first source / drain layer and the second source / drain layer on a side of the channel layer away from the groove and an inner gate stack on a side of the channel layer close to the groove, to obtain a ring-shaped dual-gate device; Etch away both ends of the annular dual-gate device to obtain a first field effect transistor and a second field effect transistor, wherein the inner gate stack after etching is used as the first gate stack of the first field effect transistor and the second field effect transistor, and the outer gate stack after etching is used as the second gate stack of the first field effect transistor and the second field effect transistor.

9. The method according to claim 7, wherein: The step of sequentially forming a first film layer and a core shaft on a substrate comprises: forming a first film layer and a second film layer stacked on the first film layer on the substrate, wherein the second film layer includes the first sacrificial layer and the insulating layer located on the first sacrificial layer; The second film layer is vertically etched to obtain the core shaft.

10. The method according to claim 8, wherein The insulating layer is made of the same material as the second sacrificial layer and the third sacrificial layer and is different from the first sacrificial layer, so that the insulating layer is etched faster than the first sacrificial layer.

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