Single-wafer integrated high-frequency bridge arm power semiconductor wafer and power conversion module

Abstract

The invention discloses a single chip integrated high-frequency bridge arm power semiconductor chip, which comprises a substrate and a device structure region, and is characterized in that the device structure region comprises a first switch region, a second switch region and a logic circuit region; a DC + electrode, a DC-electrode and an SW electrode are arranged on the power semiconductor wafer; the first switch area and the second switch area comprise long-strip-shaped areas parallel to the long sides and are arranged side by side. On the other hand, the invention further provides a power conversion module which comprises the bridge arm type circuit, and the bridge arm type circuit comprises the outer side decoupling capacitor and the power semiconductor wafer or comprises the outer side decoupling capacitor, the laminated decoupling capacitor and the power semiconductor wafer. According to the invention, the maximum equivalent width of the input loop is reduced, the frequency performance of the wafer is improved, and the sizes of the input loops formed by different device structure units are approximately the same, so that the current sharing performance and reliability during high-frequency work are improved.

Description

Technical Field

[0001] The present invention relates to the field of power converters, and in particular to a single-chip integrated high-frequency bridge arm power semiconductor chip and a power conversion module. Background Art

[0002] With advances in semiconductor technology, the operating voltage of transistors is decreasing. Consequently, the operating voltage of computing chips such as CPUs, GPUs, TPUs, and NPUs (hereinafter collectively referred to as XPUs) is also decreasing. XPUs with the same power draw increasingly higher operating currents, for example, operating currents exceeding 1000 amperes while operating voltages below 1V. Therefore, to accurately control such low voltages at such high currents, the operating frequency of power converters, or VRM modules, is increasing.

[0003] Therefore, DrMOS (also known as SPS, Switch Power Supply), a key component of the VRM module, needs to complete high current conversion at high frequency.

[0004] The circuit of the VRM module is usually a Buck circuit, such as Figure 1A As shown. Including input decoupling capacitor C bus , upper switch QH, lower switch QL, inductor L, and output capacitor Co. QH and QL form the (high-frequency) bridge arm circuit. Operating at a frequency of f, it converts the input voltage Vin into the output voltage Vo to power the XPU.

[0005] An input circuit includes an input decoupling capacitor C bus Compared with the upper switch QH and the lower switch QL, since the upper switch QH and the lower switch QL are working at high frequency, the input loop inductance L loop At high frequencies, V = L loop *di / dt and voltage overshoot, affecting efficiency, reliability and electromagnetic interference. Therefore, the input loop inductance L loop Determines the performance of the VRM module at high frequencies. Input loop inductance L loop The smaller it is, the higher the operating frequency can be.

[0006] In order to make the input circuit inductance L loop As small as possible, DrMOS increasingly adopts monolithic technology, that is, the high-frequency bridge arm circuit is integrated into a single chip to minimize the distance between the upper switch QH and the lower switch QL, thereby reducing the input loop inductance L loop The single chip contains QH, QL and a logic circuit area Logical consisting of drivers and even current sampling and temperature sampling.

[0007] The traditional single chip solution layout is usually as follows Figure 1BAs shown, the lower switch QL, the upper switch QH, and the logic circuit area Logical each occupy an area, and the areas are arranged in parallel. The input decoupling capacitor C bus It is set on the side corresponding to the arrangement direction to facilitate electrical connection with the upper switch QH and the lower switch QL respectively, which is very simple and practical. However, since the lower switch QL and the upper switch QH are concentrated in the corresponding area, the area of ​​the area is larger than the area of ​​a single switch structure unit, so the input decoupling capacitor C bus The input loop area formed by the lower switch QL and the upper switch QH is relatively large, and the frequency is relatively limited and difficult to be higher than 1MHz. Figure 1C As shown, the area occupied by QL and the area occupied by QH are divided into three groups of smaller areas (for the purpose of conveniently showing the high-frequency bridge arm grouping, Figure 1C The central axis of some small areas is shown in Figure 1C The adjacent areas marked as QH are a whole area, and the adjacent areas marked as QL are also a whole area). In this way, the input loop area of ​​the switches in each of the two adjacent areas is greatly reduced, and further reduced by connecting the circuits in parallel between the areas. The applicable frequency is greatly improved, and the operating frequency can be easily increased to 1MH. Z Even 3MH Z However, this solution requires that the chip be divided into many areas, resulting in many high and low voltage boundary lines on the chip and low chip utilization. On the other hand, Figure 1D As shown, in actual use, in order to make the loop area as small as possible, the input decoupling capacitor C bus Placed on both sides of the DrMOS chip, the actual equivalent loop inductance can be as low as 100pH or even lower, compared to traditional Figure 1B The corresponding solution is about 500pH, and the frequency characteristics can be improved several times, so it is particularly suitable for high-frequency work above 2MHz. However, due to the input decoupling capacitor C bus It is set on the outside of the chip along the partition arrangement direction, that is, perpendicular to the boundary line of the area corresponding to the upper switch QH and the lower switch QL. Therefore, the upper switch QH and the lower switch QL closer to the edge are closer to the input decoupling capacitor C bus The input loop area formed is small, while the input loop area formed by the corresponding device far away from the edge is larger, that is, the input loop area of ​​each high-frequency bridge arm circuit and the input decoupling capacitor C busInconsistent distances between the two arms result in different input loop inductances, leading to uneven current distribution during high-frequency switching, which affects switching losses. Furthermore, if different regions of the chip cannot operate synchronously, this can also cause reliability issues, which is the most important factor in DrMOS. Furthermore, if the width of the short side of the chip is reduced to ensure that the current in each high-frequency bridge arm circuit is as uniform as possible, the chip aspect ratio will become larger while maintaining the same power area size, affecting the yield rate.

[0008] Therefore, how to improve the chip structure to reduce the input loop inductance while improving the current sharing performance and reliability under high-frequency working conditions and optimizing the chip aspect ratio while maintaining the same power area is an urgent problem to be solved. Summary of the Invention

[0009] The purpose of the present invention is to provide a single-chip integrated high-frequency bridge arm power semiconductor chip and a power conversion module using the same, wherein the switch area is set to be mainly composed of long strip areas and the direction of their parallel arrangement is set to be perpendicular to the array arrangement direction of external input decoupling capacitors. On the one hand, the input loop inductance is reduced, and on the other hand, the current sharing performance and reliability under high-frequency working conditions are improved, the aspect ratio of the chip is optimized, and the chip is suitable for higher operating frequencies.

[0010] To achieve the above objectives, the present invention provides: 1. A single-chip integrated high-frequency bridge arm power semiconductor chip, characterized by comprising a substrate and a device structure region, wherein the device structure region is disposed on a surface of the substrate; the device structure region includes a first switch region, a second switch region, and a logic circuit region; the logic circuit region provides drive signals to the first switch and the second switch;

[0011] The first switch region is used to set a first switch, and the second switch region is used to set a second switch, and the first switch and the second switch are connected in series to form a high-frequency bridge arm; a DC+ electrode, a DC- electrode, and a SW electrode are provided on the power semiconductor chip, and the DC+ electrode and the DC- electrode are electrically connected to the two ends of the high-frequency bridge arm respectively, and the SW electrode is electrically connected to the midpoint end of the high-frequency bridge arm;

[0012] The device structure area has a long side and a short side, and the length of the long side is greater than the length of the short side; at least a portion of the first switch area is a first long strip area parallel to the long side, and at least a portion of the second switch area is a second long strip area parallel to the long side, and the first long strip area and the second long strip area are arranged side by side in a direction perpendicular to the long side.

[0013] Preferably, the device structure region is a long strip region, and the device structure region only includes a first long strip region and a second long strip region, and the first long strip region and the second long strip region are adjacent to and parallel to each other.

[0014] Preferably, the logic circuit area is adjacent to a short side or a long side of the power semiconductor region.

[0015] Preferably, at least one of the long sides is used to set a decoupling capacitor, the decoupling capacitor is set along the long side, the decoupling capacitor is set outside the device structure area, and the decoupling capacitor is connected in parallel with the high-frequency bridge arm.

[0016] Preferably, the second switching area surrounds at least three sides of the first switching area.

[0017] Preferably, the second switch area completely surrounds the first switch area.

[0018] Preferably, the logic circuit area is arranged at a central axis of the device structure area parallel to the long side.

[0019] Preferably, the second switch area is C-shaped, the first switch area is in a lying T-shape, the second switch area partially surrounds the first switch area, and the first switch area and the second switch area are complementary.

[0020] Preferably, the first switch area and the second switch area are both C-shaped; the C-shape located inside at least partially surrounds the logic circuit area; and the C-shape located outside surrounds at least three sides of the inner C-shape.

[0021] Preferably, the logic circuit area is in a lying T-shape.

[0022] Preferably, the first switch area is C-shaped, the second switch area completely surrounds the first switch area, and the first switch area and the second switch area are combined to form a C-shaped power area; the C-shaped power area surrounds at least three sides of the logic circuit area.

[0023] Preferably, the first switch area is C-shaped; the second switch area partially surrounds the first switch area, and the first switch area and the second switch area are combined to form a C-shaped power area; a part of the left edge of the C-shaped power area is the first switch area; the C-shaped power area surrounds at least three sides of the logic circuit area.

[0024] Preferably, the logic circuit area includes a third long strip area parallel to the long side, and the third long strip area is arranged at the central axis of the device structure area parallel to the long side.

[0025] Preferably, the central axis passes through the logic circuit area.

[0026] Preferably, the first switch area and the second switch area form a power area, and the power area surrounds at least three sides of the logic circuit area.

[0027] Preferably, the power area surrounds the entire logic circuit area.

[0028] Preferably, the logic circuit area divides the device structure area into a first switch area group and a second switch area group, and the first switch area group and the second switch area group are respectively arranged on opposite sides of the logic circuit area; and the first switch area group and the second switch area group are symmetrical along the central axis; the first switch area and the second switch area are respectively arranged in the first switch area group and in the second switch area group.

[0029] Preferably, the switch areas arranged on both sides of the logic circuit area are in the shape of long strips, and the long sides of each long strip are parallel to each other.

[0030] Preferably, the device structure area further includes a driving area, and the driving area is in the shape of a long strip parallel to the long side; the driving area is arranged between each adjacent two of the logic area, the first switch area and the second switch area.

[0031] Preferably, only one of the switch areas arranged on both sides of the logic circuit area is in a strip shape.

[0032] Preferably, the second switching area surrounds at least three sides of the first switching area.

[0033] Preferably, the second switch area completely surrounds the first switch area.

[0034] Preferably, the second switch area is C-shaped and the first switch area is strip-shaped; the first switch area is adjacent to the logic circuit area at one long side, and is adjacent to the second switch area at the other long side and both short sides.

[0035] Preferably, the device structure area further includes a driving area, and the driving area is in the shape of a long strip parallel to the long side; each first switching area is adjacent to at least one driving area, and / or each second switching area is adjacent to at least one driving area.

[0036] Preferably, a bus layer is provided above the device structure area, and the bus layer includes a DC+ bus wiring layer, a DC- bus wiring layer and a SW bus wiring layer, and the DC+ electrode, DC- electrode and SW electrode are electrically connected to the high-frequency bridge arm through the corresponding bus wiring layer.

[0037] Preferably, the SW bus wiring layer is arranged across the first switch area and the second switch area; the DC+ bus wiring layer is arranged on the first switch area and the DC- bus wiring layer is arranged on the second switch area, or, the DC+ bus wiring layer is arranged on the second switch area and the DC- bus wiring layer is arranged on the first switch area.

[0038] Preferably, the power semiconductor chip further includes a DC+ bus lead-out component, a DC- bus lead-out component and a SW bus lead-out component, and each of the wiring areas is provided with at least one bus lead-out component; the bus lead-out components are electrically connected to the corresponding wiring areas; and the total cross-sectional area of ​​the SW bus lead-out component is greater than the total cross-sectional area of ​​the DC+ bus lead-out component.

[0039] Preferably, the device structure area includes a first sub-area, the second switch area in the first sub-area surrounds at least three sides of the first switch area; the first sub-area corresponds to the first bus layer, and the DC+ bus wiring layer in the first bus layer semi-surrounds the DC- bus wiring layer and the SW bus wiring layer.

[0040] Preferably, the device structure area includes a second sub-area, the first switch area and the second switch area in the second sub-area are both long strips, and the first switch area is arranged between the second switch areas; the second sub-area corresponds to the second bus layer, the SW bus wiring layer of the second bus layer spans the second switch area, and the length of the SW bus wiring layer in the vertical column direction is greater than 50% of the length of the second sub-area in the vertical column direction; the DC+ bus wiring layer of the second bus layer is arranged between the DC- bus wiring layers.

[0041] Preferably, the DC+ electrodes in two adjacent second bus layers are electrically connected, and the DC- electrodes in two adjacent second bus layers are electrically connected.

[0042] Preferably, the SW bus wiring layer includes two extension sections, and the two extension sections are respectively arranged between the DC+ bus wiring layer and two DC- bus wiring layers.

[0043] Preferably, the device structure area includes a second sub-area, the first switch area and the second switch area in the second sub-area are both long strips, and the first switch area is arranged between the second switch areas; the second sub-area corresponds to the second bus layer, and the second bus layer is arranged in the vertical column direction in the order of DC-bus wiring layer, SW bus wiring layer, DC+bus wiring layer, SW bus wiring layer and DC-bus wiring layer; a bus lead-out piece is respectively provided on each of the DC-bus wiring layer, SW bus wiring layer and DC+bus wiring layer.

[0044] Preferably, the device structure area includes a second sub-area, the first switch area and the second switch area in the second sub-area are both long strips, and the first switch area in the second sub-area is arranged between the second switch area and the logic circuit area; the second sub-area corresponds to the second bus layer, and the planar layout of the second bus layer is arranged in sequence in the vertical column direction in the order of DC- bus wiring layer, SW bus wiring layer and DC+ bus wiring layer; bus lead-out parts are respectively provided on the DC- bus wiring layer, SW bus wiring layer and DC+ bus wiring layer.

[0045] Preferably, the DC- bus wiring layer, the SW bus wiring layer and the DC+ bus wiring layer are all in the shape of long strips; and the bus lead-out members are aligned and arranged along a vertical column direction.

[0046] Preferably, the bus lead-out pieces arranged on the SW bus wiring layer are staggered from the bus lead-out pieces arranged on the DC- bus wiring layer and the DC+ bus wiring layer; the DC- bus wiring layer, the SW bus wiring layer and the DC+ bus wiring layer are respectively arranged to alternately change width along the lateral direction, and are wider at the positions where the bus lead-out pieces are arranged.

[0047] Preferably, the device structure area includes a first sub-area and a second sub-area, the first switch area and the second switch area in the first sub-area are arranged in an enclosed manner; the first switch area and the second switch area in the second sub-area are arranged parallel to each other; the first sub-area is located at the end of the second sub-area; the DC-bus wiring layer, the SW bus wiring layer and the DC+bus wiring layer in the second sub-area are formed as multiple repeating units repeated side by side; the DC-bus wiring layer in the first sub-area is connected to the DC-bus wiring layer in the second sub-area; the SW bus wiring layer in the first sub-area is connected to the SW bus wiring layer in the second sub-area; the DC+bus wiring layer in the first sub-area is connected to the DC+bus wiring layer in the second sub-area.

[0048] Preferably, the device structure area further includes a built-in capacitor area;

[0049] The built-in capacitor region and the first switch region are adjacent to each other along the long side direction, and / or the built-in capacitor region and the second switch region are adjacent to each other along the long side direction;

[0050] The built-in capacitor area is used to set the device area capacitor, and the device area capacitor is connected in parallel with the high-frequency bridge arm.

[0051] Preferably, the device structure area is arranged layer by layer from the inside to the outside in the order of the built-in capacitor area, the first switch area and the second switch area in the plane layout.

[0052] Preferably, the device structure area is arranged in a planar layout in the order of the first switch area, the second switch area and the built-in capacitor area, layer by layer from the inside to the outside.

[0053] Preferably, there are at least two first switch areas and at least two second switch areas respectively, and the device structure areas are arranged in sequence in the vertical column direction in the plane layout in the order of the second switch area, the first switch area, the built-in capacitor area, the first switch area and the second switch area.

[0054] Preferably, at least two second switch areas are provided, and the device structure areas are arranged layer by layer from the inside out in the order of the second switch area, the built-in capacitor area, the first switch area and the second switch area in the plane layout.

[0055] Preferably, the power semiconductor chip further comprises a built-in layer capacitor, which is formed by a dielectric layer embedded in the bus wiring layer; the built-in layer capacitor is connected in parallel with the high-frequency bridge arm.

[0056] Preferably, the bus wiring layer further includes a capacitor connection pad, and the capacitor connection pad is located at a corresponding position of the logic circuit area projected on the bus wiring layer.

[0057] Preferably, the capacitor connection pads are provided in plurality and arranged in an array.

[0058] Preferably, the logic circuit area provides two groups of driving signals with a 180-degree phase shift to the first switch area group and the second switch area group.

[0059] Preferably, the device structure area includes a plurality of switch area groups of equal area, each switch area group includes at least one first switch area and at least one second switch area; the logic circuit area is used to provide at least two groups of mutually staggered drive signals to the switch area groups, and each group of drive signals drives a different switch area group respectively.

[0060] Preferably, the plurality of switch area groups are arranged along the central axis of the device structure area, and are symmetrically arranged on both sides of the central axis of the device structure area.

[0061] Preferably, the first switch area and the second switch area in each of the switch area groups are both in the shape of long strips.

[0062] Preferably, the multiple switch area groups include first to fourth switch area groups, the first switch area group and the third switch area group are located on one side of the central axis of the device structure area, and the second switch area group and the fourth switch area group are located on the other side of the central axis of the device structure area; the logic circuit area is used to provide four groups of drive signals that are sequentially staggered by 90 degrees to the first to fourth switch area groups.

[0063] Preferably, the logic circuit area is located on the central axis of the device structure area, and the multiple switch area groups are symmetrically arranged on opposite sides of the logic circuit area.

[0064] Another aspect of the present invention provides a power conversion module, characterized by comprising a bridge arm circuit;

[0065] The bridge arm circuit includes an outer decoupling capacitor and any one of the aforementioned power semiconductor chips; the outer decoupling capacitor array is arranged outside at least one long side of the power semiconductor chip, and the outer decoupling capacitor is connected in parallel with the high-frequency bridge arm.

[0066] Preferably, the bridge arm circuit further includes a stacked decoupling capacitor; the stacked capacitor is stacked above the power semiconductor chip and its position corresponds to the logic circuit area; the stacked decoupling capacitor is connected in parallel with the high-frequency bridge arm; the stacked decoupling capacitor is a silicon capacitor.

[0067] Compared with the prior art, the present invention has the following beneficial effects:

[0068] 1. The present invention arranges the first and second switch regions, or portions of their long strip-shaped regions, in a direction parallel to the long sides, extending the total length of the intersection between the two as much as possible, thereby reducing the maximum equivalent width of the input loop, reducing the input loop area and the corresponding loop inductance, and improving the frequency performance of the chip;

[0069] 2. The boundary line between the first and second switching zones of the present invention is parallel to the long side of the chip, while the arrangement of the strips is perpendicular to the long side of the chip. This corresponds to the arrangement direction of the high-frequency bridge arm being perpendicular to the array direction of the input decoupling capacitor. As a result, the input loops formed by the different device structural units are of approximately the same size, improving the current sharing performance and reliability during high-frequency operation.

[0070] 3. The present invention improves the synchronization of the switching devices in hard switching operation by setting a driving area adjacent to the switching area; and reduces the bus impedance by setting a bus wiring layer formed by combining multiple sub-areas of a repeated structure;

[0071] 4. The present invention forms multi-band and multi-level input circuit decoupling through a combination of internal and external decoupling capacitors, thereby further improving the frequency performance of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0072] Figures 1A to 1D This is a schematic diagram of the structure of a power semiconductor chip with integrated high-frequency bridge arms in a single chip in the prior art;

[0073] Figures 2A to 2M This is a schematic structural diagram of embodiment 1 of the present invention;

[0074] Figure 3A and Figure 3BThis is a structural diagram of embodiment 2 of the present invention;

[0075] Figures 4A to 4H This is a structural diagram of embodiment 3 of the present invention;

[0076] Figures 5A to 5C This is a structural diagram of a fourth embodiment of the present invention;

[0077] Figures 6A to 6F This is a structural diagram of Embodiment 5 of the present invention;

[0078] Figure 7 This is a structural diagram of embodiment 6 of the present invention. DETAILED DESCRIPTION

[0079] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0080] A common single-chip integrated DrMOS chip size in the prior art is 3.2mm×5mm. At this time, the maximum equivalent width WL of the input loop on the chip is Figure 1D The solution shown is half of the short side width, that is, WL = 0.5 × 3.2 = 1.6 mm; Therefore, in order to better reveal the beneficial effects of the present invention, the following embodiments are mainly based on this specification or the same wafer area (16 mm 2 ) specifications are described above, the solution of the present invention is not limited to this and can also be used for other size specifications.

[0081] Example 1

[0082] like Figure 2A and Figure 2B As shown, the power semiconductor chip of this embodiment includes a substrate 1 and a device structure area 2. The device structure area 2 is arranged on a surface of the substrate 1. The device structure area 2 includes a first switch area, a second switch area and a logic circuit area Logical; the first switch area is used to set a plurality of first switches, and the second switch area is used to set a plurality of second switches. The first switches and the second switches are connected in series to form a plurality of high-frequency bridge arms. Figure 2A The layout of the device structure area 2 is shown. In this embodiment, the first switch corresponds to Figure 1A The upper switch QH in the circuit shown, the second switch corresponds to Figure 1AThe lower switch QL in the circuit shown, therefore the corresponding first switch area is marked with QH, and the second switch area is marked with QL; in some other embodiments, the first switch area can also be used to set the lower switch QL, and the second switch area can be used to set the upper switch QH. The logic circuit area Logical is used to provide drive signals to the first switch and the second switch. In some embodiments, the driver corresponding to the first switch or the second switch can be set in the logic circuit area Logical, and the drive signal forms a drive current through the driver to drive the corresponding switching device. Signal devices with other functions such as temperature sampling devices and current sampling devices can also be provided in the logic circuit area. Those skilled in the art can make corresponding settings as needed. The power semiconductor chip has a long side and a short side. In this embodiment, the length of the long side is 5 mm, and the width of the short side is 3.2 mm.

[0083] The power semiconductor chip is provided with a DC+ electrode, a DC- electrode and a SW electrode. The DC+ electrode and the DC- electrode are electrically connected to the two ends of the high-frequency bridge arm respectively, and the SW electrode is electrically connected to the midpoint end of the high-frequency bridge arm. The circuit topology of this embodiment can be referred to Figure 1A , the upper switch QH and the lower switch QL in the figure are both structures in which multiple device structural units are connected in parallel.

[0084] In this embodiment, the first switch region is arranged in a long strip in the center of the device structure region 2. The logic circuit region, Logical, is adjacent to one end of the first switch region. The second switch region is C-shaped, surrounding (i.e., semi-enclosing) the first switch region on three sides. Specifically, the lower switch QL is arranged outside the upper switch QH. Because the long direction of the long strip of the first switch region is parallel to the long side of the power semiconductor chip, the total length Lj of the intersection between the first and second switch regions in this layout can be set as long as possible. In the device structure region 2, excluding the left and right sides, the middle portion can be considered as the long strip regions corresponding to the lower switch QL, upper switch QH, and lower switch QL, arranged in parallel in a direction perpendicular to the long sides. The intersection of the long strip regions contributes a major portion of the total intersection length Lj. It is not difficult to understand that the power area Sp of a DrMOS single chip is equivalent to the sum of the areas of the first switch area and the second switch area and is limited by the chip area. Since the power area Sp can be regarded as the product of the total length of the junction line Lj and the maximum equivalent width WL of the input loop, that is, Sp = Lj × WL, therefore, when the power area Sp remains unchanged, the longer the total length of the junction line Lj, ​​the shorter the maximum equivalent width WL of the corresponding input loop, and the smaller the corresponding input loop area, the input loop inductance L loop The smaller it is, the higher the applicable frequency is. Under the same 3.2mm×5mm chip size, the maximum equivalent width WL of the input loop of this embodiment is compared with Figure 1DThe solution shown is also 1.6mm, and the applicable frequency can be as high as 2MHZ or even above 3MHZ, which is far better than Figure 1B Moreover, in this embodiment, the number of high-voltage and low-voltage regions is 1 each (for the purpose of conveniently illustrating the high-frequency bridge arm grouping, the first switch region is Figure 2B It is shown in the form of being divided into two; the same is true in other subsequent figures, which will not be repeated). Therefore, in this aspect, it has Figure 1B The same advantages as shown in the scheme are avoided Figure 1D The disadvantage of the large number of partitions in the shown scheme. Figure 2B The cross-sectional view of the power semiconductor wafer of this embodiment is shown. It only needs to dig a high-voltage area (also called high-voltage well) in the device structure area 2 to make the upper switch QH. The process difficulty is relatively low. Figure 1B The scheme shown adds little to the process challenges, resulting in better wafer fabrication yield and reliability.

[0085] On the other hand, it can be seen that the direction of the switch area boundary line corresponds to the direction of repeated arrangement of device structural units with the same circuit function, and the arrangement direction of the switch areas arranged in parallel corresponds to the arrangement direction of the high-frequency bridge arm from one end to the other. Figure 2C As shown, when multiple input decoupling capacitors C bus When placed around the edge of the chip, due to the input decoupling capacitor C bus The array direction is parallel to the boundary line of the switch area, which can make the high-frequency bridge arm formed by the combination of each upper switch QH and lower switch QL relative to the input decoupling capacitor C bus The positional relationship is similar, so the equivalent width of the input loop is more uniform (the input loop is shown in the form of a dotted triangle in the figure. The equivalent width of each input loop corresponds to WL, and the equivalent bottom length is affected by the input decoupling capacitor C bus size restrictions). Figures 1B to 1D In the corresponding solution, due to the decoupling capacitor C bus The array direction is the same as the arrangement direction of the switch area and perpendicular to the direction of the intersection line. Therefore, the equivalent width of the input loop formed by the device structure unit far away from the edge is larger, and the equivalent width of the input loop formed by the device structure unit close to the edge is smaller. Different input loop widths will lead to uneven current in different parts. The current sharing capability of this embodiment is better than Figures 1B to 1D The corresponding solution can therefore achieve better performance at the same frequency, or a higher operating frequency can be set for the same performance. This means that it is easier to achieve synchronous operation of each region during high-frequency switching, greatly improving reliability, reducing switching losses, and increasing efficiency. The operating frequency of this embodiment can be higher than 2MHz or even higher than 3MHz.

[0086] In some other embodiments, under the concept that the switching area is formed by a long strip area parallel to the long side as much as possible and the high-frequency bridge arms are arranged side by side through the long strip areas to be perpendicular to the corresponding edges of the chip, the device structure area of ​​the chip can also have other layout forms to be suitable for more application scenarios.

[0087] In a preferred embodiment, if Figure 2C As shown, the second switch area is a long strip with an internal opening, and the first switch area is a long strip surrounded by the second switch area on all four sides (i.e., fully surrounded). The long sides of the first and second switch areas are parallel to the long sides of the chip. Generally speaking, the total area of ​​the upper switch QH is set to be smaller than the total area of ​​the lower switch QL, making it more suitable to be placed in the outer circle. In the fully surrounded solution, the logic circuit area Logical is adjacent to more device structural units corresponding to the lower switch QL, which makes it easier to implement functions such as current sampling. Because current sampling is generally performed by sampling the device structural units corresponding to the lower switch QL and then calculating using the mirror current source method. In this embodiment, the maximum equivalent width WL of the input loop is also close to 1.6mm, and the frequency characteristics are comparable.

[0088] It should be noted that the long strip mentioned in the present invention does not necessarily have to be a strict rectangle. It means that the length of one axis of the figure is greater than 1.1 times the length of the axis in the other direction to be a long strip referred to in the present invention, and preferably greater than 1.5 times. Similar shapes with different edges, such as runway shapes, ovals, and gourd shapes, can all be considered long strips. The parallel relationship between the direction of the long strip and the long side can also be defined accordingly: the center line of the long direction of the long strip is a straight line or a curve composed of multiple nearly straight lines. The fitted straight line of the center line is parallel to the long side of the wafer.

[0089] In a preferred embodiment, if Figure 2D As shown, the second switch area is C-shaped, with the C-shaped opening parallel to the long side of the chip, and the first switch area is a lying T-shaped, and the shapes of the first switch area and the second switch area are complementary; the advantage of this is that the frequency characteristics corresponding to the maximum equivalent width WL of the input loop are retained, which is close to 1.6mm. However, since the first switch area and the second switch area both extend to the edge of the power area, the electrical interconnection can be set more flexibly.

[0090] In a preferred embodiment, if Figure 2E As shown, the first switch area and the second switch area are both C-shaped, and the inner C-shaped opening matches the shape of the logic circuit area Logical. The logic circuit area Logical can be a long strip or as shown in FIG. Figure 2EThe T-shape shown is a reclining T-shape. The outer C-shape surrounds the inner C-shape on three sides. The advantage of this is that the distance between the logic circuit area Logical and the various device structural units of the upper switch QH and lower switch QL is closer, which facilitates the provision of control drive signals or current sampling. The embedding of the logic circuit area Logical also further extends the total length of the intersection line Lj and reduces the maximum equivalent width WL of the input loop, making it suitable for smaller chip aspect ratios. The extreme may even be close to a square, or better frequency characteristics can be obtained at the same aspect ratio. For example, at the same chip size, the maximum equivalent width WL of the input loop can be reduced to approximately 1.4mm, supporting higher operating frequencies.

[0091] In a preferred embodiment, if Figure 2F As shown, the semi-enclosed layout is replaced with a fully enclosed layout, which is equivalent to the combination of two semi-enclosed structures. The second switch area, the first switch area, and the logic circuit area Logical are nested in a long strip, with the logic circuit area Logical located in the center. The first switch area surrounds the Logical circuit area on all four sides (i.e., fully surrounds it), and the second switch area surrounds the first switch area on all four sides. The advantage of this arrangement is that almost the entire perimeter of the chip is used to extend the total length of the intersection line Lj, ​​making the maximum equivalent width WL of the input loop smaller, which can be reduced to 1.3mm, and improving frequency characteristics. In addition, the chip structure is symmetrical, which provides great flexibility for subsequent packaging.

[0092] The switch area can adopt a more complex shape, so that the total length Lj of the boundary line can be longer or even exceed the perimeter of the chip, thereby further reducing the maximum equivalent width WL of the input loop and optimizing the aspect ratio of the chip. Figure 2G As shown, the first switch area is C-shaped, and the second switch area surrounds the first switch area to form a hollow C-shape. This results in a very long boundary line length Lj, while the maximum equivalent width WL of the input loop is very small, for example, 1mm or 0.8mm, or even less. The logic circuit area Logical can be located at the opening of the hollow C-shape, which is both closer to the upper switch QH and the lower switch QL and facilitates signal pin routing. When the chip aspect ratio is 1, one pair of chip edges can be defined as the long side, and the other pair as the short side. The long direction of the long strip area in the switch area layout is as parallel to the long side as possible, facilitating the placement and electrical connection of the input decoupling capacitors.

[0093] In a preferred embodiment, if Figure 2HAs shown, the first switch area is C-shaped, and the second switch area does not completely surround the first switch area but only half-surrounds the long strip area of ​​the C-shape from the direction of the C-shaped opening (and is connected), thereby forming a serpentine area. The logic circuit area Logical is also half-surrounded by the serpentine area. The first switch area and the logic circuit area Logical are separated by the second switch area, and one side of the first switch area is located at the edge of the chip. This solution can also form a longer total boundary length Lj and a smaller maximum equivalent width WL of the input loop, for example, 0.8 mm.

[0094] The logic circuit area Logical can also be set along the horizontal center axis of the chip, dividing the power area into upper and lower parts to reduce wiring complexity, simplify the structure while taking into account frequency characteristics. Since the length of the upper and lower parts remains unchanged, but the width becomes less than half of the chip width, this layout can also set the chip aspect ratio closer to 1. In a preferred embodiment, if Figure 2I As shown, in the upper and lower power zones, the two first switch zones are adjacent to the logic circuit zone, while the two second switch zones surround the first switch zones on three sides. Because the second switch zones are C-shaped with a shallow opening, this semi-enclosed layout primarily utilizes the length of the long sides of the wafer. The surrounding areas on both sides contribute little to the total boundary length Lj. In this embodiment, the maximum equivalent width WL of the input loop is 1.5mm.

[0095] In a preferred embodiment, if Figure 2J As shown, Figure 2I Similarly, in this embodiment, the maximum equivalent width WL of the input loop is 1.5 mm, but the first switch area and the second switch area no longer have a surrounding or surrounded relationship, but are completely arranged in parallel in a long strip shape. Figure 2I The layout shown is much simpler.

[0096] In a preferred embodiment, if Figure 2K As shown, the power zone is similarly divided into upper and lower sections by the logic circuit area (Logical) along the horizontal center axis. In each section, the second switch area surrounds the first switch area on all four sides. The elongated first switch area is used to house the upper switch QH, while the second switch area is used to house the lower switch QL. For a 3.2mm × 5mm wafer size, the maximum equivalent width WL of the input loop can potentially approach 0.6mm or even lower.

[0097] For application scenarios where the frequency is not particularly high, such as when the operating frequency is between 1 and 3 MHz, the embodiment with the simplest layout that meets the concept of the present invention can be adopted. Figure 2L and Figure 2MAs shown, in a preferred embodiment, the logic circuit area Logical is located on one side of the long side or short side of the chip in the device structure area 2 and is parallel to the long strip power area. The power area is divided into two parts along the long side direction, which are respectively set as the first switch area and the second switch area, respectively used to set the upper switch QH and the lower switch QL. When using this chip, an input decoupling capacitor C is set along the long side direction. bus ,but Figure 2L and Figure 2M The corresponding maximum equivalent widths WL of the input loop are 2.5 mm and 3.2 mm respectively.

[0098] While this embodiment uses a Buck diode as an example, it is also applicable to other high-frequency bridge circuits. Specifically, a single-wafer process is used to integrate at least two series-connected power switching devices (referred to as an upper switch QH and a lower switch QL) in a bridge circuit onto a single wafer to achieve high-frequency operation. The single-wafer process can be Silicon, GaN, or a hybrid of Silicon and GaN, or other materials or processes that can integrate multiple functional device structural units on a single wafer.

[0099] Example 2

[0100] When the high-frequency bridge arm is operating, at least one of the switching devices is in high-frequency hard-switching operation, either entirely or occasionally. Therefore, the capability of the driver driving it affects the switching losses of the device. The drive current provided by the driver to the hard-switching switching device will produce corresponding differences in time characteristic distribution due to differences in the corresponding circuit lengths of different device structural units. This difference will affect the switching synchronization of different device structural units of the switching device. Therefore, the optimal design is to place the driver as close as possible to the hard-switching switching device and distribute it as evenly as possible. For the Buck circuit, the upper switch QH is a hard-switching switching device. For the Boost circuit, the lower switch QL is a hard-switching switching device. For the Buck-Boost bidirectional operating circuit, both are hard-switching switching devices.

[0101] Therefore, in this embodiment, to ensure high-frequency characteristics, a driver area Driver is specifically divided in the device structure area 2, and the driver area Driver is distributed in the power area. The driver area Driver is at least adjacent to each area of ​​the switching device used to set hard switching operation in the power area, and is evenly distributed.

[0102] Figure 3A The structure of the power semiconductor wafer of this embodiment is shown. Figure 3AThe logic circuit area (Logical) and each switch area are parallel to the long side of the chip. For the chip used for the Buck circuit, the first switch area of ​​the upper switch QH is set adjacent to the driver area (Driver). The driver area and the first switch area are of similar length to achieve close and balanced driving. Figure 3B The logic circuit Logical area is on one side, and the driver area Driver is set on both sides of the adjacent long side of the first switch area to achieve Figure 3A The effect is similar to that of the middle scheme. Since the current provided by the logic circuit area to the driver area Driver is only a tiny drive signal current, the separation of the two does not significantly affect the driving effect. As can be seen from the cross-sectional view, semiconductor processing is required to isolate different functional areas within the device structure area, respectively used to accommodate at least four types of devices: the upper switch QH, the lower switch QL, the driver, and other logic circuits. More areas mean a smaller maximum equivalent width WL of the input loop corresponding to the high-frequency bridge arm along the short side of the wafer, improving high-frequency characteristics, but also increasing the complexity of the manufacturing process. Therefore, embodiments of the present invention can achieve a balanced design between high-frequency performance and complexity through different layout adjustments, meeting different application scenarios at various stages of the market, in the near future, and in the long term. Obviously, the driver for the lower switch QL can also be located nearby and arranged in parallel to achieve better driving performance for the lower switch QL. The driver area Driver of this embodiment can accommodate drivers for only one of the upper switch QH or the lower switch QL, or both.

[0103] In this embodiment, the layout division of the first switch area, the second switch area, and the logical circuit area Logical can use any of the schemes described in the first embodiment or the schemes derived by analogy or combination based on the inventive concept thereof. The various area divisions in this embodiment and the first embodiment are schematic diagrams of the functional area layout of the device structure area on the wafer substrate to achieve:

[0104] 1. Implement different loop inductances in the power region, and perform different levels of subdivision and arrangement of the upper switch QH and lower switch QL to balance the chip's manufacturing complexity and high-frequency characteristics;

[0105] 2. The power area and logic circuit area are arranged in different forms to balance the high-frequency characteristics of the power area, the aspect ratio of the chip, and the convenience of signal pin lead-out;

[0106] 3. Divide the driving area of ​​the switching device into a driving area Driver and further arrange it to achieve high-frequency balanced driving characteristics.

[0107] Obviously, the advantages brought by these three aspects to the single-chip integrated device can be combined with each other and are not limited to the embodiments shown above.

[0108] Example 3

[0109] This embodiment further demonstrates the wiring structure from the device structure area of ​​a power semiconductor chip to the electrodes. The arrangement of the device structure area of ​​the chip lays the foundation for the high-frequency performance of the chip. However, the current collection of the various functional areas of the device structure area of ​​the chip, especially the power area, is not sufficient to rely solely on the electrical interconnection within the semiconductor material. The RDL wiring layer or the wiring layer of the packaging substrate is required to achieve low-impedance interconnection and convergence of the various parts of the semiconductor area. Therefore, the wiring structure also needs to be optimized for the layout of different functional areas. Since the first switch area and the second switch area in the embodiment of the present invention are both mainly formed by long strips parallel to the long sides, and the edges or corners of the short sides usually form an enclosing structure, the layout design of the convergence wiring layer can be provided for the enclosing sub-area 3 and the sub-area 4 of the parallel repeating unit respectively. The sub-area 4 of the parallel repeating unit can be divided into a sandwich shape and a double-layer shape. By combining various sub-areas 3 / 4, the optimal convergence wiring layer structure corresponding to most of the schemes in the aforementioned embodiments can be obtained.

[0110] in:

[0111] Surrounding sub-area 3: One of the first switch area and the second switch area surrounds the other on two sides (i.e., corners, equivalent to the corners of a four-side or three-side surrounded structure) or three sides (half-surrounds). Figure 4A The lower left figure shows a situation where the second switch region corresponding to the lower switch QL surrounds the first switch region corresponding to the upper switch QH on three sides.

[0112] Sub-region 4 of parallel repeating unit: The first and second switching regions are arranged parallel to each other in the sub-region. The wiring structure of the sub-region can be repeated side by side as a repeating unit to form a wiring structure of a longer region, usually in a sandwich shape or a double-layer shape. Structures with more layers can be obtained by analogy. Figure 4A The lower right figure shows a situation where the second switch area corresponding to the lower switch QL sandwiches the first switch area corresponding to the upper switch QH from above and below to form a sandwich-shaped sub-area. Figure 4D The lower figure shows a double-layer sub-region in which the first switching region and the second switching region each have only one layer.

[0113] For the enclosed sub-area 3, the wiring bus, from inside to outside, consists of wiring area 51 (corresponding to one of the DC- / DC+ electrodes; in this embodiment, wiring area 51 is electrically connected to the high-voltage terminal of the upper switch QH and the DC+ electrode), wiring area 52 (corresponding to the SW electrode; in this embodiment, wiring area 52 is electrically connected to the midpoint of the high-frequency bridge arm and the SW electrode), and wiring area 53 (corresponding to the other of the DC- / DC+ electrodes; in this embodiment, wiring area 53 is electrically connected to the low-voltage terminal of the lower switch QL and the DC- electrode). The SW electrode carries the highest current of all electrodes, and wiring across the switch area allows for the lowest impedance, high-current interconnection. Each electrode's corresponding bus lead-out member 6 (which can be a lead-out pad or lead-out via) is located on the corresponding wiring area 51 / 52 / 53 to facilitate current transmission. The total current-conducting cross-sectional area of ​​the bus lead-out member 6 corresponding to the SW electrode is preferably larger than that of the DC- or DC+ electrode to ensure balanced current density across each current path and minimize current loss.

[0114] For the sub-regions 4 of the sandwich-shaped parallel repeating unit, there can be several different arrangements for different application scenarios.

[0115] like Figure 4A The embodiment shown in the lower right figure is suitable for occasions where the maximum equivalent width WL of the input circuit is relatively narrow. Due to the relatively narrow maximum equivalent width WL of the input circuit, the number of bus lead-out components 6 that can be arranged in the same column in the vertical direction is relatively limited. Only three mutually separated wiring areas and three bus lead-out components 6 can be arranged in the same column. Therefore, on the left side of the sub-area 4, the wiring area 52 spans the first switch area in the middle layer of the sandwich and can be interconnected with the second switch areas in the upper and lower layers and the second switch area in the middle layer. The length of the wiring area 52 in the vertical direction should be greater than 50% of the length of the sub-area 4. On the right side of the sub-area 4, the mutually separated wiring areas 53, wiring area 51 and wiring area 53 are respectively electrically connected to one layer of the sandwich shape. The wiring areas 53 between adjacent sub-areas 4 bypass the wiring areas 52 and are connected horizontally into one piece. Each wiring layer has its own bus lead-out component 6.

[0116] like Figure 4B The embodiment shown is suitable for the case where the maximum equivalent width WL of the input loop is in the middle. In the vertical direction, five mutually separated wiring areas and three bus lead-out members 6 can be arranged in the same column. Figure 4A As for the wiring structure in FIG, the wiring area 52 can bypass the wiring area 51 from both sides, extend through between the wiring area 51 and the wiring area 53, and be connected horizontally to form a piece, so as to minimize the bus impedance on the SW electrode.

[0117] like Figure 4CThe embodiment shown is suitable for occasions where WL is wider. In this case, five mutually separated wiring areas and five bus lead-out parts 6 can be set along the vertical column direction, so that the wiring layers can be set in parallel. The five wiring areas along the vertical column direction are wiring area 53, wiring area 52, wiring area 51, wiring area 52 and wiring area 53, respectively. Each wiring area 51 / 52 / 53 is respectively provided with a corresponding bus lead-out part 6. Such a wiring structure enables the device structural units of the power area to be interconnected to the bus lead-out part 6 through a relatively consistent impedance, thereby achieving minimum bus impedance. Of course, each wiring area 51 / 52 / 53 does not have to be of equal width in the horizontal direction, and can also adopt a structure similar to Figure 4D In the form of Figure (b), the bus lead-out parts 6 corresponding to the wiring area 52 are staggered in the vertical column direction, and the wiring areas 51 / 52 / 53 are wider at the positions where the bus lead-out parts 6 are set, and narrower at the interval positions of the bus lead-out parts 6, so as to achieve a balance between the lead-out part setting and the bus impedance.

[0118] Figure 4D The wiring structure arrangement in sub-region 4 of a double-layer parallel repeating unit is shown. (a) In the figure, wiring area 53, wiring area 52, and wiring area 51 corresponding to DC-, SW, and DC+ are arranged in parallel, with wiring area 52 located at the junction of the first and second switch areas. Each wiring area 51 / 52 / 53 is provided with a corresponding bus lead 6. (b) In the figure, the bus lead 6 corresponding to wiring area 52 and the bus lead 6 corresponding to wiring areas 51 / 53 are staggered in the vertical direction. Wiring areas 51 / 53 are wider at the locations where the bus lead 6 is provided and narrower at the intervals, so as to reasonably transfer the wiring area to wiring layer 52 and achieve minimum bus impedance and loss for the SW electrodes.

[0119] Figures 4E to 4H Several structures are shown in which a complete bus wiring layer is formed by combining multiple sub-areas. The bus lead-out members 6 are not shown in the figures. Obviously, the bus lead-out members 6 can be arranged as densely as possible while meeting the process precision requirements. The shape of the bus wiring layer can be fine-tuned according to the shape of the bus lead-out members 6, so that the wiring area at the location where the bus lead-out members 6 are arranged is locally widened, while other locations are locally narrowed. This is not further illustrated in this embodiment.

[0120] Figures 4E to 4GThree bus wiring layer structures corresponding to the same device structure area layout (left figure). The complete power area is composed of a semi-enclosed sub-area 3 and a sub-area 4 of a sandwich-shaped parallel repeating unit. For the power area composed only of a semi-enclosed sub-area 3 or only of a sub-area 4 of a sandwich-shaped parallel repeating unit, the corresponding bus wiring layer structure can be deduced by analogy and will not be listed here. In the combined complete bus wiring layer, the wiring area 51 corresponding to the DC+ electrode occupies the smallest percentage of area, usually less than 20%; the wiring area 52 corresponding to the SW electrode occupies the largest proportion, usually greater than 40%; and the area of ​​the wiring area 53 corresponding to the DC- electrode is usually greater than 20%. Preferably, the device structure area can adopt a layout in which the logic circuit area Logical divides the power area into two from the middle, and at this time the aspect ratio of each power area is larger. The multiple types of areas combined into a chip are arranged in sequence, and the electrical connection distance is shorter, which not only realizes high frequency and low loop, but also realizes low impedance and large current.

[0121] Figure 4H The busbar wiring layer structure corresponding to another device structure area layout (left image) is shown. The complete power area consists of a corner-enclosed sub-area 3 and a double-layered parallel repeating unit sub-area 4. For power areas consisting only of corner-enclosed sub-areas 3 or only of double-layered parallel repeating units, the corresponding busbar wiring layer structure can be derived by analogy and is not listed here. Preferably, the device structure area can adopt a layout that divides the power area in half along the middle, using the logic circuit area Logial. In this case, the aspect ratio of each power area is greater. The first switch area and second switch area of ​​each power area are both elongated and arranged parallel to the long side of the chip. The first switch area corresponding to the upper switch QH is close to the logic circuit area Logical, that is, located on the inner side. The second switch area corresponding to the lower switch QL is close to the edge of the chip, that is, located on the outer side. The corresponding busbar wiring layers of each power area, from the horizontal center axis outward, are the elongated wiring layer 51 corresponding to the DC+ electrode, the elongated wiring layer 52 corresponding to the SW electrode, and the elongated wiring layer 53 corresponding to the DC- electrode. Of course, in other embodiments, the long strip-shaped wiring area can also be shaped like a discontinuous dashed line, so that the inner wiring area extends to the edge of the long side to facilitate lateral electrical connection. The signal pins of the logic circuit area can be arranged at the transverse center axis of the chip, or can be led to the outside of the short side of the chip.

[0122] Example 4

[0123] Since the input circuit needs to connect the high-frequency bridge arm and the input decoupling capacitor C bus A closed loop is formed after parallel connection. Since the present invention is used for high frequency scenarios, the input decoupling capacitor C bus The electrical interconnection is crucial. This embodiment shows the power semiconductor chip of the power bridge arm integrated on a single chip and the input decoupling capacitor Cbus The specific method of assembling to form a module.

[0124] like Figure 5A As shown, in order to make each device structure unit of the power semiconductor chip as close as possible to the input decoupling capacitor C bus To achieve decoupling, a long strip array of multiple capacitors is placed outside the long side of the power semiconductor chip. The electrical connection wiring between each capacitor and the chip is perpendicular to the long side of the chip, that is, parallel to the short side, so that the two ends of each capacitor are electrically connected to the DC+ electrode and DC- electrode respectively. bus The total input loop inductance L formed by the high-frequency bridge arm loop , which is formed by the parasitic inductance of multiple small loops in parallel, so the overall inductance is very small. Moreover, by arranging two capacitor arrays symmetrically on the outside of the two long sides, the total input loop inductance L can be further reduced. loop Typically, a capacitor array is made up of multiple small-sized multilayer ceramic capacitors assembled through a substrate and electrically connected to the chip.

[0125] Since the capacitor array has many pins that need to be electrically connected to the DC+ electrode or DC- electrode of the chip, and one of them (such as the DC+ electrode) is usually set in the middle of the chip. Figure 5B As shown, in the capacitor interconnect wiring layer 7 (which can be provided on the module substrate), the vertical wiring corresponding to the DC+ electrode segments the wiring corresponding to the DC- and SW electrodes into dashed lines. Because this vertical wiring can be relatively thin, as long as each dashed line segment has sufficient area for the busbar lead 6, there is virtually no impact on the interconnect impedance, while achieving ultra-low loop inductance.

[0126] Figure 5A In the capacitor array shown, two adjacent capacitors are arranged in opposite directions of electrical properties, that is, the electrical properties of adjacent electrodes are the same, for example, both correspond to DC+ electrodes or both correspond to DC- electrodes. This has the advantage of requiring fewer wirings and making better use of wiring layer resources. Moreover, since the electrical properties of adjacent electrodes are the same, the capacitors can also be placed more compactly, making full use of space. Of course, just from the input loop inductance L loop In terms of Figure 5C There is a chance to achieve Figure 5A Smaller input loop inductance L loop However, the electrical properties of the two adjacent electrodes of two adjacent capacitors are different, which places higher requirements on wiring and is suitable for scenarios with higher operating frequencies. Figure 5CThe wiring areas 51 / 53 in the middle respectively lead the DC+ electrode and DC- electrode to the long side edge of the chip and set corresponding bus lead-out parts, while directly forming a horizontal multi-segment dotted line shape in the wiring area 52 / 53 of the bus wiring layer.

[0127] Example 5

[0128] In the solution of the fourth embodiment, the total input loop inductance L loop It can be as low as less than 0.5nH. However, when the operating frequency is very high, such as higher than 2MHz or even higher, only the external decoupling capacitor C bus_Pkg The input loop formed is not ideal, and a chip integrated capacitor C needs to be set on or inside the chip. bus_Die .like Figure 6A As shown, the external decoupling capacitor C bus_Die and chip integrated capacitor C bus_Pkg They are connected in parallel with the high-frequency bridge arm to form two loops, and the total equivalent inductance of the outer decoupling capacitor is L loop_Pkg and the total equivalent inductance L of the chip integrated capacitor circuit loop_Pkg This double-loop effect provides multi-level decoupling. This reduces the total equivalent inductance to a minimum. Chip-integrated capacitors are classified into two types: built-in capacitors and stacked decoupling capacitors integrated above the power semiconductor chip.

[0129] In a preferred embodiment, as shown in FIG. Figure 6B As shown, a stacked decoupling capacitor 8 can be integrated on the chip. A capacitor with an array pin, such as a silicon capacitor, can be used and welded to the chip. Therefore, a capacitor connection pad corresponding to the silicon capacitor pin needs to be reserved on the chip surface. Since the current density of the chip is very high, the metal layer on the surface of the chip has a great influence on the current carrying capacity. In conventional chip layout, the capacitor connection pad will occupy these resources, resulting in increased loss. However, in this embodiment, the logic circuit area Logical is arranged horizontally on the central axis of the chip, so the capacitor connection pad can be arranged in the area corresponding to the logic circuit area Logical in the bus wiring layer, so that the silicon capacitor is also arranged in the corresponding position. Because the logic circuit area Logical does not require high current wiring, the wiring resources can be left to the silicon capacitor. Figure 5CBased on the arrangement of the chip and the outer decoupling capacitors shown, a long silicon capacitor or an equivalent long silicon capacitor composed of multiple silicon capacitors is placed on the horizontal long strip portion of the long logic circuit area Logical, and a corresponding wiring and other electrical connection structures are set on the bus wiring layer of the chip. The pins of the long silicon capacitor are electrically alternately arranged in the long side direction and are connected to the circuit nodes corresponding to the DC+ electrode and DC- electrode of each power zone nearby to form multiple small loops, which are equivalently connected in parallel to each other to achieve an extremely small total equivalent inductance L of the chip integrated capacitor loop. loop_Die Preferably, the thickness of the silicon capacitor can be set to be thinner than 0.1 mm or even 0.05 mm, so as to better lead out the power or signal pins of the chip.

[0130] Figure 6B It is a pre-formed stacked decoupling capacitor that is interconnected with the power semiconductor chip at the power level through welding or electroplating, which is also called the Cap on Die process. This integration method is relatively difficult to package and relatively inflexible. In some other embodiments, the Cap in Die process can also be used, that is, the capacitor is a built-in capacitor formed in situ during the production process of the chip. For example, the device area capacitor is formed in the device structure area of ​​the chip through etching and other processes, or a built-in layered capacitor is formed by placing a dielectric layer between two or more wiring layers. Because it is a semiconductor process, it has high precision and can be flexibly set.

[0131] In a preferred embodiment, if Figure 6C As shown, the device structure area is also provided with a built-in capacitor area 9, which is arranged in the middle of the power area. The first switch area and the second switch area are arranged in sequence on four sides, which can increase the operating frequency to 5MHz. In a preferred embodiment, as shown in FIG. Figure 6D As shown, the built-in capacitor area 9 is surrounded by the power area on four sides, and the power area is also surrounded by four sides. Such a setting can reduce the impact on the power area wiring. In a preferred embodiment, as Figure 6E As shown, the built-in capacitor area 9 is arranged in a strip shape along the horizontal central axis, and the first switch area and the second switch area in the power area on both sides are also strip shapes parallel to the long sides. Figure 6C and Figure 6D In the combination of the two schemes, built-in capacitor regions 9 are provided at the center and periphery of the power region, further reducing loop inductance and enabling higher frequency applications, such as up to 10 MHz. The built-in capacitor regions 9 in each embodiment are also primarily formed by elongated strips, with the strips running parallel to the boundary between the first and second switches and being as long as possible.

[0132] like Figure 6FThe power area is distributed in a four-sided surrounding pattern of the second, first, and second switch areas corresponding to the lower switch QL, upper switch QH, and lower card switch QL to achieve a longer total boundary length Lj and a smaller maximum equivalent width WL of the input loop, thereby improving frequency performance. The built-in capacitor area 9 is set between the two second switch areas and surrounds them in the same long strip shape. An operating frequency higher than 10MHz can be achieved. Further setting another built-in capacitor area outside the outer power area or in the center of the inner power area can achieve a higher operating frequency, even higher than 20MHz.

[0133] The setting of the built-in capacitor area and the layout of the power area and the logic circuit area Logical can be combined with each other in various forms, and there are many ways to implement them, which are not limited to the examples provided. The essence is still that the long strip areas of the first and second switch areas form a boundary line as long as possible, and the long strip area of ​​the built-in capacitor area 9 also forms a boundary line with the same direction and as long as possible with the long strip areas of the first / second switch areas. More preferably, multiple built-in capacitor areas 9 can be set, each adjacent to a different switch area, so that the device area capacitor is respectively adjacent to the high-voltage end and the low-voltage end of the high-frequency bridge arm and is connected in parallel with the high-frequency bridge arm.

[0134] The placement of built-in capacitors is not restricted by the location of the logic area. However, when the logic area is located at the horizontal center axis, a cap-on-die solution can be used to achieve greater capacitance using preformed capacitors while virtually eliminating the need for wafer power routing resources.

[0135] However, when the logical circuit area Logical is set in the middle, in order to make better use of the space, the logical circuit area Logical becomes very narrow and long, which causes some functional units in the area to be far away from the signal pins, and the impedance and inductance are relatively large. This has a certain impact on the pins that need to be connected to high-frequency capacitors, such as power supply pins. Since both Cap on Die and Cap in Die, the capacitor can be composed of multiple independent small capacitor units. Therefore, these small capacitor units can be combined into chip integrated capacitors C bus_Die At the same time, some area can be used to form the capacitors required by the logic circuit area, such as the power supply decoupling capacitors in the logic circuit area. This allows for both high-frequency operation in the power area and reliable operation in the logic circuit area.

[0136] For this embodiment, the chip integrated capacitor C is integrated inside or on the surface of the chip. bus_Die In the case of forming a power module, the long edge of the chip is integrated with more external decoupling capacitors C through packaging or substrate. bus_Pkg, achieving multi-level loop inductance decoupling effect. Among them, the chip integrated capacitor C bus_Die The equivalent total capacitance should be more than 5 times the total capacitance of the upper switch QH and the lower switch QL, and less than the external decoupling capacitor C bus_Pkg 0.2 times of the equivalent total capacitance, while the chip integrated capacitor C bus_Die The total equivalent inductance L of the chip integrated capacitor loop formed by the high-frequency bridge arm loop_Die , should be smaller than the external decoupling capacitor C bus_Pkg The total equivalent inductance L of the outer decoupling capacitor loop formed by the high-frequency bridge arm loop_Pkg 0.7 times of that in order to form an effective composite multi-band decoupling effect.

[0137] Example 6

[0138] Figure 7 The layout of the device structure area in this embodiment is shown. In some of the aforementioned embodiments, the logic circuit area (Logical) divides the power area into multiple parts, for example, into two. This allows the two separate power areas to receive different control drive signals and operate independently. Each power area can be an independent half-bridge, operate in parallel to achieve greater synchronous current, or operate 180 degrees out of phase to form two circuits or a full-bridge circuit with staggered phase control. For higher-frequency scenarios, each power area can be further divided into two independent parts, resulting in a single chip with four independent power areas, enabling four circuits to operate with 90 degrees out of phase, achieving higher-frequency staggered phase conversion. The integration of multiple circuits on a single chip not only increases the power unit integration density but also reduces the total number of signal pins, reducing system complexity. For example, when integrating four circuits, the number of signal pins corresponding to the logic area's power supply, current sampling, temperature sampling, and other functions is reduced from four times to one. Furthermore, since the power areas are placed close together in actual use, the currents on the power pins are staggered on the package substrate, significantly reducing and offsetting the high-frequency current components of the power pins and traces of the DC+ and DC- electrodes, thereby reducing losses.

[0139] In summary, each embodiment optimizes the performance of power semiconductor chips integrated with high-frequency, high-current switching bridge arms by arranging the upper switch QH and the lower switch QL in the power zone to achieve the minimum WL and the longest Lj, interspersing the logic circuit area Logical with the power zone to reduce the aspect ratio of the chip to improve the yield or achieve a smaller WL and a longer Lj with the same aspect ratio, partitioning the driver to achieve high-frequency synchronous drive, setting the chip integrated capacitor to achieve the minimum loop, combining the internal and external decoupling capacitors to achieve multi-band decoupling, and taking into account the utilization of the small power loop and the bus wiring layer area by overlapping the position of the stacked capacitor and the logic circuit area Logical, and single-chip multi-circuit operation, etc., thus solving the challenges at the chip level. The above embodiments achieve balanced operation of each power unit of the chip under high-frequency switching action, so that the chip can operate with high current at high frequency. However, in actual use, the package lead impedance of each power electrode of the chip, especially the AC impedance, will still affect the current sharing effect inside the chip. Therefore, the package lead impedance also needs to be uniform and symmetrical.

[0140] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims, not the foregoing description, and all variations within the meaning and range of equivalents of the claims are intended to be included therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0141] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A single-chip integrated high-frequency bridge arm power semiconductor chip, characterized in that: The device structure area includes a substrate and a device structure area, wherein the device structure area is arranged on a surface of the substrate; the device structure area includes a first switch area, a second switch area and a logic circuit area; the logic circuit area provides a driving signal to the first switch and the second switch; The first switch region is used to set a first switch, and the second switch region is used to set a second switch, and the first switch and the second switch are connected in series to form a high-frequency bridge arm; a DC+ electrode, a DC- electrode, and a SW electrode are provided on the power semiconductor chip, and the DC+ electrode and the DC- electrode are electrically connected to the two ends of the high-frequency bridge arm respectively, and the SW electrode is electrically connected to the midpoint end of the high-frequency bridge arm; The device structure area has a long side and a short side, and the length of the long side is greater than the length of the short side; at least a portion of the first switch area is a first long strip area parallel to the long side, and at least a portion of the second switch area is a second long strip area parallel to the long side, and the first long strip area and the second long strip area are arranged side by side in a direction perpendicular to the long side.

2. The power semiconductor chip according to claim 1, characterized in that The device structure region is a long strip region, and the device structure region only includes a first long strip region and a second long strip region, and the first long strip region and the second long strip region are adjacent to and parallel to each other.

3. The power semiconductor chip according to claim 2, characterized in that The logic circuit area is arranged adjacent to a short side or a long side of the power semiconductor region.

4. The power semiconductor chip according to claim 1, wherein: At least one of the long sides is used to set a decoupling capacitor, the decoupling capacitor is set along the long side, the decoupling capacitor is set outside the device structure area, and the decoupling capacitor is connected in parallel with the high-frequency bridge arm.

5. The power semiconductor chip according to claim 1, wherein: The second switching region surrounds at least three sides of the first switching region.

6. The power semiconductor chip according to claim 5, characterized in that The second switch area completely surrounds the first switch area.

7. The power semiconductor chip according to claim 6, characterized in that The logic circuit area is arranged at a central axis of the device structure area parallel to the long side.

8. The power semiconductor chip according to claim 5, characterized in that The second switch area is C-shaped, the first switch area is a lying T-shaped, the second switch area partially surrounds the first switch area, and the first switch area and the second switch area are complementary.

9. The power semiconductor chip according to claim 5, characterized in that The first switch area and the second switch area are both C-shaped; the C-shape located inside at least partially surrounds the logic circuit area; and the C-shape located outside surrounds at least three sides of the inner C-shape.

10. The power semiconductor chip according to claim 9, characterized in that The logic circuit area is in a lying T shape.

11. The power semiconductor chip according to claim 9, characterized in that The first switch area is C-shaped, the second switch area completely surrounds the first switch area, and the first switch area and the second switch area are combined to form a C-shaped power area; the C-shaped power area surrounds at least three sides of the logic circuit area.

12. The power semiconductor chip according to claim 9, characterized in that The first switch area is C-shaped; the second switch area partially surrounds the first switch area, and the first switch area and the second switch area are combined to form a C-shaped power area; a part of the left edge of the C-shaped power area is the first switch area; the C-shaped power area surrounds at least three sides of the logic circuit area.

13. The power semiconductor chip according to claim 1, wherein: The logic circuit area includes a third long strip area parallel to the long side, and the third long strip area is arranged at the central axis of the device structure area parallel to the long side.

14. The power semiconductor chip according to claim 13, characterized in that The central axis passes through the logic circuit area.

15. The power semiconductor chip according to claim 13, wherein: The first switch region and the second switch region form a power region, and the power region surrounds at least three sides of the logic circuit region.

16. The power semiconductor chip according to claim 15, characterized in that The power area surrounds the entire logic circuit area.

17. The power semiconductor chip according to claim 13, characterized in that The logic circuit area divides the device structure area into a first switch area group and a second switch area group, and the first switch area group and the second switch area group are respectively arranged on opposite sides of the logic circuit area; and the first switch area group and the second switch area group are symmetrical along the central axis; the first switch area group and the second switch area group are respectively provided with a first switch area.

18. The power semiconductor chip according to claim 17, characterized in that The switch areas arranged on both sides of the logic circuit area are both in the shape of long strips, and the long sides of each long strip are parallel to each other.

19. The power semiconductor chip according to claim 18, characterized in that The device structure area further includes a driving area, which is in the shape of a long strip parallel to the long side; the driving area is arranged between each adjacent two of the logic area, the first switch area and the second switch area.

20. The power semiconductor chip according to claim 18, wherein Only one of the switch areas arranged on both sides of the logic circuit area is in a strip shape.

21. The power semiconductor chip according to claim 17, wherein: The second switching region surrounds at least three sides of the first switching region.

22. The power semiconductor chip according to claim 21, characterized in that The second switch area completely surrounds the first switch area.

23. The power semiconductor chip according to claim 21, characterized in that The second switch area is C-shaped, and the first switch area is strip-shaped; the first switch area is adjacent to the logic circuit area at one long side, and is adjacent to the second switch area at the other long side and both short sides.

24. The power semiconductor chip according to claim 1, characterized in that The device structure area further includes a driving area, which is in the shape of a long strip parallel to the long side; each first switching area is adjacent to at least one driving area, and / or each second switching area is adjacent to at least one driving area.

25. The power semiconductor chip according to claim 1, characterized in that A bus layer is provided above the device structure area, and the bus layer includes a DC+ bus wiring layer, a DC- bus wiring layer and a SW bus wiring layer. The DC+ electrode, DC- electrode and SW electrode are electrically connected to the high-frequency bridge arm through the corresponding bus wiring layer.

26. The power semiconductor chip according to claim 25, characterized in that The SW bus wiring layer is arranged across the first switch area and the second switch area; the DC+ bus wiring layer is arranged on the first switch area and the DC- bus wiring layer is arranged on the second switch area, or the DC+ bus wiring layer is arranged on the second switch area and the DC- bus wiring layer is arranged on the first switch area.

27. The power semiconductor chip according to claim 25, characterized in that It also includes a DC+ bus lead-out piece, a DC- bus lead-out piece and a SW bus lead-out piece, and each wiring area is provided with at least one bus lead-out piece; the bus lead-out piece is electrically connected to the corresponding wiring area; the total cross-sectional area of ​​the SW bus lead-out piece is greater than the total cross-sectional area of ​​the DC+ bus lead-out piece.

28. The power semiconductor chip according to claim 25, characterized in that The device structure area includes a first sub-area, and the second switch area in the first sub-area surrounds at least three sides of the first switch area; the first sub-area corresponds to the first bus layer, and the DC+ bus wiring layer in the first bus layer semi-surrounds the DC- bus wiring layer and the SW bus wiring layer.

29. The power semiconductor chip according to claim 25, characterized in that The device structure area includes a second sub-area, the first switch area and the second switch area in the second sub-area are both long strips, and the first switch area is arranged between the second switch areas; the second sub-area corresponds to the second bus layer, the SW bus wiring layer of the second bus layer spans the second switch area, and the length of the SW bus wiring layer in the vertical column direction is greater than 50% of the length of the second sub-area in the vertical column direction; the DC+ bus wiring layer of the second bus layer is arranged between the DC- bus wiring layers.

30. The power semiconductor wafer according to claim 29, wherein: The DC+ electrodes in two adjacent second bus layers are electrically connected, and the DC- electrodes in two adjacent second bus layers are electrically connected.

31. The power semiconductor chip according to claim 29, characterized in that The SW bus wiring layer includes two extending sections, and the two extending sections are respectively arranged between the DC+ bus wiring layer and two DC- bus wiring layers.

32. The power semiconductor chip according to claim 25, characterized in that The device structure area includes a second sub-area, the first switch area and the second switch area in the second sub-area are both long strips, and the first switch area is arranged between the second switch areas; the second sub-area corresponds to the second bus layer, and the second bus layer is arranged in a vertical column direction in the order of DC- bus wiring layer, SW bus wiring layer, DC+ bus wiring layer, SW bus wiring layer and DC- bus wiring layer; each of the DC- bus wiring layer, SW bus wiring layer and DC+ bus wiring layer is respectively provided with a bus lead-out component.

33. The power semiconductor chip according to claim 25, characterized in that The device structure area includes a second sub-area, the first switch area and the second switch area in the second sub-area are both long strips, and the first switch area in the second sub-area is arranged between the second switch area and the logic circuit area; the second sub-area corresponds to the second bus layer, and the planar layout of the second bus layer is arranged in sequence in the vertical column direction according to the order of DC- bus wiring layer, SW bus wiring layer and DC+ bus wiring layer; bus lead-out parts are respectively provided on the DC- bus wiring layer, SW bus wiring layer and DC+ bus wiring layer.

34. The power semiconductor chip according to claim 33, characterized in that The DC- bus wiring layer, the SW bus wiring layer and the DC+ bus wiring layer are all in the shape of long strips; the bus lead-out members are aligned and arranged along the vertical column direction.

35. The power semiconductor chip according to claim 33, characterized in that The bus lead-out pieces arranged on the SW bus wiring layer are staggered from the bus lead-out pieces arranged on the DC- bus wiring layer and the DC+ bus wiring layer; the DC- bus wiring layer, the SW bus wiring layer and the DC+ bus wiring layer are respectively arranged to alternately change width and narrow along the lateral direction, and are wider at the positions where the bus lead-out pieces are arranged.

36. The power semiconductor wafer according to claim 25, wherein: The device structure area includes a first sub-area and a second sub-area, the first switch area and the second switch area in the first sub-area are arranged in an enclosed manner; the first switch area and the second switch area in the second sub-area are arranged parallel to each other; the first sub-area is located at the end of the second sub-area; the DC-bus wiring layer, the SW bus wiring layer and the DC+bus wiring layer in the second sub-area are formed as multiple repeating units repeated side by side; the DC-bus wiring layer in the first sub-area is connected to the DC-bus wiring layer in the second sub-area; the SW bus wiring layer in the first sub-area is connected to the SW bus wiring layer in the second sub-area; the DC+bus wiring layer in the first sub-area is connected to the DC+bus wiring layer in the second sub-area.

37. The power semiconductor chip according to claim 1, characterized in that The device structure area also includes a built-in capacitor area; The built-in capacitor region and the first switch region are adjacent to each other along the long side direction, and / or the built-in capacitor region and the second switch region are adjacent to each other along the long side direction; The built-in capacitor area is used to set the device area capacitor, and the device area capacitor is connected in parallel with the high-frequency bridge arm.

38. The power semiconductor chip according to claim 37, characterized in that The device structure area is arranged in layers from the inside to the outside in the order of the built-in capacitor area, the first switch area and the second switch area in a plane layout.

39. The power semiconductor chip according to claim 37, characterized in that The device structure area is arranged in layers from the inside to the outside in the order of the first switch area, the second switch area and the built-in capacitor area in a plane layout.

40. The power semiconductor wafer according to claim 37, wherein There are at least two first switch areas and second switch areas respectively, and the device structure areas are arranged in sequence in the vertical column direction in the plane layout according to the second switch area, the first switch area, the built-in capacitor area, the first switch area and the second switch area.

41. The power semiconductor chip according to claim 37, characterized in that There are at least two second switch areas, and the device structure areas are arranged layer by layer from the inside to the outside in the order of the second switch area, the built-in capacitor area, the first switch area, and the second switch area in a plane layout.

42. The power semiconductor chip according to claim 25, characterized in that It also includes a built-in layer capacitor, which is formed by a dielectric layer embedded in the bus wiring layer; the built-in layer capacitor is connected in parallel with the high-frequency bridge arm.

43. The power semiconductor chip according to claim 25, characterized in that The bus wiring layer further includes a capacitor connection pad, and the capacitor connection pad is located at a corresponding position of the logic circuit area projected in the bus wiring layer.

44. The power semiconductor chip according to claim 43, characterized in that The capacitor connection pads are provided in a plurality arranged in an array.

45. The power semiconductor chip according to claim 17, characterized in that The logic circuit area provides two groups of driving signals with a 180-degree phase shift to the first switch area group and the second switch area group.

46. ​​The power semiconductor chip according to claim 1, characterized in that The device structure area includes multiple switch area groups of equal area, each switch area group includes at least one first switch area and at least one second switch area; the logic circuit area is used to provide at least two groups of mutually out-of-phase drive signals to the switch area groups, and each group of drive signals drives a different switch area group respectively.

47. The power semiconductor chip according to claim 46, characterized in that The plurality of switch area groups are arranged along the central axis of the device structure area and are symmetrically arranged on both sides of the central axis of the device structure area.

48. The power semiconductor chip according to claim 46, characterized in that The first switch area and the second switch area in each switch area group are both in a long strip shape.

49. The power semiconductor chip according to claim 47, characterized in that The multiple switch area groups include the first to fourth switch area groups, the first switch area group and the third switch area group are located on one side of the central axis of the device structure area, and the second switch area group and the fourth switch area group are located on the other side of the central axis of the device structure area; the logic circuit area is used to provide four groups of drive signals that are sequentially staggered by 90 degrees to the first to fourth switch area groups.

50. The power semiconductor chip according to claim 46, characterized in that The logic circuit area is located on the central axis of the device structure area, and the multiple switch area groups are symmetrically arranged on two opposite sides of the logic circuit area.

51. A power conversion module, characterized in that: The invention comprises a bridge arm circuit; The bridge arm circuit includes an external decoupling capacitor and a power semiconductor chip as described in any one of claims 1 to 47; the external decoupling capacitor array is arranged on the outside of at least one long side of the power semiconductor chip, and the external decoupling capacitor and the high-frequency bridge arm are connected in parallel.

52. The power conversion module according to claim 51, characterized in that: The bridge arm circuit also includes a stacked decoupling capacitor; the stacked capacitor is stacked above the power semiconductor chip and its position corresponds to the logic circuit area; the stacked decoupling capacitor is connected in parallel with the high-frequency bridge arm; the stacked decoupling capacitor is a silicon capacitor.

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