Automatic test device for integrated circuit ESD level test

Abstract

The invention relates to an automatic test device for an integrated circuit ESD level test, and belongs to the technical field of integrated circuit test. The device comprises an ESD (Electro-Static Discharge) test pin scanning control panel, an AIMDA-1000 full-automatic test machine and a remote ETP-2 static test platform. Wherein the scanning control panel comprises a RelayA module, an RLTry module and a diode indicator lamp, and can realize automatic pin switching, test triggering and connection state indication; the full-automatic testing machine controls the relay and sends a trigger instruction through a program; the static test platform is used for generating static analog signals. When the device is connected, the scanning board is connected to the IC to be tested and is correctly connected with the test machine and the static test platform, a program is operated after parameters are set, and forward and reverse ESD tests of all PINs of the IC can be automatically completed. The problems that manual testing is time-consuming, labor-consuming and error-prone are solved, testing efficiency and accuracy can be improved, the number of pins can be set according to requirements, and full automation of testing is achieved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an automatic testing device for ESD level testing of integrated circuits. Background Art

[0002] In addition to basic electrical parameters, IC packaging testing requires another critical parameter: anti-static level testing. Based on the characteristics of electrostatic discharge (ESD), the industry has established four ESD test models: the Human Body Model (HBM), the Machine Model (MM), the Charged Device Model (CDM), and the IEC61000-4-2 discharge model.

[0003] The current testing method is manual. When testing multi-pin ICs, manual pin switching is required. Each pin test requires manually triggering the MM (HBM) electrostatic test platform by repeatedly pressing the TRIGGER button six times to complete a forward and reverse voltage test. Disadvantages: 1. Pin switching requires manual change. For a 20-pin product, this requires over 300 changes. 2. Each test requires six key presses on the test platform. Both of these drawbacks are time-consuming and labor-intensive. Therefore, it is necessary to design a device that automatically tests and automatically changes pin positions to address these issues. Summary of the Invention

[0004] In response to the problems existing in the prior art, the present invention proposes an automatic testing device for ESD level testing of integrated circuits, which has solved the problems mentioned in the background art.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] An automatic test device for ESD level testing of integrated circuits, comprising:

[0007] ESD test pin scanning control board, the scanning control board includes:

[0008] Relay_A module is used to connect to the fully automatic test machine to achieve automatic pin switching and connect the IC test pin to the output of the electrostatic test platform through the relay;

[0009] RL_Try module, used to control the automatic testing of the electrostatic test platform;

[0010] The fully automatic tester controls the relays on the ESD test pin scanning board through the RLYA card to achieve automatic pin switching and send instructions to trigger the test on the electrostatic test platform;

[0011] The electrostatic test platform includes an electrostatic discharge generator and an electrostatic test platform. The electrostatic discharge generator is used to set the test mode, voltage, number of times and the interval time between each test. The electrostatic test platform is used to input the simulated electrostatic model to the test pin of the IC to be tested, and the internal TRIGGER key lead is connected to the ESD test pin scanning board to realize automatic testing.

[0012] As a further technical solution of the present invention: the ESD test pin scanning control board is provided with an interface for accessing the IC to be tested, and the interface includes ESD_POS, ESD_NEG, VCC and GND interfaces, wherein ESD_POS and ESD_NEG are respectively connected to the positive and negative output terminals of the HBM (MM) electrostatic test platform, and VCC and GND are connected to the VCC and GND pins of the IC to be tested.

[0013] As a further technical solution of the present invention: the Relay_A module includes a relay array, and the relay array is connected to each PIN to be tested of the IC through relays.

[0014] As a further technical solution of the present invention: the RL_Try module is connected to the TRIGGER button of the HBM (MM) electrostatic test platform through a lead, receives the trigger signal sent by the fully automatic tester, and controls the HBM (MM) electrostatic test platform to perform the test operation.

[0015] As a further technical solution of the present invention: the fully automatic test machine AIMDA-1000 is connected to the Relay_A module of the ESD test pin scanning control board through the RLYA card, and the main control program is used to control the relay switching pin and send a trigger signal to the RL_Try module.

[0016] As a further technical solution of the present invention: the test process of the test device includes: connecting the IC to be tested PIN, HBM (MM) electrostatic test platform into the test state, performing a forward voltage test, resetting the test voltage and number of times, performing a reverse voltage test, resetting the test voltage and number of times, and repeating in sequence until all PINs to be tested are tested.

[0017] As a further technical solution of the present invention: the forward voltage test and the reverse voltage test are both performed 5 times, with an interval of 500 mS between each test.

[0018] In the above technical solution, the technical effects and advantages provided by the present invention are:

[0019] 1. No need to manually switch pins or repeatedly trigger the electrostatic test platform.

[0020] 2. Save manpower and time, and significantly improve efficiency.

[0021] 3. The number of test integrated chip pins can be set according to needs.

[0022] 4. There will be no problems such as missed or incorrect pin combination testing due to manual switching. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 It is a system structure diagram of the present invention.

[0025] Figure 2 It is an operation flow chart of the present invention. DETAILED DESCRIPTION

[0026] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] It should be noted that the terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used in this article are for illustrative purposes only and do not represent the only implementation method.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains; the terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention; the term "and / or" used herein includes any and all combinations of one or more of the associated listed items.

[0029] The present invention provides Figure 1 and Figure 2 The drawings shown are specifically an automatic test device for ESD level testing of integrated circuits, including:

[0030] The ESD test pin scanning control board, as the core component of the device, integrates the Relay_A module, the RL_Try module, and a diode indicator. The Relay_A module automatically switches the connection between the IC pins under test and the HBM(MM) electrostatic test platform output via a relay array. The RL_Try module connects to the TRIGGER button on the HBM(MM) electrostatic test platform via wires to automatically trigger the test. The diode indicator is connected in series with each pin connection path to display the connection status.

[0031] AIMDA-1000 fully automatic tester: Connects to the Relay_A module of the ESD test pin scanning control board through the RLYA card. A main control program is written using supporting open-source software to control the relay pin switching and send a trigger signal to the RL_Try module.

[0032] Electrostatic test platform Yuanfang ETP-2: The EMS61000-2A electrostatic discharge generator is connected to the HBM(MM) electrostatic test platform to set test parameters; the TRIGGER key lead of the HBM(MM) electrostatic test platform is connected to the RL_Try module, and the output end is connected to the scanning board through ESD_POS and ESD_NEG.

[0033] The test process is as follows:

[0034] Connect the IC to be tested to the corresponding interface of the ESD test pin scanning board and ensure that VCC and GND are correctly connected;

[0035] Connect the Relay_A module to the RLYA card of AIMDA-1000 and the RL_Try module to the TRIGGER button of the HBM(MM) electrostatic test platform;

[0036] On the EMS61000-2A ESD generator, set the test mode (such as HBM or MM), test voltage, number of discharges (such as 5), and the interval between each discharge (such as 500mS).

[0037] Enter the pin number of the IC to be tested on the AIMDA-1000 tester, load and run the test program;

[0038] After the program runs, it automatically completes the following steps:

[0039] Connect the first PIN to be tested of IC;

[0040] HBM (MM) electrostatic test platform enters the test state;

[0041] Start forward voltage test 5 times;

[0042] The test voltage is reset to zero, and the test times are reset to zero;

[0043] Change the test voltage to reverse and enter the test state;

[0044] Reverse voltage test 5 times;

[0045] The test voltage is reset to zero, and the test times are reset to zero;

[0046] Connect the second PIN to be tested on the IC and repeat the above test steps until all PINs to be tested are tested.

[0047] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered in all respects as illustrative and non-restrictive, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations that come within the meaning and range of equivalents of the claims be embraced therein.

[0048] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment have also been appropriately combined to form other implementation methods that are easy for those skilled in the art to understand.

Claims

1. An automatic test device for ESD level testing of integrated circuits, It is characterized by including: ESD test pin scanning control board, the scanning control board includes: Relay_A module is used to connect to the fully automatic test machine to achieve automatic pin switching and connect the IC test pin to the output of the electrostatic test platform through the relay; RL_Try module, used to control the automatic testing of the electrostatic test platform; The fully automatic tester controls the relays on the ESD test pin scanning board through the RLYA card to achieve automatic pin switching and send instructions to trigger the test on the electrostatic test platform; The electrostatic test platform includes an electrostatic discharge generator and an electrostatic test platform. The electrostatic discharge generator is used to set the test mode, voltage, number of times and the interval time between each test. The electrostatic test platform is used to input the simulated electrostatic model to the test pin of the IC to be tested, and the internal TRIGGER key lead is connected to the ESD test pin scanning board to realize automatic testing.

2. The automatic testing device for ESD level testing of integrated circuits according to claim 1, characterized in that: The ESD test pin scanning control board is provided with an interface for accessing the IC to be tested, and the interface includes ESD_POS, ESD_NEG, VCC and GND interfaces, wherein ESD_POS and ESD_NEG are respectively connected to the positive and negative poles of the electrostatic test platform output terminal, and VCC and GND are connected to the VCC and GND pins of the IC to be tested.

3. The automatic testing device for ESD level testing of integrated circuits according to claim 1, characterized in that: The Relay_A module includes a relay array, and the relay array is connected to each PIN to be tested of the IC through relays.

4. The automatic testing device for ESD level testing of integrated circuits according to claim 1, characterized in that: The RL_Try module is connected to the TRIGGER button of the electrostatic test platform through a lead, receives a trigger signal sent by the fully automatic test machine, and controls the electrostatic test platform to perform a test operation.

5. The automatic testing device for ESD level testing of integrated circuits according to claim 1, characterized in that: The fully automatic test machine is connected to the Relay_A module of the ESD test pin scanning control board through the RLYA card. The main control program is used to control the relay to switch the pins and send a trigger signal to the RL_Try module.

6. The automatic testing device for ESD level testing of integrated circuits according to claim 1, characterized in that: The test process of the test device includes: connecting the IC PIN to be tested, the electrostatic test platform enters the test state, performing a forward voltage test, resetting the test voltage and times, performing a reverse voltage test, resetting the test voltage and times, and repeating in sequence until all PINs to be tested are tested.

7. The automatic testing device for ESD level testing of integrated circuits according to claim 1, characterized in that: The forward voltage test and the reverse voltage test were both performed 5 times, with an interval of 500 mS between each test.

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