Prototype verification system and method for low-voltage power distribution control chip

Abstract

The invention provides a prototype verification system and method for a low-voltage power distribution control chip, and the system comprises a verification device and a simulation device, the simulation device is connected with the verification device through data, and the verification device is used for generating a test signal; the simulation device is used for storing the mapping result of the functional module in the target chip; obtaining a signal transmission constraint based on a time division multiplexing strategy, a preset physical connection line number and an original transmission signal in the target chip; and performing signal transmission on the test signal in the simulation device based on the signal transmission constraint, so that the simulation device performs signal processing on the test signal to obtain a processing result, and then the verification device obtains a prototype verification result based on the processing result. According to the method, the communication efficiency is improved, and the original transmission signal is limited in the preset number of physical connection lines, namely, different services are allowed to be processed on one physical connection line in different time intervals, so that multi-service concurrency is supported, and the number of covered service scenes is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of low-voltage power distribution control chips, and in particular to a prototype verification system and method for a low-voltage power distribution control chip. Background Art

[0002] As smart grids transition towards digitalization and intelligence, low-voltage distribution systems, the "last mile" of the power network, face unprecedented technical challenges. The explosive growth of distributed energy resources, electric vehicle charging stations, and user-side bidirectional interaction has led to a dramatic increase in node density and a highly heterogeneous mix of services in distribution networks. Traditional general-purpose processor-based control solutions have demonstrated shortcomings in dynamic environmental adaptability, multi-service collaboration, safety protection mechanisms, and energy efficiency. Distribution equipment is constantly exposed to harsh operating conditions such as strong electromagnetic interference and drastic fluctuations in temperature and humidity. The anti-interference design of existing chips makes it difficult to ensure the integrity and real-time performance of critical data (such as fault signals and harmonic parameters). Therefore, there is an urgent need for lightweight control chips that can efficiently perform data acquisition, monitoring, control, and management in low-voltage distribution, ensuring system stability and responsiveness. For example, in the event of a lightning strike or sudden load change, the communication bit error rate of general-purpose chips can soar to 10⁻³, far exceeding the 10⁻⁶ threshold required by smart grids. At the same time, smart grid services require simultaneous processing of millisecond-level data collection, edge computing (such as load forecasting and fault location), and dual-mode communication (HPLC / RF adaptive switching). Traditional serial processing architectures typically experience response delays exceeding 50ms, failing to meet the 20ms real-time requirement of technical specifications. Furthermore, cyberattacks on power monitoring systems are increasing at an average annual rate of 37%. Traditional solutions that rely on software encryption carry the risk of key leakage, with side-channel attacks having a success rate exceeding 15%, making it difficult to meet the hardware-level security requirements of security regulations. Currently, both domestic and international research and development of low-voltage power distribution chips have achieved some breakthroughs. However, while newly launched smart grid-specific SoCs have improved functional integration, their architectures are still based on general-purpose MCUs, resulting in a trade-off between redundant computing power and energy efficiency. TI chips generally have an energy efficiency rating below 1GOPS / mW, rigid communication protocols (supporting only single-mode PLC or ZigBee), and lack hardware support for dual-mode adaptive switching. While heterogeneous computing architectures recently proposed by domestic research institutions have demonstrated excellent performance in accelerating business processing and providing security isolation, significant flaws have been exposed during prototype verification.

[0003] The core difficulty in prototype verification lies in insufficient coverage of business scenarios. Existing test vectors primarily focus on functional correctness verification and lack stress testing for concurrent multi-service operations and sudden loads. A typical power distribution scenario requires the chip to complete the entire process of "data acquisition → FFT harmonic analysis → CRC check → dual-mode communication switching → security encryption" within 10ms. However, traditional FPGA verification platforms are limited by logic resources and cannot fully deploy the data pipeline, resulting in critical path timing violations not being identified in advance. Summary of the Invention

[0004] The present invention aims to provide a prototype verification system and method for a low-voltage power distribution control chip to solve the above-mentioned technical problems, improve communication efficiency, and thereby cover a larger number of business scenarios.

[0005] In order to solve the above technical problems, the present invention provides a prototype verification system for a low-voltage power distribution control chip, comprising: a verification device and a simulation device, wherein the simulation device is connected to the verification device via data, wherein:

[0006] The verification device is used to generate a test signal;

[0007] The simulation device is used to:

[0008] Storing the mapping results of the functional modules in the target chip;

[0009] Obtaining signal transmission constraints based on a time division multiplexing strategy, a preset number of physical connections, and an original transmission signal in the target chip;

[0010] The test signal is transmitted in the simulation device based on the signal transmission constraint, so that the simulation device processes the test signal to obtain a processing result, and then the verification device obtains a prototype verification result based on the processing result.

[0011] In the above scheme, the verification device is used to generate test signals to provide a basis for subsequent testing; the simulation device is used to store the mapping results of the functional modules in the target chip, thereby constructing an operational model to verify whether the target chip is feasible; the simulation device is further used to obtain signal transmission constraints based on the time division multiplexing strategy, the preset number of physical connections, and the original transmission signal in the target chip; based on the signal transmission constraints, the test signal is transmitted within the simulation device, so that the simulation device processes the test signal to obtain a processing result, and the verification device obtains a prototype verification result based on the processing result. In this way, the original transmission signal in the target chip is limited to the preset number of physical connections, more effectively utilizing the bandwidth of the communication channel, avoiding channel idleness, reducing the number of required physical connections, and making more full use of limited resources, thereby improving communication efficiency. In addition, the original transmission signal is limited to the preset number of physical connections, that is, different services can be processed on a physical connection within different time intervals, thereby supporting multi-service concurrency and increasing the number of covered business scenarios.

[0012] Furthermore, the simulation device includes an FPGA platform, a high-speed connection board and a debugging board, the FPGA platform is connected to the high-speed connection board via data, and the FPGA platform is connected to the debugging board via data, wherein:

[0013] The debugging board is used to obtain the test signal;

[0014] The FPGA platform is used to store the mapping results of the functional modules in the target chip, and obtain the signal transmission constraints based on the time division multiplexing strategy, the preset number of physical connections and the original transmission signal in the target chip, so that the high-speed connection board transmits the test signal in the FPGA platform based on the signal transmission constraints, and then the FPGA platform processes the test signal to obtain a processing result.

[0015] In the above solution, signal transmission within the FPGA platform is achieved through a high-speed connection board. The transmission process needs to follow the signal transmission constraints, thereby limiting the original transmission signal to the preset number of physical connections, allowing different services to be processed on one physical connection within different time intervals, thereby supporting multi-service concurrency and increasing the number of covered business scenarios.

[0016] Furthermore, the test signal includes an HPLC test signal and an RF test signal, and the FPGA platform includes a pre-processing FPGA unit, a core computing FPGA unit, and a post-processing FPGA unit. The pre-processing FPGA unit, the core computing FPGA unit, and the post-processing FPGA unit are mapping results of the functional modules, respectively. The FPGA platform performs signal processing on the test signal to obtain a processing result, including:

[0017] The pre-processing FPGA unit is used to pre-process the HPLC test signal to obtain an HPLC pre-processing signal, so that the high-speed connection board transmits the HPLC pre-processing signal to the core computing FPGA unit based on the signal transmission constraint;

[0018] The core computing FPGA unit is configured to perform frequency domain analysis on the HPLC preprocessing signal to obtain an HPLC target signal, and preprocess the RF test signal based on the HPLC target signal to obtain an RF target signal, so that the high-speed connection board transmits the RF target signal and the HPLC target signal to the post-processing FPGA unit;

[0019] The post-processing FPGA unit is used to perform result calibration, data compression, encryption and protocol encapsulation on the RF target signal and the HPLC target signal to obtain a processing result.

[0020] In the above scheme, the complete data processing flow is simulated through the pre-processing FPGA unit, the core computing FPGA unit, and the post-processing FPGA unit, from the data acquisition of FPGA1 to the post-processing output of FPGA3, thereby indirectly checking whether the entire process of the target chip can be completed correctly.

[0021] Furthermore, the pre-processing FPGA unit is used to pre-process the HPLC test signal to obtain an HPLC pre-processed signal, including:

[0022] Obtaining the HPLC test signal from the debugging board;

[0023] Filtering the HPLC test signal to obtain a filtered HPLC signal;

[0024] The filtered HPLC signal is normalized to obtain an HPLC preprocessed signal.

[0025] In the above solution, the pre-processing FPGA unit pre-processes the HPLC test signal to provide clean, noise-reduced data for subsequent data processing.

[0026] Furthermore, the FPGA platform also includes a global clock, which is used to generate a global clock frequency, so that the preprocessing FPGA unit preprocesses the HPLC test signal based on the global clock frequency to obtain an HPLC preprocessing signal, and then enables the core computing FPGA unit to perform frequency domain analysis on the HPLC preprocessing signal based on the global clock frequency to obtain an HPLC target signal, and preprocess the RF test signal to obtain an RF target signal.

[0027] Furthermore, the post-processing FPGA unit includes an independent clock, which is used to generate a separate clock frequency so that the post-processing FPGA unit performs result calibration, data compression and protocol encapsulation on the RF target signal and the HPLC target signal based on the separate clock frequency to obtain a processing result.

[0028] In the above scheme, the pre-processing FPGA unit and the core computing FPGA unit perform data processing based on the same global clock frequency, thereby achieving synchronous operation, and the post-processing FPGA unit performs data processing based on a separate clock frequency, thereby ensuring the security of the post-processing FPGA unit.

[0029] Furthermore, the FPGA platform is also used for:

[0030] Obtaining the computational intensities of the pre-processing FPGA unit, the core computing FPGA unit, and the post-processing FPGA unit respectively;

[0031] Based on the computing intensity and the total amount of resources, a resource allocation strategy is obtained so that the FPGA platform allocates resources to the pre-processing FPGA unit, the core computing FPGA unit and the post-processing FPGA unit based on the resource allocation strategy.

[0032] In the above solution, resources are dynamically allocated based on computing intensity, thereby meeting the computing requirements of the pre-processing FPGA unit, the core computing FPGA unit, and the post-processing FPGA unit.

[0033] Furthermore, the post-processing FPGA unit is packaged by a metal shielding cover.

[0034] In the above solution, the FPGA processing unit is securely protected by a metal shielding cover.

[0035] Furthermore, the simulation device is used to obtain signal transmission constraints based on a time division multiplexing strategy, a preset number of physical connections, and an original transmission signal in the target chip, including:

[0036] Obtaining the number of original transmission signals in the target chip;

[0037] Obtaining the number of multiplexed signals for each target physical connection based on a ratio of the preset number of physical connections to the number of original transmission signals;

[0038] Based on the preset time period and the number of multiplexed signals of each physical connection, the length of each time slice is obtained;

[0039] The signal transmission constraint is obtained based on the number of multiplexed signals and the length of the time slice.

[0040] In the above solution, by multiplexing the original transmission signal in a preset number of physical connections, each physical connection can transmit signals of different services, thereby supporting multi-service concurrency and increasing the number of covered business scenarios.

[0041] The present invention also provides a prototype verification method for a low-voltage power distribution control chip, which is implemented based on a prototype verification system for a low-voltage power distribution control chip and specifically includes the following steps:

[0042] generating a test signal by a verification device;

[0043] The mapping results of the functional modules in the target chip are stored through a simulation device; based on the time division multiplexing strategy, the preset number of physical connections and the original transmission signal in the target chip, the signal transmission constraints are obtained; based on the signal transmission constraints, the test signal is transmitted in the simulation device, so that the simulation device processes the test signal to obtain a processing result, and then the verification device obtains a prototype verification result based on the processing result.

[0044] In the above scheme, based on the above-mentioned prototype verification system of a low-voltage power distribution control chip, a verification device generates test signals to provide a basis for subsequent testing; a simulation device stores the mapping results of the functional modules in the target chip, thereby constructing an operational model to verify whether the target chip is feasible; the simulation device obtains signal transmission constraints based on the time division multiplexing strategy, the preset number of physical connections, and the original transmission signal in the target chip; based on the signal transmission constraints, the test signal is transmitted in the simulation device, so that the simulation device processes the test signal to obtain a processing result, and then the verification device obtains a prototype verification result based on the processing result. In this way, the original transmission signal in the target chip is limited to the preset number of physical connections, more effectively utilizing the bandwidth of the communication channel, avoiding channel idleness, reducing the number of required physical connections, and making more full use of limited resources, thereby improving communication efficiency. In addition, the original transmission signal is limited to the preset number of physical connections, that is, different services can be processed on a physical connection within different time intervals, thereby supporting multi-service concurrency and increasing the number of covered business scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of a prototype verification system architecture for a low-voltage power distribution control chip provided by one embodiment of the present invention;

[0046] Figure 2 A schematic diagram of the layout of an FPGA platform, a high-speed connection board, and a debugging board provided in one embodiment of the present invention;

[0047] Figure 3 A schematic diagram of the UVM verification platform architecture provided by one embodiment of the present invention;

[0048] Figure 4 A schematic flow chart of a prototype verification method for a low-voltage power distribution control chip provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0049] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0050] See Figure 1 This embodiment provides a prototype verification system for a low-voltage power distribution control chip, including: a verification device and a simulation device, the simulation device and the verification device are connected via data, wherein:

[0051] a verification device for generating a test signal;

[0052] Simulation device for:

[0053] Storing the mapping results of the functional modules in the target chip;

[0054] Based on the time division multiplexing strategy, the preset number of physical connections and the original transmission signal in the target chip, the signal transmission constraint is obtained;

[0055] The test signal is transmitted in the simulation device based on the signal transmission constraint, so that the simulation device processes the test signal to obtain a processing result, and then the verification device obtains a prototype verification result based on the processing result.

[0056] It should be noted that the verification device is used to generate test signals to provide a basis for subsequent testing; the simulation device is used to store the mapping results of the functional modules in the target chip, thereby constructing an operational model to verify whether the target chip is feasible; the simulation device is also used to obtain signal transmission constraints based on the time division multiplexing strategy, the preset number of physical connections, and the original transmission signal in the target chip; based on the signal transmission constraints, the test signal is transmitted within the simulation device, so that the simulation device processes the test signal to obtain a processing result, and then the verification device obtains a prototype verification result based on the processing result. In this way, the original transmission signal in the target chip is limited to the preset number of physical connections, more effectively utilizing the bandwidth of the communication channel, avoiding channel idleness, reducing the number of required physical connections, and making more full use of limited resources, thereby improving communication efficiency. In addition, by limiting the original transmission signal to the preset number of physical connections, different services can be processed on a single physical connection within different time intervals, thereby supporting multi-service concurrency and increasing the number of covered business scenarios.

[0057] refer to Figure 2 In another embodiment, the simulation device includes an FPGA platform, a high-speed connection board, and a debugging board, the FPGA platform and the high-speed connection board are connected via data, and the FPGA platform and the debugging board are connected via data, wherein:

[0058] Debug board, used to obtain test signals;

[0059] The FPGA platform is used to store the mapping results of the functional modules in the target chip, and obtain signal transmission constraints based on the time division multiplexing strategy, the preset number of physical connections and the original transmission signal in the target chip, so that the high-speed connection board can transmit the test signal in the FPGA platform based on the signal transmission constraints, and then the FPGA platform can process the test signal to obtain the processing result.

[0060] It should be noted that the debugging board obtains the test signal from the verification device and then sends it to the FPGA platform to verify the mapping results of the functional modules of the FPGA platform. During the verification process, the FPGA platform transmits the test signal through the high-speed connection board and signal transmission constraints. At the same time, the FPGA platform processes the test signal to obtain the processing result.

[0061] In another embodiment, the test signal includes an HPLC test signal and an RF test signal. The FPGA platform includes a pre-processing FPGA unit, a core computing FPGA unit, and a post-processing FPGA unit. The pre-processing FPGA unit, the core computing FPGA unit, and the post-processing FPGA unit are mapping results of the functional modules. The FPGA platform performs signal processing on the test signal to obtain a processing result, including:

[0062] A preprocessing FPGA unit is used to preprocess the HPLC test signal to obtain an HPLC preprocessing signal, so that the high-speed connection board transmits the HPLC preprocessing signal to the core computing FPGA unit based on the signal transmission constraint;

[0063] The core computing FPGA unit is used to perform frequency domain analysis on the HPLC preprocessing signal to obtain the HPLC target signal, and preprocess the RF test signal based on the HPLC target signal to obtain the RF target signal, so that the high-speed connection board can transmit the RF target signal and the HPLC target signal to the post-processing FPGA unit;

[0064] The post-processing FPGA unit is used to perform result calibration, data compression, encryption and protocol encapsulation on the RF target signal and the HPLC target signal to obtain the processing result.

[0065] In another embodiment, the preprocessing FPGA unit is used to preprocess the HPLC test signal to obtain the HPLC preprocessed signal, including:

[0066] Get HPLC test signal from debug board;

[0067] Filtering the HPLC test signal to obtain a filtered HPLC signal;

[0068] The filtered HPLC signal was normalized to obtain the HPLC preprocessed signal.

[0069] It should be noted that the FPGA platform is used to store the mapping results of the functional modules in the target chip, where the functional modules include the HPLC / RF dual-mode communication module, the national secret SM4 coprocessor and other above-mentioned chip prototype functional modules. Therefore, after mapping the functional modules to the FPGA platform, an FPGA array is obtained. The FPGA array includes a pre-processing FPGA unit, a core computing FPGA unit and a post-processing FPGA unit. Below, FPGA1 is the pre-processing FPGA unit, FPGA2 is the core computing FPGA unit, and FPGA3 is the post-processing FPGA unit. For example, the HPLC modulator (2-30MHz) is deployed to FPGA1, and the RF transceiver (470-510MHz) is deployed to FPGA2. Although the actual frequency bands do not overlap, there may be harmonic interference, so they are deployed separately to reduce cross-domain signal interference. At the same time, the security domain is centralized, integrating the national secret SM4 coprocessor and PUF key generation unit into FPGA3. Their computing tasks are as follows: Preprocessing stage (FPGA1): Preprocesses the HPLC test signal, such as data acquisition, noise filtering, and normalization, to obtain the HPLC preprocessed signal. This signal is then processed using the HPLC modulator's low-speed, high-precision ADC interface (sampling error <0.1%) and differential routing (spacing ≥3W) to ensure signal integrity. Core computing stage (FPGA2): Executes an FFT algorithm to perform frequency domain analysis on the transmitted HPLC preprocessed signal to obtain the HPLC target signal. This converts the HPLC preprocessed signal to the frequency domain to obtain harmonic characteristics, thereby identifying any anomalies. This signal is then processed collaboratively with the RF transceiver (470-510MHz) to process multi-channel signals. The RF test signal received by the RF transceiver is preprocessed based on the HPLC target signal to obtain the RF target signal. This converts the HPLC target signal to the frequency domain, adjusting the RF communication strategy, such as avoiding interference bands. It is understood that the RF target signal can also be converted to the frequency domain using the FFT, facilitating subsequent verification of RF receiver anomalies. Post-processing stage (FPGA3): Result calibration, data compression, and protocol encapsulation are performed on the HPLC and RF target signals to obtain the processing results. By simulating the complete data processing flow, from data acquisition on FPGA1 to post-processing output on FPGA3, the correct completion of the entire process is verified. This includes verification of the acquisition of HPLC test signals by the HPLC modulator in FPGA1, the acquisition of RF test signals by the RF transceiver, signal transmission between FPGA1, FPGA2, and FPGA3 based on signal transmission constraints, and encryption on FPGA3.

[0070] Furthermore, the FFT used for frequency domain analysis is mapped to the edge computing module in the target chip. The edge computing module is responsible for performing fast Fourier transform (FFT) on high-speed signals (such as data collected by HPLC and RF transceivers) to extract harmonic characteristics.

[0071] Furthermore, a blank area (200μm) is reserved around FPGA1, FPGA2, and FPGA3 to prevent signal interference. The connection between FPGAs uses a high-speed connection board, which carries TDM multiplexed signals on each channel through the GTY high-speed serial interface (16Gbps). It is understood that the high-speed connection board includes high-speed connection board 1, high-speed connection board 2, and high-speed connection board 3. FPGA1 outputs a TDM multiplexed signal that complies with signal transmission constraints through the TDM controller, and reaches high-speed connection board 1 through the GTY differential pair 1 interface. The TDM multiplexed signal is then transmitted to high-speed connection board 2. High-speed connection board 2 transmits the TDM multiplexed signal to FPGA2 through GTY differential pair 2. FPGA2 removes the signal transmission constraints through TDM demultiplexing logic and normally interacts with FPGA3 through high-speed connection board 3 to avoid affecting the security of FPGA3. It is understandable that based on the specific interaction content between FPGA1 and FPGA2, the TDM multiplexed signal can be used to refer to multiple signals. Debugging of FPGA1, FPGA2, and FPGA3 is performed through JTAG and serial ports. The debug interface includes an LED to indicate the current working status.

[0072] Furthermore, the debug board includes multiple debug interface groups: debug interface group 1, debug interface group 2, and debug interface group 3. These multiple debug interface groups correspond to FPGA1, FPGA2, and FPGA3. The following is a verification of HPLC / RF dual-mode communication based on the FPGA platform, high-speed connection board, and debug interface, thereby verifying whether the target chip HPLC / RF dual-mode communication can switch normally:

[0073] The input test signals include: analog signals: analog signals generated by a signal generator, used to test HPLC communication; digital signals: test sequences generated by the UVM verification platform, used to control communication mode switching and verify RF communication; communication mode switching instructions: control instructions sent through the SPI interface, used to trigger switching between HPLC and RF.

[0074] (1) Initialize the test environment:

[0075] Connect the signal generator to the HPLC interface of FPGA1; connect the RF signal generator and receiver to the RF interface of FPGA2; and connect the debug board to the UVM verification platform to generate test sequences and monitor signals.

[0076] Configure the UVM verification platform to generate a test sequence. Configure the initial states of FPGA1 and FPGA2 to ensure they are in HPLC communication mode.

[0077] (2) Perform HPLC communication test:

[0078] Generate a known HPLC signal through a signal generator and input it to the HPLC modulator interface of FPGA1 through JTAG1.

[0079] FPGA1 receives and processes the HPLC signal and inputs it to FPGA2. FPGA2 receives the processed signal and transmits the data to an external verification device for analysis through the interface of the debug board. The verification device verifies whether the received HPLC data is consistent with the sent data.

[0080] (3) Triggering communication mode switching:

[0081] Sending a switching command: The UVM verification platform generates a switching command and sends it to FPGA1 through the debug board, triggering the switch from HPLC mode to RF mode. A logic analyzer monitors the internal signals of FPGA1 and FPGA2 through the JTAG1 and JTAG2 interfaces on the debug board, recording key signal waveforms during the switching process. LED1 and LED2 indicators on the debug board confirm that FPGA1 and FPGA2 have successfully switched to RF mode.

[0082] (4)RF communication test:

[0083] An RF signal generator generates an RF signal and inputs it to the RF transceiver interface of FPGA2 via JTAG2. FPGA2 receives and processes the RF signal, which is then input to FPGA3. FPGA3 then receives the processed RF signal and transmits the data to the verification device for analysis via the interface of the debug board. The verification device verifies that the RF data received is consistent with the data sent.

[0084] Then continue to trigger the communication mode switch and switch back to HPLC mode. Use the logic analyzer to monitor the internal signals of FPGA1 and FPGA2 through the JTAG interface, record the key signal waveforms during the switching process, and use the LED1 and LED2 indicators to confirm whether FPGA1 and FPGA2 have successfully switched back to HPLC mode.

[0085] By using a logic analyzer to measure the time from sending the switching instruction to completing the switching, ensure that the switching time meets the design requirements, and compare the data received before and after the switching to ensure that there is no data loss or error during the switching process. Thus, the verification of the HPLC / RF dual-mode communication switching is completed. It is understandable that the LED1 and LED2 indicator lights are used to confirm whether FPGA1 and FPGA2 have been successfully switched. For example, LED2 displays green when switching to RF mode, and LED1 displays green when switching back to HPLC mode. In addition, the operating data of FPGA1 and FPGA2 during the HPLC / RF dual-mode communication process can also be sent to the verification device for monitoring through serial port 1 and serial port 2. It is understandable that, in the above, HPLC signals, switching instructions, and RF signals are all test signals.

[0086] Furthermore, the following demonstrates the security verification of FPGA3 based on the FPGA platform, high-speed connection board, and debug interface, thereby verifying whether any abnormalities exist in the target chip's security-related functional modules: The test signal includes a security test signal. The ambient temperature of the FPGA platform is adjusted, and a security test signal is sent to FPGA3 via serial port 3 in debug interface group 3, triggering the SM4 coprocessor to execute encryption tasks. Serial port 3 is used to obtain the key digest generated by the PUF based on a preset period and send it to the verification device. This digest is then compared with the output value at normal temperature, thus performing a high-temperature stress test on FPGA3. A high-precision power consumption acquisition module can also be used to simulate a differential power consumption attack (DPA) as a test signal to verify the protection capabilities of the security domain (such as the SM4 coprocessor in FPGA3). The power consumption trace is read via the JTAG3 interface, allowing the verification device to check whether the trace can conceal critical information, ensuring an attack success rate of less than 0.1%. Furthermore, LED 3 can be used to determine whether FPGA3 is operating normally, preventing malfunctions.

[0087] Furthermore, the FPGA 1 further includes an ADC interface, which is used for sampling. The sampling accuracy of the ADC can be obtained through the debugging board to verify whether there is a problem with the sampling of the ADC interface.

[0088] Furthermore, FPGA1 includes a TDM controller, and FPGA2 integrates TDM demultiplexing logic to implement signal transmission constraints. That is, signal transmission constraints are used to limit the process of signal interaction between FPGA1 and FPGA2 through the high-speed connection board. Because FPGA3 is a security module, the time division multiplexing strategy allows multiple service signals to be transmitted on one physical connection, which may affect the security of FPGA3. Therefore, TDM demultiplexing logic is integrated in FPGA2 to restore the signal communication between FPGA2 and FPGA3 to the original signal transmission method.

[0089] In another embodiment, the FPGA platform also includes a global clock, which is used to generate a global clock frequency, so that the preprocessing FPGA unit preprocesses the HPLC test signal based on the global clock frequency to obtain an HPLC preprocessing signal, and then enables the core computing FPGA unit to perform frequency domain analysis on the HPLC preprocessing signal based on the global clock frequency to obtain an HPLC target signal, and preprocess the RF test signal to obtain an RF target signal.

[0090] In another embodiment, the post-processing FPGA unit includes an independent clock, which is used to generate a separate clock frequency so that the post-processing FPGA unit performs result calibration, data compression and protocol encapsulation on the RF target signal and the HPLC target signal based on the separate clock frequency to obtain a processing result.

[0091] It should be noted that FPGA1 and FPGA2 use a global clock, synchronizing all functional modules in FPGA1 and FPGA2 based on the same global clock frequency. This ensures global synchronization and facilitates design and verification. However, FPGA3, as the security core, uses an independent clock domain with jitter less than 10ps RMS, preventing global clock skew from affecting timing and optimizing the local clock tree.

[0092] In another embodiment, the post-processing FPGA unit is encapsulated by a metal shield.

[0093] It should be noted that FPGA3, as a security core, is encapsulated in a metal shield to prevent electromagnetic radiation leakage and reduce the risk of side-channel attacks.

[0094] In another embodiment, the FPGA platform is further configured to:

[0095] Obtain the computational intensities of the pre-processing FPGA unit, the core computation FPGA unit, and the post-processing FPGA unit respectively;

[0096] Based on the computing intensity and the total amount of resources, a resource allocation strategy is obtained so that the FPGA platform allocates resources to the pre-processing FPGA unit, the core computing FPGA unit and the post-processing FPGA unit based on the resource allocation strategy.

[0097] It should be noted that the FPGA programmable logic resources serve as a dynamically partitioned physical carrier, split into three pipeline stages based on data flow: pre-processing (FPGA1), core computation (FPGA2), and post-processing (FPGA3). Resource utilization and processing efficiency are optimized based on data flow characteristics. Dynamic resource allocation is achieved through hardware resource pooling and real-time load balancing. Hardware resource pooling divides the FPGA's programmable resources (LUTs, DSP, and BRAM) into multiple "virtual computing units" and allocates them to different computational stages (pre-processing, core computation, and post-processing) based on the computational intensity of the pre-processing FPGA unit, core computation FPGA unit, and post-processing FPGA unit. For example, during peak FFT computation, the core computation stage is inherently computationally intensive. Therefore, the DSP slice allocation ratio of FPGA2 is dynamically adjusted (from the default 50% to 80%), enabling FPGA2 to complete tasks more efficiently. Real-time load balancing uses an embedded soft core (such as MicroBlaze) to monitor the resource utilization and data queue depth of each FPGA unit in real time. For example, when FPGA2's DSP utilization exceeds 90%, dynamic task migration is triggered.

[0098] In another embodiment, a simulation device, configured to obtain a signal transmission constraint based on a time division multiplexing strategy, a preset number of physical lines, and an original transmission signal in a target chip, includes:

[0099] Obtain the number of original transmission signals in the target chip;

[0100] Based on the ratio of the preset number of physical connections and the number of original transmission signals, the number of multiplexed signals of each target physical connection is obtained;

[0101] Based on the preset time period and the number of multiplexed signals of each physical connection, the length of each time slice is obtained;

[0102] Based on the number of multiplexed signals and the length of the time slice, signal transmission constraints are obtained.

[0103] It should be noted that m:1 time division multiplexing (TDM) is used for the signals transmitted across units between FPGA1 and FPGA2, and the number of physical connections used to transmit the signals is compressed to 1 / m% of the original design, thereby saving costs and improving the utilization efficiency of the physical connections, more effectively utilizing the bandwidth of the communication channel, avoiding idle physical connection channels, reducing the number of required physical connections, and making more full use of limited resources, thereby improving communication efficiency and allowing different services to be processed on one physical connection within different time intervals, thereby supporting multi-service concurrency and increasing the number of covered business scenarios. For example, assuming that the number of original transmission signals is k, the preset number of physical connections is n, k / n is the number of multiplexed signals for each target physical connection, that is, the number of multiplexed signals that can be used to transmit each target physical connection, assuming that the preset time period is T, and the number of multiplexed signals for each physical connection is k / n, then the length of each time slice is That is, target physical connection 1 transmits signal 1 in time slot 1, signal 2 in time slot 2, and so on, and transmits signal k / n in time slot k / n. Target physical connection 2 transmits signals 1+k / n in time slot 1, signal 2+k / n in time slot 2, and so on, up to target physical connection n. Signal transmission constraints limit the number of multiplexed signals and the length of the time slot for each physical connection. Signals transmitted across units between FPGA1 and FPGA2 must comply with these constraints.

[0104] Furthermore, TDM insertion and optimization: control signals (SPI configuration signals, etc.) use 2:1 TDM with a multiplexing period of 20ns; high-speed data (ADC sampling streams, etc.) use 4:1 TDM with a multiplexing period of 5ns; the eye opening of the TDM channel is simulated through the IBIS model (>0.7UI) to ensure signal integrity.

[0105] Critical path preservation strategy: The Turbo code iterative decoder and SM4's S-box conversion unit are deployed on FPGA3 to enclose timing-sensitive modules and configure an independent PLL for the encryption module.

[0106] Furthermore, layout and routing constraints were applied to the FPGA platform and high-speed connection board, improving resource utilization and reducing critical path latency through refined constraints. Specifically, the communication modules were centrally arranged, with blank areas reserved around the RF transceiver modules as shielded isolation zones. The routing rules were optimized as follows:

[0107] Differential pair matching: The ADC differential pair is located close to the HP Bank (High-Performance I / O Bank) of FPGA1 to shorten the analog signal path. A 100Ω differential impedance is added to the high-speed connection board (FR4 stackup: 5-mil trace width, 10-mil spacing, 8-mil dielectric thickness). A 100Ω termination resistor is deployed on the receiving end (FPGA1 side). The P / N signal trace length difference within the differential pair is ≤5 mil, and the phase error is <1°. Ground shield vias are added on both sides of the ADC differential pair, with a spacing of ≤λ / 10 (λ is the highest frequency wavelength). The analog ADC power supply (AVDD) and the digital power supply (DVDD) are isolated by a ferrite bead and π-type filter, with a ripple of <10mV.

[0108] Crosstalk suppression: The spacing between adjacent signal lines is ≥ 3 times the line width (3W rule); the parallel wiring of high-speed buses (>100MHz) is ≤ 500μm.

[0109] By using functional module mapping, hardware resource pooling, dynamic resource partitioning strategy and time-division multiplexing mechanism, the utilization of LUTs and FFs is balanced, which improves the utilization of FPGA resources. By reducing routing congestion and timing violations, the performance and reliability of the chip prototype in complex power distribution scenarios are significantly enhanced.

[0110] In another embodiment, a design that has undergone logic synthesis and place-and-route is converted into an FPGA-executable bitstream file and optimized for multi-FPGA collaboration. The specific process for programming download and system configuration includes: The target bitstream generation rules retain the original place-and-route results for unmodified modules (such as ADC drivers), reducing compilation time; defining reconfigurable partitions (RPs) for the RF band select module (470 / 485 / 510MHz) to support in-field band switching; and multi-FPGA collaborative optimization to ensure cross-chip timing constraints.

[0111] The JESD204B protocol is used to synchronize multiple FPGA clocks, calibrate the global clock tree, and configure the initial parameters of the temperature sensor (MAX31826) and noise injection module through the SPI interface.

[0112] Read back the bitstream via the JTAG interface and calculate the CRC32 checksum (which must be consistent with the original file). Generate a .twr file and confirm that all path setup / hold time margins are ≥ 0.5ns. Verify and debug by reading internal signal waveforms in real time via the virtual JTAG online monitoring interface and observing key signal waveforms using trigger conditions set on the embedded logic analyzer (ILA).

[0113] In another embodiment, the verification device obtains the prototype verification result based on the processing result, including:

[0114] In order to establish a comprehensive verification system covering functional correctness, performance boundaries, safety mechanisms, extreme working conditions, multi-service concurrency, security attacks and other scenarios, and ensure the reliability and robustness of the chip in complex power distribution scenarios, the verification level can be divided into the following categories: hierarchical unit level, verification content: module logic function (such as ADC interface, SI4 core), tools + methods: UVIM + Verdi waveform analysis; subsystem level, verification content: multi-module collaboration (such as dual-mode switching control chain), tools + methods: FPGA prototype + ILA online debugging; system level, verification content: end-to-end business flow (metering → encryption → communication), tools + methods: real load simulation + power consumption monitoring; security special, verification content: side channel attack defense, fault injection fault tolerance, tools + methods: dedicated probe station + EM scanner.

[0115] Key verification scenarios include extreme operating condition testing and concurrent stress testing. Extreme operating conditions include maintaining ADC sampling accuracy under voltage fluctuations (±20% VDD) and SM4 throughput during temperature shock (-40°C → +85°C cycle); concurrent stress tests include simulating communication conflicts when 256 nodes are connected simultaneously and DVFS response time under burst load (0→100% step).

[0116] Among them, the UVM verification platform architecture is as follows Figure 3As shown, the top-level structure is Testbench Top, which includes UVM Test and UVM Env. Together, they form the logical framework of the verification platform. The physical layer connects to the DUT via interfaces. UVM Test is the test control layer, which can call different test cases according to the verification plan, set parameters such as the ADC sampling rate and RF communication frequency band, and initiate sequence execution. UVM Env is the verification environment container, which contains all verification functional components: the Agent cluster, Virtual Sequencer, Scoreboard, and Coverage Collector. It integrates interface driver, monitoring, and verification modules to form a complete verification loop and provides a configuration database to support cross-component parameter transfer. Each Agent corresponds to a DUT interface (such as the Agent (ADC) interface and the Agent (RF) interface). It internally includes a Driver, Monitor, and Sequencer. The DUT interface can be used to connect to the ADC, SM4, RF, etc. The Driver converts the transactions generated by the Sequence into interface signals; the Monitor captures the DUT output in real time, converts it into transactions, and sends them to the Scoreboard; the Sequencer manages the execution order of the Sequences and supports priority scheduling. The Virtual Sequencer does not drive the signal directly, but it associates the Sequencer of multiple Agents through handles to coordinate the timing synchronization across interfaces (such as triggering RF transmission after ADC sampling is completed) to support concurrent execution of complex scenarios. The Scoreboard is independent of the Agent, but receives transactions sent by all Monitors. It is responsible for comparing the DUT output with the reference model and detecting abnormal behavior. The Assert Checker is used for real-time verification and error detection of the DUT. The Coverage Collector is parallel to the Scoreboard, receives transactions from the Monitor, defines coverage groups, calculates functional coverage and code coverage, generates coverage reports, and guides the supplementation of test cases. The power distribution chip verification process is as follows:

[0117] (1) Scenario configuration: Test selects the test mode (measurement accuracy test, dual-mode switching pressure test, etc.);

[0118] (2) Incentive generation: Sequence generates transactions that meet the characteristics of the power distribution business;

[0119] (3) Interface driver: Driver converts the transaction into physical signals to drive the DUT;

[0120] (4) Response capture: Monitor collects DUT output and converts it into transaction;

[0121] (5) Result analysis: Scoreboard performs data verification, and Coverage Collector performs coverage statistics;

[0122] (6) Regression testing: All test cases are automatically executed through Jenkins and reports are generated.

[0123] Embedding an ILA (Integrated Logic Analyzer) core in the FPGA logic supports real-time capture of key signal waveforms (such as HPLC modulation signals); using MicroBlaze software to collect logic resource utilization, memory queue depth, and power consumption traces in real time and provide test information; inserting virtual probes to monitor internal bus status in real time allows for rapid identification of design defects and closed-loop repairs. For example, the following are some typical problems and solutions:

[0124] Problem phenomenon: Dual-mode switching timeout, root cause analysis: state machine priority conflict, solution: restructure switching logic and add arbitration mechanism; Problem phenomenon: SM4 encryption result occasional error, root cause analysis: insufficient critical path timing margin, solution: insert pipeline stage + increase power supply voltage; Problem phenomenon: RF receiving sensitivity does not meet the standard, root cause analysis: LNA impedance matching deviation, solution: adjust PCB matching network (srmith circle diagram optimization); Problem phenomenon: secure boot signature failure, root cause analysis: insufficient PUF entropy source stability, solution: add pre-conditioning circuit + post-processing algorithm.

[0125] This application achieves a systematic breakthrough in mixed signal verification efficiency, dynamic environment adaptability, and security protection level through the deep integration of multi-FPGA collaborative architecture and virtualized IO interface. Based on the timing-driven intelligent segmentation algorithm and 4:1 time division multiplexing (TDM) technology, dual-mode communication, security encryption, and edge computing modules are efficiently mapped to the FPGA array, reducing the cross-domain signal interaction delay to less than 5μs, which is 3 times faster than the traditional serial architecture. At the same time, the FPGA resource utilization rate is increased by 40% through hardware resource pooling and dynamic load balancing mechanism. Combining the mixed signal interface with the dynamic environment simulator, it accurately reproduces harsh working conditions such as strong electromagnetic interference (100V / m field strength), sudden changes in temperature and humidity (-40℃~85℃ cycle), and voltage fluctuation (±20% VDD). The measured bit error rate is compressed from 2 orders of magnitude to less than 5% compared with the simulation value, ensuring that the ADC sampling accuracy still maintains 12 effective bits in extreme environments. The SM4 encryption throughput is stable at 5000 times / second, and the entropy of the PUF key is greater than 0.99. In the field of security verification, through the centralized security domain architecture and metal shield packaging technology, combined with high-precision attack simulation (laser injection positioning accuracy of ±10μm) and independent clock domain design (jitter <10ps RMS), the success rate of side-channel attacks is suppressed to below 0.1%, and the communication switching success rate is increased to 99.9%, meeting the EMVCo L4 level protection standard. In addition, based on the UVM verification platform and the embedded ILA logic analyzer, the automated test system achieves full coverage verification of 256 concurrent nodes, sudden load steps, and multi-service conflict scenarios. The code coverage rate exceeds 94%, the debugging efficiency is increased by 3 times, and the regression test cycle is shortened by 60%. It provides a chip verification solution for smart grid construction with high environmental adaptability (temperature change tolerance increased by 70%), strong real-time performance (20ms level response) and hardware-level security protection capabilities, effectively promoting the reliable deployment and technological iteration of distribution equipment under complex working conditions.

[0126] See Figure 4 This embodiment also provides a prototype verification method for a low-voltage power distribution control chip, comprising the following steps:

[0127] Step S1: Generate a test signal through a verification device;

[0128] Step S2: The mapping results of the functional modules in the target chip are stored through the simulation device; based on the time division multiplexing strategy, the preset number of physical connections and the original transmission signal in the target chip, the signal transmission constraint is obtained; based on the signal transmission constraint, the test signal is transmitted in the simulation device, so that the simulation device processes the test signal to obtain the processing result, and then the verification device obtains the prototype verification result based on the processing result.

[0129] This embodiment provides a prototype verification system based on the above-mentioned low-voltage power distribution control chip. The verification device generates test signals to provide a basis for subsequent testing. The simulation device stores the mapping results of the functional modules in the target chip, thereby constructing an operational model to verify whether the target chip is feasible. The simulation device obtains signal transmission constraints based on the time division multiplexing strategy, the preset number of physical connections, and the original transmission signal in the target chip. Based on the signal transmission constraints, the test signal is transmitted in the simulation device so that the simulation device processes the test signal to obtain a processing result, and the verification device obtains a prototype verification result based on the processing result. In this way, the original transmission signal in the target chip is limited to the preset number of physical connections, more effectively utilizing the bandwidth of the communication channel, avoiding channel idleness, reducing the number of required physical connections, and making more full use of limited resources, thereby improving communication efficiency. In addition, the original transmission signal is limited to the preset number of physical connections, that is, different services can be processed on a physical connection within different time intervals, thereby supporting multi-service concurrency and increasing the number of covered business scenarios.

[0130] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A prototype verification system for a low-voltage power distribution control chip, characterized in that: include: A verification device and a simulation device, wherein the simulation device is connected to the verification device via data, wherein: The verification device is used to generate a test signal; The simulation device is used to: Storing the mapping results of the functional modules in the target chip; Obtaining signal transmission constraints based on a time division multiplexing strategy, a preset number of physical connections, and an original transmission signal in the target chip; The test signal is transmitted in the simulation device based on the signal transmission constraint, so that the simulation device processes the test signal to obtain a processing result, and then the verification device obtains a prototype verification result based on the processing result.

2. A prototype verification system for a low-voltage power distribution control chip according to claim 1, characterized in that: The simulation device includes an FPGA platform, a high-speed connection board and a debugging board, wherein the FPGA platform is connected to the high-speed connection board via data, and the FPGA platform is connected to the debugging board via data, wherein: The debugging board is used to obtain the test signal; The FPGA platform is used to store the mapping results of the functional modules in the target chip, and obtain the signal transmission constraints based on the time division multiplexing strategy, the preset number of physical connections and the original transmission signal in the target chip, so that the high-speed connection board transmits the test signal in the FPGA platform based on the signal transmission constraints, and then the FPGA platform processes the test signal to obtain a processing result.

3. A prototype verification system for a low-voltage power distribution control chip according to claim 2, characterized in that: The test signal includes an HPLC test signal and an RF test signal. The FPGA platform includes a pre-processing FPGA unit, a core computing FPGA unit, and a post-processing FPGA unit. The pre-processing FPGA unit, the core computing FPGA unit, and the post-processing FPGA unit are mapping results of the functional modules. The FPGA platform performs signal processing on the test signal to obtain a processing result, including: The pre-processing FPGA unit is used to pre-process the HPLC test signal to obtain an HPLC pre-processing signal, so that the high-speed connection board transmits the HPLC pre-processing signal to the core computing FPGA unit based on the signal transmission constraint; The core computing FPGA unit is configured to perform frequency domain analysis on the HPLC preprocessing signal to obtain an HPLC target signal, and preprocess the RF test signal based on the HPLC target signal to obtain an RF target signal, so that the high-speed connection board transmits the RF target signal and the HPLC target signal to the post-processing FPGA unit; The post-processing FPGA unit is used to perform result calibration, data compression, encryption and protocol encapsulation on the RF target signal and the HPLC target signal to obtain a processing result.

4. A prototype verification system for a low-voltage power distribution control chip according to claim 3, characterized in that: The preprocessing FPGA unit is used to preprocess the HPLC test signal to obtain an HPLC preprocessing signal, including: Obtaining the HPLC test signal from the debugging board; Filtering the HPLC test signal to obtain a filtered HPLC signal; The filtered HPLC signal is normalized to obtain an HPLC preprocessed signal.

5. The prototype verification system of a low-voltage power distribution control chip according to claim 3, characterized in that: The FPGA platform also includes a global clock, which is used to generate a global clock frequency, so that the preprocessing FPGA unit preprocesses the HPLC test signal based on the global clock frequency to obtain an HPLC preprocessing signal, and then enables the core computing FPGA unit to perform frequency domain analysis on the HPLC preprocessing signal based on the global clock frequency to obtain an HPLC target signal, and preprocess the RF test signal to obtain an RF target signal.

6. A prototype verification system for a low-voltage power distribution control chip according to claim 3, characterized in that: The post-processing FPGA unit includes an independent clock, which is used to generate a separate clock frequency so that the post-processing FPGA unit performs result calibration, data compression and protocol encapsulation on the RF target signal and the HPLC target signal based on the separate clock frequency to obtain a processing result.

7. The prototype verification system of a low-voltage power distribution control chip according to claim 3, characterized in that: The FPGA platform is also used for: Obtaining the computational intensities of the pre-processing FPGA unit, the core computing FPGA unit, and the post-processing FPGA unit respectively; Based on the computing intensity and the total amount of resources, a resource allocation strategy is obtained so that the FPGA platform allocates resources to the pre-processing FPGA unit, the core computing FPGA unit and the post-processing FPGA unit based on the resource allocation strategy.

8. The prototype verification system of a low-voltage power distribution control chip according to claim 3, characterized in that: The post-processing FPGA unit is encapsulated by a metal shielding cover.

9. The prototype verification system of a low-voltage power distribution control chip according to claim 1, characterized in that: The simulation device is used to obtain signal transmission constraints based on a time division multiplexing strategy, a preset number of physical connections, and an original transmission signal in the target chip, including: Obtaining the number of original transmission signals in the target chip; Obtaining the number of multiplexed signals for each target physical connection based on a ratio of the preset number of physical connections to the number of original transmission signals; Based on the preset time period and the number of multiplexed signals of each physical connection, the length of each time slice is obtained; The signal transmission constraint is obtained based on the number of multiplexed signals and the length of the time slice.

10. A prototype verification method for a low-voltage power distribution control chip, characterized in that: The prototype verification system based on a low-voltage power distribution control chip is implemented, which specifically includes the following steps: generating a test signal by a verification device; The mapping results of the functional modules in the target chip are stored through a simulation device; based on the time division multiplexing strategy, the preset number of physical connections and the original transmission signal in the target chip, the signal transmission constraints are obtained; based on the signal transmission constraints, the test signal is transmitted in the simulation device, so that the simulation device processes the test signal to obtain a processing result, and then the verification device obtains a prototype verification result based on the processing result.

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