A semiconductor device etching method

Abstract

The application provides a semiconductor device etching method, which comprises the following steps: providing a preset substrate; wherein the preset substrate comprises a conductor layer; a conductor layer etching step, wherein chlorine-containing gas is introduced into a reaction chamber as etching gas, and the conductor layer is etched with the upper film layer of the conductor layer as a mask until the next film layer is exposed; and a de-excitation step, wherein the upper electrode power and the lower electrode power are both controlled to be off, and a passivation gas is introduced into the reaction chamber; wherein the passivation gas comprises hydrogen-containing gas. After the conductor layer is etched, the de-excitation step is added, the upper electrode power and the lower electrode power are both controlled to be zero, the accumulated electric charge on the wafer surface in the conductor layer etching step is neutralized, the electric field distribution on the wafer surface is more uniform, the hydrogen-containing gas is introduced into the chamber as the passivation gas, the interface defect of the gate oxide layer in the semiconductor device is passivated, the uniformity of the threshold voltage of the P-type transistor is optimized, and the product yield is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device etching method. Background Technology

[0002] In integrated circuit manufacturing, dry etching is an essential method for device fabrication, allowing for precise control over the desired device morphology and ensuring its electrical performance. Aluminum (Al), with its low resistivity, low cost, and ease of etching, has become a core structure for achieving electrical and physical connections between chips and external circuits. Currently, to ensure etching precision, dry etching technology is commonly used to etch Al substrates, with photoresist serving as a mask. The threshold voltage (VT) of a P-type transistor (a MOSFET with an n-type substrate, p-channel, and current carried by hole flow) is the core bridge connecting the device's physical characteristics and circuit function, directly affecting the chip's power consumption, speed, noise margin, and reliability. The uniformity of the P-type transistor threshold voltage is one of the core challenges in modern chip design and manufacturing. Poor threshold voltage uniformity leads to inconsistent turn-on / turn-off speeds among different P-type transistors within the same chip, causing logic gate delay differences (such as clock skew or race conditions), disrupting timing synchronization, and in severe cases, causing functional errors. However, during the etching process of aluminum pads, plasma-induced damage to P-type MOSFETs is prone to occur. High-energy ions generated during etching may penetrate the gate oxide layer and form charge traps or interface states in the oxide layer. P-type MOSFETs are sensitive to positive charges, and the accumulation of positive charges will cause the voltage threshold to shift negatively. At the same time, ultraviolet photons or electron bombardment in the plasma may weaken the integrity of the gate oxide layer, resulting in increased leakage current and voltage threshold drift. This leads to poor uniformity of the threshold voltage of P-type transistors and reduces product yield. Summary of the Invention

[0003] In view of this, the purpose of the present invention is to provide a semiconductor device etching method that can significantly improve the uniformity of the threshold voltage of P-type transistors and improve product yield.

[0004] To achieve the above objectives, the technical solutions adopted in the embodiments of the present invention are as follows:

[0005] In a first aspect, embodiments of the present invention provide a semiconductor device etching method, comprising:

[0006] A preset substrate is provided; wherein the preset substrate includes a conductor layer;

[0007] In the conductor layer etching step, chlorine-containing gas is introduced into the reaction chamber as the etching gas, and the conductor layer is etched using the upper film layer as a mask until the next film layer is exposed.

[0008] In the extinguishing step, both the upper and lower electrode power are turned off, and a passivation gas is introduced into the reaction chamber; wherein, the passivation gas includes hydrogen-containing gas.

[0009] Furthermore, the present invention provides a first possible implementation of the first aspect, wherein the passivation gas includes a nitrogen-containing gas and a hydrogen-containing gas, the nitrogen-containing gas including nitrogen gas, and the hydrogen-containing gas including hydrogen gas or ammonia gas.

[0010] Furthermore, this embodiment of the invention provides a second possible implementation of the first aspect, wherein the nitrogen-containing gas includes nitrogen gas and the hydrogen-containing gas includes hydrogen gas;

[0011] The flow rate ratio of nitrogen to hydrogen is 2:1 to 3:1.

[0012] Furthermore, the present invention provides a third possible implementation of the first aspect, wherein the preset substrate further includes a photoresist layer located above the conductive layer;

[0013] Prior to the conductor layer etching step, the semiconductor device etching method further includes:

[0014] In the photoresist etching step, oxygen-containing gas is introduced into the reaction chamber to etch the photoresist layer until the next film layer is exposed.

[0015] Furthermore, this embodiment of the invention provides a fourth possible implementation of the first aspect, wherein the preset substrate further includes a dielectric anti-reflection layer located between the photoresist layer and the conductive layer;

[0016] Following the conductor layer etching step, the semiconductor device etching method further includes:

[0017] In the dielectric antireflection layer etching step, chlorine-containing gas is introduced into the reaction chamber, and the dielectric antireflection layer is etched using the photoresist layer as a mask until the conductor layer is exposed.

[0018] Furthermore, the present invention provides a fifth possible implementation of the first aspect, wherein the preset substrate further includes a metal bonding layer located below the conductive layer;

[0019] Following the conductor layer etching step, the semiconductor device etching method further includes:

[0020] In the metal bonding layer etching step, chlorine-containing gas is introduced into the reaction chamber as an etching gas, and the metal bonding layer is etched using the conductor layer as a mask until the next film layer is exposed.

[0021] Furthermore, the present invention provides a sixth possible implementation of the first aspect, wherein the preset substrate further includes a metal barrier layer and an etching stop layer located below the metal bonding layer;

[0022] Following the conductor layer etching step, the semiconductor device etching method further includes:

[0023] In the metal barrier layer etching step, chlorine-containing gas is introduced into the reaction chamber as an etching gas, and the metal barrier layer is etched using the metal bonding layer as a mask until the etching stop layer is exposed.

[0024] Furthermore, this embodiment of the invention provides a seventh possible implementation of the first aspect, wherein the method further includes:

[0025] The preset substrate, after completing the metal barrier layer etching step, is passed into the photoresist removal chamber. Hydrogen-containing gas and oxygen-containing gas are introduced into the photoresist removal chamber to remove the photoresist layer and residual chloride ions from the preset substrate after completing the metal barrier layer etching step.

[0026] Furthermore, this invention provides an eighth possible implementation of the first aspect, wherein the step of introducing hydrogen-containing gas and oxygen-containing gas into the deresin chamber to remove the photoresist layer and residual chloride ions from the preset substrate after the metal barrier layer etching step is completed includes:

[0027] In the chloride ion removal step, the desizing chamber is controlled at a first pressure, and hydrogen-containing gas is introduced into the desizing chamber to remove the chloride ions remaining in the preset substrate after the metal barrier layer etching step is completed.

[0028] In the first photoresist layer removal step, the desizing chamber is controlled at a second pressure, and oxygen-containing gas and hydrogen-containing gas are introduced into the desizing chamber to etch and remove the photoresist layer and residual chloride ions; wherein, the second pressure is less than the first pressure, and the flow rate of hydrogen-containing gas in the first photoresist layer removal step is less than the flow rate of hydrogen-containing gas in the chloride ion removal step.

[0029] In the second photoresist layer removal step, the desizing chamber is controlled at a second pressure, and oxygen-containing gas is introduced into the desizing chamber to etch and remove the photoresist layer and residual chloride ions; wherein, the proportion of oxygen-containing gas introduced in the second photoresist layer removal step is greater than the proportion of oxygen-containing gas introduced in the first photoresist layer removal step.

[0030] Furthermore, the present invention provides a ninth possible implementation of the first aspect, wherein, in the conductor layer etching step and / or the metal bonding layer etching step, the chlorine-containing gas includes BCl3 and Cl2, and the flow rate ratio of BCl3 to Cl2 is 2:1 to 3:1.

[0031] This invention provides a semiconductor device etching method, comprising: providing a preset substrate; wherein the preset substrate includes a conductor layer; a conductor layer etching step, wherein a chlorine-containing gas is introduced into a reaction chamber as an etching gas, and the conductor layer is etched using a previous film layer as a mask until the next film layer is exposed; and a quenching step, wherein the power of the upper electrode and the power of the lower electrode are both turned off, and a passivation gas is introduced into the reaction chamber; wherein the passivation gas includes a hydrogen-containing gas. This invention adds a quenching step after etching the conductor layer, controlling both the upper and lower electrode power to zero. This neutralizes the charge accumulated on the wafer surface during the conductor layer etching step, making the electric field distribution on the wafer surface more uniform, thereby improving the uniformity of the threshold voltage of the P-type transistor. By introducing hydrogen-containing gas into the chamber as a passivation gas during the quenching step, the interface defects of the gate oxide layer in the semiconductor device can be passivated, optimizing the uniformity of the threshold voltage of the P-type transistor and reducing the random distribution of gate charge traps. Under the combined effect of shutting down the RF power supply and introducing the passivation gas, the uniformity of the threshold voltage of the P-type transistor is significantly improved, thus increasing the product yield.

[0032] Other features and advantages of the embodiments of the present invention will be set forth in the following description, or some features and advantages may be inferred from the description or determined without doubt, or may be learned by practicing the techniques described above in the embodiments of the present invention.

[0033] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0034] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0035] Figure 1 The graph shows the current threshold voltage of P-type transistors as a function of the number of wafers.

[0036] Figure 2 A flowchart of a semiconductor device etching method provided by an embodiment of the present invention is shown;

[0037] Figures 3a to 3f This invention provides a flowchart of a preset substrate etching process according to an embodiment of the invention.

[0038] Figure 4 The figure shows a curve of the threshold voltage of a P-type transistor as a function of the number of wafers after using the semiconductor device etching method provided in this embodiment of the invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be described below in conjunction with the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0040] Currently, the etching process of aluminum pads generates a large amount of positive charge accumulation, leading to plasma-induced damage (PMOSPID) in P-type transistors. This results in poor threshold voltage uniformity in P-type transistors (PMOS transistors refer to MOSFETs with an n-type substrate, p-channel, and current transported by hole flow). Specifically, on the one hand, high-energy ions generated by dry etching (such as Cl2 / BCl3 plasma) may penetrate the gate oxide layer, forming charge traps or interface states within it. P-type transistors are sensitive to positive charges, and the accumulation of positive charges leads to a negative shift in the threshold voltage. On the other hand, bombardment by ultraviolet photons or electrons in the plasma may weaken the integrity of the oxide layer, resulting in increased leakage current and threshold voltage drift. See also... Figure 1 The graph shown illustrates the variation of the threshold voltage of a P-type transistor with the number of wafers. Figure 1 As can be seen, the relevant semiconductor device etching technology still suffers from poor uniformity of the threshold voltage of P-type transistors.

[0041] To address the aforementioned problems, this invention provides a semiconductor device etching method, which will be described in detail below.

[0042] This embodiment provides a semiconductor device etching method, which can be applied to semiconductor process equipment. See [link to documentation]. Figure 2 The flowchart shown illustrates a semiconductor device etching method, which mainly includes the following steps:

[0043] Step S202: Provide a preset substrate;

[0044] See also Figure 3a The schematic diagram of the preset substrate structure shown above includes a conductor layer 303. The preset substrate is introduced into the reaction chamber of a plasma etching machine to etch the conductor layer in the preset substrate. The plasma etching machine can be an ICP plasma etching machine.

[0045] In one implementation, such as Figure 3a As shown, the aforementioned preset substrate also includes a photoresist layer 301, a dielectric antireflective layer 302, a conductor layer 303, a metal bonding layer 304, a metal barrier layer 305, and an etching stop layer 306.

[0046] Step S204, conductor layer etching step: Chlorine-containing gas is introduced into the reaction chamber as etching gas, and the conductor layer is etched using the upper film layer as a mask until the next film layer is exposed.

[0047] The chlorine-containing gas mentioned above may include BCl3 and / or Cl2. Since the main material of the conductor layer is aluminum, when chlorine-containing gas is introduced into the reaction chamber, the chloride ions obtained by ionization can react with aluminum to generate AlCl3.

[0048] During the etching process of the conductor layer, the chamber pressure is controlled at 6-10 mT; the upper electrode power is 1000-1500 W; the lower electrode power is 300-400 W; the current ratio of the upper electrode power and the lower electrode power is controlled at 0.4-0.6; the process time is related to the thickness of the conductor layer, and the range of the process time can be, for example, 230-300 s.

[0049] In one embodiment, during the conductor layer etching step, the chlorine-containing gas provided in this embodiment includes BCl3 and Cl2, with a flow rate ratio of BCl3 to Cl2 of 1:2 to 1:3. The main reaction for etching the conductor layer is as follows:

[0050] Al2O3+6BCl3→2AlCl3↑+3B2O3+6Cl2↑

[0051] 2Al + 3Cl → 2AlCl3↑

[0052] The flow ratio of BCl3 to Cl2 is a key parameter for adjusting the critical dimensions and angles of conductor layer etching. By adding BCl3 to the chlorine-containing gas, the B in BCl3 can play a bombardment role during etching to protect the sidewalls of the conductor layer. By setting the flow ratio range of BCl3 to Cl2, the etching efficiency of the conductor layer can be improved while protecting the sidewall morphology.

[0053] In one specific embodiment, 150-200 sccm of BCl3 and 250-300 sccm of Cl2 can be introduced into the chamber. In another embodiment, 20-30 sccm of CH4 can also be introduced into the chamber as a sidewall protective gas.

[0054] Step S206, extinguishing step: control both the upper electrode power and the lower electrode power to be turned off, and introduce passivation gas into the reaction chamber.

[0055] The high power in the conductor layer etching step makes it easy for plasma to accumulate charge on the wafer surface, resulting in uneven electric field distribution on the wafer and causing PID problem in P-type transistors. Ultimately, the uniformity of the threshold voltage of P-type transistors deteriorates. By adding a quenching step after the conductor layer etching step, the charge on the wafer surface can be neutralized, making the electric field distribution on the wafer more uniform, reducing the random distribution of gate charge traps in P-type transistors, and passivating oxide layer interface defects, thus optimizing the uniformity of the threshold voltage (VT) of P-type transistors.

[0056] The passivation gases mentioned above include nitrogen-containing gases and hydrogen-containing gases. By introducing nitrogen-containing gas into the reaction chamber, the sidewalls of the etched conductor layer can be protected to avoid affecting the sidewall morphology. By introducing hydrogen-containing gas into the reaction chamber, it can react with chloride ions in the chamber to reduce the charge injection of the gate oxide layer, thereby passivating the oxide layer interface defects.

[0057] The semiconductor device etching method provided in this embodiment, by adding a quenching step after etching the conductor layer and controlling both the upper and lower electrode power to be zero, can neutralize the charge accumulated on the wafer surface during the conductor layer etching step, making the electric field distribution on the wafer surface more uniform, thereby improving the uniformity of the threshold voltage of the P-type transistor. By introducing passivating gases such as nitrogen-containing gas and hydrogen-containing gas into the cavity during the quenching step, the gate oxide layer interface defects in the semiconductor device can be passivated, optimizing the uniformity of the threshold voltage of the P-type transistor and reducing the random distribution of gate charge traps in the P-type transistor. Under the combined effect of shutting off the RF power supply and introducing passivating gas, the uniformity of the threshold voltage of the P-type transistor is significantly improved, thereby increasing the product yield.

[0058] In one embodiment, the nitrogen-containing gas in the quenching step provided in this embodiment includes nitrogen gas, and the hydrogen-containing gas includes hydrogen gas or ammonia gas.

[0059] In the quenching step, the chamber pressure is controlled at 8-15 mT; the power of the upper electrode and the power of the lower electrode are both controlled at 0 W; 50-100 sccm N2 and 40-60 sccm H2 are introduced into the chamber as passivation gases, which can passivate and reduce the interface defects of the gate oxide layer and optimize the uniformity of the threshold voltage (VT) of the P-type transistor; the process time is 20-30 s.

[0060] In one embodiment, the nitrogen-containing gas provided in this embodiment includes nitrogen gas, and the hydrogen-containing gas includes hydrogen gas; the flow ratio of nitrogen gas to hydrogen gas is 2:1 to 3:1. By introducing nitrogen gas and hydrogen gas in a ratio of 2:1 to 3:1 into the reaction chamber, the sidewalls of the conductor layer can be better protected, and the interface defects of the gate oxide layer can be passivated and reduced.

[0061] In one embodiment, the preset substrate provided in this embodiment further includes a photoresist layer located above the conductive layer;

[0062] Prior to the conductor layer etching step, the semiconductor device etching method also includes:

[0063] In the photoresist etching step, oxygen-containing gas is introduced into the reaction chamber to etch the photoresist layer until the next film layer is exposed.

[0064] The photoresist layer is etched laterally using oxygen. During the etching process, an inert gas, such as nitrogen or argon, can be introduced into the chamber as a dilution and passivation gas.

[0065] In one embodiment, the chamber pressure can be controlled at 8-15 mT. Since excessively high upper electrode power will cause a large consumption of the photoresist layer, it is easy to cause insufficient masking in subsequent etching. Therefore, the upper electrode power is controlled at 300-600 W, and the lower electrode power is controlled at 0 to reduce the consumption of the photoresist layer. The current ratio of the upper electrode power is controlled at 0.4-0.6. 15-30 sccm of O2 is introduced as the main etching gas, and 100-200 sccm of N2 is introduced as the dilution gas and passivation gas. The etching time is related to the thickness of the photoresist layer and can be 10-30 s.

[0066] In one embodiment, the preset substrate provided in this embodiment further includes a dielectric anti-reflection layer located between the photoresist layer and the conductive layer;

[0067] Following the conductor layer etching step, the semiconductor device etching method also includes:

[0068] In the dielectric antireflection layer etching step, chlorine-containing gas is introduced into the reaction chamber, and the dielectric antireflection layer is etched using the photoresist layer as a mask until the conductor layer is exposed.

[0069] The main purpose of the dielectric anti-reflective layer is to eliminate the standing wave effect. During the etching process, the chamber pressure is controlled at 6-10 mT, the upper electrode power is controlled at 1000-1500 W, the lower electrode power is controlled at 300-400 W, and the current ratio of the upper and lower electrode power is controlled at 0.4-0.6. Chlorine-containing gas is introduced into the chamber as the main etching gas, such as 100-150 sccm of BCl3 and 100-150 sccm of Cl2. The etching time is related to the thickness of the dielectric anti-reflective layer. Fluorine-containing gases can also be used to etch the dielectric anti-reflective layer, but in this etching process, the underlying material of the dielectric anti-reflective layer is aluminum. Fluorine and aluminum will form solid products such as aluminum fluoride, which will contaminate the chamber and cause wafer scrap. Therefore, BCl3 / Cl2 must be used as the main etching gas in this etching step. The etching reaction is as follows:

[0070] SiO₂ + 4Cl → SiCl₄↑ + O₂↑

[0071] In one embodiment, the preset substrate provided in this embodiment further includes a metal bonding layer located below the conductive layer;

[0072] Following the conductor layer etching step, the semiconductor device etching method also includes:

[0073] In the metal bonding layer etching step, chlorine-containing gas is introduced into the reaction chamber as the etching gas, and the metal bonding layer is etched using the conductor layer as a mask until the next film layer is exposed.

[0074] The chamber process parameters in the metal bonding layer etching step are the same as those in the conductor layer etching step, which can avoid the discontinuity between the conductor layer and the metal bonding layer sidewalls.

[0075] The etching step mainly etches the remaining conductor layer and the metal bond layer. The purpose of the metal bond layer is to act as an adhesive layer and prevent electromigration. During the etching process, the chamber pressure is controlled at 6-10 mT; the upper electrode power is 1000-1500 W; the lower electrode power is 300-400 W; the current ratio of the upper electrode power and the lower electrode power is controlled at 0.4-0.6; the process time is related to the thickness of the conductor layer, and the process time of the metal bond layer etching step can be in the range of 230-300 s.

[0076] In one embodiment, the preset substrate provided in this embodiment further includes a metal barrier layer and an etching stop layer located below the metal adhesive layer;

[0077] Following the conductor layer etching step, the semiconductor device etching method also includes:

[0078] In the metal barrier layer etching step, chlorine-containing gas is introduced into the reaction chamber as the etching gas, and the metal barrier layer is etched using the metal bonding layer as a mask until the etching stop layer is exposed.

[0079] During the etching of the metal barrier layer, a chlorine-containing gas is introduced into the chamber as the main etching gas. This chlorine-containing gas may include BCl3 and / or Cl2. During the etching process, the chamber pressure can be controlled at 6-10 mT, the upper electrode power at 700-1000 W, and the lower electrode power at 550-550 W. The current ratio of the upper electrode power to the lower electrode power is controlled at 0.4-0.6. 200-250 sccm of BCl3 and 100-150 sccm of Cl2 are introduced into the chamber as the main etching gas, and the flow ratio of BCl3 to Cl2 can be 2:1 to 3:1. 10-15 sccm of CH4 is introduced as a sidewall protective gas. The etching time is related to the thickness of the metal barrier layer, and the process time can be, for example, 40-80 s.

[0080] In one embodiment, the method provided in this embodiment further includes:

[0081] The pre-selected substrate, after completing the metal barrier layer etching step, is transferred to the desizing chamber. Hydrogen-containing gas and oxygen-containing gas are introduced into the desizing chamber to remove the photoresist layer and residual chloride ions from the pre-selected substrate after completing the metal barrier layer etching step.

[0082] By introducing hydrogen gas into the desizing chamber, residual chloride ions on the preset substrate after etching can be removed; by introducing oxygen gas into the desizing chamber, the photoresist layer on the preset substrate can be removed.

[0083] In one embodiment, this embodiment provides a specific implementation method for introducing hydrogen-containing gas and oxygen-containing gas into a desizing chamber to remove the photoresist layer and residual chloride ions from a preset substrate after the metal barrier layer etching step has been completed:

[0084] In the chloride ion removal step, the desizing chamber is controlled at the first pressure, and hydrogen-containing gas is introduced into the desizing chamber to remove the chloride ions remaining on the preset substrate after the metal barrier layer etching step is completed.

[0085] The hydrogen-containing gas mentioned above can be H2O and / or NH3, and the value of the first pressure can be 3-6T. In one embodiment, in the chloride ion removal step, 1500-3000 sccm of H2O is introduced into the chamber, the upper electrode power is controlled to be 1500-2500W, and the process time can be 100-150s.

[0086] In the first photoresist layer removal step, the desizing chamber is controlled at a second pressure, and oxygen-containing gas and hydrogen-containing gas are introduced into the desizing chamber to etch and remove the photoresist layer and residual chloride ions; wherein, the second pressure is lower than the first pressure, and the flow rate of hydrogen-containing gas in the first photoresist layer removal step is lower than the flow rate of hydrogen-containing gas in the chloride ion removal step.

[0087] The aforementioned hydrogen-containing gas can be H2O and / or NH3, the aforementioned oxygen-containing gas can be O2, and the aforementioned second pressure can range from 0.5 to 1T. In one embodiment, the upper electrode power is controlled at 2000-3000W; the O2 gas flow rate is controlled at 3000-5000 sccm; the N2 gas flow rate is controlled at 200-500 sccm; the H2O gas flow rate is controlled at 800-1200 sccm; and the process time is 30-50s.

[0088] In the second photoresist removal step, the deresist chamber is controlled at a second pressure, and oxygen-containing gas is introduced into the deresist chamber to etch and remove the photoresist layer and residual chloride ions; wherein, the proportion of oxygen-containing gas introduced in the second photoresist removal step is greater than the proportion of oxygen-containing gas introduced in the first photoresist removal step.

[0089] The oxygen-containing gas mentioned above can be O2, and the value range of the second pressure can be 0.5-1T. In one embodiment, the upper electrode power is controlled to be 2000-3000W; the O2 gas flow rate is controlled to be 3000-5000sccm; the N2 gas flow rate is controlled to be 200-500sccm; and the process time is 200-400s.

[0090] To thoroughly clean the photoresist layer and chloride ions in the chamber, the above chloride ion removal step and photoresist layer second removal step can be repeated 3-4 times.

[0091] The semiconductor device etching method provided in this embodiment introduces a quenching step between the conductor layer etching and the metal bond layer etching (i.e., main etching and over-etching) to neutralize surface charges, making the electric field distribution more uniform during the conductor layer etching and metal bond layer etching stages. By introducing a mixture of nitrogen-containing gas and hydrogen-containing gas during the quenching step, oxide layer interface defects can be passivated. Overall, this reduces the random distribution of gate charge traps in P-type transistors and significantly improves the uniformity of the threshold voltage (VT) of P-type transistors.

[0092] Based on the foregoing embodiments, this embodiment provides an example of using the aforementioned semiconductor device etching method to improve the uniformity of the threshold voltage of a P-type transistor after aluminum pad etching, such as... Figures 3a to 3f The preset substrate etching flowchart shown can be followed as follows:

[0093] Step 1: Provide a preset substrate and transfer the preset substrate into the etching reaction chamber.

[0094] like Figure 3a As shown, the aforementioned preset substrate (also referred to as an aluminum pad) includes a photoresist layer 301, a dielectric anti-reflective layer 302, a conductor layer 303, a metal bonding layer 304, a metal barrier layer 305, and an etching stop layer 306. The photoresist layer 301 is etched laterally using an oxygen / inert gas mixture.

[0095] The aforementioned aluminum pads can first be etched using an ICP plasma etching machine to remove the film layer, and then a stripping chamber can be used to remove residual photoresist and chloride ions. In the reaction chamber of the ICP plasma etching machine, the upper and lower power supply frequencies can be set to 13.56MHz, the power application mode for both the upper and lower electrodes is continuous wave, the temperature of the electrostatic chuck during the process is 40-60℃, the electrostatic adsorption voltage is 2200-2600V, and the helium pressure on the back side of the wafer is 6-10T; in the stripping chamber, the temperature of the electrostatic chuck can be set to 200-300℃.

[0096] During the etching process, the chamber pressure is controlled at 8-15 mT. Since excessively high upper electrode power would cause significant photoresist consumption, potentially leading to insufficient mask coverage during subsequent etching, the upper electrode power is set to 300-600 W. No lower electrode power is used to reduce photoresist consumption. The current ratio of the upper electrode power is 0.4-0.6. 15-30 sccm of O2 is introduced into the chamber as the main etching gas, and 100-200 sccm of N2 is introduced as a dilution and passivation gas. The etching time is 10-30 s.

[0097] Step 2, as follows Figure 3b As shown, using photoresist layer 301 as a mask, the dielectric anti-reflection layer 302 is etched. The purpose of the dielectric anti-reflection layer 302 is to eliminate the standing wave effect. During the etching process, the chamber pressure is controlled at 6-10 mT; the upper electrode power is controlled at 1000-1500 W; the lower electrode power is controlled at 300-400 W; the current ratio is 0.4-0.6; 100-150 sccm of BCl3 and 100-150 sccm of Cl2 are introduced into the chamber as the main etching gases. The etching reaction is as follows:

[0098] SiO₂ + 4Cl → SiCl₄↑ + O₂↑

[0099] The anti-reflective etching medium can also be etched using fluorine-containing gases. However, in this process, the underlying material is aluminum, and fluorine and aluminum will form solid products such as aluminum fluoride, which will contaminate the chamber and cause the wafer to be scrapped. Therefore, BCl3 and / or Cl2 must be used as the main etching gas in this step; the etching time is 20-40 seconds.

[0100] Step 3, as follows Figure 3c As shown, the conductor layer 303 is etched using the dielectric anti-reflection layer 302 as a mask. During the etching process, the chamber pressure is controlled at 8-15 mT; the upper electrode power is controlled at 1000-1500 W; the lower electrode power is controlled at 300-400 W; the current ratio of the upper and lower electrode powers is controlled at 0.5-0.8; 150-200 sccm of BCl3 and 250-300 sccm of Cl2 are introduced into the reaction chamber as the main etching gases; 20-30 sccm of CH4 is introduced as the sidewall protection gas. The amount of CH4 introduced is a key factor in product yield; too much or too little CH4 may cause corrosion problems; the etching time is controlled at 230-300 s. The main reactions of the etched conductor layer are as follows:

[0101] Al2O3+6BCl3→2AlCl3↑+3B2O3+6Cl2↑

[0102] 2Al + 3Cl → 2AlCl3↑

[0103] Step 4: Due to the high power during the etching stage of the conductor layer, the plasma easily accumulates charge on the wafer surface, causing uneven electric field distribution and leading to PID problems in P-type transistors. Ultimately, this results in poor uniformity of the threshold voltage (VT) of the P-type transistor. Therefore, adding a quenching step between the etching of the conductor layer and the etching of the metal bond layer is a key step to solve this problem. During the etching process, the chamber pressure is controlled at 8-15 mT; the power of the upper electrode and the lower electrode are controlled at 0 W. 50-100 sccm of N2 and 40-60 sccm of H2 are introduced into the chamber as passivation gases (N2 and NH3 can also be introduced). This passivates and reduces defects at the gate oxide interface, optimizing the uniformity of the threshold voltage (VT) of the P-type transistor. The process time is 20-30 s.

[0104] Step 5, as follows Figure 3d As shown, the metal bonding layer 304 is etched using the conductor layer 303 as a mask. The purpose of the metal bonding layer is to act as an adhesive layer and prevent electromigration. During the etching process, the chamber pressure is controlled at 8-15 mT, the upper electrode power is controlled at 1000-1500 W, the lower electrode power is controlled at 300-400 W, the current ratio of the upper electrode power to the lower electrode power is controlled at 0.5-0.8, 150-200 sccm of BCl3 and 250-300 sccm of Cl2 are introduced into the reaction chamber as the main etching gas, and 20-30 sccm of CH4 is introduced as the sidewall protection gas; the etching time is controlled at 80-120 s.

[0105] Step 6, as follows Figure 3e As shown, the metal bonding layer 304 is used as a mask to etch the metal barrier layer 305. The purpose of the metal barrier layer is to prevent copper from diffusing into the aluminum. During the etching process, the chamber pressure is controlled at 6-10 mT, the upper electrode power is controlled at 700-1000 W, the lower electrode power is controlled at 550-550 W, the current ratio is 0.4-0.6, and 200-250 sccm of BCl3 and 100-150 sccm of Cl2 are introduced into the chamber as the main etching gas; 10-15 sccm of CH4 is introduced as the sidewall protection gas, and the etching time is controlled at 40-80 s.

[0106] Step 7, transfer the preset substrate into the de-adhesive chamber, such as... Figure 3f As shown, photoresist layer 301 is etched away:

[0107] 1. Passivation step: Control the chamber pressure to 3-6T, control the upper electrode power to 1500-2500W, the flow rate of H2O (or NH3) gas introduced into the chamber to be 1500-3000sccm, and the process time to be 100-150s.

[0108] 2. Strip-1 step: Control the chamber pressure to 0.5-1T; control the upper electrode power to 2000-3000W; control the flow rate of O2 gas into the chamber to 3000-5000sccm; control the flow rate of N2 gas into the chamber to 200-500sccm; control the flow rate of H2O gas into the chamber to 800-1200sccm; and control the process time to 30-50s.

[0109] 3. Strip-2 step: Control the chamber pressure to 0.5-1T, control the upper electrode power to 2000-3000W, the flow rate of O2 gas into the chamber to 3000-5000sccm, the flow rate of N2 gas into the chamber to 200-500sccm, and the process time to 200-400s.

[0110] Repeat steps Passivation to Strip-2 for 3 to 4 cycles to thoroughly remove residual photoresist and chloride ions.

[0111] By introducing a quenching step between the main etching and over-etching steps to neutralize surface charges, the electric field distribution during the etching stages of the conductor layer and the metal bond layer is made more uniform. Furthermore, the introduction of H2 or N2 / H2 mixed gas during this quenching step can passivate oxide layer interface defects. Overall, this reduces the random distribution of gate charge traps in the P-type transistor, significantly improving the uniformity of the P-type transistor threshold voltage (VT). (See example...) Figure 4 The graph shown is a curve illustrating the change in threshold voltage of a P-type transistor with the number of wafers after using the semiconductor device etching method provided in this embodiment. Figure 4 As can be seen, adding the quenching step can significantly improve the uniformity of the threshold voltage (VT) of the P-type transistor.

[0112] This invention provides an electronic device, which includes a processor and a memory. The memory stores a computer program that can run on the processor. When the processor executes the computer program, it implements the steps of the method provided in the above embodiments.

[0113] This invention provides a computer-readable medium storing computer-executable instructions. When these computer-executable instructions are invoked and executed by a processor, they cause the processor to implement the methods described in the above embodiments.

[0114] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working process of the system described above can be referred to the corresponding process in the foregoing embodiments, and will not be repeated here.

[0115] Furthermore, in the description of the embodiments of the present invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0116] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0117] Finally, it should be noted that the above-described embodiments are merely specific implementations of the present invention, used to illustrate the technical solutions of the present invention, and not to limit it. The scope of protection of the present invention is not limited thereto. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments within the technical scope disclosed in the present invention, or make equivalent substitutions for some of the technical features; and these modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device etching method, characterized in that, include: A preset substrate is provided; wherein the preset substrate includes a conductor layer; In the conductor layer etching step, chlorine-containing gas is introduced into the reaction chamber as the etching gas, and the conductor layer is etched using the upper film layer as a mask until the next film layer is exposed. In the extinguishing step, both the upper and lower electrode power are turned off, and a passivation gas is introduced into the reaction chamber; wherein, the passivation gas includes a nitrogen-containing gas and a hydrogen-containing gas, the nitrogen-containing gas includes nitrogen gas, and the hydrogen-containing gas includes hydrogen gas or ammonia gas; The preset substrate further includes a photoresist layer located above the conductor layer; before the conductor layer etching step, the semiconductor device etching method further includes: a photoresist layer etching step, in which oxygen-containing gas is introduced into the reaction chamber to etch the photoresist layer until the next film layer is exposed. The preset substrate further includes a dielectric anti-reflection layer located between the photoresist layer and the conductor layer; after the conductor layer etching step, the semiconductor device etching method further includes: a dielectric anti-reflection layer etching step, in which chlorine-containing gas is introduced into the reaction chamber, and the dielectric anti-reflection layer is etched using the photoresist layer as a mask until the conductor layer is exposed.

2. The method according to claim 1, characterized in that, The nitrogen-containing gas includes nitrogen, and the hydrogen-containing gas includes hydrogen. The flow rate ratio of nitrogen to hydrogen is 2:1 to 3:

1.

3. The method according to claim 1, characterized in that, The preset substrate also includes a metal bonding layer located below the conductor layer; Following the conductor layer etching step, the semiconductor device etching method further includes: In the metal bonding layer etching step, chlorine-containing gas is introduced into the reaction chamber as an etching gas, and the metal bonding layer is etched using the conductor layer as a mask until the next film layer is exposed.

4. The method according to claim 3, characterized in that, The preset substrate also includes a metal barrier layer and an etching stop layer located below the metal bonding layer; Following the conductor layer etching step, the semiconductor device etching method further includes: In the metal barrier layer etching step, chlorine-containing gas is introduced into the reaction chamber as an etching gas, and the metal barrier layer is etched using the metal bonding layer as a mask until the etching stop layer is exposed.

5. The method according to claim 4, characterized in that, Also includes: The preset substrate, after completing the metal barrier layer etching step, is passed into the photoresist removal chamber. Hydrogen-containing gas and oxygen-containing gas are introduced into the photoresist removal chamber to remove the photoresist layer and residual chloride ions from the preset substrate after completing the metal barrier layer etching step.

6. The method according to claim 5, characterized in that, The step of introducing hydrogen-containing and oxygen-containing gas into the desizing chamber to remove the photoresist layer and residual chloride ions from the preset substrate after the metal barrier layer etching step is completed includes: In the chloride ion removal step, the desizing chamber is controlled at a first pressure, and hydrogen-containing gas is introduced into the desizing chamber to remove the chloride ions remaining in the preset substrate after the metal barrier layer etching step is completed. In the first photoresist layer removal step, the desizing chamber is controlled at a second pressure, and oxygen-containing gas and hydrogen-containing gas are introduced into the desizing chamber to etch and remove the photoresist layer and residual chloride ions; wherein, the second pressure is less than the first pressure, and the flow rate of hydrogen-containing gas in the first photoresist layer removal step is less than the flow rate of hydrogen-containing gas in the chloride ion removal step. In the second photoresist layer removal step, the desizing chamber is controlled at a second pressure, and oxygen-containing gas is introduced into the desizing chamber to etch and remove the photoresist layer and residual chloride ions; wherein, the proportion of oxygen-containing gas introduced in the second photoresist layer removal step is greater than the proportion of oxygen-containing gas introduced in the first photoresist layer removal step.

7. The method according to claim 3, characterized in that, In the conductor layer etching step and / or the metal bonding layer etching step, the chlorine-containing gas includes BCl3 and Cl2, and the flow rate ratio of BCl3 to Cl2 is 2:1 to 3:1.

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