Noise reduction circuit, power supply circuit, reading circuit and detection circuit

Abstract

The invention discloses a noise reduction circuit, a power supply circuit, a reading circuit and a detection circuit, relates to the field of MEMS interface circuits, and is used for reducing low-frequency noise of an MEMS sensor interface circuit. The power supply circuit comprises a charge pump circuit and a noise reduction circuit, and the noise reduction circuit comprises a reference noise suppression circuit and a charge pump noise suppression circuit. The input end of the reference noise suppression circuit is used for accessing a clock signal, a power supply, a reference voltage and a feedback voltage, and the output end is grounded through a capacitor C1 and outputs a second voltage. The power supply voltage of the charge pump noise suppression circuit is used for connecting a first voltage to be subjected to noise reduction, the input end is connected with a second voltage, and the output end respectively outputs a third voltage and the feedback voltage. According to the invention, the low-frequency noise transmitted by the high-voltage feedback driving circuit and the charge pump circuit in the MEMS sensor interface circuit is reduced, and the measurement precision of the MEMS sensor is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of MEMS interface circuits, in particular to a noise reduction circuit, a power supply circuit, a readout circuit and a detection circuit. Background Art

[0002] The combination of MEMS-based capacitive microsensor structures and CMOS-based sensor interface integrated circuits has enabled the miniaturization of sensors such as accelerometers, gyroscopes, and detectors. Furthermore, while the application of closed-loop solutions to sensors significantly improves their linearity, it also introduces new noise into the sensor due to the influence of high-voltage power supply noise on the high-voltage feedback drive circuit.

[0003] See also Figure 1 In traditional sensing solutions, to increase the measurement range of sensors like accelerometers, a high-voltage feedback drive circuit (typically with an output voltage of tens or even hundreds of volts) is introduced into a closed-loop circuit to offset the large displacement of the movable mass (MASS) caused by sudden acceleration changes. Because this high-voltage power supply is often generated by a charge pump circuit, its output noise is transmitted through the circuit lines to the MEMS sensor drive electrodes DT and DB, affecting the measurement accuracy of sensors like accelerometers, gyroscopes, and detectors, particularly their ability to detect weak signals. Because sensors primarily output signals in the low-frequency band and have very low amplitudes, they are easily affected by the low-frequency noise (1 / f noise) introduced by the CMOS process. The main sources of 1 / f noise in sensor interface circuits are divided into two parts. One part is the 1 / f noise present in each on-chip reference voltage VREF. This noise is applied to the signal chain along with the reference voltage. When the amplitude of the weak signal to be detected is on the order of tens of uV, it is easily overwhelmed by the inherent low-frequency noise, making it difficult for the detection circuit to distinguish between signal and noise. The second part is the noise of the high-voltage feedback drive power supply. Typically, the high-voltage feedback drive power supply (>10V) of the MEMS sensor interface circuit is generated by boosting the chip's power supply (5V or lower) through a charge pump circuit. Its low-frequency noise is directly applied to the sensitive detection circuit of the MEMS sensor through high-voltage electrostatic force, causing the sensitive detection circuit of the MEMS sensor to experience irregular weak vibrations under the influence of this noise, thereby deteriorating the sensor's measurement accuracy. Summary of the Invention

[0004] The object of the present invention is to provide a noise reduction circuit, a power supply circuit, a readout circuit and a detection circuit to reduce the low-frequency noise of the MEMS sensor interface circuit in order to address all or part of the above-mentioned problems.

[0005] The technical solution adopted in the present invention is as follows: A noise reduction circuit comprising a reference noise suppression circuit and a charge pump noise suppression circuit; The input end of the reference noise suppression circuit is used to receive a clock signal, a power supply, a reference voltage and a feedback voltage, the output end is grounded via a capacitor C1, and the output end outputs a second voltage; The power supply voltage of the charge pump noise suppression circuit is used to access the first voltage to be reduced, the input end is connected to the second voltage, and the output end outputs the third voltage and the feedback voltage respectively.

[0006] Furthermore, the reference noise suppression circuit includes a first chopping circuit, an operational amplifier circuit, a second chopping circuit and a dual-end to single-ended operational amplifier circuit; the input end of the first chopping circuit is used to access the clock signal, reference voltage and feedback voltage, and the output end is connected to the input end of the operational amplifier circuit; the input end of the second chopping circuit is respectively connected to the output end of the operational amplifier circuit and the clock signal, and the output end is connected to the dual-end to single-ended operational amplifier circuit; the output end of the dual-end to single-ended operational amplifier circuit outputs the second voltage.

[0007] Furthermore, the structures of the first chopping circuit and the second chopping circuit are as follows: The invention comprises a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; the source of the first PMOS tube and the source of the second PMOS tube are both connected to the positive input terminal; the source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the negative input terminal; the gate of the first PMOS tube and the gate of the fourth PMOS tube are both connected to the clock signal; the gate of the second PMOS tube and the gate of the third PMOS tube are both connected to the inverted clock signal; the drain of the first PMOS tube and the drain of the third PMOS tube are both connected to the positive output terminal; the drain of the second PMOS tube and the drain of the fourth PMOS tube are both connected to the negative output terminal.

[0008] Furthermore, the dual-end to single-end operational amplifier circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first NPN transistor, a second NPN transistor, a first fixed resistor, and a second fixed resistor; The source of the fifth PMOS transistor is connected to the positive output terminal of the second chopper circuit, and the drain is respectively connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor; The source of the sixth PMOS transistor is connected to the negative output terminal of the second chopper circuit, and the drain is connected to the drain of the second NMOS transistor; the drain of the sixth PMOS transistor outputs the second voltage; The substrate of the fifth PMOS transistor is connected to the substrate of the sixth PMOS transistor; The source of the first NMOS transistor is connected to the collector of the first NPN transistor; The source of the second NMOS transistor is connected to the collector of the second NPN transistor; The emitter of the first NPN transistor is grounded via the first fixed resistor; the emitter of the second NPN transistor is grounded via the second fixed resistor; the base of the first NPN transistor is connected to the base of the second NPN transistor.

[0009] Furthermore, the charge pump noise suppression circuit includes a third NMOS transistor, a seventh PMOS transistor, a third fixed resistor, a fourth fixed resistor and a first variable resistor; The gate of the third NMOS transistor is connected to the second voltage, the source is grounded, and the drain is connected to the gate of the seventh PMOS transistor and the third fixed resistor respectively; The source of the seventh PMOS transistor is connected to the third fixed resistor and is connected to the first voltage; the drain of the seventh PMOS transistor is connected in series with the fourth fixed resistor and the first variable resistor and then to ground; the drain of the seventh PMOS transistor outputs the third voltage; The feedback voltage is drawn between the fourth fixed resistor and the first variable resistor.

[0010] In another aspect, the present invention further provides a power supply circuit, comprising a charge pump circuit and the above-mentioned noise reduction circuit; The input end of the charge pump circuit is used to connect to the power supply, the output end is grounded via the capacitor C2, and the output end outputs the first voltage.

[0011] In another aspect, the present invention further provides a readout circuit, which includes the above-mentioned power supply circuit, In another aspect, the present invention further provides a detection circuit, comprising a capacitive MEMS sensor and the above-mentioned readout circuit, wherein the readout circuit is connected to the capacitive MEMS sensor.

[0012] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: The present invention reduces the low-frequency noise transmitted by the high-voltage feedback drive circuit and the charge pump circuit in the MEMS sensor interface circuit, thereby reducing the influence of the low-frequency noise on the weak signal detected by the MEMS sensor and improving the measurement accuracy of the MEMS sensor. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The present invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 This is a diagram showing the structure of a detection circuit using a MEMS sensor.

[0014] Figure 2 It is a structural diagram of the power supply circuit provided in an embodiment of the present application.

[0015] Figure 3 is a structural diagram of a reference noise suppression circuit in an embodiment of the present application.

[0016] Figure 4 It is a structural diagram of the first chopping circuit in an embodiment of the present application.

[0017] Figure 5 It is a structural diagram of a dual-ended to single-ended operational amplifier circuit in an embodiment of the present application.

[0018] Figure 6 is a structural diagram of a charge pump noise suppression circuit in an embodiment of the present application.

[0019] Figure 7 is a structural diagram of the noise reduction circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] All features disclosed in this specification, or all steps in the disclosed methods or processes, except mutually exclusive features and / or steps, can be combined in any manner.

[0021] Any feature disclosed in this specification (including any appended claims and abstract), unless otherwise stated, may be replaced by other equivalent or similar features. In other words, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

[0022] In scenarios where the detection circuits of MEMS sensors (such as accelerometers, gyroscopes, and detectors) are miniaturized by combining MEMS and CMOS technologies, low-frequency noise introduced into the interface circuit by both the high-voltage feedback drive power supply and the reference voltage VREF can degrade the measurement accuracy of the MEMS sensor. Embodiments of the present application provide a noise reduction circuit, a power supply circuit, a readout circuit, and a detection circuit. These circuits are designed to reduce the low-frequency noise introduced by the reference voltage VREF and the high-voltage feedback drive power supply, respectively. Low-dropout linear voltage regulation technology is used to reduce the impact of the low-frequency noise of the reference voltage VREF on the final power supply voltage. Chopping technology is used to modulate the low-frequency (1 / F) noise in the reference voltage VREF to a high frequency. Filtering technology is used to filter out the high-frequency noise, thereby filtering out the low-frequency noise in the reference voltage VREF and reducing the impact of the low-frequency noise of the reference voltage VREF on the final power supply voltage, thereby improving the measurement accuracy of the MEMS sensor.

[0023] An embodiment of the present application provides a noise reduction circuit, which is applied to a power supply circuit of a MEMS sensor readout circuit, for reducing low-frequency noise in a reference voltage VREF and a high-voltage feedback drive power supply, respectively.

[0024] See attached Figure 2 , assuming that the high-voltage feedback drive power supply is generated by the charge pump circuit CP to boost the power supply AVDD of the chip. The charge pump circuit CP is designed based on the Dickson charge pump, which boosts the 5V power supply AVDD to more than 10V. Due to the influence of the clock, the boosted high-voltage feedback drive power supply usually has large ripple and noise. In an embodiment of the present application, the first voltage PUMP_OUT represents the high-voltage feedback drive power supply to be noise reduced. In order to meet the high-precision detection requirements, the noise and ripple of the first voltage PUMP_OUT need to be effectively suppressed.

[0025] The noise reduction circuit includes a reference noise suppression circuit NSC1 and a charge pump noise suppression circuit NSC2. The reference noise suppression circuit NSC1 is used to reduce the noise of the reference voltage VREF, and the charge pump noise suppression circuit NSC2 is used to reduce the noise of the first voltage PUMP_OUT. The input end of the reference noise suppression circuit NSC1 is used to connect to the clock signal CLK, the power supply AVDD, the reference voltage VREF and the feedback voltage VFB. The output end of the reference noise suppression circuit NSC1 is grounded via a capacitor C1, and the output end outputs a second voltage V01. The power supply voltage of the charge pump noise suppression circuit NSC2 is used to connect to the first voltage PUMP_OUT to be reduced. The input end of the charge pump noise suppression circuit NSC2 is connected to the second voltage V01. The output end of the charge pump noise suppression circuit NSC2 outputs a third voltage HVOUT and the feedback voltage VFB respectively. The third voltage HVOUT is the power supply voltage ultimately output to the high-voltage feedback drive circuit.

[0026] like Figure 3As shown, as an optional embodiment, the reference noise suppression circuit NSC1 includes a first chopper circuit CHOPPER1, an operational amplifier circuit AMP, a second chopper circuit CHOPPER2, and a dual-ended to single-ended operational amplifier circuit D2S. The inputs of the first chopper circuit CHOPPER1 are connected to a clock signal CLK, a reference voltage VREF, and a feedback voltage VFB. The reference voltage VREF serves as the non-inverting input, the feedback voltage VFB serves as the inverting input, and the clock signal CLK serves as the operating clock. The output of the first chopper circuit CHOPPER1 is connected to the input of the operational amplifier circuit AMP. The inputs of the first chopper circuit CHOPPER1 include a positive output and a negative output. The operational amplifier circuit AMP is a differential amplifier circuit. The positive output of the first chopper circuit CHOPPER1 is connected to the non-inverting input of the operational amplifier circuit AMP, while the negative output is connected to the inverting input of the operational amplifier circuit AMP. The inputs of the second chopper circuit CHOPPER2 are respectively connected to the output of the operational amplifier circuit AMP and the clock signal CLK. The clock signal CLK serves as the operating clock. The input of the second chopper circuit CHOPPER2 includes a positive input and a negative input, wherein the positive input is connected to the inverting output of the operational amplifier circuit AMP, and the negative input is connected to the non-inverting output of the operational amplifier circuit AMP. The output of the second chopper circuit CHOPPER2 is connected to a dual-end-to-single-ended operational amplifier circuit D2S. The output of the second chopper circuit CHOPPER2 includes a positive output and a negative output, wherein the positive output is connected to the non-inverting input of the dual-end-to-single-ended operational amplifier circuit D2S, and the negative output is connected to the inverting input of the dual-end-to-single-ended operational amplifier circuit D2S. The output of the dual-end-to-single-ended operational amplifier circuit D2S outputs a second voltage V01. That is, the output of the dual-end-to-single-ended operational amplifier circuit D2S is connected to capacitor C1.

[0027] The reference noise suppression circuit NSC1 modulates the reference voltage VREF to a high frequency using the clock signal CLK via the first chopper circuit CHOPPER1. Low-frequency noise contained in the reference voltage VREF is also modulated to a high frequency. The operational amplifier circuit AMP simultaneously amplifies the modulated noise, offset components, and valid signal. The second chopper circuit CHOPPER2 demodulates the amplified modulated signal to restore the signal. However, the noise and offset components contained in the modulated signal are modulated to the chopping frequency and are filtered out.

[0028] The two chopper circuits (the first chopper circuit CHOPPER1 and the second chopper circuit CHOPPER2) have the same structure. For ease of description, the structure of the first chopper circuit CHOPPER1 is used for description herein.

[0029] In some optional embodiments, such as Figure 4As shown, the structure of the first chopper circuit CHOPPER1 is designed as follows: the first chopper circuit CHOPPER1 includes a PMOS transistor MP1 (i.e., a first PMOS transistor), a PMOS transistor MP2 (i.e., a second PMOS transistor), a PMOS transistor MP3 (i.e., a third PMOS transistor) and a PMOS transistor MP4 (i.e., a fourth PMOS transistor).

[0030] The sources of MP1 and MP2 are both connected to the first positive input terminal VIP1. For example, the sources of MP1 and MP2 are connected and connected to the first positive input terminal VIP1. The sources of MP3 and MP4 are both connected to the first negative input terminal VIN1. The gates of MP1 and MP4 are both connected to the CKP signal, which is equivalent to the clock signal CLK. The gates of MP2 and MP3 are both connected to the CKN signal, which is the inverted clock signal CLK. The drains of MP1 and MP3 are both connected to the first positive output terminal VOP1. The drains of MP2 and MP4 are both connected to the first negative output terminal VON1.

[0031] The second chopper circuit, CHOPPER2, has the same structure as the first chopper circuit, CHOPPER1, including PMOS transistors MP5, MP6, MP7, and MP8. The connections between these four MOS transistors correspond to the connections between MP1, MP2, MP3, and MP4. To distinguish it from the other chopper circuits, the two input terminals of the second chopper circuit, CHOPPER2, are referred to as the second positive input terminal and the second negative input terminal. Its two output terminals are referred to as the second positive output terminal VOP2 and the second negative output terminal VON2.

[0032] The operational amplifier circuit performs differential amplification on the input signal. The operational amplifier circuit can use an existing packaged device, or construct a differential amplifier circuit based on the differential amplification principle.

[0033] In some optional embodiments, such as Figure 5 As shown, the dual-ended to single-ended operational amplifier circuit D2S includes a PMOS transistor MP9 (i.e., a fifth PMOS transistor), a PMOS transistor MP10 (i.e., a sixth PMOS transistor), an NMOS transistor MN1 (i.e., a first NMOS transistor), an NMOS transistor MN2 (i.e., a second NMOS transistor), a first NPN-type transistor NPN1, a second NPN-type transistor NPN2, a resistor R1, and a resistor R2.

[0034] The source of MP9 is connected to the positive output terminal VOP2 of the second chopper circuit CHOPPER2. The drain of MP9 is connected to the drain of MN1, the gate of MN1, and the gate of MN2, respectively. The source of MP10 is connected to the negative output terminal VON2 of the second chopper circuit CHOPPER2, and the drain of MP10 is connected to the drain of MN2. The drain of MP10 outputs the second voltage V01. The substrate of MP9 is connected to the substrate of MP10 and is connected to the first bias voltage VB1. The gates of MP9 and MP10 are connected to the second bias voltage VB2, respectively. The source of MN1 is connected to the collector of NPN1. The source of MN2 is connected to the collector of NPN2. MN1 and MN2 form a current mirror, achieving a single-ended output from a dual-ended input. The emitter of NPN1 is grounded via resistor R1. The emitter of NPN2 is grounded via resistor R2. Resistors R1 and R2 improve linearity while effectively suppressing the effects of ground noise on the second voltage V01. The bases of NPN1 and NPN2 are connected and connected to a second bias voltage, VB3. Using an NPN transistor as a current source bias circuit can effectively improve circuit matching performance and further reduce the probability of circuit mismatch compared to designs using MOS transistors.

[0035] Taking a sine wave signal as an example, signal modulation in the time domain is the multiplication of the signal wave and the carrier; signal demodulation is the multiplication of the modulated signal and the carrier again. Let the signal wave be , the carrier is , t represents time, represents the angular frequency. Then the modulated signal for: Formula 1: ; Since the demodulation clock is consistent with the modulation clock, the demodulated signal for: Formula 2: .

[0036] When the low-frequency noise is When , after passing through the chopping circuit twice, the low-frequency noise is decomposed into two parts as shown in Formula 2. The amplitude of the low-frequency part is 1 / 2 times of the original noise, and the high-frequency part has been modulated to 2 times the modulation frequency. This effectively suppresses the low-frequency noise. When the input offset voltage of the operational amplifier circuit AMP is represented, after passing through the chopper circuit once, the offset voltage is modulated to the modulation frequency as shown in Formula 1 and can be filtered out by low-pass filtering.

[0037] As an optional implementation, Figure 6As shown, the charge pump noise suppression circuit NSC2 includes an NMOS transistor MN3 (ie, a third NMOS transistor), a PMOS transistor MP11 (ie, a seventh PMOS transistor), a resistor R3, a resistor R4, and a variable resistor VAR1.

[0038] The gate of MN3 is connected to the second voltage V01, the source of MN3 is grounded, and the drain of MN3 is connected to the gate of MP11 and resistor R3, respectively. The source of MP11 is connected to resistor R3 and is connected to the first voltage PUMP_OUT. Resistor R3 is used to establish a verified DC operating point for the gate of MP11 and also defines the current in its branch. The drain of MP11 is connected in series with resistor R4 and variable resistor VAR1, and then to ground. The drain of MP11 outputs the third voltage HVOUT. The feedback voltage VFB is drawn between resistor R4 and resistor VAR1.

[0039] The above-mentioned reference noise suppression circuit NSC1 part embodiment and charge pump noise suppression circuit NSC2 part embodiment can be constructed as follows Figure 7 The noise reduction circuit shown. Figure 7 The noise reduction circuit shown in the figure can effectively suppress the low-frequency noise of the first voltage PUMP_OUT while ensuring the power input and output efficiency. Its low-frequency noise suppression capability for the first voltage PUMP_OUT is: Formula 3: .

[0040] Where, PSR (Power Supply Rejection) means power supply rejection, is the equivalent resistance at the output end, Ro3 is the equivalent impedance of MN3 collector, Gain_AMP Represents the gain of the operational amplifier circuit AMP, gmn3 Indicates the transconductance of NMOS tube MN3, gmp11 Indicates the transconductance of the PMOS tube MP11.

[0041] As can be seen from Formula 3, the noise reduction circuit of the above embodiment has a noise suppression capability on the first voltage PUMP_OUT output by the charge pump that is approximately the inverse of its loop gain, and the noise suppression effect is significant.

[0042] In general, the noise reduction circuit provided in the embodiments of the present application has the following features: Compared to the traditional direct power supply method of the charge pump circuit CP, the noise reduction circuit provided in the present application combines the advantages of the chopping circuit and low-voltage dropout linear voltage regulation technology to effectively suppress the low-frequency noise of the high-voltage feedback drive power supply and the reference voltage VREF. Its advantages are specifically reflected in: 1. The output voltage ripple of the charge pump circuit CP is effectively suppressed, which can provide a more stable power supply for the high-voltage feedback drive circuit in the MEMS sensor closed-loop circuit; 2. The chopping technology is used to suppress the low-frequency noise of the reference voltage VREF, further reducing the impact of low-frequency noise and op amp input offset on the output high-voltage power supply; 3. The rational use of NPN transistors effectively improves the matching performance of the circuit and reduces the probability of circuit offset; 4. The use of low-voltage dropout linear voltage regulation technology improves the load regulation rate of the output high-voltage power supply, while also minimizing the margin loss of the charge pump circuit CP output voltage.

[0043] According to the concept of the present application, the embodiment of the present application also provides a power supply circuit. The power supply circuit is suitable for MEMS sensor readout circuit. Figure 1 As shown, the power supply circuit includes a charge pump circuit CP and a noise reduction circuit designed in any of the above embodiments. The input end of the charge pump circuit CP is used to connect to the power supply AVDD, the output end is grounded via a capacitor C2, and the output end outputs a first voltage PUMP_OUT.

[0044] In addition, the present application also provides a readout circuit, which includes the above-mentioned power supply circuit. More specifically, in some embodiments, see the attached Figure 1 The readout circuit includes a power supply circuit and a high-voltage feedback drive circuit. The power supply circuit supplies power to the high-voltage feedback drive circuit, that is, the power supply circuit connects the output third voltage HVOUT to the high-voltage feedback drive circuit.

[0045] In addition, see the attached Figure 1 The present application also provides a detection circuit, including a capacitive MEMS sensor and the above-mentioned readout circuit. The readout circuit is connected to the capacitive MEMS sensor. According to the embodiment of the readout circuit described above, the high-voltage feedback drive circuit is connected to the capacitive MEMS sensor. Figure 1 In FIG, Cd1 and Cd2 are the equivalent capacitances between the movable mass block MASS and the upper plate and the lower plate of the driving capacitor, respectively.

[0046] The present invention is not limited to the aforementioned specific embodiments, but extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.

Claims

1. A noise reduction circuit, characterized in that: including a reference noise suppression circuit and a charge pump noise suppression circuit; The input end of the reference noise suppression circuit is used to receive a clock signal, a power supply, a reference voltage and a feedback voltage, the output end is grounded via a capacitor C1, and the output end outputs a second voltage; The power supply voltage of the charge pump noise suppression circuit is used to access the first voltage to be reduced, the input end is connected to the second voltage, and the output end outputs the third voltage and the feedback voltage respectively.

2. The noise reduction circuit according to claim 1, wherein: The reference noise suppression circuit includes a first chopper circuit, an operational amplifier circuit, a second chopper circuit and a dual-end to single-ended operational amplifier circuit; the input end of the first chopper circuit is used to receive the clock signal, the reference voltage and the feedback voltage, and the output end is connected to the input end of the operational amplifier circuit; the input end of the second chopper circuit is respectively connected to the output end of the operational amplifier circuit and the clock signal, and the output end is connected to the dual-end to single-ended operational amplifier circuit; the output end of the dual-end to single-ended operational amplifier circuit outputs the second voltage.

3. The noise reduction circuit according to claim 2, wherein: The structures of the first chopping circuit and the second chopping circuit are as follows: The invention comprises a first PMOS tube, a second PMOS tube, a third PMOS tube and a fourth PMOS tube; the source of the first PMOS tube and the source of the second PMOS tube are both connected to the positive input terminal; the source of the third PMOS tube and the source of the fourth PMOS tube are both connected to the negative input terminal; the gate of the first PMOS tube and the gate of the fourth PMOS tube are both connected to the clock signal; the gate of the second PMOS tube and the gate of the third PMOS tube are both connected to the inverted clock signal; the drain of the first PMOS tube and the drain of the third PMOS tube are both connected to the positive output terminal; the drain of the second PMOS tube and the drain of the fourth PMOS tube are both connected to the negative output terminal.

4. The noise reduction circuit according to claim 2, wherein: The dual-end to single-end operational amplifier circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first NPN transistor, a second NPN transistor, a first fixed resistor and a second fixed resistor; The source of the fifth PMOS transistor is connected to the positive output terminal of the second chopper circuit, and the drain is respectively connected to the drain of the first NMOS transistor, the gate of the first NMOS transistor, and the gate of the second NMOS transistor; The source of the sixth PMOS transistor is connected to the negative output terminal of the second chopper circuit, and the drain is connected to the drain of the second NMOS transistor; the drain of the sixth PMOS transistor outputs the second voltage; The substrate of the fifth PMOS transistor is connected to the substrate of the sixth PMOS transistor; The source of the first NMOS transistor is connected to the collector of the first NPN transistor; The source of the second NMOS transistor is connected to the collector of the second NPN transistor; The emitter of the first NPN transistor is grounded via the first fixed resistor; the emitter of the second NPN transistor is grounded via the second fixed resistor; the base of the first NPN transistor is connected to the base of the second NPN transistor.

5. The noise reduction circuit according to claim 1, wherein: The charge pump noise suppression circuit includes a third NMOS transistor, a seventh PMOS transistor, a third fixed-value resistor, a fourth fixed-value resistor and a first variable resistor; The gate of the third NMOS transistor is connected to the second voltage, the source is grounded, and the drain is connected to the gate of the seventh PMOS transistor and the third fixed resistor respectively; The source of the seventh PMOS transistor is connected to the third fixed resistor and is connected to the first voltage; the drain of the seventh PMOS transistor is connected in series with the fourth fixed resistor and the first variable resistor and then to ground; the drain of the seventh PMOS transistor outputs the third voltage; The feedback voltage is drawn between the fourth fixed resistor and the first variable resistor.

6. A power supply circuit, characterized in that: comprising a charge pump circuit and a noise reduction circuit as claimed in any one of claims 1 to 5; The input end of the charge pump circuit is used to connect to the power supply, the output end is grounded via the capacitor C2, and the output end outputs the first voltage.

7. A readout circuit, characterized in that: Comprising the power supply circuit as claimed in claim 6.

8. A detection circuit comprising a capacitive MEMS sensor, characterized in that: The device further comprises a readout circuit as claimed in claim 7, wherein the readout circuit is connected to the capacitive MEMS sensor.

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