Broadband background calibration module and method and time-interleaved analog-to-digital converter

Abstract

The invention provides a broadband background calibration module and method and a time-interleaved analog-to-digital converter, the broadband background calibration module comprises a clock source, N error compensation units and N error estimation units, and N is a natural number greater than or equal to 2; the clock source is used for providing N clock signals, and each clock signal has a preset phase difference; the input ends of the error estimation units are connected with the output ends of the error compensation units in a one-to-one correspondence mode, and corresponding phase compensation signals are generated based on the relative offset of the corresponding sampling clocks and the reference clocks. And the input end of each error compensation unit is connected to the clock source and the output end of the corresponding error estimation unit, and performs phase compensation on the corresponding clock signal based on the phase compensation signal to obtain a sampling clock of each sub-ADC unit in the time-interleaved analog-to-digital converter. According to the broadband background calibration module, the broadband background calibration method and the time-interleaved analog-to-digital converter, broadband calibration can be realized, and meanwhile, obvious increase in area and power consumption cannot be brought.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a broadband background calibration module, method and time-interleaved analog-to-digital converter. Background Art

[0002] With the advancement of electronics and communications technology, the bandwidth of various communication systems continues to increase. The analog-to-digital converter (ADC), the bridge between digital systems and the analog world, has seen its data throughput rapidly increase. Most mainstream high-speed ADCs now utilize time interleaving technology. A time-interleaved analog-to-digital converter (TIADC) staggers the sampling phases of multiple sub-ADCs, alternately sampling the same signal in time and integrating the digital codes at the output, ultimately doubling the sampling rate.

[0003] However, variations in layout design and chip manufacturing can lead to variations in consistency between sub-channels, severely limiting overall performance. Channel-to-channel mismatches in TIADC systems include offset mismatch, gain mismatch, and sampling time mismatch. Analyzing and correcting these mismatches can significantly improve overall ADC performance.

[0004] Sampling time mismatch refers to the uneven phase difference between the sampling clocks of adjacent sub-channels. If the time interval is not the ideal Ts, or the time delay of the input signal reaching each sub-channel is inconsistent, it will lead to sampling time mismatch. Figure 1 As shown, under ideal conditions, each sampling time t0, t1...t M-2 , t M-1 Uniform distribution (the time difference between adjacent sampling moments is Ts). Figure 2 As shown, in actual use, each sampling time t0, t1...t M-2 , t M-1 There may be mismatches, and the amount of mismatch (δ0, δ1...δ M-2 , δ M-1 ) are not exactly the same, resulting in inconsistent time differences between sampling moments. Therefore, for a time-interleaved analog-to-digital converter with M channels, as long as there is a deviation in the sampling clocks of any two sub-ADCs, the system can be considered to have sampling clock mismatch. Sampling clock mismatch will cause distortion and noise in the spectrum, such as Figure 3 As shown in FIG, performing sampling clock mismatch calibration on the time-interleaved analog-to-digital converter is the key to ensuring high accuracy of the overall ADC.

[0005] To ensure the normal operation of the chip, it is generally necessary to add TIADC channel mismatch calibration technology. The traditional reference channel-based calibration method requires the introduction of an additional channel. During the calibration process, the remaining channels gradually approach the reference channel to eliminate the channel mismatch, but this method will incur additional area and power consumption overhead. Calibration based on the derivative filter of the first-order Taylor expansion approximation is widely used in digital domain calibration, but this method may fail to calibrate the integer frequency points, which seriously limits the performance of the wideband ADC. Calibration methods based on the statistical characteristics of the output signal usually have slow convergence speed and certain requirements for the input signal.

[0006] In fields such as radar and communications, the input signal usually far exceeds the Nyquist band. Therefore, a sampling mismatch calibration technology that can achieve broadband signal calibration is very necessary in time-interleaved ADC systems.

[0007] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of the present invention and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the technical background section of the present invention, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0008] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a broadband background calibration module, method and time-interleaved analog-to-digital converter to solve the problems of the prior art TIADC inter-channel mismatch calibration technology, such as high cost, limited broadband ADC performance, slow convergence speed, and requirements for input signals.

[0009] To achieve the above objectives and other related objectives, the present invention provides a broadband background calibration module for calibrating sampling time mismatch of a time-interleaved analog-to-digital converter. The broadband background calibration module includes at least:

[0010] A clock source, N error compensation units, and N error estimation units, where N is a natural number greater than or equal to 2;

[0011] The clock source is used to provide N clock signals, each clock signal having a preset phase difference;

[0012] The input end of each error estimation unit is connected to the output end of each error compensation unit in a one-to-one correspondence, and a corresponding phase compensation signal is generated based on the relative offset between the sampling clock output by the corresponding error compensation unit and the reference clock;

[0013] The input end of each error compensation unit is connected to the clock source and the output end of the corresponding error estimation unit, and receives a clock signal respectively. The phase compensation is performed on the corresponding clock signal based on the phase compensation signal provided by the error estimation unit to obtain the sampling clock of each sub-ADC unit in the time-interleaved analog-to-digital converter; wherein the phase difference between adjacent sampling clocks after compensation is consistent.

[0014] Optionally, the error estimation unit includes a phase detection module, a majority voting counter and a delay adjustment counter;

[0015] The phase detection module is connected to the output end of the corresponding error compensation unit to detect whether the sampling clock is ahead or behind the reference clock;

[0016] The majority voting counter counts the advance and lag of the sampling clock respectively, and outputs the voting result according to the majority voting principle;

[0017] The delay adjustment counter is connected to the output end of the majority voting counter and adjusts the phase compensation signal based on the voting result.

[0018] More optionally, the phase detection module is implemented using a trigger; the input end of the trigger is connected to the corresponding sampling clock, the clock end is connected to the reference clock, and the detection result is output; the majority voting counter counts the advance and lag situations in the detection result when the corresponding sampling clock arrives.

[0019] Optionally, the error compensation unit includes a decoder and a variable delay line;

[0020] The decoder receives the corresponding phase compensation signal and decodes the phase compensation signal to obtain the delay control signal of the variable delay line;

[0021] The input end of the variable delay line receives a corresponding clock signal, and adjusts the delay time of the clock signal to obtain the sampling clock.

[0022] More optionally, the variable delay line comprises a capacitor delay array and at least two stages of cascaded inverters;

[0023] One end of the M delay units in the capacitor delay array is connected between two stages of cascaded inverters, and the other end is grounded; based on the delay control signal, the corresponding delay unit is selected to be turned on to adjust the delay time; M is a natural number greater than or equal to 2.

[0024] To achieve the above objectives and other related objectives, the present invention further provides a broadband background calibration method for calibrating a sampling time mismatch of a time-interleaved analog-to-digital converter. The broadband background calibration method at least comprises:

[0025] 1) providing N clock signals with a preset phase difference, and providing each clock signal to each sub-ADC unit in the time-interleaved analog-to-digital converter as a sampling clock; wherein N is a natural number greater than or equal to 2;

[0026] 2) Detecting the relative phase relationship between each sampling clock and the reference clock, determining whether the corresponding sampling clock is ahead or behind, and providing a determination result;

[0027] 3) generating corresponding phase compensation signals based on the advance or lag of each sampling clock, and adjusting the delay time of the corresponding clock signal based on each phase compensation signal to achieve phase adjustment of the corresponding sampling clock;

[0028] 4) Return to step 2) until the phase differences between adjacent sampling clocks after compensation are consistent.

[0029] Optionally, in step 2), when the corresponding sampling clock arrives, it is determined whether the sampling clock is ahead of or behind the sampling clock.

[0030] More optionally, step 2) further includes the step of determining the final judgment of the advance or lag by majority voting within a preset period after obtaining the preliminary judgment of the advance or lag.

[0031] Optionally, in step 1), in the initial state, each clock signal obtains the corresponding sampling clock after an initial delay time; in step 3), when it is detected that the corresponding sampling clock is ahead, the delay time is increased by a preset time length; when it is detected that the corresponding sampling clock is lagging, the delay time is reduced by the preset time length.

[0032] More optionally, the initial delay time is configured as a middle value of the delay adjustment range.

[0033] Optionally, when at least two adjacent inconsistent determination results occur continuously, it is determined that the current sampling clock has completed calibration.

[0034] To achieve the above objectives and other related objectives, the present invention further provides a time-interleaved analog-to-digital converter, the time-interleaved analog-to-digital converter comprising at least: a sampling module, N sub-ADC units, a data selection module, and the above-mentioned broadband background calibration module;

[0035] The input end of the sampling module receives an analog input signal, and samples the analog input signal based on N sampling clocks provided by the broadband background calibration module;

[0036] The input end of each sub-ADC unit is connected to the output end of the sampling module, and performs analog-to-digital conversion on the N sampling signals output by the sampling module;

[0037] The data selection module is connected to the output end of each sub-ADC unit and outputs the data converted by each sub-ADC unit in sequence.

[0038] As described above, the broadband background calibration module, method, and time-interleaved analog-to-digital converter of the present invention have the following beneficial effects:

[0039] 1. In the broadband background calibration module, method and time-interleaved analog-to-digital converter of the present invention, the calibration of sampling time mismatch is independent of the input signal and is a broadband calibration method.

[0040] 2. The broadband background calibration module of the present invention does not significantly increase the area and power consumption, and has a low implementation cost.

[0041] 3. The broadband background calibration module, method and time-interleaved analog-to-digital converter of the present invention adopt majority voting technology, which has a certain suppression effect on clock jitter and noise, thereby improving accuracy.

[0042] 4. The broadband background calibration method of the present invention is background calibration, and the calibration value is continuously updated without affecting the normal conversion work of the analog-to-digital converter. At the same time, this calibration is independent of the offset mismatch calibration and gain mismatch calibration of the time-interleaved analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 Shown is a schematic diagram of the distribution of sampling times under ideal conditions.

[0044] Figure 2 The diagram shows the distribution of sampling times in actual applications.

[0045] Figure 3 Illustration of the output spectrum of a time-interleaved analog-to-digital converter shown with sampling time mismatch.

[0046] Figure 4 Shown is a structural schematic diagram of the broadband background calibration module of the present invention.

[0047] Figure 5 Shown is a schematic structural diagram of the first compensation channel of the present invention.

[0048] Figure 6 It is a schematic diagram showing an implementation of the phase detection module of the present invention.

[0049] Figure 7 Display as Figure 6 Schematic diagram of the working principle of the phase detection module.

[0050] Figure 8 It is a schematic structural diagram of the first error compensation unit of the present invention.

[0051] Figure 9It is a schematic diagram showing the principle of the reference clock of the present invention detecting each sampling clock.

[0052] Figure 10 Shown is a flow chart of the broadband background calibration method of the present invention.

[0053] Figure 11 Shown is a schematic structural diagram of the time-interleaved analog-to-digital converter of the present invention.

[0054] Component number description

[0055] 1 Broadband background calibration module

[0056] 11 Clock Source

[0057] 121 First error compensation unit

[0058] 12a decoder

[0059] 12b variable delay line

[0060] 12N Nth error compensation unit

[0061] 131 First Error Estimation Unit

[0062] 13a Phase detection module

[0063] 13b Majority Vote Counter

[0064] 13c Delay Adjustment Counter

[0065] 13N Nth error estimation unit

[0066] 2 Sampling Module

[0067] 3 sub-ADC units

[0068] 4 Data selection module DETAILED DESCRIPTION

[0069] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0070] See also Figures 1 to 11It should be noted that the diagrams provided in this embodiment are merely schematic illustrations of the basic concept of the present invention. Therefore, the diagrams only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0071] In a multi-channel time-interleaved analog-to-digital converter, the source of the sampling time mismatch comes from the uneven phase difference on the sampling clock. Therefore, the present invention compensates the sampling clock of each ADC sub-unit through an additional calibration module to ensure that the sampling clock has a uniform (same) phase difference. In the calibration module and calibration method proposed in this patent, the calibration of the sampling mismatch error does not depend on the input signal, and there is no need to integrate an additional signal generator inside the chip. Therefore, the calibration implementation cost is extremely low, and the calibration of broadband input signals can be completed. In addition, since the calibration module and calibration method of the present invention directly eliminate the uneven phase difference of the sampling clock from the root, they are relatively independent of the calibration of offset mismatch and gain mismatch, and there is no problem of mutual restraint.

[0072] like Figure 4 As shown, the present invention provides a broadband background calibration module 1 for calibrating the sampling time mismatch of a time-interleaved analog-to-digital converter. The broadband background calibration module includes:

[0073] A clock source 11, N error compensation units, and N error estimation units, where N is a natural number greater than or equal to 2. The value of N can be set according to the number of sub-ADC units in the time-interleaved analog-to-digital converter, including but not limited to 6, 8, 10, 16, 24, and 32, which are not detailed here.

[0074] like Figure 4 As shown, the clock source 11 is used to provide N clock signals, denoted as CK[N-1:0], and each clock signal CK[N-1:0] has a preset phase difference.

[0075] Specifically, errors are introduced during the generation and transmission of each clock signal CK[N-1:0]. This error causes unequal phase differences between adjacent clock signals CK[N-1:0], thereby causing sampling time mismatch of each sub-ADC unit.

[0076] like Figure 4 As shown, each error compensation unit corresponds to each error estimation unit one by one, and one error compensation unit and one error estimation unit form a compensation channel for realizing compensation for one clock signal; that is, there are N compensation channels corresponding to N clock signals one by one for compensation.

[0077] Specifically, the input of each error estimation unit is connected to the output of the corresponding error compensation unit, and a corresponding phase compensation signal is generated based on the relative offset between the sampling clock output by the corresponding error compensation unit and the reference clock. In this embodiment, each error estimation unit is denoted as a first error estimation unit 131 through an Nth error estimation unit 13N. Each error estimation unit detects whether the sampling clock advances or lags relative to the reference clock and generates a corresponding phase compensation signal based on the detection result. In this embodiment, the structures of each error estimation unit are identical. In actual use, the structures of each error estimation unit can be customized as needed, as long as they can detect the phase relationship between the sampling clock and the reference clock, and this embodiment is not limiting.

[0078] Specifically, the input of each error compensation unit is connected to the clock source 11 and the output of the corresponding error estimation unit. Each error compensation unit receives a clock signal and performs phase compensation on the corresponding clock signal based on the phase compensation signal provided by the error estimation unit to obtain a sampling clock for each sub-ADC unit in the time-interleaved analog-to-digital converter. In this embodiment, each error estimation unit is denoted as a first error compensation unit 121 ... an Nth error compensation unit 12N. Each error estimation unit receives a clock signal and adjusts the delay of the clock signal to obtain a sampling clock for each sub-ADC unit. After compensation, the phase differences between adjacent sampling clocks are consistent. In this embodiment, the structures of each error compensation unit are identical. In actual use, the structures of each error compensation unit can be individually configured as needed to achieve a consistent phase difference between adjacent sampling clocks after compensation, and this embodiment is not limited thereto.

[0079] like Figure 5 As shown, in this embodiment, the first compensation channel is taken as an example, including a first error compensation unit 121 and a first error estimation unit 131. The corresponding signal adaptive adjustment of other compensation channels will not be described in detail here.

[0080] Specifically, if Figure 5 As shown, the first error estimation unit 131 includes a phase detection module 13a, a majority voting counter 13b and a delay adjustment counter 13c.

[0081] More specifically, the phase detection module 13a is connected to the output of the corresponding error compensation unit to detect whether the sampling clock is ahead or behind the reference clock CLKref. Figure 6 As shown, the phase detection module 13a is implemented by a trigger (D trigger), the input terminal D of the trigger is connected to the corresponding sampling clock CLK0, the clock terminal Clk is connected to the reference clock CLKref, and the detection result DFFout0 is output; Figure 7As shown, when the sampling clock CLK0 is ahead of the reference clock CLKref (in this case, the sampling clock CLK0 is a solid line), the rising edge of the reference clock CLKref detects the high-level sampling clock CLK0 and outputs a high-level detection result DFFout0. Until the next rising edge of the reference clock CLKref, the detection result DFFout0 transitions to a low level (in this case, the detection result DFFout0 is a solid line). When the sampling clock CLK0 lags behind the reference clock CLKref (in this case, the sampling clock CLK0 is a dotted line), the rising edge of the reference clock CLKref detects the low-level sampling clock CLK0 and outputs a low-level detection result DFFout0 (in this case, the detection result DFFout0 is a dotted line). Therefore, by using the output of the phase detection module 13a as direction information for adjusting the sampling clocks of each sub-ADC unit, the sampling clock can be correctly adjusted.

[0082] More specifically, majority voting counter 13b counts the number of sampling clock advances and lags, respectively, and outputs the voting result based on the majority voting principle. In this embodiment, based on the phase detection module 13a being implemented using a trigger, majority voting counter 13b counts the number of advances and lags in the detection results corresponding to the arrival of the corresponding sampling clock. That is, for majority voting counter 13b in the first compensation channel, it only counts the number of advances and lags when the sampling clock CLK0 arrives, and does not count the detection results output during other reference clock CLKref cycles. Simultaneously, majority voting counter 13b records the number of high and low levels within a preset number of cycles, and uses the level with the highest number as the voting result, outputting the corresponding level, thereby ensuring calibration accuracy. For example, if the preset number of cycles is set to 16, and there are 12 high levels and 4 low levels within 16 cycles, the voting result is a high level. The number of preset cycles is set based on actual needs. In theory, a larger number of preset cycles results in higher accuracy.

[0083] More specifically, the delay adjustment counter 13c is connected to the output of the majority voting counter 13b and adjusts the phase compensation signal CTL0 based on the voting result. For example, the delay adjustment counter 13c has an initial count value, which corresponds to the initial delay time of the variable delay line 12b. (In this example, the initial count value is set to the middle value of the counting range. For example, if the counting range is set to 0-63, the initial count value is set to 31. In this case, the initial delay time is set to the middle value of the delay adjustment range, and can be set as needed in actual use.) The delay adjustment counter 13c performs an operation of adding 1 or subtracting 1 on the previous count value based on the voting result and inputs the adjusted count value into the first error compensation unit 121.

[0084] Specifically, if Figure 8 As shown, in this example, the first error compensation unit 121 includes a decoder 12a and a variable delay line 12b.

[0085] More specifically, the decoder 12a receives the corresponding phase compensation signal CTL0 and decodes the phase compensation signal CTL0 to obtain the delay control signal of the variable delay line 12b. The decoder 12a can be configured according to the structure of the variable delay line 12b, which will not be described in detail here.

[0086] More specifically, the input end of the variable delay line 12b receives the corresponding clock signal CK[0], adjusts the delay time of the clock signal CK[0], and obtains the corresponding sampling clock CLK0. Any variable delay line 12b structure is applicable to the present invention. As an example, Figure 8 As shown, the variable delay line 12b includes a capacitor delay array and at least two cascaded inverters. One end of the M delay units in the capacitor delay array is connected between the two cascaded inverters, and the other end is grounded, where M is a natural number greater than or equal to 2. Each delay unit includes a capacitor and a switch in series. When the switch is closed under the control of a delay control signal, the corresponding capacitor is connected to the delay line, resulting in a delay related to the capacitance value. The delay capability of the variable delay line 12b is t delay Mainly composed of load capacitance C delay The total capacitance of the capacitors connected to the delay line is determined by the size of the capacitors, which satisfies: Among them, V DD is the power supply voltage, I ave is the average current that charges and discharges the inverter over one cycle. The variable delay line 12b selects the corresponding delay unit to conduct based on the delay control signal to adjust the delay time. As an example, at the beginning of calibration, the total number of capacitors is at an intermediate position. Ultimately, based on the majority vote, the code value at the input of decoder 12a will repeatedly jump within ±1, indicating the completion of the calibration result. Therefore, the calibration accuracy of the broadband background calibration module 1 of the present invention depends on the accuracy of the variable delay line 12b and is not closely related to the detection circuit.

[0087] The calibration process of the present invention belongs to background calibration. When the PVT of the environment changes, the clock skew changes. At this time, the variable delay line 12b will be adjusted again to follow the changes in the external environment in real time to ensure that each sampling clock has a uniform phase difference.

[0088] The present invention also provides a broadband background calibration method for calibrating a sampling time mismatch of a time-interleaved analog-to-digital converter. The broadband background calibration method comprises:

[0089] 1) Provide N clock signals with a preset phase difference, and provide each clock signal to each sub-ADC unit in the time-interleaved analog-to-digital converter as a sampling clock; wherein N is a natural number greater than or equal to 2.

[0090] Specifically, in this embodiment, in the initial state, each clock signal obtains its corresponding sampling clock after an initial delay time. The initial delay time of each clock signal should be kept consistent as much as possible. As an example, the initial delay time is configured as the middle value of the delay adjustment range; in actual use, it can be set as needed.

[0091] 2) Detect the relative phase relationship between each sampling clock and the reference clock respectively, and determine whether the corresponding sampling clock is ahead or behind, and provide a determination result.

[0092] Specifically, if Figure 9 As shown, in this embodiment, a reference clock is used to sample each sampling clock to obtain a detection result, wherein each sampling clock corresponds to a period of the reference clock in sequence. The detection result obtained when the sampling clock arrives can be used as a judgment result to reflect information about whether each sampling clock is ahead of or behind the reference clock.

[0093] Specifically, in order to improve calibration accuracy, in this embodiment, after obtaining a preliminary judgment of whether to be ahead or behind, a majority voting principle is adopted within a preset period to determine a final judgment of whether to be ahead or behind.

[0094] 3) Generate corresponding phase compensation signals based on the advance or lag of each sampling clock, and adjust the delay time of the corresponding clock signal based on each phase compensation signal to achieve adjustment of the phase of the corresponding sampling clock.

[0095] Specifically, when it is detected that the corresponding sampling clock is ahead, the delay time is increased by a preset time length, and the sampling clock is moved back, so that the phase of the sampling clock is close to that of the reference clock; when it is detected that the corresponding sampling clock is behind, the delay time is reduced by a preset time length, and the sampling clock is moved forward, so that the phase of the sampling clock is close to that of the reference clock.

[0096] 4) Return to step 2) until the phase differences between adjacent sampling clocks after compensation are consistent.

[0097] Specifically, the delay time of the clock signal is continuously adjusted according to the relative phase relationship between the sampling clock and the reference clock so that the phase of the corresponding cycle of each sampling clock is consistent with that of the reference clock. Since the cycles of the reference clock are the same, the phase difference between adjacent sampling clocks is the same (i.e., one reference clock cycle).

[0098] It should be noted that in actual use, the phases of the corresponding cycles of the sampling clock and the reference clock may not be completely aligned. In this embodiment, when the judgment results of adjacent advances or lags are inconsistent, the current sampling clock is considered to have completed calibration. The calibration accuracy is determined by the accuracy of the variable delay line. To improve the accuracy of the calibration completion judgment, multiple (three or more) consecutive advance or lag judgment results can be monitored. When the judgment result repeatedly jumps between advance and lag, the calibration is considered complete.

[0099] like Figure 10 As shown, in this embodiment, the broadband background calibration method of the present invention is implemented based on the broadband background calibration module 1 of the present invention. The calibration process is as follows: After the chip is powered on, background calibration begins, and the sampling clock of each sub-ADC unit is fed into the corresponding error estimation unit. Each sampling clock is sampled based on the rising edge of the reference clock to obtain the phase signal of the sampling clock in each compensation channel. Based on the detection results of the majority voting counter at the arrival of the corresponding sampling clock, and a majority vote is performed on the detection results over multiple consecutive cycles, the delay adjustment counter adjusts the count value of the phase compensation signal according to the voting results (leading or lagging results correspond to +1 or -1 in the count value, respectively). The phase compensation signal is decoded to obtain the delay control signal of the variable delay line. Based on the delay control signal, the number of capacitors in the capacitor delay array that are turned on is adjusted. The detection and adjustment process is repeated until the majority voting counter's decision results are different before and after, indicating that the channel is calibrated. When all channels are calibrated, the phase difference between adjacent sampling clocks is consistent. If the environment changes, causing the phase to change, the detection and adjustment steps are repeated.

[0100] like Figure 11 As shown, the present invention further provides a time-interleaved analog-to-digital converter, which includes: a broadband background calibration module 1 of the present invention, a sampling module 2, N sub-ADC units 3 and a data selection module 4.

[0101] The broadband background calibration module 1 provides N sampling clocks, each with a consistent phase difference between adjacent sampling clocks. The sampling module 2 receives an analog input signal at its input and samples the analog input signal based on the N sampling clocks. The inputs of each sub-ADC unit 3 are connected to the output of the sampling module 2 and perform analog-to-digital conversion on the N sampled signals output by the sampling module 2. The data selection module 4 is connected to the output of each sub-ADC unit 3 and sequentially outputs the converted data from each sub-ADC unit 3.

[0102] In summary, the present invention provides a broadband background calibration module, method and time-interleaved analog-to-digital converter, wherein the broadband background calibration module includes a clock source, N error compensation units and N error estimation units, where N is a natural number greater than or equal to 2; the clock source is used to provide N clock signals, each clock signal has a preset phase difference; the input end of each error estimation unit is connected to the output end of each error compensation unit in a one-to-one correspondence, and a corresponding phase compensation signal is generated based on the relative offset between the sampling clock output by the corresponding error compensation unit and the reference clock; the input end of each error compensation unit is connected to the clock source and the output end of the corresponding error estimation unit, respectively receives a clock signal, and performs phase compensation on the corresponding clock signal based on the phase compensation signal provided by the error estimation unit to obtain the sampling clock of each sub-ADC unit in the time-interleaved analog-to-digital converter; the phase difference between each adjacent sampling clock after compensation is consistent. The broadband background calibration module, method and time-interleaved analog-to-digital converter of the present invention can realize broadband calibration without significantly increasing the area and power consumption. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial utilization value.

[0103] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A broadband background calibration module for calibrating the sampling time mismatch of a time-interleaved analog-to-digital converter, characterized in that: The broadband background calibration module at least includes: A clock source, N error compensation units, and N error estimation units, where N is a natural number greater than or equal to 2; The clock source is used to provide N clock signals, each clock signal having a preset phase difference; The input end of each error estimation unit is connected to the output end of each error compensation unit in a one-to-one correspondence, and a corresponding phase compensation signal is generated based on the relative offset between the sampling clock output by the corresponding error compensation unit and the reference clock; The input end of each error compensation unit is connected to the clock source and the output end of the corresponding error estimation unit, and receives a clock signal respectively. The phase compensation is performed on the corresponding clock signal based on the phase compensation signal provided by the error estimation unit to obtain the sampling clock of each sub-ADC unit in the time-interleaved analog-to-digital converter; wherein the phase difference between adjacent sampling clocks after compensation is consistent.

2. The broadband background calibration module according to claim 1, characterized in that: The error estimation unit includes a phase detection module, a majority voting counter and a delay adjustment counter; The phase detection module is connected to the output end of the corresponding error compensation unit to detect whether the sampling clock is ahead or behind the reference clock; The majority voting counter counts the advance and lag of the sampling clock respectively, and outputs the voting result according to the majority voting principle; The delay adjustment counter is connected to the output end of the majority voting counter and adjusts the phase compensation signal based on the voting result.

3. The broadband background calibration module according to claim 2, characterized in that: The phase detection module is implemented using a trigger; the input end of the trigger is connected to the corresponding sampling clock, the clock end is connected to the reference clock, and the detection result is output; the majority voting counter counts the leading and lagging situations in the detection result when the corresponding sampling clock arrives.

4. The broadband background calibration module according to claim 1, characterized in that: The error compensation unit includes a decoder and a variable delay line; The decoder receives the corresponding phase compensation signal and decodes the phase compensation signal to obtain the delay control signal of the variable delay line; The input end of the variable delay line receives a corresponding clock signal, and adjusts the delay time of the clock signal to obtain the sampling clock.

5. The broadband background calibration module according to claim 2, characterized in that: The variable delay line includes a capacitor delay array and at least two stages of cascaded inverters; One end of the M delay units in the capacitor delay array is connected between two stages of cascaded inverters, and the other end is grounded; based on the delay control signal, the corresponding delay unit is selected to be turned on to adjust the delay time; M is a natural number greater than or equal to 2.

6. A broadband background calibration method for calibrating the sampling time mismatch of a time-interleaved analog-to-digital converter, characterized in that: The broadband background calibration method at least includes: 1) providing N clock signals with a preset phase difference, and providing each clock signal to each sub-ADC unit in the time-interleaved analog-to-digital converter as a sampling clock; wherein N is a natural number greater than or equal to 2; 2) Detecting the relative phase relationship between each sampling clock and the reference clock, determining whether the corresponding sampling clock is ahead or behind, and providing a determination result; 3) generating corresponding phase compensation signals based on the advance or lag of each sampling clock, and adjusting the delay time of the corresponding clock signal based on each phase compensation signal to achieve phase adjustment of the corresponding sampling clock; 4) Return to step 2) until the phase differences between adjacent sampling clocks after compensation are consistent.

7. The broadband background calibration method according to claim 6, characterized in that: In step 2), when the corresponding sampling clock arrives, it is determined whether the sampling clock is ahead of or behind the sampling clock.

8. The broadband background calibration method according to claim 6 or 7, characterized in that: Step 2) also includes the step of determining the final judgment of whether to be ahead or behind by using the majority voting principle within a preset period after obtaining the preliminary judgment of whether to be ahead or behind.

9. The broadband background calibration method according to claim 6, characterized in that: In step 1), in the initial state, each clock signal obtains the corresponding sampling clock after an initial delay time; in step 3), when it is detected that the corresponding sampling clock is ahead, the delay time is increased by a preset time length; when it is detected that the corresponding sampling clock is lagging, the delay time is reduced by the preset time length.

10. The broadband background calibration method according to claim 9, characterized in that: The initial delay time is configured as a middle value of the delay adjustment range.

11. The broadband background calibration method according to claim 6, characterized in that: When at least two adjacent determination results are inconsistent, it is determined that the current sampling clock has completed calibration.

12. A time-interleaved analog-to-digital converter, characterized in that: The time-interleaved analog-to-digital converter comprises at least: a sampling module, N sub-ADC units, a data selection module and a broadband background calibration module according to any one of claims 1 to 5; The input end of the sampling module receives an analog input signal, and samples the analog input signal based on N sampling clocks provided by the broadband background calibration module; The input end of each sub-ADC unit is connected to the output end of the sampling module, and performs analog-to-digital conversion on the N sampling signals output by the sampling module; The data selection module is connected to the output end of each sub-ADC unit and outputs the data converted by each sub-ADC unit in sequence.

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