Dual-threshold stacked nanosheet device and preparation method thereof
By integrating channels with different thresholds in semiconductor devices and using metal gates of different thicknesses and materials to control the thresholds, the contradiction between power consumption and performance is resolved, the combination of low power consumption and high turn-on current is achieved, and the application flexibility and efficiency of the device are improved.
Patent Information
- Application Number
- CN202510736018.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-06-04
- Publication Date
- 2025-09-12
AI Technical Summary
Existing semiconductor devices have difficulty balancing power consumption and performance, and a single threshold voltage limits their flexibility and efficiency in different application scenarios.
A dual-threshold stacked nanosheet device is designed. By integrating two channels with different thresholds in the same device and using metal gates of different thicknesses and materials to control the threshold, low power consumption and high turn-on current are achieved.
It achieves both low power consumption and high turn-on current in different application scenarios, improving the flexibility and efficiency of the device.
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Figure CN120640705A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a dual-threshold stacked nanosheet device and a preparation method thereof. Background Art
[0002] With the continuous advancement of semiconductor technology, nanosheet structures have garnered widespread attention in the field of high-performance integrated circuits due to their unique properties and potential. However, practical applications of nanosheet devices still face a number of challenges. Existing semiconductor devices generally face a trade-off between power consumption and performance, and the demand for maintaining or improving device performance while pursuing low power consumption is growing.
[0003] Traditional semiconductor devices typically have a single threshold voltage, which limits their flexibility and efficiency in different application scenarios. For example, in low-power applications, a lower threshold voltage helps reduce device turn-on power consumption, but may sacrifice static power consumption and device stability. In high-performance applications, a higher threshold voltage can provide better device control and stability, but is often accompanied by higher turn-on power consumption.
[0004] In view of this, the present invention is proposed. Summary of the Invention
[0005] The purpose of the present invention is to provide a dual-threshold stacked nanosheet device and a preparation method thereof, which achieves both low power consumption and high turn-on current by integrating two channels with different thresholds into the same device.
[0006] The present invention provides a dual-threshold stacked nanosheet device, comprising a substrate and a stacked nanosheet arranged on the substrate, wherein the stacked nanosheet comprises a plurality of stacked nanosheet channels, a high-K dielectric layer and a metal gate are sequentially arranged between the plurality of nanosheet channels, and the metal gate below the bottom nanosheet channel is different from the other metal gates in at least thickness.
[0007] There is no strict restriction on the thickness difference between the metal gate below the bottom nanosheet channel and the rest of the metal gates. The thickness of the metal gate below the bottom nanosheet channel only needs to be different from the thickness of the rest of the metal gates. More specifically, the thickness difference between the metal gate below the bottom nanosheet channel and the rest of the metal gates can be 3-10nm.
[0008] Furthermore, the material of the metal gate below the bottom nanosheet channel is different from that of the other metal gates; more specifically, the difference between the material type of the metal gate below the bottom nanosheet channel and the material type of the other metal gates may be ≥1.
[0009] The metal gate includes at least one N-type work function metal and / or a P-type work function metal. In this case, the metal gate below the bottom nanosheet channel and the remaining metal gates have a smaller thickness, including at least one N-type work function metal or P-type work function metal, while the thicker metal gate includes at least one N-type work function metal or P-type work function metal and at least one other metal gate.
[0010] There is no strict restriction on the type of N-type work function metal or P-type work function metal, and it can be reasonably set according to actual needs; specifically, the N-type work function metal can be selected from at least one of TiAlC, TiAl, V2O5, ZnO, and TiO2; the P-type work function metal can be selected from at least one of TiN, TaN, NiO, Cu2O, and MnO.
[0011] The present invention also provides a method for preparing a dual-threshold stacked nanosheet device, comprising the following steps:
[0012] S1: growing a sacrificial layer and a channel layer sequentially on the substrate, and controlling the thickness of the bottom sacrificial layer to be different from that of the other sacrificial layers;
[0013] S2: Photolithography and etching to form a fin-type active area;
[0014] S3: Fabricate sidewalls and source / drain regions, selectively remove the sacrificial layer, and form a stacked nanosheet comprising multiple nanosheet channels;
[0015] S4: Filling high-K dielectric and metal gate, controlling the metal gate under the bottom nanosheet channel to be different from the remaining metal gates at least in thickness.
[0016] In step S1 , there is no strict limitation on the substrate, and bulk silicon, SOI, FDSOI and other semiconductor substrate materials can be used.
[0017] The material of the sacrificial layer can be Si x Ge 1-x , where 0.3≤x≤0.9; the channel layer can be made of Si. The thickness and number of the sacrificial and channel layers are not strictly limited and can be appropriately set based on actual needs. Specifically, the thickness of the bottom sacrificial layer can be 5-30 nm, and the thickness of the remaining sacrificial layers can be 5-30 nm. There is no strict limit on the thickness difference between the bottom sacrificial layer and the remaining sacrificial layers, as long as the thickness of the bottom sacrificial layer is different from that of the remaining sacrificial layers. More specifically, the thickness difference between the bottom sacrificial layer and the remaining sacrificial layers can be 3-10 nm.
[0018] The thickness of the channel layer can be 5-20nm. The channel layer can be an intrinsic channel or lightly doped according to actual needs. There is no strict restriction on the doping type and doping elements of the channel layer, which can be reasonably set according to actual needs. The doping concentration of the channel layer can be 1017 / cm 3 .
[0019] In step S3, the doping type of the source and drain regions is not fixed according to P type or N type; the doping concentration of the source and drain regions can be 10 16 -10 21 / cm 3 .
[0020] In step S4, the material of the high-K dielectric can be HfO2, La2O3, Al2O3, etc.; the thickness of the high-K dielectric layer can be 1-5 nm.
[0021] When filling the metal gate, first fill at least one N-type work function metal or P-type work function metal in the sacrificial layer area with a smaller thickness, and then fill at least one N-type work function metal, P-type work function metal or metal gate of other materials in the sacrificial layer area with a larger thickness, so that the metal gate under the bottom nanosheet channel is different from the other metal gates at least in thickness.
[0022] The present invention integrates two channels with different thresholds into the same device, thereby achieving both low power consumption and high turn-on current, thereby improving the flexibility and efficiency of the device in different application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS
[0023] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0024] Figure 1 is a schematic structural diagram of the substrate;
[0025] Figure 2 Si x Ge 1-x Schematic diagram of the structure of / Si stack;
[0026] Figure 3 Schematic diagram of the structure of the fin-type active area;
[0027] Figure 4 Schematic diagram of the structure of the sidewall and source and drain regions;
[0028] Figure 5 Schematic diagram of the structure of stacked nanosheets;
[0029] Figure 6 Schematic diagram of the local structure of the dual-threshold stacked nanosheet device.
[0030] Description of reference numerals:
[0031] 1: substrate; 2: germanium silicon layer; 21: bottom germanium silicon layer; 22: remaining germanium silicon layers; 3: silicon layer; 4: sidewall spacer; 5: source; 6: drain; 71: bottom metal gate; 72: remaining metal gates. DETAILED DESCRIPTION
[0032] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present application belongs.
[0033] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular also includes the plural. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.
[0034] The following will clearly and completely describe the technical solutions of the present invention in conjunction with the embodiments. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.
[0035] Example 1
[0036] The preparation method of the dual-threshold stacked nanosheet device of this embodiment comprises the following steps:
[0037] 1. Provide substrate
[0038] There is no strict limitation on the substrate 1 used, and bulk silicon, SOI, FDSOI and other semiconductor substrate materials may be used. This embodiment is described by taking the SOI substrate as an example.
[0039] like Figure 1 As shown, the SOI substrate includes a Si substrate, a Box layer (ie, an insulating isolation layer) and a top silicon layer (top silicon channel) arranged in sequence from bottom to top, wherein the Box layer is an extremely thin silicon oxide (SiO2) layer.
[0040] 2. Making stacked nanosheets
[0041] A sacrificial layer and a channel layer are sequentially epitaxially grown on a substrate, and the thickness of the bottom sacrificial layer is controlled to be different from that of the remaining sacrificial layers. The thickness difference between the bottom sacrificial layer and the remaining sacrificial layers can be 3 - 10 nm. There are no strict restrictions on the materials, thicknesses, and number of layers of the sacrificial layer and the channel layer, and they can be reasonably set according to actual requirements.
[0042] In this embodiment, a nanosheet structure formed by the most classic SiGe stacked epitaxy method is taken as an example for illustration. In other embodiments, a three-dimensional nanosheet structure formed by other methods can also be used.
[0043] Combined with Figure 2 、 Figure 3 As shown, a germanium-silicon layer 2 (Si x Ge 1-x , 0.6 < x < 1) and a silicon layer 3 (Si-channel-2) are sequentially epitaxially grown on the top silicon layer (top silicon Channel-1) of the substrate 1 to form a Si x Ge 1-x / Si stack, where the thickness (T HKMG 1) of the bottom germanium-silicon layer 21 is different from the thickness (T HKMG 2) of the remaining germanium-silicon layers 22 above it. In this embodiment, two different thicknesses are taken as an example for illustration. In the actual process, the thickness of each germanium-silicon layer can be different.
[0044] More specifically, the thickness of the bottom germanium-silicon layer 21 can be 5 - 30 nm, the thickness of the remaining germanium-silicon layers 22 can be 5 - 30 nm, and the thickness of the silicon layer 3 can be 5 - 20 nm. There is no strict restriction on the size of the thickness difference between the bottom germanium-silicon layer 21 and the remaining germanium-silicon layers 22. As long as the thickness of the bottom germanium-silicon layer 21 is different from that of the remaining germanium-silicon layers 22. More specifically, the thickness difference between the bottom germanium-silicon layer 21 and the remaining germanium-silicon layers 22 can be 3 - 10 nm, and the thickness of the bottom germanium-silicon layer 21 can be greater than or less than the thickness of the remaining germanium-silicon layers 22.
[0045] The channel layer (i.e., the silicon layer 3) can be an intrinsic channel or can be lightly doped according to actual needs. There are no strict restrictions on the doping type and doping elements of the channel layer, and they can be reasonably set according to actual needs. The doping concentration of the channel layer can be 10 17 / cm 3 。
[0046] 3. Lithography and etching to form Fin
[0047] Combined with Figure 3 As shown, a fin (Fin) active region structure is fabricated through conventional lithography and etching processes.
[0048] 4. Fabricate sidewalls and source / drain regions
[0049] Combined with Figure 4 As shown, a shallow trench isolation layer is formed on the Fin active area structure, and after CMP flattening, annealing and etching are performed to expose the Si x Ge 1-x / Si stacked structure.
[0050] Deposit a gate oxide layer and an amorphous silicon film, and etch to form a dummy gate.
[0051] The sidewall 4 is made in a conventional way. After the sidewall 4 is formed, the source 5 and drain 6 are grown by epitaxial growth technology, and the source and drain doping is performed. The type of source and drain doping is not fixed according to P type or N type. The doping concentration of the source and drain region can be 10 16 -10 21 / cm 3 .
[0052] 5. Release the nanosheet channel
[0053] Combine Figure 5 As shown, an interlayer dielectric layer (ILD0) is deposited, a CMP process is performed to expose the dummy gate, and then the dummy gate is removed by etching.
[0054] Selective removal of the SiGe layer 2 (Si x Ge 1-x ), releasing the nanosheet channel (Si-channel-2, i.e. silicon layer 3).
[0055] 6. Filling high-K metal gate (HKMG)
[0056] Combine Figure 6 As shown, a high-K dielectric layer (not shown) is first deposited. The material of the high-K dielectric layer can be HfO2, La2O3, Al2O3, etc., and the thickness of the high-K dielectric layer can be 1-5nm; then a metal gate is deposited, and the thickness difference between the underlying silicon germanium layer 21 and the remaining silicon germanium layers 22 is used to fill in different amounts and / or thicknesses of work function metals, so that the metal gate under the underlying nanosheet channel (i.e., the underlying metal gate 71) is at least different in thickness from the remaining metal gates 72, thereby adjusting the threshold.
[0057] For example, when ALD fills high-k dielectric (HK) and metal gate (MG), assuming T HKMG1 <T HKMG2 , when a layer of work function metal is filled in, T HKMG1 The area has been filled, but T HKMG2 The area is thicker and not fully filled. At this time, one or more layers of metal with the same or different work function materials are filled to make the thresholds of channel 1 (top silicon Channel-1) and channel 2 (Channel-2) different. HKMG1 With T HKMG2 The thickness relationship can be adjusted according to actual needs.
[0058] Select the corresponding work function metal type according to the device type; for example, NMOS devices select N-type work function metal, and the N-type work function metal is selected from at least one of TiAlC, TiAl, V2O5, ZnO, and TiO2; PMOS devices select P-type work function metal, and the P-type work function metal is selected from at least one of TiN, TaN, NiO, Cu2O, and MnO.
[0059] 7. Metal Interconnect
[0060] Chemical mechanical planarization (CMP) is used to remove excess metal gates, followed by interlayer dielectric (ILD) filling.
[0061] Photolithography and etching of the interlayer dielectric to form contact holes, cleaning and removal of the natural oxide layer in the contact holes, filling the contact holes with contact metal and performing silicidation annealing.
[0062] Deposit a metal layer, perform photolithography and etching, and form the first interconnection metal layer M1.
[0063] Combine Figure 6 As shown, the dual-threshold stacked nanosheet device of this embodiment includes a substrate 1 and a stacked nanosheet disposed on substrate 1. The stacked nanosheet includes multiple stacked nanosheet channels (Channel-2, i.e., silicon layer 3). A high-K dielectric layer (not shown) and a metal gate are sequentially disposed between the multiple nanosheet channels. The metal gate below the bottom nanosheet channel (i.e., bottom metal gate 71) is at least different in thickness from the remaining metal gates 72. Sidewall spacers 4 are disposed on both sides of the stacked nanosheet, and a source 5 and a drain 6 are disposed on either side of the sidewall spacers 4.
[0064] There is no strict restriction on the thickness difference between the bottom metal gate 71 and the remaining metal gates 72. The thickness of the bottom metal gate 71 only needs to be different from the thickness of the remaining metal gates 72. More specifically, the thickness difference between the bottom metal gate 71 and the remaining metal gates 72 can be 3-10nm.
[0065] Furthermore, the material of the bottom metal gate 71 may also be different from that of the other metal gates 72 ; more specifically, the difference between the material type of the bottom metal gate 71 and the material type of the other metal gates 72 may be ≥1.
[0066] The metal gate includes at least one N-type work function metal and / or a P-type work function metal. In this case, among the bottom metal gate 71 and the remaining metal gates 72, the thinner metal gate includes at least one N-type work function metal or P-type work function metal, while the thicker metal gate, in addition to including at least one N-type work function metal or P-type work function metal, also includes at least one N-type work function metal, P-type work function metal, or a metal gate made of another material. There is no strict restriction on the type of N-type work function metal or P-type work function metal and it can be appropriately set according to actual needs.
[0067] In addition to the above differences, other structures of the dual-threshold stacked nanosheet device of this embodiment can adopt conventional structures in the art.
[0068] In this embodiment, by adjusting Si x Ge 1-x The thickness of the Si / Si stack is adjusted to adjust the fill thickness of the high-K metal gate in the bottom channel. By filling different amounts and / or types of work function metals, the thresholds of the bottom channel (top silicon Channel-1) and the nanosheet channel (Channel-2) are modulated to form a threshold range. At low thresholds, only the bottom channel is turned on, and at high thresholds, both are turned on simultaneously, thereby reducing static power consumption. This method can be applied to the field of low-power circuits. The above method integrates two channels with different thresholds into the same device, thereby achieving both low power consumption and high turn-on current, improving the flexibility and efficiency of the device in different application scenarios.
[0069] Example 2
[0070] This embodiment is a specific implementation of embodiment 1 (T HKMG1 <T HKMG2 ).
[0071] Specifically, when preparing a dual-threshold stacked nanosheet device, the thickness of the bottom germanium silicon layer 21 is 10nm, the thickness of the remaining germanium silicon layer 22 is 14nm, and the thickness of the silicon layer 3 is 10nm; the thickness of the high-K dielectric layer is 4nm, the thickness of the bottom metal gate 71 is 6nm, and the thickness of the remaining metal gate 72 is 10nm. The material of the bottom metal gate 71 and the remaining metal gate 72 is TiN (P type).
[0072] In the dual-threshold stacked nanosheet device of this embodiment, the threshold of the bottom channel (top silicon Channel-1) is 0.16V, and the threshold of the nanosheet channel (Channel-2) is -0.33V.
[0073] Example 3
[0074] This embodiment is another specific implementation of embodiment 1 (T HKMG1 >T HKMG2 ).
[0075] Specifically, when preparing a dual-threshold stacked nanosheet device, the thickness of the bottom germanium silicon layer 21 is 14nm, the thickness of the remaining germanium silicon layer 22 is 10nm, and the thickness of the silicon layer 3 is 10nm; the thickness of the high-K dielectric layer is 4nm, the thickness of the bottom metal gate 71 is 10nm, and the thickness of the remaining metal gate 72 is 6nm. The material of the remaining metal gate 72 is TiAlC filled in first, and the material of the bottom metal gate 71 includes TiN that is continued to be filled in addition to the TiAlC filled in first.
[0076] In the dual-threshold stacked nanosheet device of this embodiment, the threshold of the bottom channel (top silicon Channel-1) is -0.21V, and the threshold of the nanosheet channel (Channel-2) is 0.34V.
[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A dual-threshold stacked nanosheet device, characterized in that: The invention comprises a substrate and a stacked nanosheet arranged on the substrate, wherein the stacked nanosheet comprises a plurality of stacked nanosheet channels, a high-K dielectric layer and a metal gate are sequentially arranged between the plurality of nanosheet channels, and the metal gate below the bottom nanosheet channel is different from the other metal gates in thickness at least.
2. The dual-threshold stacked nanosheet device according to claim 1, characterized in that: The thickness difference between the metal gate below the bottom nanosheet channel and the rest of the metal gate is 3-10nm.
3. The dual-threshold stacked nanosheet device according to claim 1, wherein: The metal gate beneath the bottom nanosheet channel is made of a different material than the rest of the metal gate.
4. The dual-threshold stacked nanosheet device according to claim 1, wherein: The metal gate includes at least one N-type work function metal and / or P-type work function metal.
5. The dual-threshold stacked nanosheet device according to claim 4, characterized in that: The N-type work function metal is selected from at least one of TiAlC, TiAl, V2O5, ZnO, and TiO2; the P-type work function metal is selected from at least one of TiN, TaN, NiO, Cu2O, and MnO.
6. A method for preparing a dual-threshold stacked nanosheet device, characterized in that: The steps include: S1: growing a sacrificial layer and a channel layer sequentially on the substrate, and controlling the thickness of the bottom sacrificial layer to be different from that of the other sacrificial layers; S2: Photolithography and etching to form a fin-type active area; S3: Fabricate sidewalls and source / drain regions, selectively remove the sacrificial layer, and form a stacked nanosheet comprising multiple nanosheet channels; S4: Filling high-K dielectric and metal gate, controlling the metal gate under the bottom nanosheet channel to be different from the remaining metal gates at least in thickness.
7. The preparation method according to claim 6, characterized in that The material of the sacrificial layer is Si x Ge 1-x , where 0.3≤x≤0.9; the material of the channel layer is Si.
8. The preparation method according to claim 6, characterized in that The thickness of the bottom sacrificial layer is 5-30 nm, and the thickness of the remaining sacrificial layers is 5-30 nm; the difference in thickness between the bottom sacrificial layer and the remaining sacrificial layers is 3-10 nm.
9. The preparation method according to claim 6, characterized in that The doping concentration of the source and drain regions is 10 16 -10 21 / cm 3 .
10. The preparation method according to claim 6, characterized in that The doping concentration of the channel layer is 10 17 / cm 3 .