Comb-shaped p-GaN gate semiconductor device integrated with LFER and HEMT

Abstract

The invention discloses a comb-shaped p-GaN gate semiconductor device integrated with an LFER and an HEMT, relates to a semiconductor technology, and provides a scheme for solving the problem of contradiction between on resistance and high voltage resistance in the prior art. The comb-shaped p-GaN gate semiconductor device integrating the LFER and the HEMT comprises the LFER integrated on one side of a substrate and the HEMT integrated on the other side of the substrate. The LFER and the HEMT are physically segmented through an isolation groove; the HEMT is provided with a comb-shaped first p-GaN layer on the corresponding AlGaN barrier layer, and the first p-GaN layer is provided with a first grid electrode matched with the first p-GaN layer in shape; the LFER is provided with a comb-shaped second p-GaN layer on the corresponding AlGaN barrier layer, and comb teeth of the second p-GaN layer are respectively provided with a corresponding second grid electrode. The LFER has the advantages that the contradictory relation between the conduction power consumption and the withstand voltage of the LFER is optimized through the comb-shaped second p-GaN layer, and low conduction resistance is kept while the breakdown voltage is increased. Meanwhile, the manufacturing process is compatible with a traditional p-GaN gate HEMT process, and monolithic integration with a traditional p-GaN gate HEMT device can be achieved.

Description

Technical Field

[0001] The present invention relates to semiconductor technology, and in particular to a comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT. Background Art

[0002] As a third-generation semiconductor, GaN material features a wide bandgap, high breakdown field strength, and high electron mobility, making it more suitable for high-frequency, high-power devices than traditional Si materials. Due to the polarization effect of the AlGaN / GaN heterojunction, traditional HEMT devices exhibit normally-on characteristics, while power electronics applications require normally-off devices, requiring specialized processes. Currently, the most mature process is the p-GaN gate process, which has already been commercialized. However, the problem of high gate leakage current caused by insufficient barrier at the interface between the p-GaN layer and the gate metal still exists.

[0003] In transistors such as MOSFETs, the PN junction formed by the device structure itself forms a body diode. This body diode provides a path for reverse current when the transistor is turned off, which can prevent voltage spikes and device damage, and can also achieve freewheeling function in topologies such as half-bridge. However, there is no body diode in the GaN HEMT device structure, so an external parallel diode is required to provide a reverse current path, but this solution has the following disadvantages: (1) The on-state voltage of the external SiC or GaN SBD is usually between 0.7 and 1.5V, which will generate large conduction losses. (2) The external solution will introduce additional parasitic parameters. The parasitic inductance caused by the bonding wire or PCB trace will cause voltage overshoot and circuit oscillation during high-frequency switching, increasing EMI noise. (3) The external diode requires independent packaging, PCB layout and heat dissipation design, which will lead to an increase in circuit area and system complexity.

[0004] Currently, researchers have proposed a variety of solutions for integrating diodes into GaN HEMTs: the University of Electronic Science and Technology of China proposed a parallel integration solution using PIN avalanche diodes, but since the on-state voltage of the PIN diode is as high as 3V, it results in large conduction losses; Xidian University proposed a parallel solution using integrated SBDs. Although this avoids many of the shortcomings of external diodes, the on-state voltage of the integrated SBD method in this solution is still very high, and the breakdown voltage of the GaN HEMT device after the integrated SBD is lower than that of the GaN HEMT without the SBD, thus sacrificing the device's high-voltage blocking capability to a certain extent. The structure of the integrated SBD uses a Schottky junction diode, which naturally has a Schottky voltage drop. According to common knowledge, this voltage drop is approximately 0.5V or more.

[0005] A patent filed by Chen Jing et al. at the Hong Kong University of Science and Technology uses fluorine ion implantation to pinch off the electron gas channel at the AlGaN / GaN heterojunction interface, thereby fabricating LFER. However, fluorine ion implantation can inject defects and impurities into the barrier layer and channel, potentially reducing channel carrier mobility and raising thermal stability issues.

[0006] TSMC's patent application describes an LFER structure. The technical parameters published in the patent show that when the drift length LD is 9μm, the breakdown voltage of the LFER is only 660V, and the voltage resistance level is relatively low.

[0007] The patent application filed by the University of Electronic Science and Technology of China describes an LFER structure with a composite gate. The composite gate structure consists of an enhancement gate structure and a depletion gate structure, where the enhancement gate structure is achieved by etching and thinning the barrier layer. Etching and thinning the barrier layer is difficult to precisely control and is prone to introducing impurities, which can easily lead to unstable threshold voltage and high on-resistance. Its voltage resistance is mainly achieved by increasing the length of the depletion channel, which is inefficient, will increase the device area and cost, and the dynamic on-resistance is difficult to control.

[0008] The patent applied for by the Institute of Microelectronics describes an LFER structure and manufacturing method. The second anode metal in the patent directly contacts the AlGaN barrier layer, that is, the gate is a traditional Schottky contact, and the corresponding device is a normally-on device, which is difficult to meet the safety requirements in actual power applications.

[0009] The Fifth Institute of Electronics has disclosed a LFER structure. The patent focuses on a hybrid anode structure with a gate and floating electrode structure, namely an ohmic contact electrode short-circuited with an enhanced insulated gate structure. The enhanced insulated gate structure has extremely high requirements for etching depth and quality, and the etching process is prone to introducing external impurities, making it difficult to achieve low on-state voltage and low on-state resistance. Therefore, the enhanced insulated gate structure has not yet been commercialized. According to the withstand voltage data published in the patent, the breakdown voltage it can achieve is about 400V, which is relatively low.

[0010] Wei Jin and others from Peking University improved the dynamic on-resistance degradation of p-GaN gate devices by introducing a p-GaN thin layer in the gate-drain region. However, since the introduced entire p-GaN thin layer partially depletes the two-dimensional electron gas between the barrier layer and the channel layer, that is, reduces the concentration of the two-dimensional electron gas, the absolute on-resistance value of the device in the on state is larger than that of the device without the p-GaN thin layer.

[0011] Recently, Jiawei Cui et al. from Peking University achieved a high breakdown voltage (~2.5kV) by embedding a p-GaN / AlGaN / GaN junction termination extension (JTE) structure in the anode region of the LFER. However, this solution suffers from the problems of large increase in on-resistance at high voltage and high on-voltage (~1V), which leads to large conduction losses.

[0012] USTC has disclosed an LFER with an island electrode structure. The island electrode enhances the depletion effect of carriers in the depletion region, resulting in a higher on-state voltage and increased conduction loss.

[0013] Therefore, how to simultaneously achieve diode integration with low on-state voltage and high withstand voltage characteristics while maintaining the normally-off characteristics of the p-GaN gate remains a technical challenge that needs to be solved urgently.

[0014] References:

[0015] [1]WANG H, WEI J, XIE R, et al. Maximizing the Performance of 650-V p-GaNGate HEMTs: Dynamic RON Characterization and Circuit Design Considerations[J]. IEEE Transactions on Power Electronics, 2017, 32(7):5539-49.

[0016] [2] Wang Zhuocheng, Chen Wanjun, Sun Ruize, et al. A p-GaN HEMT device with integrated avalanche diode structure, CN117393562A[P / OL].

[0017] [3] Jiang Xi, Pan Chaofan, Yuan Song, et al. A GaN HEMT device with integrated reverse diode and its preparation method, CN119317145A[P / OL].

[0018] [4] Chen Jing, Chen Wanjun, Zhou Chunhua. Integrated HEMT and lateral field effect rectifier combination, method and system, CN101562182A[P / OL].

[0019] [5] Huang Jingyuan, Cai Mingwei, Qiu Hanqin. HEMT-compatible lateral rectifier structure, CN105742348A[P / OL].

[0020] [6] Chen Wanjun, Cui Xingtao, Shi Yijun, et al. A gallium nitride heterojunction lateral rectifier, CN107910370A[P / OL].

[0021] [7] Kang Xuanwu, Liu Xinyu, Huang Sen, et al. A lateral gallium nitride power rectifier device and its manufacturing method, CN108365018A[P / OL].

[0022] [8] Shi Yijun, Chen Si, Fu Zhiwei, et al. Semiconductor devices, CN111952354A[P / OL].

[0023] [9] Wei Jin, Wu Yanlin, Yang Junjie, et al. A low dynamic resistance enhancement mode GaN device, CN115472686A[P / OL].

[0024]

[10] CUI J,YANG J,YU J,et al.GaN-on-sapphire JTE-anode lateral field-effect rectifier for improved breakdown voltage(>2.5kV)and dynamic RON[J].Applied Physics Letters, 2024,125(17).

[0025]

[11] Yang Shu, Tang Xi, Bian Xiuyi, et al. Group III nitride devices and preparation methods, CN118352422A[P / OL]. Summary of the Invention

[0026] The present invention aims to provide a comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT to solve the problems existing in the above-mentioned prior art.

[0027] The comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT described in the present invention comprises an LFER integrated on one side of a substrate and a HEMT integrated on the other side of the substrate; the LFER and HEMT are physically separated by an isolation trench;

[0028] The HEMT is provided with a comb-shaped first p-GaN layer on the corresponding AlGaN barrier layer, and a first gate with a matching shape is provided on the first p-GaN layer;

[0029] The LFER is provided with a comb-shaped second p-GaN layer on the corresponding AlGaN barrier layer, and corresponding second gates are respectively provided on the comb teeth of the second p-GaN layer.

[0030] The comb-shaped p-GaN gate semiconductor device described in the present invention, which integrates an LFER and a HEMT, has the advantage that the LFER and HEMT are integrated and connected via external metal wires to achieve parallel ohmic contact, resulting in low-loss bidirectional conduction. This structure eliminates the need for external diodes, reducing both parasitic capacitance and parasitic inductance while also reducing circuit area. The comb-shaped second p-GaN layer optimizes the conflicting relationship between the LFER's on-state power consumption and withstand voltage, increasing the breakdown voltage while maintaining low on-resistance. The manufacturing process of the present invention is also compatible with conventional p-GaN gate high electron mobility transistor processes, enabling monolithic integration with conventional p-GaN gate HEMT devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic structural diagram of the comb-shaped p-GaN gate semiconductor device described in the present invention.

[0032] Figure 2 It is a schematic structural diagram of the comb-shaped p-GaN gate semiconductor device described in the present invention after the interconnection metal is hidden.

[0033] Figure 3 It is a schematic diagram of the structure of the comb-shaped p-GaN gate semiconductor device of the present invention after the interconnection metal and the second gate are hidden.

[0034] Figure 4 FIG. 4 is a schematic diagram of the dimensions of the second p-GaN layer. FIG.

[0035] Reference numerals:

[0036] 101-substrate, 102-GaN buffer layer, 103-GaN channel layer, 104-AlGaN barrier layer;

[0037] 201 - first p-GaN layer, 202 - first source, 203 - first drain, 204 - first gate;

[0038] 211 - second p-GaN layer, 212 - second source, 213 - second drain, 214 - second gate, 215 - interconnecting metal. DETAILED DESCRIPTION

[0039] like Figures 1 to 4 As shown, the comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT described in the present invention includes an LFER integrated on one side of a substrate 101 and a HEMT integrated on the other side of the substrate 101; the LFER and the HEMT are physically separated by an isolation trench;

[0040] The HEMT is provided with a comb-shaped first p-GaN layer 201 on the corresponding AlGaN barrier layer 104, and a first gate 204 with a matching shape is provided on the first p-GaN layer 201;

[0041] The LFER is provided with a comb-shaped second p-GaN layer 211 on the corresponding AlGaN barrier layer 104 , and corresponding second gates 214 are respectively provided on the comb teeth of the second p-GaN layer 211 .

[0042] The specific structure includes an AlGaN barrier layer 104, a GaN channel layer 103, a GaN buffer layer 102 and a substrate 101 stacked in sequence; the isolation trench is provided in the middle of the AlGaN barrier layer 104 and the GaN channel layer 103; the AlGaN barrier layer 104 is provided with a mutually isolated first source 202, a first p-GaN layer 201 and a first drain 203 above one side of the isolation trench, and a mutually isolated second source 212, a second p-GaN layer 211 and a second drain 213 above the other side of the isolation trench; the first gate 204 is provided on the first p-GaN layer 201; the second gate 214 is provided on the second p-GaN layer 211, and the second source 212 and the second gate 214 are electrically connected via an interconnect metal 215;

[0043] The first p-GaN layer 201, the first source 202, the first drain 203, the first gate 204, the AlGaN barrier layer 104 and the GaN channel layer 103 constitute the HEMT;

[0044] The second p-GaN layer 211 , the second source 212 , the second drain 213 , the second gate 214 , the interconnect metal 215 , the AlGaN barrier layer 104 and the GaN channel layer 103 constitute the LFER.

[0045] The isolation trench penetrates the AlGaN barrier layer 104 and extends into the GaN channel layer 103 .

[0046] The comb teeth of the first p-GaN layer 201 extend freely from the first source 202 to the first drain 203 .

[0047] The comb teeth of the second p-GaN layer 211 extend freely from the second source 212 to the second drain 213 .

[0048] The structure of the first p-GaN layer 201 is the same as that of the second p-GaN layer 211 .

[0049] The relationship between the comb-tooth width d1, comb-tooth spacing d2 and duty cycle η of the second p-GaN layer 211 is: Where n is the number of comb teeth.

[0050] The second p-GaN layer 211 has a length L of 1 μm to 100 μm and a width W of 5 μm to 1000 μm.

[0051] The operating principle of the comb-shaped p-GaN gate semiconductor device integrating an LFER and a HEMT described in this invention is as follows: For the HEMT, a p-GaN layer is introduced into the gate region of the AlGaN / GaN heterojunction. The polarization effect between the p-GaN and AlGaN forms a depletion region below the gate, blocking the two-dimensional electron gas (2DEG) and ensuring the device's normally-off characteristics. For the LFER, the anode is formed by shorting the second gate and the second source, and the cathode is the second drain. The introduction of p-GaN depletes the 2DEG channel below the anode, achieving forward conduction characteristics controlled by the anode voltage. This device has two significant advantages. First, during forward conduction, the device voltage drop is determined solely by the operating current and the resistance between the source and drain, eliminating the barrier voltage drop of traditional PIN or SBDs. This allows for an ultra-low on-state voltage drop of 0.4V or even lower, significantly reducing conduction losses. Second, the LFER uses a p-GaN gate structure similar to that between the gate and drain of the main HEMT device. Therefore, the HEMT device integrated with the LFER does not sacrifice the withstand voltage of the original HEMT device. In contrast, traditional SBD devices typically have a breakdown voltage lower than the breakdown voltage of HEMTs of the same specifications due to the image force barrier lowering effect. Therefore, the device structure proposed in this invention significantly outperforms traditional SBD or PIN diode integration in terms of both the voltage drop when the diode is conducting and the reverse withstand voltage of the device.

[0052] When in use, the first drain and the second source can be shorted together by an external metal wire, and the first source and the second drain can be shorted together, so that the LFER and the HEMT are connected in parallel. GS Exceeds the device threshold voltage V TH , and the drain-source voltage V DS When the voltage V is positive, the HEMT is forward-conducting, electrons flow from the first source to the first drain through the 2DEG channel, and current flows from the first drain to the first source. At this time, the LFER is turned off due to its reverse bias. DS is negative, and the HEMT's V GS At 0V, the HEMT is turned off, and current flows through the LFER channel from the second source to the second drain, achieving reverse conduction. This invention integrates the LFER with the HEMT, achieving low-loss bidirectional conduction through parallel ohmic contacts. This design eliminates the need for external diodes, reduces parasitic capacitance and inductance, and reduces circuit area.

[0053] Regarding the working principle of the comb-shaped second p-GaN layer 211: During the p-GaN gate device fabrication process, the two-dimensional electron gas beneath the p-GaN region is depleted, causing the device to be in the off state without an external bias, thus achieving normally-off operation. By metal-connecting the source and gate to form an LFER, the anode voltage acts directly on the gate, and the threshold voltage determines the LFER's turn-on voltage. By controlling the doping concentration and thickness of the p-GaN, a low turn-on voltage can be achieved, reducing conduction losses.

[0054] First, the comb-shaped p-GaN layer covering the surface of the barrier layer in the gate-drain region can effectively shield the interface states or traps on the barrier layer surface, reducing their capture of channel electrons, thereby suppressing the dynamic on-resistance degradation caused by the interface states. When the gate is forward biased, the comb-shaped p-GaN layer injects holes into the device. These holes recombine with deep-level negative charge centers in the buffer layer, neutralizing their repulsive effect, thereby reducing the scattering of the two-dimensional electron gas and further reducing the dynamic on-resistance. The deep-level negative charge centers are such as ionized traps.

[0055] Secondly, after the comb-shaped p-GaN gate field plate is introduced into the gate-drain region, the electric field lines originally concentrated at the gate edge are dispersed to the edge of the field plate formed by the p-GaN. The extended comb-shaped p-GaN and the n-type two-dimensional electron gas under the barrier layer form a lateral superjunction structure similar to a pn junction, which weakens the electric field peak at the gate metal edge and makes the electric field distribution between the gate and drain more uniform. Therefore, this comb-shaped field plate structure not only reduces the electric field concentration effect at the gate edge, but also forms a more uniform electric field distribution in the drift region, thereby improving the breakdown voltage of the device.

[0056] Again, although the introduction of p-GaN has the above-mentioned advantages, as mentioned above, due to the coverage of p-GaN, the two-dimensional electron gas between the barrier layer and the channel layer directly below the area will be partially depleted. Therefore, its concentration is lower than the two-dimensional electron gas concentration in the area without p-GaN coverage, which will lead to a decrease in the number of carriers when the device is forward-conducted, thereby increasing the forward on-resistance and reducing the on-current. In order to resolve this contradiction, a comb-shaped p-GaN gate structure is formed by selectively etching a portion of the p-GaN, reducing the total coverage area of ​​the p-GaN, and thereby reducing the degree of reduction in the two-dimensional electron gas concentration caused by the longitudinal depletion of p-GaN. Therefore, this structural design can effectively reduce the forward on-resistance and on-voltage of the device and increase the on-current of the device. When the drain or cathode is under high-voltage bias conditions, the width d1 of the P-GaN comb teeth and the spacing d2 between teeth are reasonably designed according to the duty cycle η. Due to the lateral depletion effect between the p-GaN teeth, it can be ensured that the area between the teeth will not be etched by the p-GaN, resulting in a reduction in the reverse withstand voltage of the device.

[0057] Therefore, compared with conventional p-GaN gate HEMT or LFER structures, LFER and HEMT devices using comb-shaped p-GaN gate structures can not only effectively increase the reverse breakdown voltage of the device and reduce the dynamic on-resistance of the device, but also achieve lower forward conduction voltage drop and on-resistance of the device, effectively improving the performance and reliability of the device.

[0058] Those skilled in the art can make various other corresponding changes and deformations based on the technical solutions and concepts described above, and all of these changes and deformations should fall within the scope of protection of the claims of the present invention.

Claims

1. A comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT, comprising an LFER integrated on one side of a substrate (101) and a HEMT integrated on the other side of the substrate (101); the LFER and HEMT are physically separated by an isolation trench; It is characterized by: The HEMT is provided with a comb-shaped first p-GaN layer (201) on the corresponding AlGaN barrier layer (104), and a first gate (204) with a matching shape is provided on the first p-GaN layer (201); The LFER is provided with a comb-shaped second p-GaN layer (211) on the corresponding AlGaN barrier layer (104), and corresponding second gates (214) are respectively provided on the comb teeth of the second p-GaN layer (211).

2. The comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT according to claim 1, characterized in that: The relationship between the comb tooth width d1, comb tooth spacing d2 and duty cycle η of the second p-GaN layer (211) is: Where n is the number of comb teeth.

3. The comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT according to claim 1, characterized in that: The second p-GaN layer (211) has a length L of 1 μm to 100 μm and a width W of 5 μm to 1000 μm.

4. The comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT according to claim 1, characterized in that: The specific structure comprises an AlGaN barrier layer (104), a GaN channel layer (103), a GaN buffer layer (102) and a substrate (101) stacked in sequence; the isolation trench is provided in the middle of the AlGaN barrier layer (104) and the GaN channel layer (103); the AlGaN barrier layer (104) is provided with a mutually isolated first source (202), a first p-GaN layer (201) and a first drain (203) above one side of the isolation trench, and a mutually isolated second source (212), a second p-GaN layer (211) and a second drain (213) above the other side of the isolation trench; the first gate (204) is provided on the first p-GaN layer (201); the second gate (214) is provided on the second p-GaN layer (211), and the second source (212) and the second gate (214) are electrically connected via an interconnecting metal (215); The first p-GaN layer (201), the first source (202), the first drain (203), the first gate (204), the AlGaN barrier layer (104) and the GaN channel layer (103) constitute the HEMT; The second p-GaN layer (211), the second source (212), the second drain (213), the second gate (214), the interconnecting metal (215), the AlGaN barrier layer (104) and the GaN channel layer (103) constitute the LFER.

5. The comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT according to claim 4, characterized in that: The isolation trench penetrates the AlGaN barrier layer (104) and extends into the GaN channel layer (103).

6. The comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT according to claim 4, characterized in that: The comb teeth of the first p-GaN layer (201) extend freely in a direction from the first source (202) to the first drain (203).

7. The comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT according to claim 4, characterized in that: The comb teeth of the second p-GaN layer (211) extend freely from the second source (212) to the second drain (213).

8. The comb-shaped p-GaN gate semiconductor device integrating LFER and HEMT according to claim 4, characterized in that: The structure of the first p-GaN layer (201) and the second p-GaN layer (211) may have the same or different thicknesses.

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