Field effect transistor, preparation method thereof and integrated circuit

Abstract

The invention relates to a field effect transistor, a preparation method thereof and an integrated circuit, and belongs to the technical field of semiconductor devices. The field effect transistor comprises an N + substrate layer, an N-drift layer and a gate structure which are sequentially stacked in the thickness direction, a plurality of channel repetition units arranged at intervals are arranged on the side, facing the gate structure, in the N-drift layer, and the orthographic projection of the gate structure on the N-drift layer covers the channel repetition units; wherein each channel repeating unit comprises a JFET (Junction Field Effect Transistor) region and a plurality of conducting channels arranged on the outer side of the JFET region; the conductive channels comprise first channels arranged on the two opposite sides of the JFET region in the first direction and second channels arranged on the two opposite sides of the JFET region in the second direction, and the first direction and the second direction are both perpendicular to the thickness direction. By increasing the number of conducting channels, the overlapping area of the gate structure and the JFET region is further reduced, and the on resistance and Miller capacitance of the device can be synchronously reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a field effect transistor and a method for manufacturing the same, and an integrated circuit. Background Art

[0002] In existing field-effect transistor structures, the area below the gate is primarily composed of the conductive channel region and the overlapping area between the gate structure and the junction field-effect transistor (JFET) region. The conductive channel is typically located only along the length of the gate electrode at the lower edge of the gate structure, resulting in a high on-resistance and a large Miller capacitance. However, with the development of power devices, the power density of devices continues to increase, requiring the on-resistance of the devices to be increasingly smaller, and the Miller capacitance, which affects switching losses, to be as small as possible. Therefore, there is an urgent need to design a new field-effect transistor structure that can simultaneously reduce the on-resistance and Miller capacitance of the device. Summary of the Invention

[0003] To solve the above problems, the purpose of this application includes providing a field effect transistor and a method for manufacturing the same, and an integrated circuit, so as to simultaneously reduce the on-resistance and Miller capacitance of the device.

[0004] In a first aspect, an embodiment of the present application provides a field effect transistor, comprising an N+ substrate layer, an N-drift layer and a gate structure stacked in sequence along a thickness direction, a plurality of spaced channel repetition units are provided on the side of the N-drift layer facing the gate structure, and the orthographic projection of the gate structure on the N-drift layer covers the channel repetition unit; wherein each channel repetition unit includes a JFET region and a plurality of conductive channels arranged outside the JFET region; the conductive channel includes a first channel arranged on opposite sides of the JFET region along a first direction, and a second channel arranged on opposite sides of the JFET region along a second direction, and the first direction and the second direction are both perpendicular to the thickness direction.

[0005] In the above technical solution, by providing a plurality of spaced-apart channel repeating units and providing a first channel along a first direction and a second channel along a second direction in each channel repeating unit, the density (number) of conductive channels is increased within a certain device repeating unit (cell pitch) size, thereby reducing the overlapping area of ​​the gate structure and the JFET region, thereby simultaneously reducing the on-resistance and Miller capacitance of the device.

[0006] In some embodiments of the present application, multiple channel repeating units are spaced apart in the N-drift layer along a first direction. The multiple channel repeating units are arranged along the first direction, corresponding to the first channel being arranged along the first direction, which can simplify the device structure design and reduce costs.

[0007] In some embodiments of the present application, multiple channel repeating units are arranged in a matrix within the N-drift layer. The matrix arrangement indicates that the multiple channel repeating units can be arranged in any manner of 1 row × 1 column or more. For example, when the first direction and the second direction are perpendicular, the multiple channel repeating units can be arranged in columns along the first direction and rows along the second direction to form a matrix arrangement. Thus, within a certain device repeating unit (cell pitch) size, the density (number) of the conductive channels can be further increased, thereby reducing the overlap area between the gate structure and the JFET region, thereby further reducing the on-resistance and Miller capacitance of the device.

[0008] In some embodiments of the present application, multiple conductive channels are arranged around the outside of the JFET region. This surrounding arrangement provides greater structural design flexibility, allowing parameters such as the number, width, and spacing of the conductive channels to be flexibly adjusted as needed, thereby further improving the device's electrical performance, such as enhancing current control capability and gate control efficiency.

[0009] In some embodiments of the present application, the shape of the channel repeating unit is square, circular, polygonal, diamond, or irregular. The channel repeating unit can be designed into a variety of shapes as needed, which increases design flexibility. In addition to the conductive channels arranged along the first direction and the second direction, conductive channels along other directions can also be designed, that is, the number, direction, and other parameters of the channels can be flexibly adjusted, thereby further reducing the on-resistance and Miller capacitance of the device.

[0010] In some embodiments of the present application, a plurality of P-well regions are provided in the N-drift layer on a side facing the gate structure, an N+ source region is provided in each P-well region, and the orthographic projection of the gate structure on the N-drift layer covers part of the N+ source region, part of the P-well region, and part of the N-drift layer located between the two P-well regions; wherein, the part of the N-drift layer covered by the orthographic projection of the gate structure on the N-drift layer forms a JFET region, and the part of the P-well region located between the JFET region and the N+ source region forms a conductive channel.

[0011] In some embodiments of the present application, a source and a drain are further included, the source is arranged on the side of the N-drift layer away from the N+ substrate layer, and the drain is arranged on the side of the N+ substrate layer away from the N-drift layer; wherein the source covers the gate structure and contacts at least a portion of the N+ source region.

[0012] In a second aspect, an embodiment of the present application provides a method for preparing the field effect transistor provided in the first aspect, comprising the following steps:

[0013] forming an N-drift layer on one side surface of the N+ substrate layer;

[0014] A plurality of P-well regions are formed in the N-drift layer on a side facing away from the N+ substrate layer, and a JFET region is formed in the N-drift layer between two portions of the P-well regions; the P-well regions include a first P-well region disposed on opposite sides of the JFET region along a first direction, and a second P-well region disposed on opposite sides of the JFET region along a second direction; wherein both the first direction and the second direction are perpendicular to a thickness direction of the N-drift layer;

[0015] An N+ source region is formed in the P-well region, and a portion of the P-well region between the N+ source region and the JFET region forms a conductive channel. One of the JFET regions and a plurality of conductive channels located outside the JFET region are defined as a channel repeating unit. Part of the first P-well region between the N+ source region and the JFET region forms a first channel, and part of the second P-well region between the N+ source region and the JFET region forms a second channel.

[0016] A gate structure is formed on a surface of a side of the N-drift layer where the P-well region is provided, and an orthographic projection of the gate structure on the N-drift layer covers the channel repeating unit.

[0017] In the above technical solution, by designing a first P-well region along a first direction and a second P-well region along a second direction when forming a P-well region within the N-drift layer, the area of ​​the P-well region is increased within a certain device repeating unit size. This increases the number of conductive channels after forming an N+ source region within the P-well region, thereby reducing the overlap area between the gate structure and the JFET region, thereby simultaneously reducing the device's on-resistance and Miller capacitance. This preparation method features simple process operation and high flexibility, making it suitable for industrial applications.

[0018] In some embodiments of the present application, after forming an N+ source region in the P-well region, the further step includes: forming a source electrode on a surface of the N-drift layer facing away from the N+ substrate layer, and forming a drain electrode on a surface of the N+ substrate layer facing away from the N-drift layer; wherein the source electrode covers the gate structure and contacts at least a portion of the N+ source region.

[0019] In a third aspect, an embodiment of the present application provides an integrated circuit, comprising the field effect transistor provided in the first aspect of the present application, or comprising a field effect transistor prepared by the preparation method provided in the second aspect of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0021] Figure 1It is a schematic diagram of the planar structure of a field effect transistor in the prior art.

[0022] Figure 2 For the Figure 1 Cross-sectional view along line AA0.

[0023] Figure 3 For the Figure 1 Cross-section of the BB0 line.

[0024] Figure 4 This is a schematic diagram of the cross-sectional structure after an N-drift layer is formed on one side surface of an N+ substrate layer provided in the first embodiment of the present application.

[0025] Figure 5 For Figure 4 The cross-sectional structure diagram is shown after a P-well region and a JFET region are formed in the N-drift layer.

[0026] Figure 6 for Figure 5 Schematic diagram of the planar structure.

[0027] Figure 7 For Figure 5 The cross-sectional view of the P-well region after the N+ source region is formed is shown.

[0028] Figure 8 for Figure 7 Schematic diagram of the planar structure.

[0029] Figure 9 For Figure 7 The cross-sectional structure diagram is shown after a P+ source region is formed in part of the N-drift layer.

[0030] Figure 10 For Figure 9 The cross-sectional structure diagram shown is a schematic diagram of the N-drift layer surface after a gate structure is formed.

[0031] Figure 11 A schematic diagram of the planar structure of the field effect transistor provided in the first embodiment of the present application.

[0032] Figure 12 For the Figure 11 Cross-section along line AA1.

[0033] Figure 13 For the Figure 11 Cross-section of line BB1.

[0034] Figure 14 A schematic diagram of the planar structure of a field effect transistor provided in the second embodiment of the present application.

[0035] Figure 15 For the Figure 14Cross-section view along line AA2.

[0036] Figure 16 For the Figure 14 Cross-section of the BB2 line.

[0037] Description of main component markings:

[0038] 10a, 10, 20 - N+ substrate layer; 11a, 11, 21 - N-drift layer; 12a, 12, 22 - P-well region; 121 - first P-well region; 122 - second P-well region; 13a, 13, 23 - JFET region; 14a, 14, 24 - N+ source region; 15a, 15, 25 - conductive channel; 151, 251 - first channel; 152, 252 - second channel; 16a, 16, 26 - P+ source region; 17a, 17, 27 - gate structure; 171a, 171, 271 - gate oxide layer; 172a, 172, 272 - gate; 173a, 173, 273 - interlayer dielectric layer; 18a, 18, 28 - source; 19a, 19, 29 - drain; C - channel repeating unit; X - first direction; Y - second direction; Z - third direction. DETAILED DESCRIPTION

[0039] Below, the field effect transistor, its preparation method, and the embodiment of the integrated circuit of the present application are described in detail with appropriate reference to the accompanying drawings. However, unnecessary detailed descriptions may be omitted. For example, detailed descriptions of well-known matters and repeated descriptions of substantially the same structures may be omitted. This is to avoid the following description from becoming unnecessarily lengthy and to facilitate understanding by those skilled in the art. In addition, the drawings and the following description are provided to enable those skilled in the art to fully understand the present application and are not intended to limit the subject matter described in the claims.

[0040] Unless otherwise specified, all embodiments and optional embodiments of the present application can be combined with each other to form a new technical solution.

[0041] Unless otherwise specified, all technical features and optional technical features of this application can be combined with each other to form a new technical solution.

[0042] Unless otherwise specified, all steps of the present application may be performed sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), indicating that the method may include steps (a) and (b) performed sequentially, or may include steps (b) and (a) performed sequentially. For example, the method may further include step (c), indicating that step (c) may be added to the method in any order, for example, the method may include steps (a), (b) and (c), or may include steps (a), (c) and (b), or may include steps (c), (a) and (b), etc.

[0043] It should be noted that the semiconductor field terms used in this application are technical terms commonly used by those skilled in the art. For example, for P-type and N-type doping, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0044] See Figure 1 、 Figure 2 and Figure 3 , Figure 1 Schematic diagram of a planar structure of a field effect transistor in the prior art. Figure 2 For the Figure 1 The cross-section of line AA0, Figure 3 For the Figure 1 Cross-sectional view along line BB0. The existing field-effect transistor structure includes a drain 19a, an N+ substrate layer 10a, an N-drift layer 11a, a gate structure 17a, and a source 18a, which are stacked sequentially along the thickness direction. The N-drift layer 11a is provided with a JFET region 13a along the length direction (i.e., the first direction X) and a conductive channel 15a disposed on opposite sides of the JFET region 13a. The orthographic projection of the gate structure 17a on the N-drift layer 11a covers the JFET region 13a and the conductive channel 15a. It can be seen that the conductive channel 15a, the JFET region 13a, and the corresponding gate structure 17a in the prior art are all arranged along the same direction (i.e., the length direction). The area below the gate structure 17a is mainly composed of the area of ​​the conductive channel 15a region and the overlapping area of ​​the gate structure 17a and the JFET region 13a. This results in a higher on-resistance and a larger Miller capacitance of the device. However, with the development of power devices, the power density of devices continues to increase, which requires that the on-resistance of the devices be increasingly smaller and the Miller capacitance, which affects switching losses, be as small as possible. Therefore, it is urgent to design a new field-effect transistor structure to simultaneously reduce the on-resistance and Miller capacitance of the device.

[0045] Based on this, an embodiment of the present application provides a field effect transistor, which increases the density (number) of conductive channels within a certain device repetition unit (cell pitch) size by setting a plurality of spaced-apart channel repetition units and setting a first channel along a first direction and a second channel along a second direction in each channel repetition unit, thereby reducing the overlapping area of ​​the gate structure and the JFET region, thereby simultaneously reducing the on-resistance and Miller capacitance of the device.

[0046] The field effect transistor referred to in this application may be a metal-oxide-semiconductor transistor (MOSFET), an insulated gate bipolar transistor (IGBT), etc., and this application does not limit this.

[0047] The specific structure and preparation method of the field effect transistor provided in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0048] The present application also provides a method for preparing a field effect transistor. Figures 4 to 13 This is a schematic diagram of the manufacturing process of the field effect transistor of the first embodiment of this application. Figures 4 to 13 The method for preparing a field effect transistor provided in the first embodiment of the present application includes the following steps:

[0049] S10, see Figure 4 , an N-drift layer 11 is formed on one side surface of the N+ substrate layer 10 .

[0050] The N+ substrate layer 10 is a heavily doped silicon substrate, a silicon carbide substrate or a gallium oxide substrate, etc. The doping concentration of the N+ substrate layer 10 can be 10 18 cm -3 ~6×10 20 cm -3 A lightly doped N-drift layer 11 can be epitaxially grown on the surface of the N+ substrate layer 10 by an epitaxial process. The thickness of the N-drift layer 11 can be 1 μm to 500 μm, and the doping concentration can be 10 12 cm -3 ~10 17 cm -3 .

[0051] S11, see Figure 5 and Figure 6 A plurality of P-well regions 12 are formed in the N-drift layer 11 on a side facing away from the N+ substrate layer 10, and a JFET region 13 is formed in the N-drift layer 11 between a portion of the two P-well regions 12. The P-well region 12 includes a first P-well region 121 disposed on opposite sides of the JFET region 13 along a first direction X, and a second P-well region 122 disposed on opposite sides of the JFET region 13 along a second direction Y. Both the first direction X and the second direction Y are perpendicular to the thickness direction of the N-drift layer 11.

[0052] It can be understood that the P-well region 12 is only provided in the top area of ​​the N-drift layer 11 , ie, at a certain distance from the N+ substrate layer 10 , so that the N-drift layer 11 can ensure the withstand voltage performance of the device.

[0053] It can be understood that the P-well regions 12 along different directions may partially overlap, so that the JFET region 13 between two P-well regions 12 along the first direction X and the JFET region 13 along the second direction Y may be the same.

[0054] The P-well region 12 and the JFET region 13 can be formed by performing ion implantation on one side of the N-drift layer 11, implanting Al ions or B ions. In some embodiments, the P-well region 12 is lightly doped, and the doping concentration can be 8×10 15 cm 3 ~10 18 cm 3 .

[0055] In the embodiment of the present application, the first direction X corresponds to the length direction of the N-drift layer 11 , and the second direction Y corresponds to the width direction of the N-drift layer 11 , that is, the first direction X and the second direction Y are perpendicular to each other.

[0056] It is understood that in other embodiments, the first direction X and the second direction Y may be any different directions and may not be perpendicular. In addition, in addition to the first direction X and the second direction Y, more P-well regions 12 in different directions may be provided, which can be selected according to actual needs.

[0057] S12, see Figure 7 and Figure 8 An N+ source region 14 is formed in the P-well region 12 , and a conductive channel 15 is formed in a portion of the P-well region 12 between the N+ source region 14 and the JFET region 13 .

[0058] A JFET region 13 and a plurality of conductive channels 15 located outside the JFET region 13 are defined as a channel repeating unit C, and the N-drift layer 11 includes two or more channel repeating units C arranged at intervals.

[0059] In the embodiment of the present application, a plurality of channel repeating units C are arranged at intervals along the first direction X, and a plurality of conductive channels 15 surround the JFET region 13 .

[0060] In the embodiment of the present application, the conductive channel 15 includes a plurality of first channels 151 arranged along a first direction X, and a plurality of second channels 152 arranged along a second direction Y. Two first channels 151 and two second channels 152 surround a JFET region 13 to form a channel repeating unit C.

[0061] It can be understood that the portion of the first P-well region 121 between the N+ source region 14 and the JFET region 13 forms the first channel 151 , and the portion of the second P-well region 122 between the N+ source region 14 and the JFET region 13 forms the second channel 152 .

[0062] In some embodiments, an N+ source region 14 with a high doping concentration can be formed by ion implantation in the P-well region 12. The doping concentration of the N+ source region 14 is lower than the doping concentration of the N+ substrate layer 10, and the doping concentration can be 10 17 cm 3 ~10 20 cm 3 .

[0063] See Figure 9 After forming the N+ source region 14 in the P-well region 12 , the method further includes: forming a P+ source region 16 on a side of the N+ source region 14 away from the JFET region 13 , wherein the P+ source region 16 is disposed in the N-drift layer 11 .

[0064] The high-concentration doped P+ source region 16 can be formed by implanting Al ions or B ions into the N-drift layer 11 between the two P-well regions 12. The doping concentration of the P+ source region 16 can be 10 16 cm 3 ~10 19 cm 3 By setting the P+ source region 16, it is beneficial for the P well region 12 to better connect to the source 18 to form an ohmic contact (see Figure 12 ).

[0065] S13, see Figure 10 A gate structure 17 is formed on a surface of the N-drift layer 11 on one side of which the P-well region 12 is provided. The orthographic projection of the gate structure 17 on the N-drift layer 11 covers the channel repeating unit C.

[0066] The orthographic projection of the gate structure 17 on the N-drift layer 11 covers a portion of the N+ source region 14 .

[0067] In some embodiments, the gate structure 17 includes a gate oxide layer 171, a gate 172, and an interlayer dielectric layer 173 stacked in sequence. A method for forming the gate structure 17 may include: forming the gate oxide layer 171 on a side surface of the N-drift layer 11 using a thermal growth process; forming the gate 172 on a surface of the gate oxide layer 171; and forming the interlayer dielectric layer 173 on a surface of the gate 172, wherein the interlayer dielectric layer 173 covers the gate 172 and the gate oxide layer 171.

[0068] The gate 172 may be formed by in-situ deposition of polysilicon (Poly-Si) or a metal film on the surface of the gate oxide layer 171. The gate oxide layer 171 may be made of silicon dioxide (SiO). The interlayer dielectric layer 173 may be made of silicon dioxide (SiO) and may be formed on the surface of the gate 172 by chemical vapor deposition (CVD).

[0069] In some embodiments, after forming the interlayer dielectric layer 173, the following steps may be performed: forming a source contact hole by photolithography and etching the interlayer dielectric layer 173 to expose the P+ source region 16 and at least a portion of the N+ source region 14 and the P well region 12, so as to facilitate subsequent contact with the source 18 (see Figure 12 ) forms an ohmic contact.

[0070] See Figure 11 、 Figure 12 and Figure 13 After step S13 , the process further includes: forming a source 18 on a surface of the N-drift layer 11 facing away from the N+ substrate layer 10 by a sputtering process, and forming a drain 19 on a surface of the N+ substrate layer 10 facing away from the N-drift layer 11 .

[0071] The source 18 covers the gate structure 17 , and forms an ohmic contact with the P+ source region 16 and at least a portion of the N+ source region 14 and the P-well region 12 . The drain 19 forms an ohmic contact with the N+ substrate layer 10 .

[0072] The first embodiment of the present application also provides a field effect transistor prepared by the above preparation method, Figure 11 This is a schematic diagram of the structure of the field effect transistor provided in the first embodiment of the present application. Figure 12 For the Figure 11 The cross-section of line AA1, Figure 13 For the Figure 11 Cross-section of line BB1. Figure 11 、 Figure 12 and Figure 13 The field effect transistor includes an N+ substrate layer 10, an N-drift layer 11, and a gate structure 17 stacked sequentially along the thickness direction. A plurality of P-well regions 12 are provided on the side of the N-drift layer 11 facing the gate structure 17, and a plurality of JFET regions 13 are formed therein. The JFET region 13 is formed between two P-well regions 12. An N+ source region 14 is provided in each P-well region 12. A conductive channel 15 is formed in the portion of the P-well region 12 located between the N+ source region 14 and the JFET region 13. Each JFET region 13 and the plurality of conductive channels 15 located outside the JFET region 13 are defined as a channel repeating unit C. That is, the field effect transistor includes two or more channel repeating units C disposed at intervals. The orthographic projection of the gate structure 17 on the N-drift layer 11 covers the channel repeating unit C and a portion of the N+ source region 14.

[0073] A first direction X, a second direction Y, and a third direction Z are defined within the field effect transistor, wherein the first direction X corresponds to the length direction of the field effect transistor, the second direction Y corresponds to the width direction, and the third direction Z corresponds to the thickness direction. That is, the first direction X, the second direction Y, and the third direction Z are perpendicular to each other.

[0074] In some embodiments, two or more channel repeating units C are spaced apart along the first direction X in the N-drift layer 11 .

[0075] It can be understood that in other embodiments, the channel repeating units C can be arranged in other directions or arranged in disorder.

[0076] Please continue to see Figure 11 、 Figure 12 and Figure 13 In some embodiments, the conductive channel 15 includes a first channel 151 disposed at two opposite sides of the JFET region 13 along a first direction X, and a second channel 152 disposed at two opposite sides of the JFET region 13 along a second direction Y.

[0077] It is understandable that in other embodiments, the conductive channel 15 may further include a third channel, a fourth channel, etc. arranged along other directions. This application does not limit this and it can be arranged according to actual needs.

[0078] Will Figure 11 and Figure 1 、 Figure 13 and Figure 2 By comparison, it can be seen that in the embodiment of the present application, compared with the prior art, within a certain device repeating unit size, a second channel 152 is added. Figure 1 The original JFET region 13 a is partially replaced by the second channel 152 , that is, the number of conductive channels 15 is increased, and the overlapping area of ​​the JFET region 13 and the gate structure 17 is reduced.

[0079] In some embodiments, the shape of the channel repeating unit C can be square, circular, polygonal, diamond or any other irregular shape.

[0080] In some embodiments, the plurality of conductive channels 15 in each channel repeating unit C are disposed around the outside of the JFET region 13 .

[0081] It is understood that the shape of the channel repeating unit C can be controlled by the number and surrounding arrangement of the multiple conductive channels 15. In this embodiment, the channel repeating unit C is square, and each channel repeating unit C includes two first channels 151 and two second channels 152. The two first channels 151 and the two second channels 152 are arranged around the outside of the JFET region 13.

[0082] Please continue to see Figure 11 、 Figure 12 and Figure 13 The field effect transistor further includes a source 18 and a drain 19. The source 18 is disposed on the side of the N-drift layer 11 where the gate structure 17 is disposed, and the drain 19 is disposed on the side of the N+ substrate layer 10 facing away from the N-drift layer 11. A P+ source region 16 is also disposed on the side of the N+ source region facing away from the JFET region 13. The P+ source region 16 is disposed in a portion of the N-drift layer 11 between the two P-well regions 12. The source 18 covers the gate structure 17 and contacts the P+ source region 16 and at least a portion of the N+ source region 14 and the P-well region 12.

[0083] Please continue to see Figure 12 The gate structure 17 includes a gate oxide layer 171, a gate 172 and an interlayer dielectric layer 173. The gate oxide layer 171 is arranged between the gate 172 and the N-drift layer 11. The interlayer dielectric layer 173 covers the gate 172 and the gate oxide layer 171, and the interlayer dielectric layer 173 is in contact with the source 18.

[0084] See Figure 14 、 Figure 15 and Figure 16 The second embodiment of the present application also provides a field effect transistor, which has a structure roughly the same as that of the field effect transistor provided in the first embodiment of the present application. The present application will not elaborate on the same parts here. The difference between the two is that: in the field effect transistor, multiple channel repetition units C are arranged in a matrix in the N-drift layer 11.

[0085] It can be understood that the “matrix arrangement” referred to in this application refers to an arrangement in an m×n matrix, where m≥2 and n≥2.

[0086] In the embodiment of the present application, a plurality of channel repeating units C are arranged in a matrix with columns in the first direction X and rows in the second direction Y, where m>3 and n=2.

[0087] Will Figure 14 and Figure 11 By comparison, it can be seen that in the field effect transistor of the second embodiment, the number of channel repeating units C is greater. In addition to the conductive channels 25 arranged along the edge of the gate structure 27, a plurality of conductive channels 25 are also arranged in the corresponding inner region of the gate structure 27.

[0088] In addition, an embodiment of the present application further provides an integrated circuit, comprising the field effect transistor of the first embodiment or the second embodiment, or a field effect transistor prepared by the above-mentioned preparation method.

[0089] The embodiments described above are part of the embodiments of the present application, rather than all of the embodiments. The detailed description of the embodiments of the present application is not intended to limit the scope of the present application for protection, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

Claims

1. A field effect transistor, characterized in that: The invention comprises an N+ substrate layer, an N-drift layer and a gate structure stacked in sequence along the thickness direction, wherein two or more spaced-apart channel repeating units are provided on a side of the N-drift layer facing the gate structure, and the orthographic projection of the gate structure on the N-drift layer covers the channel repeating units; Wherein, each of the channel repetition units includes a JFET region and a plurality of conductive channels arranged outside the JFET region; the conductive channels include a first channel arranged on opposite sides of the JFET region along a first direction, and a second channel arranged on opposite sides of the JFET region along a second direction, and the first direction and the second direction are both perpendicular to the thickness direction.

2. The field effect transistor according to claim 1, wherein Two or more channel repeating units are spaced apart and arranged in the N-drift layer along the first direction.

3. The field effect transistor according to claim 1, wherein A plurality of the channel repeating units are arranged in a matrix in the N-drift layer.

4. The field effect transistor according to claim 1, wherein A plurality of conductive channels are arranged around the outside of the JFET region.

5. The field effect transistor according to claim 1 or 4, characterized in that: The shape of the channel repeating unit is square, circular, polygonal, diamond or irregular.

6. The field effect transistor according to claim 1, wherein A plurality of P-well regions are provided in the N-drift layer on a side facing the gate structure, an N+ source region is provided in each of the P-well regions, and an orthographic projection of the gate structure on the N-drift layer covers a portion of the N+ source region, a portion of the P-well region, and a portion of the N-drift layer located between two of the P-well regions; Part of the N-drift layer covered by the orthographic projection of the gate structure on the N-drift layer forms the JFET region, and part of the P-well region located between the JFET region and the N+ source region forms the conductive channel.

7. The field effect transistor according to claim 6, characterized in that It also includes a source and a drain, the source is arranged on the side of the N-drift layer away from the N+ substrate layer, and the drain is arranged on the side of the N+ substrate layer away from the N-drift layer; wherein the source covers the gate structure and the source contacts part of the N+ source region.

8. A method for preparing a field effect transistor according to any one of claims 1 to 7, characterized in that: The following steps are involved: forming an N-drift layer on one side surface of the N+ substrate layer; A plurality of P-well regions are formed in the N-drift layer on a side facing away from the N+ substrate layer, and a JFET region is formed in the N-drift layer between two of the P-well regions; the P-well regions include a first P-well region disposed on opposite sides of the JFET region along a first direction, and a second P-well region disposed on opposite sides of the JFET region along a second direction; wherein the first direction and the second direction are both perpendicular to the thickness direction of the N-drift layer; An N+ source region is formed in the P-well region, and a portion of the P-well region located between the N+ source region and the JFET region forms a conductive channel, and one of the JFET regions and a plurality of conductive channels disposed outside the JFET region are defined as a channel repeating unit; wherein a portion of the first P-well region located between the N+ source region and the JFET region forms a first channel, and a portion of the second P-well region located between the N+ source region and the JFET region forms a second channel; A gate structure is formed on a surface of the N-drift layer on one side of which the P-well region is provided, wherein an orthographic projection of the gate structure on the N-drift layer covers the channel repeating unit.

9. The preparation method according to claim 8, characterized in that After forming the N+ source region in the P-well region, the method further includes: A source is formed on a surface of the N-drift layer facing away from the N+ substrate layer, and a drain is formed on a surface of the N+ substrate layer facing away from the N-drift layer; wherein the source covers the gate structure and contacts a portion of the N+ source region.

10. An integrated circuit, characterized in that: A field effect transistor comprising any one of claims 1 to 7, or a field effect transistor prepared by the preparation method according to claim 8 or 9.

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