Semiconductor device and manufacturing method thereof
By designing source/drain parts and cross-gate stack structures with different conductivity types in the Nanosheet device, the punch-through effect caused by insufficient source/drain isolation is solved, and multi-threshold voltage control is achieved, which is suitable for low-power applications.
Patent Information
- Application Number
- CN202510665942.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-22
- Publication Date
- 2025-09-12
AI Technical Summary
Insufficient source/drain isolation in Nanosheet devices leads to punch-through effects, and it is difficult to achieve multi-threshold voltage control in the same device.
By designing the first source/drain and the second source/drain in the semiconductor device to be doped with different conductivity types respectively to form a pn junction, and forming a cross-gate stack structure on the substrate, the space charge region is used to reduce the punch-through effect, and the threshold voltages of the two groups of channel parts are independently regulated by the gate operation voltage.
It effectively reduces the punch-through current and realizes the regulation of multiple threshold voltages in a single device, making it suitable for low-power application scenarios.
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Figure CN120640732A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device with a regulated bottom channel threshold and a manufacturing method thereof. Background Art
[0002] With the continuous development of semiconductor technology, nanosheet-based device structures have received widespread attention in the field of high-performance integrated circuits due to their unique performance and potential.
[0003] In the process of realizing the concept of the present disclosure, the inventors discovered that the Nanosheet device in the related art has technical problems such as a punch-through effect caused by insufficient source / drain isolation and difficulty in achieving multiple threshold voltages for a single device. Summary of the Invention
[0004] In view of this, the present disclosure provides a semiconductor device and a method for manufacturing the same.
[0005] One aspect of the present disclosure provides a semiconductor device, comprising:
[0006] A substrate; a first channel portion on the substrate; a first source / drain portion, respectively located on opposite sides of the first channel portion in a first direction; a second channel portion on the first channel portion; a second source / drain portion, respectively located on opposite sides of the second channel portion in the first direction; a gate stack, extending in a second direction intersecting the first direction to intersect with the first channel portion and the second channel portion; wherein the first source / drain portion and the second source / drain portion are at least partially in contact with each other and are respectively doped to have different conductivity types.
[0007] According to the embodiment of the present disclosure, the doping concentration of the first source / drain portion and the second source / drain portion is 1×10 16 cm -3 to 1×10 21 cm -3 between.
[0008] According to an embodiment of the present disclosure, the first channel portion and the second channel portion each include an intrinsic semiconductor or a lightly doped semiconductor.
[0009] According to an embodiment of the present disclosure, the first channel portion includes a single semiconductor layer, and the second channel portion includes one or more semiconductor layers.
[0010] According to an embodiment of the present disclosure, the substrate includes an SOI substrate, including a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer; the first source / drain portion includes a doped region in the SOI layer, the first channel portion includes a portion between the first source / drain portions in the SOI layer, the second channel portion includes one or more semiconductor layers above the SOI layer, and the second source / drain portion includes a semiconductor layer epitaxially grown on the first source / drain portion on opposite sides of the second channel portion.
[0011] Another aspect of the present disclosure provides a method for manufacturing a semiconductor device, comprising:
[0012] A first channel portion and first source / drain portions are formed on a substrate, respectively, on opposite sides of the first channel portion in a first direction; a second channel portion is formed on the first channel portion, and second source / drain portions are formed on the first source / drain portion on opposite sides of the second channel portion in the first direction; a gate stack is formed, and the gate stack extends in a second direction intersecting the first direction to intersect with the first channel portion and the second channel portion; wherein the first source / drain portion and the second source / drain portion are at least partially in contact with each other and are respectively doped to have different conductivity types.
[0013] According to an embodiment of the present disclosure, a first source / drain portion is formed by forming a doped region in a substrate, and a first channel portion is defined between the first source / drain portion; a channel portion and a second source / drain portion are formed on the substrate by a GAA FET process.
[0014] According to an embodiment of the present disclosure, the substrate includes an SOI substrate, including a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer; the first source / drain portion is formed in the SOI layer, and the first channel portion includes a portion between the first source / drain portions in the SOI layer.
[0015] According to the embodiment of the present disclosure, the doping concentration of the first source / drain portion and the second source / drain portion is 1×10 16 cm -3 to 1×10 21 cm -3 between.
[0016] According to an embodiment of the present disclosure, the first channel portion and the multilayer semiconductor each include an intrinsic semiconductor or a lightly doped semiconductor.
[0017] According to the embodiments of the present disclosure, by doping the first source / drain portion and the second source / drain portion, which are at least partially in contact with each other, with different conductivity types to form a pn junction, a space charge region is formed between them. This effectively reduces the punch-through effect (particularly source-drain punch-through through the first channel portion) by affecting the source / drain barrier. Furthermore, by implementing two sets of source / drain portions and channel portions in a single device, the conductive mode and gate voltage have opposite effects on the two sets of channel portions. Therefore, the two sets of channel portions can be activated separately by two threshold voltages, achieving multiple threshold voltages in a single device, making it more suitable for low-power applications. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:
[0019] Figure 1 A cross-sectional view of a semiconductor device in a first direction according to an embodiment of the present disclosure is schematically shown.
[0020] Figure 2 The flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure is schematically shown.
[0021] Figures 3 to 10 Schematically shows Figure 2 A cross-sectional view of a structure obtained after executing part of the process in the method shown in the first direction or the top direction. DETAILED DESCRIPTION
[0022] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.
[0023] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.
[0024] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.
[0025] Various structural schematic diagrams according to embodiments of the present disclosure are shown in the accompanying drawings. These figures are not drawn to scale, and for the purpose of clarity, certain details are magnified and certain details may be omitted. The shapes of the various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may design regions / layers with different shapes, sizes, and relative positions according to actual needs. In the context of the present disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intermediate layer / element between them. In addition, if a layer / element is "on" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "under" the other layer / element.
[0026] In the process of implementing the inventive concept of the present disclosure, the inventors discovered that:
[0027] As integrated circuit manufacturing processes enter the nanoscale (such as below 7nm), traditional planar transistors (Planar FET) and fin field-effect transistors (FinFET) are gradually facing physical limits. Nanosheet structures are widely used because they can be applied to scales of 3nm and below.
[0028] However, the isolation between the source / drain (S / D) and the channel in conventional nanosheet devices is insufficient, leading to source-drain punch-through. Furthermore, the threshold voltage can only be adjusted by adjusting the gate material or channel doping, making it difficult to achieve multiple threshold voltages in the same device.
[0029] In view of this, an embodiment of the present disclosure provides a semiconductor device, comprising: a substrate; a first channel portion on the substrate; a first source / drain portion, respectively located on opposite sides of the first channel portion in a first direction; a second channel portion on the first channel portion; a second source / drain portion, respectively located on opposite sides of the second channel portion in the first direction; a gate stack, extending in a second direction intersecting with the first direction to intersect with the first channel portion and the second channel portion; wherein the first source / drain portion and the second source / drain portion are at least partially in contact with each other and are respectively doped to different conductivity types.
[0030] Figure 1 A cross-sectional view of a semiconductor device in a first direction according to a disclosed embodiment is schematically shown.
[0031] like Figure 1 As shown, the semiconductor device of this embodiment may include a substrate 110, a first channel portion 120 on the substrate, and two channels located in the first channel portion 120 in a first direction (eg, Figure 1The first source / drain portions 130 on opposite sides of the first channel portion 120 (a horizontal direction in the middle of the paper), the second channel portion 160 on the first channel portion 120, the second source / drain portions 150 respectively located on opposite sides of the second channel portion 160 in the first direction, and the second source / drain portions 150 in a second direction intersecting the first direction (for example, Figure 1 The gate stack 140 extends in a direction perpendicular to the paper surface) to intersect the first channel portion 120 and the second channel portion 160.
[0032] Here, a semiconductor-on-insulator (SOI) substrate is used as an example. Substrate 110 includes a base substrate 111, a buried oxide layer 112 on base substrate 111, and an SOI layer 113 on buried oxide layer 112. However, the present disclosure is not limited thereto. For example, the technology disclosed herein can be applied to other substrates, such as bulk semiconductor substrates.
[0033] The first source / drain portion 130 may comprise a doped region in the SOI layer 113, and the first channel portion 120 may comprise a portion of the SOI layer 113 between the first source / drain portions 130. The second channel portion 140 may comprise one or more (three in this example) semiconductor layers above the SOI layer 113, and the second source / drain portion 150 may comprise a semiconductor layer epitaxially grown on the first source / drain portion 130 on opposite sides of the second channel portion 140. The doping type of the first channel portion 120 and the second channel portion 140 may be adjusted according to actual needs. For example, the first channel portion 120 and the second channel portion 140 may each comprise an intrinsic semiconductor or a lightly doped semiconductor.
[0034] According to an embodiment of the present disclosure, the first channel portion 120 includes a single semiconductor layer, and the second channel portion 160 includes one or more semiconductor layers. Figure 1 Four stacked semiconductor layers are taken as an example, but the present disclosure is not limited thereto.
[0035] According to an embodiment of the present disclosure, the first source / drain portion 130 and the second source / drain portion 150 are at least partially in contact with each other and are doped to different conductivity types. For example, the first source / drain portion 130 is heavily doped with n-type and the second source / drain portion 150 is heavily doped with p-type, or the first source / drain portion 130 is heavily doped with p-type and the second source / drain portion 150 is heavily doped with n-type. As a result, the two sets of sources / drains actually constitute a pn junction. The boundary of the pn junction forms a space charge region (i.e., a depletion region) due to carrier diffusion and recombination. The built-in electric field in this region is directed from the n-region to the p-region, which can hinder the free flow of carriers. The built-in electric field in the space charge region forms a potential barrier, preventing carriers from penetrating the channel, thereby reducing the punch-through current and leakage current.
[0036] The doping concentration of the first source / drain portion 130 and the second source / drain portion 150 can be 1×10 16 cm -3to 1×10 21 cm -3 The barrier height can be adjusted by changing the doping concentration, thereby adjusting the effect of reducing the punch-through effect.
[0037] Taking the first source / drain portion 130 as heavily doped with p-type and the second source / drain portion 150 as heavily doped with n-type as an example, the gate stack covers both the first channel portion 120 and the second channel portion 160. The pn junction formed by the two sets of source / drains will increase the threshold voltage V of the first channel portion 120. th1 Therefore, regardless of the positive or negative voltage, the threshold voltage V th1 The value may be higher than the threshold voltage V of the second channel portion 140. th2 In low power mode, the gate operating voltage is adjusted to V th2 , only the second channel portion 140 is turned on, and in high performance mode, the gate operating voltage is adjusted to V th1 , the first channel portion 120 and the second channel portion 140 are turned on at the same time. Therefore, the two groups of channels can be independently controlled by the gate operation voltage.
[0038] According to the embodiments of the present disclosure, by doping the first source / drain portion and the second source / drain portion, which are at least partially in contact with each other, with different conductivity types to form a pn junction, a space charge region is formed between them. This effectively reduces the punch-through effect (particularly source-drain punch-through through the first channel portion) by affecting the source / drain barrier. Furthermore, by implementing two sets of source / drain portions and channel portions in a single device, the conductive mode and gate voltage have opposite effects on the two sets of channel portions. Therefore, the two sets of channel portions can be activated separately by two threshold voltages, achieving multiple threshold voltages in a single device, making it more suitable for low-power applications.
[0039] Figure 2 The flowchart of the method for manufacturing a semiconductor device according to an embodiment of the present disclosure is schematically shown.
[0040] Figures 3 to 10 Schematically shows Figure 2 A cross-sectional view of a structure obtained after executing part of the process in the method shown in the first direction or the top direction.
[0041] like Figure 2 As shown, the method 200 includes operations S210 to S230.
[0042] In operation S210 , a first channel portion and first source / drain portions respectively located at opposite sides of the first channel portion in a first direction are formed on a substrate.
[0043] Reference Figure 3 and Figure 4The substrate 110 includes a base substrate 111, a buried oxide layer 112 on the base substrate 111, and an SOI layer 113 on the buried oxide layer 112. For example, the base substrate 111 may include silicon (Si), the buried oxide layer 112 may include silicon oxide, and the SOI layer 113 may include the same material as the base substrate 111, such as Si, or a different material, such as silicon germanium (GeSi). The following description uses the example of SOI layer 113 including Si as an example.
[0044] In the SOI layer 113, a doped region (e.g., a heavily doped ultra shallow junction) can be formed by, for example, ion implantation, thereby forming the first source / drain portion 130. During the ion implantation, an implantation mask (e.g., a patterned photoresist) can be used so that the first source / drain portion 130 can be formed in the SOI layer 113 in the first direction ( Figure 4 The SOI layer 113 comprises doped regions that oppose each other in the horizontal direction (in the horizontal direction within the paper). The portion of the SOI layer 113 between the first source / drain portions 130 can define the first channel portion 120. The first source / drain portions 130 are located on opposite sides of the first channel portion 120 in the first direction. Alternatively, as described above, the first channel portion 120 can be lightly doped. In this case, the SOI layer 113 can be lightly doped first to target the first channel portion, followed by doping of the first source / drain portions 130.
[0045] In operation S220 , a second channel portion is formed on the first channel portion, and second source / drain portions are formed on the first source / drain portion at opposite sides of the second channel portion in the first direction.
[0046] According to an embodiment of the present disclosure, the second channel portion and the second source / drain portion may be formed by a GAA FET (Gate All Around Field Effect Transistor) process.
[0047] Reference Figure 5 A film layer 310 is formed on the SOI layer 113 (in which the first channel portion 120 and the first source / drain portion 130 are formed) by, for example, epitaxial growth. The film layer 310 includes a plurality of sacrificial layers 311 and a plurality of second channel semiconductors 312 that are alternately stacked. The sacrificial layer 311 may include a material having an etching selectivity relative to the second channel semiconductor 312 and the SOI layer 113 so that it can be selectively removed in a subsequent process. For example, in the case where the second channel semiconductor 312 and the SOI layer 113 include Si, the sacrificial layer 311 may include Si. x Ge 1-x , x is between 0 and 1. The thickness and number of layers of the sacrificial layer 311 and the second channel semiconductor 312 can be adjusted according to actual needs and are not limited here.
[0048] The active area of the device can be defined. For example, Figure 6A A cross-sectional view along a first direction and Figure 6B The top view of Figure 5 In the structure shown, the sacrificial layer 311, the second channel semiconductor 312, and the SOI layer 113 in the non-device active area are etched, and the remaining portions of these layers can define the device active area. The etching can stop at the buried oxide layer 102. Different device active areas can be isolated from each other.
[0049] For example, an etching mask such as a photoresist (not shown) may be formed, and the photoresist may be patterned by photolithography into a pattern corresponding to the device active region to be formed. Here, the device active region may have a pattern in which the middle portion is relatively narrow (which may subsequently define a channel portion) and the ends on opposite sides of the middle portion in the first direction are relatively wide (which may subsequently define a source / drain portion), as shown in FIG. Figure 6B During the photolithography process, the mask alignment can be adjusted so that the narrower middle portion can be aligned with the first channel portion 120 defined in the SOI layer 113 , and the wider end portions can be aligned with the first source / drain portion 130 formed in the SOI layer 113 .
[0050] Reference Figure 7 , the device active region can be doped, for example, by ion implantation, to form the second source / drain portion 150. During the ion implantation, an implantation mask (e.g., a patterned photoresist) can be used so that the second source / drain portion 150 can be formed at the wider end portions as described above in the sacrificial layer 311 and the second channel semiconductor 312. The portion (the narrower middle portion) between the second source / drain portion 150 in the second channel semiconductor 312 can define the second channel portion 160. The doping depth can be controlled so that the second source / drain portion 150 can at least partially contact the first source / drain portion 130 at the bottom. In addition, as described above, the second channel portion 160 can be lightly doped. This light doping can be achieved by in-situ doping during the growth of the second channel semiconductor 312.
[0051] The second source / drain portion 150 and the first source / drain portion 130 are doped to different conductivity types. For example, the first source / drain portion 130 may be heavily doped with n-type and the second source / drain portion 150 may be heavily doped with p-type, or the first source / drain portion 130 may be heavily doped with p-type and the second source / drain portion 150 may be heavily doped with n-type. Consequently, a space charge region 320 may be formed between the second source / drain portion 150 and the first source / drain portion 130.
[0052] For example, the doping concentration of the first source / drain portion 130 and the second source / drain portion 150 may be 1×10 16 cm -3 to 1×10 21 cm -3The first channel portion 130 and the multi-layer second channel semiconductor 312 each include an intrinsic semiconductor or a lightly doped semiconductor.
[0053] Reference Figure 8 , the sacrificial layer 311 may be removed by selective etching to release the second channel portion 160 .
[0054] In operation S230 , a gate stack is formed, the gate stack extending in a second direction intersecting the first direction to intersect the first channel portion and the second channel portion.
[0055] Reference Figure 9 , an interface layer, a high dielectric constant (k) dielectric layer, and a metal gate electrode layer may be sequentially formed to obtain a final gate stack 140. The metal gate electrode layer may include a work function layer and a gate conductor layer.
[0056] For example, the interface layer may include silicon oxide (SiO 2 ), and the dielectric layer may include hafnium oxide (HfO 2 ) or aluminum oxide (Al 2 O 3 ).
[0057] Reference Figure 10 , a source / drain contact portion 170 may be formed on the second source / drain portion 150 .
[0058] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.
[0059] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.
Claims
1. A semiconductor device comprising: substrate; a first channel portion on the substrate; first source / drain portions, respectively located on two opposite sides of the first channel portion in a first direction; a second channel portion on the first channel portion; second source / drain portions, respectively located on two opposite sides of the second channel portion in the first direction; a gate stack extending in a second direction intersecting the first direction to intersect the first channel portion and the second channel portion; The first source / drain portion and the second source / drain portion are at least partially in contact with each other and are doped to different conductivity types.
2. The semiconductor device according to claim 1, wherein The doping concentration of the first source / drain portion and the second source / drain portion is 1×10 16 cm -3 to 1×10 21 cm -3 between.
3. The semiconductor device according to claim 1, wherein The first channel portion and the second channel portion each include an intrinsic semiconductor or a lightly doped semiconductor.
4. The semiconductor device according to claim 1, wherein The first channel portion includes a single semiconductor layer, and the second channel portion includes one or more semiconductor layers. The semiconductor device according to claim 1 , wherein The substrate comprises an SOI substrate, comprising a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer; The first source / drain portion includes a doped region in the SOI layer, the first channel portion includes a portion of the SOI layer between the first source / drain portions, the second channel portion includes one or more semiconductor layers above the SOI layer, and the second source / drain portion includes a semiconductor layer epitaxially grown on the first source / drain portion on opposite sides of the second channel portion.
6. A method for manufacturing a semiconductor device, comprising: forming a first channel portion and first source / drain portions respectively located on two opposite sides of the first channel portion in a first direction on a substrate; forming a second channel portion on the first channel portion, and forming second source / drain portions on the first source / drain portion at opposite sides of the second channel portion in the first direction; forming a gate stack extending in a second direction intersecting the first direction to intersect the first channel portion and the second channel portion; The first source / drain portion and the second source / drain portion are at least partially in contact with each other and are doped to different conductivity types.
7. The method according to claim 6, wherein: forming the first source / drain portion by forming a doped region in the substrate, wherein the first channel portion is defined between the first source / drain portion; The second channel portion and the second source / drain portion are formed on the substrate by a GAA FET process.
8. The method according to claim 7, wherein: The substrate comprises an SOI substrate, comprising a base substrate, a buried oxide layer on the base substrate, and an SOI layer on the buried oxide layer; The first source / drain portions are formed in the SOI layer, and the first channel portion includes a portion of the SOI layer between the first source / drain portions.
9. The method according to claim 6, wherein: The doping concentration of the first source / drain portion and the second source / drain portion is 1×10 16 cm -3 to 1×10 21 cm -3 between.
10. The method according to claim 6, wherein: The first channel portion and the multilayer semiconductor each include an intrinsic semiconductor or a lightly doped semiconductor.