Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; the semiconductor body further comprises a well region and a first region; the first region is of a first conductive type and is located on the first surface; the well region is of a second conductive type and is located on the first surface; the first region extends into the well region from the first surface; the stress adjusting layer is located on the first surface and extends into the first area from the first surface; the first side surface of the stress adjusting layer is in contact with the well region; the stress adjusting layer is used for adjusting the stress of the well region; a gate electrode; and a source electrode. According to the invention, the on-resistance of the semiconductor device can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) based on third-generation wide-bandgap semiconductors such as silicon carbide or gallium nitride has the characteristics of large critical breakdown electric field strength, high thermal conductivity, large bandgap width and high electron saturation drift velocity, making third-generation wide-bandgap semiconductor materials such as silicon carbide or gallium nitride a research hotspot for power semiconductor devices. In high-power applications such as high-speed railways, hybrid vehicles, and intelligent high-voltage direct current transmission, silicon carbide devices are given high expectations.

[0003] An important parameter of a semiconductor device is the on-resistance. The channel accounts for a large proportion of the on-resistance of a semiconductor device, but the channel mobility of current semiconductor devices is low, resulting in a high on-resistance. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the on-resistance of the semiconductor device.

[0005] According to one aspect of the present invention, there is provided a semiconductor device comprising:

[0006] A semiconductor body comprising a first surface and a second surface opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface; the well region being of a second conductivity type and located on the first surface; and the first region extending from the first surface into the well region.

[0007] a stress adjustment layer, located on the first surface and extending from the first surface into the first region; a first side surface of the stress adjustment layer contacts the well region; the stress adjustment layer is used to adjust the stress of the well region;

[0008] a gate, located on the first surface;

[0009] The source is located on the first surface.

[0010] Optionally, if the first conductivity type is N-type, the lattice spacing of the stress adjustment layer is smaller than the lattice spacing of the semiconductor body; if the first conductivity type is P-type, the lattice spacing of the stress adjustment layer is larger than the lattice spacing of the semiconductor body.

[0011] Optionally, the first surface is further provided with a groove, the groove extending from the first surface into the first region, and a side surface of the groove contacts the well region; the stress adjustment layer is located in the groove.

[0012] Optionally, the semiconductor device further comprises a first insulating layer;

[0013] The first insulating layer is located on the first surface;

[0014] The gate is located on a side of the first insulating layer away from the second surface;

[0015] Along a thickness direction of the semiconductor device, a projection of the stress adjustment layer on the second surface is located within a projection of the first insulating layer on the second surface.

[0016] Optionally, the second side surface of the stress adjustment layer is flush with a side surface of the first insulating layer; and the second side surface of the stress adjustment layer is opposite to the first side surface of the stress adjustment layer.

[0017] Optionally, if the first conductivity type is N-type, the material of the stress adjustment layer includes diamond;

[0018] If the first conductive type is P-type, the material of the stress adjustment layer includes at least one of silicon and germanium-silicon alloy.

[0019] Optionally, the thickness of the stress adjustment layer is 30% to 50% of the maximum thickness of the first region.

[0020] Optionally, the semiconductor body further includes a second region, which is set to a second conductivity type and is located on the first surface;

[0021] The second region is located on a side of the first region away from the well region, and the ion concentration of the second region is greater than the ion concentration of the well region.

[0022] Optionally, the semiconductor device further includes:

[0023] an interlayer dielectric layer, located between the gate and the source;

[0024] a drain electrode, located on a side of the second surface away from the first surface;

[0025] The packaging structure is located on a side of the source electrode away from the semiconductor body.

[0026] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0027] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface; the well region being of a second conductivity type and located on the first surface; and the first region extending from the first surface into the well region.

[0028] forming a stress adjustment layer, the stress adjustment layer being located on the first surface and extending from the first surface into the first region; wherein a first side surface of the stress adjustment layer is in contact with the well region; and the stress adjustment layer is configured to adjust stress in the well region;

[0029] forming a gate on the first surface of the semiconductor body;

[0030] A source is formed on a side of the gate away from the first surface.

[0031] Optionally, providing the semiconductor body includes:

[0032] forming a groove on the first surface of the semiconductor body, wherein the groove extends from the first surface into the first region; and a side surface of the groove contacts the well region;

[0033] The forming of the stress adjustment layer comprises:

[0034] The stress adjustment layer is formed in the groove.

[0035] Optionally, providing the semiconductor body includes:

[0036] Providing a substrate and an epitaxial layer, wherein a surface of the epitaxial layer away from the substrate is the first surface, and a surface of the substrate away from the epitaxial layer is the second surface;

[0037] forming a well region on the first surface of the semiconductor body;

[0038] forming the first region on the first surface of the semiconductor body;

[0039] The groove is formed on the first surface of the semiconductor body.

[0040] Optionally, if the first conductivity type is N-type, the lattice spacing of the stress adjustment layer is smaller than the lattice spacing of the semiconductor body; if the first conductivity type is P-type, the lattice spacing of the stress adjustment layer is larger than the lattice spacing of the semiconductor body.

[0041] According to another aspect of the present invention, a power module is provided, comprising a substrate and at least one semiconductor device as described above, wherein the substrate is used to support the semiconductor device.

[0042] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0043] The power conversion circuit includes a circuit board and at least one semiconductor device as described above, wherein the semiconductor device is electrically connected to the circuit board.

[0044] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described above, wherein the power conversion circuit is configured to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input the converted power into the load.

[0045] The technical solution of an embodiment of the present invention employs a semiconductor device comprising a semiconductor body including a first surface and a second surface disposed opposite each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface; the well region being of a second conductivity type and located on the first surface; the first region extending from the first surface into the well region; a stress adjustment layer located on the first surface and extending from the first surface into the first region; a first side surface of the stress adjustment layer contacting the well region; the stress adjustment layer being configured to adjust stress in the well region; a gate located on the first surface; and a source located on the first surface. The stress adjustment layer is configured to adjust stress in the well region, generating tensile or compressive stress in the well region, thereby reducing the effective mass and scattering probability of electron conduction in the well region, increasing the mobility of the well region, that is, increasing the mobility of the channel, and reducing on-resistance.

[0046] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0048] Figure 1 A schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0049] Figure 2 A schematic diagram of the principle of adjusting the stress of a well region using a stress adjustment layer provided by an embodiment of the present invention;

[0050] Figure 3 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0051] Figure 4 A schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0052] Figure 5 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0053] Figures 6-10 A schematic diagram of a product structure formed corresponding to the main steps of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0054] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0055] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0056] Figure 1 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention, referring to Figure 1 , semiconductor devices include:

[0057] The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other. The semiconductor body also includes a well region 103 and a first region 104. The first region 104 is configured as a first conductivity type and is located on the first surface 101. The well region 103 is configured as a second conductivity type and is located on the first surface 101. The first region 104 extends from the first surface 101 into the well region 103.

[0058] The stress adjustment layer 200 is located on the first surface 101 and extends from the first surface 101 into the first region 104 . The first side surface 201 of the stress adjustment layer 200 contacts the well region 103 . The stress adjustment layer 200 is used to adjust the stress of the well region 103 .

[0059] The gate 302 is located on the first surface 101;

[0060] The source electrode 400 is located on the first surface 101 and contacts the first region 104 .

[0061] Specifically, the semiconductor device may be a MOSFET device. In this embodiment, the semiconductor device is, for example, a planar gate MOSFET device. In some embodiments, the semiconductor device is an N-type device, in which case the first conductivity type is N-type (i.e., N-type doping), and the corresponding second conductivity type is P-type. In other embodiments, the semiconductor device is a P-type device, in which case the first conductivity type is P-type.

[0062] The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20 located on one side of the substrate 10. The surface of the substrate 10 away from the epitaxial layer 20 is the second surface 102 of the semiconductor body 100, and the surface of the epitaxial layer 20 away from the substrate 10 is the first surface 100 of the semiconductor body 100. The substrate 10 is set to the first conductivity type, and the epitaxial layer 20 is set to the first conductivity type. The ion concentration of the substrate 10 is greater than the ion concentration of the epitaxial layer 20. That is, if the first conductivity type is N-type, the substrate 10 is an N+ substrate and the epitaxial layer 20 is an N- epitaxial layer. In this embodiment, the source 400 is located on the side of the gate 302 away from the first surface 101, and the source 400 can form an ohmic contact with the first region 104.

[0063] When the second conductivity type is P-type, the well region 103 is a P-type well region, namely, a PW region. When the second conductivity type is N-type, the well region 103 is an N-type well region. The well region 103 is used to form a conductive channel.

[0064] The first region 104 is of the first conductivity type, and the ion concentration of the first region 104 is greater than the ion concentration of the epitaxial layer 20. In other words, if the first conductivity type is N-type, the first region 104 is an N+ region, and if the first conductivity type is P-type, the first region 104 is a P+ region.

[0065] In this embodiment, a stress adjustment layer 200 is further provided in the first region 104. The stress adjustment layer 200 is used to adjust the stress of the well region 103 so that the well region 103 generates tensile stress or compressive stress, thereby reducing the effective mass and scattering probability of electron conductivity in the well region 103, increasing the mobility of the well region 103, that is, increasing the mobility of the channel, and reducing the on-resistance.

[0066] The technical solution of this embodiment adopts a semiconductor device including a semiconductor body including a first surface and a second surface disposed opposite each other; the semiconductor body also including a well region and a first region; the first region being of a first conductivity type and located on the first surface; the well region being of a second conductivity type and located on the first surface; the first region extending from the first surface into the well region; a stress adjustment layer located on the first surface and extending from the first surface into the first region; a first side surface of the stress adjustment layer contacting the well region; the stress adjustment layer being configured to adjust stress in the well region; a gate located on the first surface; and a source located on the first surface. The stress adjustment layer is configured to adjust stress in the well region, generating tensile or compressive stress in the well region, thereby reducing the effective mass and scattering probability of electron conduction in the well region, increasing the mobility of the well region, that is, increasing the mobility of the channel, and reducing on-resistance.

[0067] Optionally, if the first conductivity type is N-type, the lattice spacing of the stress adjustment layer 200 is smaller than the lattice spacing of the semiconductor body 100; if the first conductivity type is P-type, the lattice spacing of the stress adjustment layer 200 is larger than the lattice spacing of the semiconductor body 100;

[0068] Specifically, Figure 2 A schematic diagram of the principle of adjusting the stress of the well region by a stress adjustment layer provided by an embodiment of the present invention. Figure 2 In the example, the first conductivity type is N type, and Figure 2 Corresponding Figure 1 An enlarged schematic diagram of the middle area Z1. Figure 1 and Figure 2 As shown, when the first conductivity type is N-type, the well region 103 is P-type, and a stress adjustment layer 200 is deposited on the surface (the sidewall in this embodiment) of the well region 103. The well region 103 is subjected to a strain effect, and a tensile stress is generated in the well region 103 ( Figure 2 (As shown by the red arrow in the figure), under the action of tensile stress, the effective mass and scattering probability of the electron conduction in well region 103 decrease, the mobility in well region 103 increases, and the on-resistance decreases. Similarly, when the first conductivity type is P-type and well region 103 is N-type, a stress adjustment layer 200 is deposited on the surface of well region 103 (the sidewall in this embodiment). The well region 103 is subjected to a strain effect, generating compressive stress. Under the action of compressive stress, the effective mass and scattering probability of the electron conduction in well region 103 decrease, the mobility in well region 103 increases, and the on-resistance decreases.

[0069] Optionally, the first surface 191 is further provided with a recess 105, which extends from the first surface into the first region 104, with the side surface of the recess 105 contacting the well region 103; the stress adjustment layer 200 is located within the recess 105. In this embodiment, the stress adjustment layer 200 is disposed within the recess 105, that is, in contact with the sidewall of the well region 103. This can better attract carriers in the epitaxial layer 20 (or drift region) to the well region 103, thereby significantly increasing the channel mobility; and it can also avoid increasing the thickness of the semiconductor device.

[0070] Alternatively, if the first conductivity type is N-type, the stress adjustment layer 200 may be made of diamond, for example, a diamond film. The semiconductor body 100 may be made of, for example, silicon carbide or gallium nitride. The carbon-carbon bond length of diamond is shorter than that of silicon carbide, thereby generating tensile stress in the well region 103.

[0071] Optionally, if the first conductivity type is P-type, the material of the stress adjustment layer 200 includes at least one of silicon and silicon-germanium (SiGe) alloy.

[0072] Optionally, continue to refer to Figure 1 The semiconductor device further includes a first insulating layer 301; the first insulating layer 301 is located on the first surface 101; the gate 302 is located on a side of the first insulating layer 301 away from the second surface 102; along the thickness direction Y of the semiconductor device, the projection of the stress adjustment layer 200 on the second surface 102 is located within the projection of the first insulating layer 301 on the second surface 102.

[0073] Specifically, in this embodiment, the first insulating layer 301 is used to isolate the gate electrode 302 from the semiconductor body 100. The gate electrode 302 is, for example, polysilicon. The orthographic projection of the stress adjustment layer 200 on the second surface 102 is completely within the orthographic projection of the first insulating layer 301 on the second surface 102. In other words, the source electrode 400 does not contact the stress adjustment layer 200. Consequently, a larger portion of the first region 104 is exposed on the first surface 101, thereby better forming an ohmic contact with the source electrode 400 and reducing contact resistance.

[0074] Optionally, continue to refer to Figure 1 In some embodiments, the second side surface 202 of the stress adjustment layer 200 is flush with the side surface of the first insulating layer 301 ; wherein the second side surface 202 of the stress adjustment layer 200 is opposite to the first side surface 201 of the stress adjustment layer 200 .

[0075] Specifically, the side surfaces of the stress adjustment layer 200 are flush with the side surfaces of the first insulating layer 301. In other words, the first insulating layer 301 does not contact the first region 103. The various regions of the first surface 101 may have uneven topography during formation, and the greater the variety, the greater the probability of unevenness. In this embodiment, the first insulating layer 301 contacts a smaller number of regions on the first surface 101, resulting in a higher flatness of the corresponding first surface 101, which helps improve the thickness uniformity of the first insulating layer 301.

[0076] Of course, in some other embodiments, such as Figure 3 As shown, Figure 3 This is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. In this embodiment, the side of the groove 105 away from the well region 103 is located on the side of the first insulating layer 301 corresponding to the side close to the gate 302 .

[0077] Alternatively, in some other embodiments, such as Figure 4 As shown, Figure 4 This is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. In this embodiment, the side of the groove 105 away from the well region 103 is located on the side of the first insulating layer 301 away from the gate 302 .

[0078] Optionally, continue to refer to Figure 1 The thickness of the stress adjustment layer 200 is 30% to 50% of the maximum thickness of the first region 104 .

[0079] Specifically, the maximum thickness of the first region 104 is the depth of ion implantation during ion implantation into the semiconductor body to form the first region 104. If the thickness of the stress adjustment layer 200 is too small, such as less than 30% of the maximum thickness of the first region 104, the contact area between the stress adjustment layer 200 and the well region 103 is too small, the strain effect on the well region 103 is small, and the impact on the on-resistance is small. On the other hand, if the thickness of the stress adjustment layer 200 is too large, such as greater than 50% of the maximum thickness of the first region 104, the conductive channel will be too narrow, which is not conducive to reducing the on-resistance. In this embodiment, the thickness of the stress adjustment layer 200 is 30% to 50% of the maximum thickness of the first region 104, which can effectively reduce the on-resistance of the semiconductor device.

[0080] Optionally, continue to refer to Figure 1Semiconductor body 100 further includes a second region 106, which is configured as the second conductivity type and is located on first surface 101. Second region 106 is located on a side of first region 104 away from well region 103, and the ion concentration in second region 106 is greater than the ion concentration in well region 103. If the second conductivity type is P-type, second region 106 can be understood as a P+ region. Second region 106 is used to improve the conductivity of the semiconductor device, forming a good contact area, thereby enhancing the performance of the semiconductor device.

[0081] Optionally, continue to refer to Figure 1 , semiconductor devices also include:

[0082] The interlayer dielectric layer 700 is located between the gate 302 and the source 400 and is used to isolate the gate 302 from the source 400 .

[0083] The drain electrode 600 is located on the second surface 102 . The material of the drain electrode 600 can be titanium, titanium nitride, or aluminum.

[0084] The packaging structure 500 includes a passivation layer 501 and a protective layer 502. The passivation layer 501 is located on the side of the source 400 away from the first surface 101. The protective layer 502 is located on the side of the passivation layer 501 away from the first surface 101. The protective layer 502 covers the passivation layer 501 and the sidewalls of the passivation layer 501 away from the edge of the semiconductor device. The area not encapsulated by the packaging structure is the lead area of ​​the gate 302, and the lead area can electrically connect the gate 302 to the outside. The material of the passivation layer 501 can be silicon dioxide and / or silicon nitride. The material of the protective layer 502 can be, for example, polyimide.

[0085] Based on the same inventive concept, the present invention also provides a method for manufacturing a semiconductor device, which is used to manufacture the semiconductor device provided by any embodiment of the present invention. Figure 5 As shown, Figure 5 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention. The method for manufacturing a semiconductor device includes:

[0086] Step S101, providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface; the well region being of a second conductivity type and located on the first surface; and the first region extending from the first surface into the well region;

[0087] Step S102 , forming a stress adjustment layer, wherein the stress adjustment layer is located on the first surface and extends from the first surface into the first region; a first side surface of the stress adjustment layer contacts the well region; the stress adjustment layer is used to adjust stress in the well region;

[0088] For example, the stress adjustment layer may be formed by deposition.

[0089] Step S103, forming a gate on the first surface of the semiconductor body;

[0090] Step S104 , forming a source electrode on a side of the gate away from the first surface.

[0091] In the method for manufacturing a semiconductor device of this embodiment, the manufactured semiconductor device adjusts the stress of the well region through a stress adjustment layer, so that the well region generates tensile stress or compressive stress, thereby reducing the effective mass and scattering probability of electron conductivity in the well region, increasing the mobility of the well region, that is, increasing the mobility of the channel, and reducing the on-resistance.

[0092] Optionally, Figures 6-10 The main steps of the method for manufacturing a semiconductor device according to the embodiment of the present invention correspond to the product structure diagram formed, with reference to Figures 6 to 10 .

[0093] Providing a semiconductor body includes: forming a groove on a first surface of the semiconductor body, the groove extending from the first surface to within the first region; and a side surface of the groove contacts the well region;

[0094] Forming the stress adjustment layer includes forming the stress adjustment layer in the groove.

[0095] For example, the stress adjustment layer may be configured to fill the entire groove.

[0096] Optionally, providing the semiconductor body includes:

[0097] A substrate and an epitaxial layer are provided, wherein a surface of the epitaxial layer away from the substrate is a first surface, and a surface of the substrate away from the epitaxial layer is a second surface.

[0098] Specifically, if Figure 6 As shown, the substrate 10 and the epitaxial layer 20 have the same doping type, and the ion concentration of the substrate 10 is greater than the doping concentration of the epitaxial layer 20. The epitaxial layer 20 may be formed by epitaxial growth on the substrate 10.

[0099] A well region is formed on the first surface of the semiconductor body; a first region is formed on the first surface of the semiconductor body; and a groove is formed on the first surface of the semiconductor body.

[0100] like Figure 7 As shown, for example, the well region 103 and the first region 104 can be formed in sequence by ion implantation. Furthermore, before forming the well region 103, the second region 106 can be formed first. P-type ion implantation can use aluminum ions or boron ions; N-type ion implantation can use phosphorus ions or nitrogen ions. Figure 8As shown, after forming the first region 104, a mask layer 900 is formed on the first surface 101. The material of the mask layer 900 is, for example, silicon dioxide. The recess 105 is etched using the mask layer 900 as a mask.

[0101] like Figure 9 As shown, after the groove 105 is etched, the mask layer 900 is retained first, and after the stress adjustment layer 200 is deposited, the mask layer 900 is removed.

[0102] Then, if Figure 10 As shown, a first insulating layer 301 and a gate 302 are formed.

[0103] Then, if Figure 1 As shown, an interlayer dielectric layer 700 is formed, and then the first insulating layer 301 is etched to expose the first region 104 and the second region 106. Subsequently, a source electrode 400, a passivation layer 501, a protection layer 502 and a drain electrode 600 are formed.

[0104] Optionally, if the first conductivity type is N-type, the lattice spacing of the stress adjustment layer is smaller than the lattice spacing of the semiconductor body; if the first conductivity type is P-type, the lattice spacing of the stress adjustment layer is larger than the lattice spacing of the semiconductor body.

[0105] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device as described in any of the embodiments of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device as described in any of the embodiments of the present invention are not further elaborated here.

[0106] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0107] Therefore, the beneficial effects of the power conversion circuit including any semiconductor device described in the embodiments of the present invention will not be repeated here.

[0108] An embodiment of the present invention further provides a vehicle including a load and a power conversion circuit according to any embodiment of the present invention. The power conversion circuit is configured to convert AC power to DC power, AC power to AC power, DC power to DC power, or DC power to AC power, and then input the converted power to the load. Therefore, the beneficial effects of the power conversion circuit described in any embodiment of the present invention in the vehicle are not further elaborated here.

[0109] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0110] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a first surface and a second surface opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface; the well region being of a second conductivity type and located on the first surface; and the first region extending from the first surface into the well region. a stress adjustment layer, located on the first surface and extending from the first surface into the first region; and a first side surface of the stress adjustment layer is in contact with the well region; The stress adjustment layer is used to adjust the stress of the well region; a gate, located on the first surface; The source is located on the first surface.

2. The semiconductor device according to claim 1, wherein If the first conductivity type is N-type, the lattice spacing of the stress adjustment layer is smaller than the lattice spacing of the semiconductor body; if the first conductivity type is P-type, the lattice spacing of the stress adjustment layer is larger than the lattice spacing of the semiconductor body.

3. The semiconductor device according to claim 1, wherein The first surface is further provided with a groove, the groove extending from the first surface into the first region, and a side surface of the groove contacts the well region; the stress adjustment layer is located in the groove.

4. The semiconductor device according to claim 1, wherein The semiconductor device further comprises a first insulating layer; a gate The first insulating layer is located on the first surface; The gate is located on a side of the first insulating layer away from the second surface; Along a thickness direction of the semiconductor device, a projection of the stress adjustment layer on the second surface is located within a projection of the first insulating layer on the second surface.

5. The semiconductor device according to claim 4, wherein The second side surface of the stress adjustment layer is flush with the side surface of the first insulating layer; and the second side surface of the stress adjustment layer is opposite to the first side surface of the stress adjustment layer.

6. The semiconductor device according to claim 2, wherein If the first conductivity type is N-type, the material of the stress adjustment layer includes diamond; If the first conductivity type is P type, the material of the stress adjustment layer includes at least one of silicon and germanium-silicon alloy.

7. The semiconductor device according to claim 1, wherein The thickness of the stress adjustment layer is 30% to 50% of the maximum thickness of the first region.

8. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a well region and a first region; the first region being of a first conductivity type and located on the first surface; the well region being of a second conductivity type and located on the first surface; and the first region extending from the first surface into the well region. forming a stress adjustment layer, the stress adjustment layer being located on the first surface and extending from the first surface into the first region; and a side surface of the stress adjustment layer being in contact with the well region; the stress adjustment layer being used to adjust stress in the well region; forming a gate on the first surface of the semiconductor body; A source is formed on a side of the gate away from the first surface.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The semiconductor body provided includes: forming a groove on the first surface of the semiconductor body, wherein the groove extends from the first surface into the first region; and a side surface of the groove contacts the well region; The forming of the stress adjustment layer comprises: The stress adjustment layer is formed in the groove.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The semiconductor body provided includes: Providing a substrate and an epitaxial layer, wherein a surface of the epitaxial layer away from the substrate is the first surface, and a surface of the substrate away from the epitaxial layer is the second surface; forming a well region on the first surface of the semiconductor body; forming the first region on the first surface of the semiconductor body; The groove is formed on the first surface of the semiconductor body.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: If the first conductivity type is N-type, the lattice spacing of the stress adjustment layer is smaller than the lattice spacing of the semiconductor body; if the first conductivity type is P-type, the lattice spacing of the stress adjustment layer is larger than the lattice spacing of the semiconductor body.

12. A power module, characterized in that: The method comprises a substrate and at least one semiconductor device according to any one of claims 1 to 7, wherein the substrate is used to carry the semiconductor device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and the power conversion circuit as claimed in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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