Trench MOSFET

Abstract

A first gate conductive material layer and a second gate conductive material layer which are isolated from each other are formed in a gate trench, a first well region and a first source region at the top are formed on the first side of the gate trench, and a second doped region with the bottom or extending below the bottom surface of the gate trench is formed on the second side of the gate trench; a second source region and a plane gate located on the outer side of the second source region are formed on the surface of the top of the second doped region, and the first source region, the second source region, the first well region, the second doped region, the second gate conductive material layer and a third gate conductive material layer of the plane gate are all connected to a source electrode. According to the invention, transverse and longitudinal grid-control diodes can be integrated, reverse follow current can be realized, conduction voltage drop can be reduced, unipolar conduction can be realized, dynamic loss can be reduced, the reliability of the device can be improved, and Miller capacitance can be reduced.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, in particular to a trench MOSFET. Background Art

[0002] The performance of traditional silicon-based semiconductor devices has gradually approached the physical limits of the material. Devices made of third-generation semiconductor materials represented by silicon carbide (SiC) have excellent working capabilities such as high frequency, high voltage, high temperature resistance, and radiation resistance. They can achieve higher power density and higher efficiency, and have broad application prospects in the field of high-power, high-temperature and high-frequency power electronics.

[0003] As a representative SiC switching device, SiC MOSFETs offer advantages such as low switching losses, high operating frequency, easy drive, and suitability for parallel operation. They are now gaining popularity and adoption in applications such as electric vehicles, charging stations, renewable energy generation, industrial control, and flexible DC transmission. However, due to the large bandgap of silicon carbide (SiC), the body diode of SiC MOSFETs exhibits a high forward voltage drop (VON > 2.7V), increasing device conduction losses. Furthermore, the non-equilibrium storage of injected minority carriers during body diode conduction and the reverse recovery of the body diode during turn-off also increase device losses. Furthermore, due to the low stacking fault energy on the basal plane of SiC, basal plane dislocations can split into Shockley partial dislocations under external forces, generating stacking faults that can cause bipolar degradation and reliability issues. Therefore, when using SiC MOSFETs, an external SiC Schottky diode is typically connected in antiparallel, but this introduces additional parasitic parameters and increases system manufacturing costs.

[0004] To protect the trench gate oxide of SiC MOSFET, Infineon proposed a half-wrapped trench structure. When forward conducting, this structure sacrifices half of the device's channel. When conducting in the third quadrant, the device's body diode conducts freewheeling current, resulting in a large conduction voltage drop and high losses. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a trench MOSFET that can integrate a gate-controlled diode, thereby achieving reverse freewheeling without the need for a body diode or an additional parallel diode, reducing the conduction voltage drop and achieving unipolar conduction, reducing conduction losses, and reducing costs.

[0006] In order to solve the above technical problems, the present invention provides a trench MOSFET comprising:

[0007] A first epitaxial layer doped with a first conductivity type is provided, and a drain region heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer.

[0008] A trench separation gate structure comprises a gate trench, a first gate conductive material layer and a second gate conductive material layer formed in the gate trench.

[0009] An inter-gate dielectric layer is located between the first gate conductive material layer and the second gate conductive material layer.

[0010] A bottom dielectric layer is located between the bottom surface of the gate trench and the first gate conductive material layer and the second gate conductive material layer.

[0011] A first side gate dielectric layer is spaced between the first side of the gate trench and the first gate conductive material layer, and a second side gate dielectric layer is spaced between the second side of the gate trench and the second gate conductive material layer.

[0012] A first well region of the second conductive type is formed in the first epitaxial layer at the first side surface of the gate trench, and the bottom surface of the first well region is located above the bottom surface of the gate trench; the surface of the first well region covered by the side of the first gate conductive material layer is used to form the first channel region of the MOSFET.

[0013] A first source region heavily doped with a first conductivity type is formed in a surface area of ​​the first well region, and a second side surface of the first well region and a second side surface of the first source region are aligned with a first side surface of the gate trench.

[0014] A second doped region of a second conductivity type is formed in the first epitaxial layer at the second side surface of the gate trench, the bottom surface of the second doped region is located below the bottom surface of the gate trench and the second doped region also extends directly below the bottom surface of the gate trench.

[0015] A second source region heavily doped with the first conductive type is formed in the surface area of ​​the second doping region, the first side surface of the second source region and the first side surface of the second doping region are aligned with the second side surface of the gate trench, and the second side surface of the second source region is located on the inner side of the second side surface of the second doping region; the surface of the second doping region covered by the side surface of the second gate conductive material layer is used to form the second channel region of the first gate-controlled diode.

[0016] A planar gate is formed on the top surface of the second doped region, and the second side surface of the second source region is aligned with the first side surface of the planar gate or extends below the planar gate; the second side surface of the planar gate extends to the surface of the first epitaxial layer outside the second side surface of the second doped region, and the planar gate includes a third gate dielectric layer and a third gate conductive material layer stacked in sequence; the surface of the second doped region covered by the third gate conductive material layer is used to form a third channel region of the second gate-controlled diode.

[0017] The first source region, the second source region, the first well region, the second doped region, the second gate conductive material layer and the third gate conductive material layer are all connected to the source electrode composed of the front metal layer through corresponding top through-holes.

[0018] A further improvement is that the material of the first epitaxial layer is a semiconductor material having a band gap width greater than the band gap width of silicon.

[0019] A further improvement is that the material of the first epitaxial layer includes SiC.

[0020] A further improvement is that the bottom dielectric layer, the first side gate dielectric layer, the second side dielectric layer, the inter-gate dielectric layer and the third gate dielectric layer are made of the same material.

[0021] The thickness of the bottom dielectric layer is greater than that of the first side gate dielectric layer; the first side gate dielectric layer and the second side gate dielectric layer have the same process structure and are formed simultaneously.

[0022] A further improvement is that the material of the bottom dielectric layer includes an oxide layer;

[0023] The second gate conductive material layer has the same process structure as the first gate conductive material layer;

[0024] The first gate conductive material layer includes a polysilicon gate;

[0025] The third gate conductive material layer includes a polysilicon gate.

[0026] A further improvement is that both the first side gate dielectric layer and the second side gate dielectric layer are thermal oxidation layers formed by a thermal oxidation process.

[0027] The inter-gate dielectric layer is formed by photolithographically etching the deposited oxide layer filled in the gate trench.

[0028] The bottom dielectric layer is composed of the deposited oxide layer after etching and a thermal oxide layer formed by thermally oxidizing the bottom surface of the gate trench.

[0029] A further improvement is that the second doped region is divided into a second well region located in the top region and a first buried layer located in the bottom region.

[0030] The process structure of the second well region is the same as that of the first well region and is formed simultaneously.

[0031] Along the length direction of the gate trench, the first buried layers are continuously distributed or arranged at intervals.

[0032] The doping concentration of the second well region is used to adjust the turn-on voltage of the first gate-controlled diode and the second gate-controlled diode.

[0033] A further improvement is that the doping concentration range of the main region of the second well region is 1E17cm -3 ~1E19cm -3 .

[0034] The doping concentration range of the surface area of ​​the second well region is 1E17cm -3 ~1E19cm -3 Or less than 1E17cm -3 Or it is lower than the doping concentration of the first epitaxial layer and makes the net doping type the first conductivity type.

[0035] A further improvement is that the top region of each first buried layer further extends into the second well region and serves as a component of the second well region.

[0036] A further improvement is that the thickness of the third gate dielectric layer is 10 nm to 60 nm.

[0037] A further improvement is that a first well contact region heavily doped with the second conductive type is formed in the surface area of ​​the first well region, and the second side surface of the first well contact region is located outside or aligned with the first side surface of the first source region; the through hole at the top of the first source region is in contact with the first well contact region at the same time and realizes the lead-out of the first well region.

[0038] A second well contact region heavily doped with a second conductivity type is formed in the surface area of ​​the second doped region, the first side of the second well contact region is aligned with the first side of the second source region, and the second side of the second well contact region is aligned with the second side of the second source region; along the length direction of the gate trench, the second source region and the second well contact region are alternately arranged.

[0039] A further improvement is that the through hole at the top of the first source region is in contact with the first well contact region at the same time and realizes the extraction of the first well region.

[0040] The through hole at the top of the second source region is in contact with the second well contact region at the same time and realizes the extraction of the second doped region.

[0041] A further improvement is that ohmic contact alloys are formed at the bottoms of the through holes on top of the first source region, the second source region, the second gate conductive material layer, and the third gate conductive material layer, respectively.

[0042] A further improvement is that a drain electrode composed of a back metal layer is formed on the back side of the drain region.

[0043] A further improvement is that the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0044] The present invention designs the trench gate as a split gate, i.e., a trench split gate. A first gate conductive material layer and a second gate conductive material layer, each isolated from each other, are simultaneously formed in the gate trench. The first gate conductive material layer is used to control a first channel region located at a first side of the gate trench, and the second gate conductive material layer is used to control a second channel region located at a second side of the gate trench. In addition, a planar gate is formed on a top surface of a second doped region located at the second side of the gate trench, and the planar gate is used to control a third channel region. Both the second and third channel regions are formed by the second doped region. A second source region is formed on a top surface of the second doped region and is located between the gate trench and the planar gate. The second source region, the second gate conductive material layer, and the third conductive material layer of the planar gate are all connected to the source, thereby simultaneously realizing a first longitudinal gate-controlled diode and a second transverse gate-controlled diode with gates and sources connected together. The two gate-controlled diodes can be turned on in the third quadrant operating state. Therefore, the present invention can integrate two gate-controlled diodes, thereby achieving reverse freewheeling without the need for a body diode or an additional parallel diode, and significantly reducing the dynamic loss of the device.

[0045] The conduction voltage drop of each gate-controlled diode corresponds to the threshold voltage when each channel region is turned on. The present invention can simultaneously reduce the conduction voltage of the two gate-controlled diodes through the second doped region, so the gate-controlled diode of the present invention has the advantage of low conduction voltage drop; the gate-controlled diode of the present invention is formed by MOSFET connection, so it also has the advantage of unipolar conduction, so there is no reverse recovery current and no bipolar degeneration, which can improve the reverse recovery characteristics and enhance reliability.

[0046] In addition, part of the second doped region of the present invention is located directly below the bottom surface of the trench gate, which can reduce the overlapping area between the gate and the drain, thereby significantly reducing the Miller capacitance and thus reducing the switching damage of the device.

[0047] In addition, since the present invention does not require an external anti-parallel Schottky diode, no additional parasitic parameters are introduced, thereby reducing system manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0049] Figure 1 Schematic diagram of the three-dimensional structure of a trench MOSFET according to an embodiment of the present invention, omitting the front structure above the interlayer film;

[0050] Figure 2 is a schematic diagram of the three-dimensional structure of the second well contact region shown on the xy plane of the trench MOSFET according to an embodiment of the present invention;

[0051] Figure 3 is a schematic diagram showing the three-dimensional structure of the second source region on the xy plane of the trench MOSFET according to an embodiment of the present invention;

[0052] Figure 4 is a cross-sectional structural diagram of the trench MOSFET according to an embodiment of the present invention, showing the second source region along the xy plane;

[0053] Figure 5 is a simplified equivalent circuit diagram of a trench MOSFET according to an embodiment of the present invention;

[0054] Figure 6 is a simplified equivalent circuit diagram showing the flow direction of the forward conduction current of the trench MOSFET according to an embodiment of the present invention;

[0055] Figure 7 is a simplified equivalent circuit diagram of a trench MOSFET according to an embodiment of the present invention, showing the flow of the third quadrant conduction current;

[0056] Figures 8-15 It is a schematic diagram of the device cross-sectional structure in each step of the manufacturing method of the trench MOSFET according to an embodiment of the present invention. DETAILED DESCRIPTION

[0057] like Figure 1 , which is a schematic diagram of the three-dimensional structure of a trench MOSFET according to an embodiment of the present invention, omitting the front structure above the interlayer film; Figure 2 1 is a schematic diagram showing the three-dimensional structure of the second well contact region 103 on the xy plane of the trench MOSFET according to an embodiment of the present invention; Figure 3 FIG. 1 is a schematic diagram showing the three-dimensional structure of the second source region 111 on the xy plane of the trench MOSFET according to an embodiment of the present invention; Figure 4 , which is a cross-sectional structure diagram of the second source region 111 of the trench MOSFET according to an embodiment of the present invention; Figure 5FIG. 1 is a simplified equivalent circuit diagram of a trench MOSFET according to an embodiment of the present invention. The trench MOSFET according to an embodiment of the present invention includes:

[0058] The first epitaxial layer 3 is doped with the first conductivity type, and a drain region 2 heavily doped with the first conductivity type is formed on the back surface of the first epitaxial layer 3 .

[0059] In the embodiment of the present invention, the material of the first epitaxial layer 3 is a semiconductor material having a band gap greater than that of silicon. The material of the first epitaxial layer 3 includes SiC.

[0060] A first epitaxial layer 3 is formed on the top surface of a semiconductor substrate. The semiconductor substrate and the first epitaxial layer 3 are made of the same material. In some embodiments, the semiconductor substrate is heavily doped with the first conductivity type, and the drain region 2 is formed from a thinned semiconductor substrate. In other embodiments, the drain region 2 can be formed by further back-side ion implantation of the thinned semiconductor substrate to heavily dope it with the first conductivity type.

[0061] The trench-separated gate structure includes a gate trench 4 , a first gate conductive material layer 72 and a second gate conductive material layer 71 formed in the gate trench 4 .

[0062] An inter-gate dielectric layer is located between the first gate conductive material layer 72 and the second gate conductive material layer 71 .

[0063] A bottom dielectric layer is interposed between the bottom surface of the gate trench 4 and the first gate conductive material layer 72 and the second gate conductive material layer 71 .

[0064] A first side gate dielectric layer is located between the first side surface of the gate trench 4 and the first gate conductive material layer 72 , and a second side gate dielectric layer is located between the second side surface of the gate trench 4 and the second gate conductive material layer 71 .

[0065] In the embodiment of the present invention, the second gate conductive material layer 71 and the first gate conductive material layer 72 have the same process structure;

[0066] The first gate conductive material layer 72 includes a polysilicon gate;

[0067] The subsequent third gate conductive material layer 13 includes a polysilicon gate.

[0068] In the embodiment of the present invention, the bottom dielectric layer, the first side gate dielectric layer, the second side dielectric layer, the intergate dielectric layer and the third gate dielectric layer 12 are made of the same material. Preferably, the bottom dielectric layer is made of an oxide layer. That is, all of them are made of an oxide layer.

[0069] In the embodiment of the present invention, the thickness of the bottom dielectric layer is greater than the thickness of the first side gate dielectric layer; the first side gate dielectric layer and the second side gate dielectric layer have the same process structure and are formed simultaneously.

[0070] In the embodiment of the present invention, preferably, both the first side gate dielectric layer and the second side gate dielectric layer are thermal oxide layers 6 formed by a thermal oxidation process.

[0071] The inter-gate dielectric layer is formed by photolithographically etching the deposited oxide layer 5 filled in the gate trench 4 .

[0072] The bottom dielectric layer is composed of an etched deposited oxide layer 5 stacked with a thermal oxide layer 6 formed by thermally oxidizing the bottom surface of the gate trench 4 .

[0073] In other embodiments, the inter-gate dielectric layer can also be formed using other processes or dielectric materials, as long as isolation between the first gate conductive material layer 72 and the second gate conductive material layer 71 is achieved. The bottom dielectric layer can also be formed using other processes or dielectric materials, and the provision of the bottom dielectric layer can improve device reliability.

[0074] A first well region 93 of the second conductive type is formed in the first epitaxial layer 3 at the first side surface of the gate trench 4, and the bottom surface of the first well region 93 is located above the bottom surface of the gate trench 4; the surface of the first well region 93 covered by the side of the first gate conductive material layer 72 is used to form the first channel region of MOSFET201.

[0075] A first source region 112 heavily doped with the first conductivity type is formed in the surface area of ​​the first well region 93 . The second side surfaces of the first well region 93 and the first source region 112 are aligned with the first side surface of the gate trench 4 . Figure 1 , an xyz coordinate system is shown. In the present application, the first side surface and the second side surface of the gate trench 4 are the side surfaces along the x-axis direction, and the length direction of the gate trench 4 is along the z-axis direction; Figure 1 In the figure, the right side surface of the gate trench 4 is the first side surface, and the left side surface is the second side surface; the first side surface of other structures is also the right side surface and the second side surface is the left side surface.

[0076] A second doped region of the second conductivity type is formed in the first epitaxial layer 3 at the second side surface of the gate trench 4, and the bottom surface of the second doped region is located below the bottom surface of the gate trench 4 and the second doped region also extends directly below the bottom surface of the gate trench 4.

[0077] In the embodiment of the present invention, the second doped region is divided into a second well region 92 located in the top region and a first buried layer 8 located in the bottom region.

[0078] The process structure of the second well region 92 is the same as that of the first well region 93 and they are formed simultaneously.

[0079] Figure 1 Also shown is a third well region 91, which can be formed simultaneously with the first well region 93 and the second well region 92. A third well contact region 101 heavily doped with the second conductivity type is also formed on the surface of the third well region 91. The third well contact region 101 can be formed simultaneously with the second well contact region 103 and the first well contact region 102 using the same process. Figure 1 FIG1 shows a complete structure of a trench MOSFET according to an embodiment of the present invention. Multiple trench MOSFETs can be integrated simultaneously on the same semiconductor substrate, and the third well region 91 and the third well contact region 101 can serve as components of other trench MOSFETs not shown.

[0080] Along the length direction of the gate trench 4 , ie, the z-axis, the first buried layers 8 are continuously distributed or arranged at intervals. Figure 1 A first buried layer 8 is formed on the xy plane shown. When the first buried layers 8 are arranged at intervals, a portion of the region remains as the first epitaxial layer 3 .

[0081] In the embodiment of the present invention, the top region of each first buried layer 8 also extends into the second well region 92 and serves as a component of the second well region 92. For the superposition of the first buried layer 8 and the second well region 92, please refer to the corresponding manufacturing method. Figure 8 and Figure 9 shown.

[0082] In other embodiments, the implantation region of the first buried layer 8 may be entirely located at the bottom of the second well region 92 .

[0083] A second source region 111 heavily doped with the first conductive type is formed in the surface area of ​​the second doping region, the first side surface of the second source region 111 and the first side surface of the second doping region are aligned with the second side surface of the gate trench 4, and the second side surface of the second source region 111 is located on the inner side of the second side surface of the second doping region; the surface of the second doping region covered by the side surface of the second gate conductive material layer 71 is used to form the second channel region of the first gate-controlled diode 202.

[0084] A planar gate is formed on the top surface of the second doped region, and the second side surface of the second source region 111 is aligned with the first side surface of the planar gate or extends below the planar gate; the second side surface of the planar gate extends to the surface of the first epitaxial layer 3 outside the second side surface of the second doped region, and the planar gate includes a third gate dielectric layer 12 and a third gate conductive material layer 13 stacked in sequence; the surface of the second doped region covered by the third gate conductive material layer 13 is used to form a third channel region of the second gate-controlled diode 203.

[0085] In some embodiments, the thickness of the third gate dielectric layer 12 is 10 nm to 60 nm. The thickness of the third gate dielectric layer 12 can further adjust the turn-on voltage of the second gate-controlled diode 203 .

[0086] Please also refer to Figure 2 and Figure 3 As shown, the first source region 112, the second source region 111, the first well region 93, the second doped region, the second gate conductive material layer 71, and the third gate conductive material layer 13 are all connected to the source electrode formed by the front metal layer 17 through corresponding vias on the top. The vias pass through the interlayer film 14.

[0087] In the embodiment of the present invention, the doping concentration of the second well region 92 is used to adjust the turn-on voltage of the first gate-controlled diode 202 and the second gate-controlled diode 203 .

[0088] The doping concentration range of the main region of the second well region 92 is 1E17 cm -3 ~1E19cm -3 .

[0089] In some embodiments, the doping concentration of the surface region of the second well region 92 is in the range of 1E17 cm -3 ~1E19cm -3 At this time, the doping concentration range of the entire depth range of the second well region 92 is 1E17cm -3 ~1E19cm -3 .

[0090] In some embodiments, the doping concentration of the surface region of the second well region 92 can be less than 1E17 cm -3 However, it is greater than the doping concentration of the first epitaxial layer 3, and the net doping concentration of the surface area of ​​the second well region 92 remains the second conductive type. The doping concentration of the surface area of ​​the second well region 92 is reduced, which can reduce the threshold voltage of the second gate-controlled diode 203. Since the gate and source of the second gate-controlled diode 203 are connected together, the threshold voltage is also the turn-on voltage between the source and the drain, so the turn-on voltage can be reduced.

[0091] In some embodiments, the doping concentration of the surface area of ​​the second well region 92 is lower than the doping concentration of the first epitaxial layer 3 and the net doping type is the first conductive type. In this case, the channel of the second gate-controlled diode 203 becomes an accumulation type.

[0092] In an embodiment of the present invention, a first well contact region 102 heavily doped with the second conductivity type is formed in the surface area of ​​the first well region 93, and the second side surface of the first well contact region 102 is located on the outside of or aligned with the first side surface of the first source region 112; the through hole at the top of the first source region 112 is in contact with the first well contact region 102 at the same time and realizes the lead-out of the first well region 93.

[0093] A second well contact region 103 heavily doped with the second conductivity type is formed in the surface area of ​​the second doped region. The first side surface of the second well contact region 103 is aligned with the first side surface of the second source region 111, and the second side surface of the second well contact region 103 is aligned with the second side surface of the second source region 111. In the length direction of the gate trench 4, the second source regions 111 and the second well contact regions 103 are alternately arranged. For the structure of the alternating arrangement of the second source regions 111 and the second well contact regions 103, please refer to Figure 1 shown.

[0094] The through hole at the top of the first source region 112 is in contact with the first well contact region 102 and realizes the extraction of the first well region 93 .

[0095] The through hole at the top of the second source region 111 is in contact with the second well contact region 103 and realizes the extraction of the second doped region.

[0096] Ohmic contact alloys are also formed at the bottoms of the through holes on the tops of the first source region 112, the second source region 111, the second gate conductive material layer 71, and the third gate conductive material layer 13. Figure 2 or Figure 3 As shown,

[0097] The ohmic contact alloy corresponding to the surface of the second source region 111 and the second well contact region 103 is individually indicated by mark 161, the ohmic contact alloy corresponding to the surface of the first source region 112 and the first well contact region 102 is individually indicated by mark 162, the ohmic contact alloy corresponding to the surface of the second gate conductive material layer 71 is individually indicated by mark 152, and the ohmic contact alloy corresponding to the surface of the third gate conductive material layer 13 is individually indicated by mark 151.

[0098] A drain electrode composed of a back metal layer 1 is formed on the back side of the drain region 2 .

[0099] In the embodiment of the present invention, the trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the trench MOSFET can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0100] In the embodiment of the present invention, the trench gate is designed as a separated gate, i.e., a separated trench gate. A first gate conductive material layer 72 and a second gate conductive material layer 71 are formed in the gate trench 4, wherein the first gate conductive material layer 72 is used to control the first channel region located at the first side of the gate trench 4, and the second gate conductive material layer 71 is used to control the second channel region located at the second side of the gate trench 4. In addition, a planar gate is formed on the top surface of the second doped region at the second side of the gate trench 4, and the planar gate is used to control the third channel region. The second channel region and the third channel region are both formed by the second doped region. A doped region is formed, and a second source region 111 is formed on the top surface of the second doped region and is located between the gate trench 4 and the planar gate. The second source region 111, the second gate conductive material layer 71 and the third conductive material layer of the planar gate are all connected to the source, so that the vertical first gate-controlled diode 202 and the horizontal second gate-controlled diode 203 with the gate and source connected together can be realized at the same time. The two gate-controlled diodes can be turned on in the third quadrant working state. Therefore, the embodiment of the present invention can integrate two gate-controlled diodes, so that reverse freewheeling can be achieved without using a body diode or an additional parallel diode, which can greatly reduce the dynamic loss of the device.

[0101] The on-state voltage drop of each gate-controlled diode corresponds to the threshold voltage when each channel region is turned on. The embodiment of the present invention can simultaneously reduce the on-state voltage of the two gate-controlled diodes through the second doped region, so the gate-controlled diode of the present invention has the advantage of low on-state voltage drop; the gate-controlled diode of the embodiment of the present invention is formed by connecting MOSFET201, so it also has the advantage of unipolar conduction, so there is no reverse recovery current and no bipolar degeneration.

[0102] In addition, part of the second doped region of the embodiment of the present invention is located directly below the bottom surface of the trench gate, which can reduce the overlapping area between the gate and the drain, thereby significantly reducing the Miller capacitance and thus reducing switching damage of the device.

[0103] In addition, since the embodiment of the present invention does not require an external anti-parallel Schottky diode, no additional parasitic parameters are introduced, thereby reducing the system manufacturing cost.

[0104] like Figure 6 , which is a simplified equivalent circuit diagram showing the flow of forward conduction current for a trench MOSFET according to an embodiment of the present invention; the trench MOSFET is integrated with a MOSFET 201, a first gate-controlled diode 202, and a second gate-controlled diode 203. During forward conduction, the gate is applied with a positive voltage greater than the threshold voltage of the MOSFET 201, and the drain is applied with a voltage greater than the source. This causes the first channel region of the MOSFET 201 to conduct, thereby forming a current Ids from the drain to the source, as shown by the dotted line 204, which is conducted through the first channel region of the MOSFET 201.

[0105] like Figure 7 , which is a simplified equivalent circuit diagram of a trench MOSFET according to an embodiment of the present invention, showing the flow direction of the on-current in the third quadrant; Figure 7 The corresponding operating state is the third quadrant operating state. When the gate voltage is less than the threshold voltage of MOSFET 201, such as 0V, MOSFET 201 is turned off, the source voltage is greater than the drain voltage, and the first gate-controlled diode 202 and the second gate-controlled diode 203 are forward biased and turned on. The conduction current of the first gate-controlled diode 202 and the second gate-controlled diode 203 corresponds to the source-to-drain current Isd shown by the dashed lines 2051 and 2052, respectively.

[0106] Typically, the threshold voltages of first gate-controlled diode 202 and second gate-controlled diode 203 are lower than the turn-on voltage of the body diode of MOSFET 201, e.g., 2.7V. The body diode is primarily formed by the PN junction of first well region 93 and first epitaxial layer 3; therefore, the currents indicated by dashed lines 2051 and 2052 are conducted first. When the difference between the source and drain voltages exceeds the turn-on voltage of the body diode, the body diode also conducts, with the conduction current shown by dashed line 2053. Therefore, in embodiments of the present invention, when the device operates in the third quadrant, the two gate-controlled diodes conduct at a voltage lower than the body diode turn-on voltage drop, providing freewheeling current and reducing system power consumption and cost.

[0107] like Figures 8 to 15 FIG. 1 is a schematic diagram of the device structure in each step of the manufacturing method of the trench MOSFET according to an embodiment of the present invention, and the corresponding cross section is the xy plane; the manufacturing method of the trench MOSFET according to an embodiment of the present invention is used to manufacture Figure 1 The trench MOSFET of the embodiment of the present invention is described with an N-type device as an example. The manufacturing method of the trench MOSFET of the embodiment of the present invention includes the following steps:

[0108] Step 1: Figure 8 As shown, a first epitaxial layer 3 doped with the first conductivity type is formed, and a drain region 2 heavily doped with the first conductivity type is formed on the back side of the first epitaxial layer 3 .

[0109] The first epitaxial layer 3 is made of silicon carbide, and the semiconductor substrate constituting the drain region 2 is also made of silicon carbide.

[0110] Step 2: Figure 8 As shown, ion implantation of the first buried layer 8 is performed.

[0111] Before ion implantation of the first buried layer 8, an oxide layer needs to be deposited as a mask layer, followed by photolithography, and then Al ion implantation is performed at a temperature of 300K to 1000K to form a P-type first buried layer 8; after the implantation is completed, the mask layer is removed and the surface is cleaned.

[0112] Step 3: Figure 9 As shown, well region implantation is performed to form well regions, including a first well region 93 , a second well region 92 and a third well region 91 . Figure 9 In the illustrated step, the first well region 93 and the second well region 92 have not yet been separated, and the third well region 91 is a component of the adjacent trench MOSFET.

[0113] Before the well region is injected, an oxide layer needs to be deposited as a mask layer, followed by photolithography, and then Al ion implantation is performed at a temperature of 300K to 1000K to form the first well region 93, the second well region 92 and the third well region 91; after the implantation is completed, the mask layer is removed and the surface is cleaned.

[0114] Step 4: Figure 10 As shown, a well contact region is formed, including a first well contact region 102, a second well contact region 103 and a third well contact region 101. The third well contact region 101 is a component of an adjacent trench MOSFET.

[0115] Before the well contact area is injected, an oxide layer needs to be deposited as a mask layer, followed by photolithography, and then Al ion injection is performed at a temperature of 300K to 1000K to form the first well contact area 102, the second well contact area 103 and the third well contact area 101; after the injection is completed, the mask layer is removed and the surface is cleaned.

[0116] Step 5: Figure 11 As shown, Figure 11 The cross-section position and Figure 10 The cross-sectional positions are different, but both are in the xy plane, forming the first source region 112 and the second source region 111. Back Figure 1 As shown, on the z-axis, the second source regions 111 and the second well contact regions 103 are alternately arranged.

[0117] Before the injection of the first source region 112 and the second source region 111, an oxide layer needs to be deposited as a mask layer, followed by photolithography, and then N ion injection is performed at a temperature of 300K to 1000K to form the first source region 112 and the second source region 111; after the injection is completed, the mask layer is removed and the surface is cleaned.

[0118] Step 6: Figure 12 As shown, gate trenches 4 are formed by etching.

[0119] Before etching the gate trench 4 , an oxide layer needs to be deposited as a mask layer, and then photolithography is performed. Thereafter, the mask layer and the first epitaxial layer 3 are etched to form the gate trench 4 . Reactive ion etching is used for etching.

[0120] Afterwards, a deposited oxide layer 5 is formed to completely fill the gate trench 4 .

[0121] After that, the deposited oxide layer 5 is etched after photolithography definition to form an inter-gate dielectric layer, while a portion of the deposited oxide layer 5 is retained on the bottom surface of the gate trench 4. Both sides of the inter-gate dielectric layer are the areas for forming the subsequent first gate conductive material layer 72 and the second gate conductive material layer 71.

[0122] Step 7: Figure 13 As shown, thermal oxidation is performed to form a thermal oxide layer 6. The thermal oxide layer 6 on the first side of the gate trench 4 serves as the first-side gate dielectric layer, and the thermal oxide layer 6 on the second side of the gate trench 4 serves as the second-side gate dielectric layer. The bottom dielectric layer is formed by stacking the thermal oxide layer 6 on the bottom surface of the gate trench 4 and the remaining deposited oxide layer 5.

[0123] In the method of the embodiment of the present invention, before thermal oxidation, a carbon cap is first covered, and then annealing is performed at a high temperature above 1600° C. to activate impurities, and thermal oxidation is performed to form a thermal oxide layer 6 .

[0124] Step 8: Figure 13 As shown, polysilicon is deposited to form a first gate conductive material layer 72 and a second gate conductive material layer 71 .

[0125] Step 9: Figure 14 As shown, a planar gate is formed by stacking the third gate dielectric layer 12 and the third gate conductive material layer 13 .

[0126] The third gate dielectric layer 12 is also formed by a thermal oxidation process.

[0127] The third gate conductive material layer 13 is formed by depositing polysilicon and performing photolithographic definition and etching.

[0128] Step 10: Figure 15 As shown, an interlayer film 14 is formed.

[0129] A through-hole opening is formed through the interlayer film 14 .

[0130] An ohmic contact alloy is formed on the bottom surface of the through-hole opening. The ohmic contact alloy is formed by depositing an alloy and then annealing it. For example, a Ni alloy is first deposited and then annealed at a temperature of 900-1200°C to form the ohmic contact alloy. The ohmic contact alloy includes: an ohmic contact alloy 161 corresponding to the surfaces of the second source region 111 and the second well contact region 103; an ohmic contact alloy 162 corresponding to the surfaces of the first source region 112 and the first well contact region 102; an ohmic contact alloy 152 corresponding to the surface of the second gate conductive material layer 71; and an ohmic contact alloy 151 corresponding to the surface of the third gate conductive material layer 13.

[0131] Back to Figure 4 As shown, a metal layer is filled in the via opening to form a via.

[0132] A front metal layer 17 is formed and patterned to form a source electrode and a gate electrode. The material of the front metal layer 17 includes AlCu.

[0133] Perform backside processing, including:

[0134] The back side of the semiconductor substrate used to form the drain region 2 is thinned. The drain region 2 is directly formed by the thinned semiconductor substrate; or, as needed, ion implantation is performed on the back side of the semiconductor substrate after thinning to ensure that the doping concentration of the drain region 2 meets the requirements.

[0135] The back metal layer 1 is formed to form the drain electrode. The back metal layer 1 is formed by back sputtering to form a Ni alloy and then annealing.

[0136] The trench MOSFET of the embodiment of the present invention realizes the integration of two gate-controlled diodes, that is, a trench split-gate silicon carbide MOSFET with integrated gate-controlled diodes is realized. Figure 5 As shown, the two integrated gate-controlled diodes 202 and 203 are connected in parallel with the body diode of MOSFET 201. When the device is forward-conducting, the gate of the device, i.e., the corresponding first gate conductive material layer 71, is applied with a forward bias, and the first well region 93 forms an inversion layer near the sidewall of the gate trench 4. The channel of MOSFET 201, i.e., the first channel region, is turned on, and electrons flow from the source through the longitudinal channel of MOSFET 201 and the drift region, i.e., the first epitaxial layer 3, to the drain, forming a forward current Ids, as shown in FIG. Figure 6 As shown; when the device is in the off state, the gate and the source are at zero potential, the drain is connected to a high potential, the first buried layer 8, the third well region 91, the first well region 93, the second well region 92 and the drift region are mutually depleted to achieve voltage resistance, wherein the first buried layer 8 can also play the role of protecting the gate oxide layer of the gate trench 4; when the device operates in the third quadrant, the source and gate of the planar gate-controlled diode, i.e., the first gate-controlled diode, and the trench gate-controlled diode, i.e., the second gate-controlled diode, are both connected to the source metal of the device and are at a high potential. Therefore, the second well region 92 forms an inversion layer near the semiconductor surface, i.e., the top surface side of the first epitaxial layer 3, and near the side wall of the gate trench 4. The channels of the two gate-controlled diodes are both turned on, and the current Isd flows from the source through the lateral channel and the longitudinal channel of the gate-controlled diode and the drift region to the drain, as shown Figure 7 shown.

[0137] An embodiment of the present invention realizes a trench-separated-gate silicon carbide MOSFET with an integrated gate-controlled diode, which has the following advantages: it effectively utilizes the area of ​​the SiC asymmetric trench-gate MOSFET sacrificed for P-type buried layer injection to shield the electric field at the bottom corner of the trench, introduces two unipolar conductive gate-controlled diodes with adjustable turn-on voltage, and utilizes the advantage of their low turn-on voltage to reduce the turn-on voltage drop of the device in the third quadrant working state, thereby reducing the conduction loss of the device and effectively improving the bipolar degradation problem of the device; in half-bridge or full-bridge applications, the device does not require an additional external reverse-parallel freewheeling diode, thereby reducing the system manufacturing cost.

[0138] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A trench MOSFET, characterized in that: include: a first epitaxial layer doped with a first conductivity type, with a drain region heavily doped with the first conductivity type formed on the back side of the first epitaxial layer; A trench-separated gate structure comprises: a gate trench, a first gate conductive material layer and a second gate conductive material layer formed in the gate trench; An inter-gate dielectric layer is provided between the first gate conductive material layer and the second gate conductive material layer; A bottom dielectric layer is provided between the bottom surface of the gate trench and the first gate conductive material layer and the second gate conductive material layer; A first side gate dielectric layer is spaced between the first side of the gate trench and the first gate conductive material layer, and a second side gate dielectric layer is spaced between the second side of the gate trench and the second gate conductive material layer; a first well region of the second conductivity type, formed in the first epitaxial layer at a first side surface of the gate trench, wherein a bottom surface of the first well region is located above a bottom surface of the gate trench; a surface of the first well region covered by a side surface of the first gate conductive material layer is used to form a first channel region of the MOSFET; A first source region heavily doped with a first conductivity type is formed in a surface area of ​​the first well region, and a second side surface of the first well region and a second side surface of the first source region are aligned with a first side surface of the gate trench; a second doped region of a second conductivity type, formed in the first epitaxial layer at a second side surface of the gate trench, wherein a bottom surface of the second doped region is located below a bottom surface of the gate trench and further extends to directly below the bottom surface of the gate trench; A second source region heavily doped with the first conductivity type is formed in a surface area of ​​the second doped region, a first side surface of the second source region and a first side surface of the second doped region are aligned with the second side surface of the gate trench, and the second side surface of the second source region is located inward of the second side surface of the second doped region; a surface of the second doped region covered by a side surface of the second gate conductive material layer is used to form a second channel region of the first gate-controlled diode; A planar gate is formed on the top surface of the second doped region, the second side surface of the second source region is aligned with the first side surface of the planar gate or extends below the planar gate; the second side surface of the planar gate extends to the surface of the first epitaxial layer outside the second side surface of the second doped region, the planar gate includes a third gate dielectric layer and a third gate conductive material layer stacked in sequence; the surface of the second doped region covered by the third gate conductive material layer is used to form a third channel region of a second gate-controlled diode; The first source region, the second source region, the first well region, the second doped region, the second gate conductive material layer and the third gate conductive material layer are all connected to the source electrode composed of the front metal layer through corresponding top through-holes.

2. The trench MOSFET according to claim 1, wherein: The material of the first epitaxial layer is a semiconductor material having a band gap width greater than that of silicon.

3. The trench MOSFET according to claim 2, wherein: The material of the first epitaxial layer includes SiC.

4. The trench MOSFET according to claim 1, wherein: The bottom dielectric layer, the first side gate dielectric layer, the second side dielectric layer, the inter-gate dielectric layer and the third gate dielectric layer are made of the same material; The thickness of the bottom dielectric layer is greater than that of the first side gate dielectric layer; the first side gate dielectric layer and the second side gate dielectric layer have the same process structure and are formed simultaneously.

5. The trench MOSFET according to claim 4, wherein: The material of the bottom dielectric layer includes an oxide layer; The second gate conductive material layer has the same process structure as the first gate conductive material layer; The first gate conductive material layer includes a polysilicon gate; The third gate conductive material layer includes a polysilicon gate.

6. The trench MOSFET according to claim 5, wherein: The first side gate dielectric layer and the second side gate dielectric layer are both thermal oxidation layers formed by a thermal oxidation process; The inter-gate dielectric layer is formed by photolithographically etching the deposited oxide layer filled in the gate trench; The bottom dielectric layer is composed of the deposited oxide layer after etching and a thermal oxide layer formed by thermally oxidizing the bottom surface of the gate trench.

7. The trench MOSFET according to claim 1, wherein: The second doped region is divided into a second well region located in the top region and a first buried layer located in the bottom region; The process structure of the second well region is the same as that of the first well region and is formed simultaneously; Along the length direction of the gate trench, the first buried layers are continuously distributed or arranged at intervals; The doping concentration of the second well region is used to adjust the turn-on voltage of the first gate-controlled diode and the second gate-controlled diode.

8. The trench MOSFET according to claim 7, wherein: The doping concentration range of the main region of the second well region is 1E17cm -3 ~1E19cm -3 ; The doping concentration range of the surface area of ​​the second well region is 1E17cm -3 ~1E19cm -3 Or less than 1E17cm -3 Or it is lower than the doping concentration of the first epitaxial layer and makes the net doping type the first conductivity type.

9. The trench MOSFET according to claim 7, wherein: The top region of each of the first buried layers further extends into the second well region and serves as a component of the second well region.

10. The trench MOSFET according to claim 5, wherein: The thickness of the third gate dielectric layer is 10 nm to 60 nm.

11. The trench MOSFET according to claim 1, wherein: A first well contact region heavily doped with the second conductivity type is formed in a surface region of the first well region, wherein a second side surface of the first well contact region is located outside or aligned with the first side surface of the first source region; A second well contact region heavily doped with a second conductivity type is formed in the surface area of ​​the second doped region, the first side of the second well contact region is aligned with the first side of the second source region, and the second side of the second well contact region is aligned with the second side of the second source region; along the length direction of the gate trench, the second source region and the second well contact region are alternately arranged.

12. The trench MOSFET according to claim 11, wherein: The through hole at the top of the first source region is in contact with the first well contact region and realizes the extraction of the first well region; The through hole at the top of the second source region is in contact with the second well contact region at the same time and realizes the extraction of the second doped region.

13. The trench MOSFET according to claim 12, wherein: Ohmic contact alloys are also formed at the bottoms of the through holes on top of the first source region, the second source region, the second gate conductive material layer, and the third gate conductive material layer, respectively.

14. The trench MOSFET according to claim 1, wherein: A drain electrode composed of a back metal layer is formed on the back side of the drain region.

15. The field effect transistor according to any one of claims 1 to 14, characterized in that: The trench MOSFET is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the trench MOSFET is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

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