A shunt SiC MOSFET structure and method of manufacture

Abstract

The application discloses a shunt type SiC MOSFET structure and a manufacturing method. The structure comprises a second conductive type doped region one in a first conductive type epitaxial layer one, a first conductive type doped region one in the second conductive type doped region one, a second conductive type doped region two penetrating through a first conductive type epitaxial layer two, located above the second conductive type doped region one and the first conductive type doped region one, a first conductive type doped region two and a second conductive type PP region adjacent to each other in the second conductive type doped region two, a second conductive type PC region one and a second conductive type PC region two adjacent to the first conductive type doped region two in the second conductive type doped region two, and a gate and a gate-like electrode located above a gate dielectric layer and not connected. When the on-current of the body diode is increased, the other carrier conduction path is opened, and the on performance of the body diode is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a shunt-type SiC MOSFET structure and its manufacturing method. Background Technology

[0002] Compared to silicon (Si), silicon carbide (SiC) boasts advantages such as three times the bandgap, ten times the breakdown field strength, and three times the thermal conductivity. Therefore, SiC MOSFETs offer advantages including low leakage current, high operating junction temperature, high breakdown voltage, high switching speed, low loss, and low heat dissipation requirements. Their switching losses and on-current density are significantly lower than those of Si IGBTs and Si MOSFETs. They have excellent application prospects in new energy power generation, new energy vehicles, and high-voltage power transmission and transformation, making them a key focus of scientific research and industrialization worldwide.

[0003] In existing SiC MOSFETs, a series of issues remain to be addressed regarding the performance and reliability of their body diodes. With the continuous development of power electronics technology, the performance requirements for power semiconductor devices are increasing. SiC MOSFETs, as a novel power device with numerous advantages, have shown great potential in many high-power, high-frequency applications. However, their body diode has become one of the key factors limiting their overall performance and reliability.

[0004] From a performance perspective, the reverse recovery characteristics of existing SiC MOSFET body diodes are not ideal. In practical high-frequency switching circuits, the reverse recovery time of the body diode is often relatively long, which leads to a large reverse recovery current during switching and consequently a significant increase in switching losses. This increased switching loss not only reduces the overall circuit efficiency but also causes the device to generate more heat during operation, affecting its heat dissipation performance and long-term reliability.

[0005] The forward voltage drop of a body diode is also relatively high. A higher forward voltage drop means that more electrical energy is dissipated as heat when the diode is on. This not only reduces the device's energy conversion efficiency but also poses greater thermal management challenges in high-power applications. This problem is particularly prominent in applications with extremely high energy efficiency requirements, such as electric vehicles and industrial power supplies.

[0006] Regarding reliability, the stability of existing SiC MOSFET body diodes has certain potential issues during long-term operation. Due to the inherent properties of SiC material and limitations of current manufacturing processes, the body diode may experience performance parameter drift during repeated switching. For example, the forward voltage drop may gradually increase over time, and the reverse recovery time may become unstable, which will seriously affect the normal operation and reliability of the circuit. Summary of the Invention

[0007] Technical Objective: To address the shortcomings of existing technologies, this invention discloses a shunt-type SiC MOSFET structure and its manufacturing method. This enables the SiC MOSFET structure to open up additional carrier conduction paths when the body diode conduction current increases, thereby improving the body diode conduction performance of the SiC MOSFET structure, reducing the body diode conduction voltage of the SiC MOSFET structure, and improving chip reliability.

[0008] Technical solution: To achieve the above technical objectives, the present invention adopts the following technical solution.

[0009] A shunt-type SiC MOSFET structure, comprising:

[0010] Drain ohmic contact region;

[0011] A first conductivity type substrate located above the drain ohmic contact region, an NE region located above the first conductivity type substrate, the NE region including a first conductivity type epitaxial layer one and a first conductivity type epitaxial layer two located above the first conductivity type epitaxial layer one;

[0012] A second conductivity type doped region 1 located in a first conductivity type epitaxial layer 1, and a first conductivity type doped region 1 located in a second conductivity type doped region 1;

[0013] Penetrating the second epitaxial layer of the first conductivity type, located above the first doped region of the second conductivity type, and the second doped region of the first conductivity type located above the first doped region of the first conductivity type; the second doped region of the first conductivity type and the second PP region of the second conductivity type are adjacent to each other in the second doped region of the second conductivity type.

[0014] The second conductivity type PC region 1 and the second conductivity type PC region 2 are located in the second conductivity type doping region 2 and are adjacent to the first conductivity type doping region 2.

[0015] A gate dielectric layer located above the first conductivity type epitaxial layer 2, the second conductivity type PC region 1, the second conductivity type PC region 2, and part of the first conductivity type doped region 2;

[0016] Gate or gate-like electrode located above the gate dielectric layer and not connected to it;

[0017] The source ohmic contact region is located above the second conductivity type PP region and part of the first conductivity type doped region 2, and is connected to the gate-like electrode.

[0018] A method for manufacturing a shunt-type SiC MOSFET structure includes the following steps:

[0019] Step 1: Form an epitaxial layer of the first conductivity type on a substrate of the first conductivity type;

[0020] Step 2: Form a second conductivity type doped region 1 in the first conductivity type epitaxial layer 1;

[0021] Step 3: Form a first conductivity type doped region in the second conductivity type doped region;

[0022] Step 4: Form a second epitaxial layer of the first conductivity type on the first epitaxial layer of the first conductivity type, on the first doped region of the second conductivity type, and on the first doped region of the first conductivity type; the second epitaxial layer of the first conductivity type and the first epitaxial layer of the first conductivity type together constitute the NE region;

[0023] Step 5: Form a second conductivity type doped region that penetrates the second epitaxial layer of the first conductivity type;

[0024] Step 6: Form a second doped region of the first conductivity type in the second conductivity type doped region;

[0025] Step 7: Form a second conductivity type PP region adjacent to the first conductivity type doped region in the second conductivity type doped region;

[0026] Step 8: Form a second conductivity type PC region 1 adjacent to the first conductivity type doped region 2 in the second conductivity type doped region 2;

[0027] Step 9: Form a second conductivity type PC region 2 adjacent to the first conductivity type PC region 2 and the first conductivity type PC region 1 in the second conductivity type doped region 2;

[0028] Step 10: A gate dielectric layer is formed on the first conductivity type epitaxial layer 2, the second conductivity type PC region 1, the second conductivity type PC region 2, and part of the first conductivity type doped region 2;

[0029] Step 11: Form a non-connected gate and gate-like electrode on the gate dielectric layer;

[0030] Step 12: Form source ohmic contact regions on the sidewall of the gate dielectric layer, the sidewall of the gate-like electrode, the second conductivity type PP region, and part of the first conductivity type doped region 2. The source ohmic contact regions are connected to the gate-like electrode.

[0031] Step 13: Form a drain ohmic contact region at the bottom of the substrate of the first conductivity type.

[0032] Beneficial effects:

[0033] The device structure disclosed in this invention enables the body diode of the shunt-type SiC MOSFET structure to enter the conduction state when the on-state current is large, thereby shunting the body diode current. That is, during freewheeling, the current not only passes through the body diode but also through the channel, thereby reducing the on-state voltage of the body diode. At the same time, since the shunt current is the majority carrier current, the hole injection current is reduced, avoiding bipolar degradation of the body diode and improving chip reliability. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a shunt-type SiC MOSFET structure according to Example 1;

[0035] Figures 2-15 This is a schematic diagram of the manufacturing process of a shunt-type SiC MOSFET structure according to Example 1;

[0036] Figure 16 This is a cross-sectional view of a shunt-type SiC MOSFET structure according to Example 1;

[0037] Wherein, 1 is a substrate of the first conductivity type, 2 is an epitaxial layer of the first conductivity type, 3 is a doped region of the second conductivity type, 4 is a doped region of the first conductivity type, 5 is an epitaxial layer of the first conductivity type, 6 is a doped region of the second conductivity type, 7 is a doped region of the first conductivity type, 8 is a PP region of the second conductivity type, 9 is a PC region of the second conductivity type, 10 is a PC region of the second conductivity type, 11 is a gate dielectric layer, 12 is a gate electrode, 13 is a gate-like electrode, 14 is a source ohmic contact region, 15 is a drain ohmic contact region, and 16 is an NE region. Detailed Implementation

[0038] The present invention will be further explained and described below with reference to the accompanying drawings and embodiments.

[0039] The embodiments are for illustrative purposes only and do not constitute a limitation on the scope of the claims. Other alternative means that can be conceived by those skilled in the art are all within the scope of the claims of this invention.

[0040] Furthermore, in the description of this invention, it should be noted that the terms "central," "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0041] Example 1

[0042] As attached Figure 1 - Appendix Figure 16 As shown, a shunt-type SiC MOSFET structure in this embodiment includes:

[0043] Drain ohmic contact area 15;

[0044] A first conductivity type substrate 1 is located on the drain ohmic contact region 15, and an NE region 16 is located on the first conductivity type substrate 1. The NE region 16 includes a first conductivity type epitaxial layer 1 2 and a first conductivity type epitaxial layer 2 5 located on the first conductivity type epitaxial layer 1 2.

[0045] The second conductivity type doped region 3 is located in the first conductivity type epitaxial layer 2, and the first conductivity type doped region 4 is located in the second conductivity type doped region 3;

[0046] The second conductive type doped region 6 extends through the first conductive type epitaxial layer 2 5, is located above the second conductive type doped region 3, and is located above the first conductive type doped region 4; the second conductive type doped region 2 7 and the second conductive type PP region 8 are located adjacent to the second conductive type doped region 2 6.

[0047] The second conductivity type PC region 9 and the second conductivity type PC region 10 are located in the second conductivity type doped region 6 and are adjacent to the first conductivity type doped region 7.

[0048] A gate dielectric layer 11 is located above the first conductivity type epitaxial layer 5, the second conductivity type PC region 9, the second conductivity type PC region 10, and part of the first conductivity type doped region 7;

[0049] A gate electrode 12 and a gate-like electrode 13 located above the gate dielectric layer 11 and not connected to each other;

[0050] The source ohmic contact region 14 is located above the second conductivity type PP region 8 and part of the first conductivity type doped region 7, and the source ohmic contact region 14 is connected to the gate-like electrode 13.

[0051] In this embodiment, the first conductivity type is N-type or P-type, and the second conductivity type is P-type or N-type.

[0052] As attached Figure 2 To be continued Figure 15 As shown, a method for manufacturing a shunt-type SiC MOSFET structure according to this embodiment includes the following steps:

[0053] Step 1: Form a first conductivity type epitaxial layer 2 on a first conductivity type substrate 1;

[0054] like Figure 2 and Figure 3 As shown, a first conductivity type epitaxial layer 2 is formed on a first conductivity type substrate 1 by epitaxial growth; the first conductivity type substrate 1 is a first conductivity type SiC substrate. The doping concentration range of the first conductivity type epitaxial layer 2 is 1E15cm⁻¹. -3 ~2E17cm -3 ;

[0055] Step 2: Form a second conductivity type doped region 3 in the first conductivity type epitaxial layer 2;

[0056] like Figure 4 As shown, ion implantation of a second conductivity type is performed in the first conductivity type epitaxial layer-2 to form a second conductivity type doped region-3. The upper surfaces of the first conductivity type epitaxial layer-2 and the second conductivity type doped region-3 are flush, and the width and thickness of the second conductivity type doped region-3 are both smaller than the width and thickness of the first conductivity type epitaxial layer-2. The thickness of the second conductivity type doped region-3 ranges from 0.3 μm to 1.5 μm, and the doping concentration ranges from 5E17 cm⁻¹. -3 ~5E18cm -3 ;

[0057] Step 3: Form a first conductivity type doped region 4 in the second conductivity type doped region 3;

[0058] like Figure 5 As shown, ion implantation of the first conductivity type is performed in the second conductivity type doped region 3 to form the first conductivity type doped region 4. The first conductivity type doped region 4 is flush with the upper surface of the second conductivity type doped region 3, and the width and thickness of the first conductivity type doped region 4 are smaller than those of the second conductivity type doped region 3. The thickness of the first conductivity type doped region 4 ranges from 0.1 μm to 1.0 μm, and the doping concentration ranges from 1E17 cm⁻¹. -3 ~2E19cm -3 ;

[0059] Step 4: A second epitaxial layer 5 of the first conductivity type is formed on the first conductivity type epitaxial layer 2, the second conductivity type doped region 3, and the first conductivity type doped region 4; the second epitaxial layer 5 of the first conductivity type and the first conductivity type epitaxial layer 2 together constitute the NE region 16.

[0060] like Figure 6 As shown, a second epitaxial layer 5 of the first conductivity type is formed by epitaxial growth on the first conductivity type epitaxial layer 2, the second conductivity type doped region 3, and the first conductivity type doped region 4. The thickness of the second epitaxial layer 5 of the first conductivity type is in the range of 0.1 μm to 1.0 μm, and the doping concentration is in the range of 1E15 cm⁻¹. -3 ~2E17cm -3 The first conductivity type epitaxial layer 5 and the first conductivity type epitaxial layer 2 are connected and together constitute the NE region 16.

[0061] Step 5: Form a second conductivity type doped region 6 that penetrates the first conductivity type epitaxial layer 5; the width of the second conductivity type doped region 6 is equal to the width of the second conductivity type doped region 3.

[0062] like Figure 7 As shown, ion implantation of a second conductivity type is performed in the first conductivity type epitaxial layer 5 to form a second conductivity type doped region 6. The second conductivity type doped region 6 penetrates the first conductivity type epitaxial layer 5, and both its upper and lower surfaces are flush with the upper and lower surfaces of the first conductivity type epitaxial layer 5. The width of the second conductivity type doped region 6 is equal to the width of the second conductivity type doped region 3. The thickness of the second conductivity type doped region 6 ranges from 0.1 μm to 1.0 μm, and the doping concentration ranges from 1E16 cm⁻¹. -3 ~1E18cm -3 ;

[0063] Step 6: Form a first conductivity type doped region 7 in the second conductivity type doped region 6; the thickness of the first conductivity type doped region 7 is less than the thickness of the second conductivity type doped region 6;

[0064] like Figure 8 As shown, ion implantation of the first conductivity type is performed in the second conductivity type doped region 6 to form the first conductivity type doped region 7; the thickness of the first conductivity type doped region 7 ranges from 0.1 μm to 1.0 μm, and the doping concentration ranges from 1E17 cm⁻¹. -3 ~2E19cm -3 The upper surface of the first conductivity type doped region 7 is flush with the upper surface of the second conductivity type doped region 6, and the width and thickness of the first conductivity type doped region 7 are smaller than the width and thickness of the second conductivity type doped region 6.

[0065] Step 7: Form a second conductivity type PP region 8 adjacent to the first conductivity type doped region 7 in the second conductivity type doped region 6;

[0066] like Figure 9 As shown, ion implantation of the second conductivity type is performed in the second conductivity type doped region 6 to form the second conductivity type PP region 8. The second conductivity type PP region 8 is adjacent to the first conductivity type doped region 7, and the two have the same thickness. The doping concentration range of the second conductivity type PP region 8 is 1E18cm. -3 ~1E20cm -3 ;

[0067] Step 8: Form a second conductivity type PC region 9 adjacent to the first conductivity type doped region 7 in the second conductivity type doped region 6;

[0068] like Figure 10 As shown, ion implantation of the second conductivity type is performed in the second conductivity type doped region 6 to form a second conductivity type PC region 9 adjacent to the first conductivity type doped region 7 and far from the second conductivity type PP region 8. The first conductivity type doped region 7 and the second conductivity type PC region 9 have the same thickness. The second conductivity type PC region 9 is connected to the first conductivity type epitaxial layer 5 in the NE region 16. The doping concentration range of the second conductivity type PC region 9 is 1E15cm. -3 ~5E16cm -3 The sum of the widths of the second conductivity type PC region 9, the second conductivity type PP region 8, and the first conductivity type doped region 7 is equal to the width of the second conductivity type doped region 6, and the length of the second conductivity type PC region 9 in the device depth direction is less than the length of the first conductivity type doped region 7.

[0069] Step 9: Form a second conductivity type PC region 10 adjacent to the first conductivity type PC region 7 and the second conductivity type PC region 9 in the second conductivity type doped region 6;

[0070] like Figure 11 As shown, ion implantation of the second conductivity type is performed in the second conductivity type doped region 6 to form a second conductivity type PC region 10 adjacent to the first conductivity type doped region 7 and the second conductivity type PC region 9, with all three having equal thickness. The second conductivity type PC region 10 is connected to the first conductivity type epitaxial layer 5 in the NE region 16; the doping concentration range of the second conductivity type PC region 10 is 5E16cm. -3 ~2E17cm -3The sum of the widths of the second conductivity type PC region 10, the second conductivity type PP region 8, and the first conductivity type doped region 7 is equal to the width of the second conductivity type doped region 6, and the sum of the lengths of the second conductivity type PC region 9 and the second conductivity type PC region 10 in the device depth direction is equal to the length of the first conductivity type doped region 7.

[0071] Step 10: A gate dielectric layer 11 is formed on the first conductivity type epitaxial layer 5, the second conductivity type PC region 9, the second conductivity type PC region 10, and a portion of the first conductivity type doped region 7.

[0072] like Figure 12 As shown, a gate dielectric layer 11 is formed on the first conductivity type epitaxial layer 5, the second conductivity type PC region 9, the second conductivity type PC region 10, and part of the first conductivity type doped region 7 by a combination of oxidation, photolithography and etching processes. The thickness of the gate dielectric layer 11 ranges from 30nm to 100nm.

[0073] Step 11: Form a non-connected gate 12 and a gate-like electrode 13 on the gate dielectric layer 11, wherein the gate 12 is located above the projection of a portion of the second conductivity type PC region 10, and the gate-like electrode 13 is located above a portion of the second conductivity type PC region 9.

[0074] like Figure 13 As shown, a polysilicon electrode is fabricated on the gate dielectric layer 11 through dielectric layer growth, photolithography, and etching processes, forming a non-connected gate 12 and a gate-like electrode 13 in one step; wherein, the gate 12 is located above the projection of a portion of the first conductivity type epitaxial layer 5, a portion of the second conductivity type PC region 10, and a portion of the first conductivity type doped region 7, and the gate-like electrode 13 is located above the projection of a portion of the first conductivity type epitaxial layer 5, a portion of the second conductivity type PC region 9, and a portion of the first conductivity type doped region 7;

[0075] Step 12: A source ohmic contact region 14 is formed on the sidewall of the gate dielectric layer 11, the sidewall of the gate-like electrode 13, the second conductivity type PP region 8, and part of the first conductivity type doped region 7. The source ohmic contact region 14 is connected to the gate-like electrode 13.

[0076] like Figure 14 As shown, a source ohmic contact region 14 is formed on the sidewall of the gate dielectric layer 11, the sidewall of the gate-like electrode 13, the second conductivity type PP region 8, and part of the first conductivity type doped region 7 through metallization and annealing processes. The source ohmic contact region 14 is connected to the gate-like electrode 13.

[0077] Step 13: Form a drain ohmic contact region 15 at the bottom of the first conductivity type substrate 1;

[0078] like Figure 15 As shown, a drain ohmic contact region 15 is formed at the bottom of the first conductivity type substrate 1 by metallization and annealing processes;

[0079] This embodiment of the SiC MOSFET structure enables the SiC MOSFET to enter the conduction state when the body diode has a large on-state current. This shunting of the body diode current means that during freewheeling, the current flows not only through the body diode but also through the channel, thereby reducing the body diode's on-state voltage. Simultaneously, since the shunted current is the majority carrier current, minority carrier injection current is reduced, preventing bipolar degradation of the body diode and improving chip reliability. The operating principle of this device is as follows:

[0080] When a positive voltage is applied to the gate 12 and the voltage is higher than the conduction threshold voltage, the surface of the second conductivity type PC region 10 is inverted to form a conductive channel, the device is turned on, and the current flow path is: drain ohmic contact region 15 → first conductivity type substrate 1 → NE region 16 → second conductivity type PC region 10 → first conductivity type doped region 7 → source ohmic contact region 14.

[0081] When the voltage applied to gate 12 is lower than the threshold voltage, the device is in the off state.

[0082] When the device is in freewheeling mode, the device channel is closed, and the current flows from the source ohmic contact region 14 to the drain ohmic contact region 15. The specific current flow path is: source ohmic contact region 14 → second conductivity type PP region 8 → second conductivity type doped region 2 6 → second conductivity type doped region 1 3 → NE region 16 → first conductivity type substrate 1 → drain ohmic contact region 15. When the freewheeling current flows through the second conductivity type doped region 6, a potential difference is generated between the second conductivity type PC region 9 and the second conductivity type PP region 8. Simultaneously, the gate-like electrode 13 in this structure is connected to the source ohmic contact region 14. Therefore, a positive voltage is generated from the gate-like electrode 13 to the second conductivity type PC region 9. When this positive voltage reaches the threshold voltage of the MOS structure formed by the gate-like electrode 13 and the second conductivity type PC region 9, the channel conducts, and the freewheeling current flows through the channel. The specific current flow path is: source ohmic contact region 14 → first conductivity type doped region 7 → second conductivity type PC region 9 → NE region 16 → first conductivity type substrate 1 → drain ohmic contact region 15. This change in the flow path causes the freewheeling current of the device to change from body diode conduction to channel conduction. Meanwhile, due to the addition of the combined structure of the second conductivity type doped region 3 and the first conductivity type doped region 4, the freewheeling current is confined in the second conductivity type doped region 6. During the flow, a larger potential difference will be generated between the second conductivity type PP region 8 and the second conductivity type PC region 9, and the channel will enter a better conduction state, with a larger proportion of the freewheeling current flowing through the channel.

[0083] In summary, when the device is blocked, the potentials of the gate 12 and the gate-like electrode 13 are the same as those of the source ohmic contact region 14, which is 0. The MOS channels of the second conductivity type PC region 9 and the second conductivity type PC region 10 are both in the off state, and the device is in the off state. When a positive voltage is applied to the gate 12, the second conductivity type PC region 10 below the gate 12 forms an inversion channel, and the device is turned on. In the freewheeling state, the current flows through the second conductivity type doped region 6, causing the voltage of the second conductivity type PC region 9 to be lower than that of the gate-like electrode 13 connected to the source ohmic contact region 14. The MOS channel of the second conductivity type PC region 9 below the gate-like electrode 13 is turned on, and the current flows.

[0084] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A shunt-type SiC MOSFET structure, characterized in that, include: Drain ohmic contact region; A first conductivity type substrate located above the drain ohmic contact region, an NE region located above the first conductivity type substrate, the NE region including a first conductivity type epitaxial layer one and a first conductivity type epitaxial layer two located above the first conductivity type epitaxial layer one; A second conductivity type doped region 1 located in a first conductivity type epitaxial layer 1, and a first conductivity type doped region 1 located in a second conductivity type doped region 1; Penetrating the second epitaxial layer of the first conductivity type, located above the first doped region of the second conductivity type, and the second doped region of the first conductivity type located above the first doped region of the first conductivity type; the second doped region of the first conductivity type and the second PP region of the second conductivity type are adjacent to each other in the second doped region of the second conductivity type. Located within the second conductivity type doped region two, adjacent to the first conductivity type doped region two, are the second conductivity type PC region one and the second conductivity type PC region two; the doping concentration range of the second conductivity type PC region one is 1E15cm⁻¹. -3 ~5E16cm -3 The doping concentration range of the second conductivity type PC region is 5E16cm⁻¹. -3 ~2E17cm -3 ; A gate dielectric layer located above the first conductivity type epitaxial layer 2, the second conductivity type PC region 1, the second conductivity type PC region 2, and part of the first conductivity type doped region 2; Gate or gate-like electrode located above the gate dielectric layer and not connected to it; The gate is located above the second projection of a portion of the second conductivity type PC region, and the gate-like electrode is located above the first projection of a portion of the second conductivity type PC region. The source ohmic contact region is located above the second conductivity type PP region and part of the first conductivity type doped region 2, and is connected to the gate-like electrode.

2. The shunt-type SiC MOSFET structure according to claim 1, characterized in that: The sum of the widths of the second conductivity type PC region 1, the second conductivity type PP region, and the first conductivity type doped region 2 is equal to the width of the second conductivity type doped region 2. The sum of the lengths of the second conductivity type PC region 1 and the second conductivity type PC region 2 in the device depth direction is equal to the length of the first conductivity type doped region 2.

3. The shunt-type SiC MOSFET structure according to claim 1, characterized in that: The first conductivity type doped region 2 and the second conductivity type PC region 1 have the same thickness, and the second conductivity type PC region 1 is connected to the first conductivity type epitaxial layer 2 in the NE region.

4. The shunt-type SiC MOSFET structure according to claim 1, characterized in that: The width of the second conductivity type doped region is equal to the width of the first conductivity type doped region, and the thickness of the second conductivity type doped region is less than the thickness of the second conductivity type doped region.

5. The shunt-type SiC MOSFET structure according to claim 1, characterized in that: The width and thickness of the first doped region of the second conductivity type are both smaller than the width and thickness of the first epitaxial layer of the first conductivity type; the width and thickness of the first doped region of the first conductivity type are both smaller than the width and thickness of the first doped region of the second conductivity type.

6. The shunt-type SiC MOSFET structure according to claim 1, characterized in that: The thickness of the second conductivity type doped region ranges from 0.3 μm to 1.5 μm, and the doping concentration ranges from 5E17 cm⁻¹. -3 ~5E18cm -3 The thickness of the first conductivity type doped region ranges from 0.1 μm to 1.0 μm, and the doping concentration ranges from 1E17 cm⁻¹. -3 ~2E19cm -3 The thickness of the second epitaxial layer of the first conductivity type ranges from 0.1 μm to 1.0 μm, and the doping concentration ranges from 1E15 cm⁻¹. -3 ~2E17cm -3 .

7. A shunt-type SiC MOSFET structure according to claim 1, characterized in that: The doping concentration range of the second conductivity type doped region is 1E16cm. -3 ~1E18cm -3 The doping concentration range of the second doped region of the first conductivity type is 1E17cm. -3 ~2E19cm -3 The doping concentration range of the PP region for the second conductivity type is 1E18cm. -3 ~1E20cm -3 .

8. A method for manufacturing a shunt-type SiC MOSFET structure, characterized in that, Includes the following steps: Step 1: Form an epitaxial layer of the first conductivity type on a substrate of the first conductivity type; Step 2: Form a second conductivity type doped region 1 in the first conductivity type epitaxial layer 1; Step 3: Form a first conductivity type doped region in the second conductivity type doped region; Step 4: Form a second epitaxial layer of the first conductivity type on the first epitaxial layer of the first conductivity type, on the first doped region of the second conductivity type, and on the first doped region of the first conductivity type; the second epitaxial layer of the first conductivity type and the first epitaxial layer of the first conductivity type together constitute the NE region; Step 5: Form a second conductivity type doped region that penetrates the second epitaxial layer of the first conductivity type; Step 6: Form a second doped region of the first conductivity type in the second conductivity type doped region; Step 7: Form a second conductivity type PP region adjacent to the first conductivity type doped region in the second conductivity type doped region; Step 8: Form a second conductivity type PC region 1 adjacent to the first conductivity type doped region 2 in the second conductivity type doped region 2; the doping concentration range of the second conductivity type PC region 1 is 1E15cm. -3 ~5E16cm -3 ; Step 9: Form a second conductivity type PC region (PC region 2) adjacent to the first conductivity type PC region (PC region 2) and the first conductivity type PC region (PC region 1) in the second conductivity type doped region (PC region 2); the doping concentration range of the second conductivity type PC region (PC region 2) is 5E16cm. -3 ~2E17cm -3 ; Step 10: A gate dielectric layer is formed on the first conductivity type epitaxial layer 2, the second conductivity type PC region 1, the second conductivity type PC region 2, and part of the first conductivity type doped region 2; Step 11: Form a non-connected gate and gate-like electrode on the gate dielectric layer; the gate is located above the second projection of a portion of the second conductivity type PC region, and the gate-like electrode is located above the first projection of a portion of the second conductivity type PC region; Step 12: Form source ohmic contact regions on the sidewall of the gate dielectric layer, the sidewall of the gate-like electrode, the second conductivity type PP region, and part of the first conductivity type doped region 2. The source ohmic contact regions are connected to the gate-like electrode. Step 13: Form a drain ohmic contact region at the bottom of the substrate of the first conductivity type.

9. The method for manufacturing a shunt-type SiC MOSFET structure according to claim 8, characterized in that: In step 11, polysilicon electrodes are fabricated on the gate dielectric layer through dielectric layer growth, photolithography, and etching processes, forming non-connected gate and gate-like electrodes in one step.

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