A low on-resistance SiC MOSFET termination structure and its fabrication process

Abstract

This invention relates to the field of MOS semiconductor technology and discloses a low on-resistance SiC MOSFET termination structure. The SiC MOSFET termination structure consists of several parallel MOS cells. Each MOS cell includes a drain, a semiconductor epitaxial layer, a source, a gate, and a gate oxide layer. The semiconductor epitaxial layer, from bottom to top, includes an N-substrate layer, an N-drift layer, a P-well layer, and an N-well layer. A P+ layer is provided on both sides of the P-well layer and the N-well layer in a single MOS cell. An N-doped layer is formed in the semiconductor epitaxial layer of a single MOS cell through ion implantation. This N-doped layer is located below and in contact with the P-well layer. This invention creates a vertical low-resistance path by adding a N-doped layer below the P-well layer. Combined with the disruption of the gate electric field uniformity in the conducting P-region, it weakens the gate's suppression of drain charge diffusion, resulting in a significant reduction in on-resistance compared to traditional structures, and consequently a significant increase in on-current.

Description

Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and in particular to a low on-resistance SiC MOSFET termination structure and its fabrication process. Background Technology

[0002] Traditional structures require thickening the drift layer or reducing its doping concentration to meet high voltage requirements, resulting in a significant increase in on-resistance; simultaneously, a uniform electric field below the gate suppresses the diffusion of drain charge to the source (see...). Figure 6 The results in A further limit the current capability; in addition, the concentrated electric field in the terminal area is prone to local breakdown, forcing the design to sacrifice resistance performance to ensure breakdown voltage reliability. Although attempts have been made to reduce resistance by injecting into the JFET region or thinning the epitaxial layer, these have exacerbated the problems of breakdown voltage degradation, process complexity and cost increase, making it difficult to meet the requirements of high performance and large-scale mass production.

[0003] An existing patent discloses a SiC-based MOSFET device with low on-resistance and its fabrication method (publication number CN115117145A). The technology disclosed in this patent has the following problems:

[0004] 1. The problem of gate electric field suppression remains unresolved: While reducing the drift region resistance through segmented doped drift layers (highly doped nx layer + low-doped n- layer), a structure similar to a "conduction P-region" is not introduced below the gate, thus failing to disrupt the gate electric field uniformity (see...). Figure 6 A) This results in the drainage charge diffusion still being suppressed, limiting the increase in conduction current.

[0005] 2. The passive nature of terminal breakdown voltage design: It relies on the coupling effect between the P well region and the low-doped drift layer to optimize the electric field (such as shielding gate dielectric), but lacks active lateral electric field modulation structures (such as side P region, covering substrate layer), resulting in insufficient edge electric field peak suppression capability and a high risk of local breakdown. Summary of the Invention

[0006] This invention provides a low on-resistance SiC MOSFET termination structure and its fabrication process to solve existing technical problems, thereby addressing the issue of uniform electric field below the gate suppressing the diffusion of drain charge to the source.

[0007] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a low on-resistance SiC MOSFET termination structure is provided. The SiC MOSFET termination structure is composed of a plurality of parallel MOS cells. Each MOS cell includes a drain, a semiconductor epitaxial layer, a source, a gate, and a gate oxide layer. The semiconductor epitaxial layer includes, from bottom to top, an N-substrate layer, an N-drift layer, a P-well layer, and an N-well layer. In a single MOS cell, P+ layers are provided on both sides of the P-well layer and the N-well layer. A doped N- layer is formed in the semiconductor epitaxial layer of a single MOS cell by ion implantation. The doped N- layer is located below the P-well layer and in contact with the P-well layer.

[0008] A conductive P-region is provided below the gate, and the upper and lower ends of the conductive P-region are in contact only with the gate and the N-drift layer, respectively.

[0009] Furthermore, the doped N-layer is located inside the N-drift layer.

[0010] Furthermore, the doped N-layer also includes a connected N-layer, the bottom end of which is in contact with the N-substrate layer.

[0011] Furthermore, the conductive P-region also includes two side P-regions, both of which are located in the region between the connected N-layers.

[0012] Furthermore, the N substrate layer also includes an intermediate substrate layer and a through substrate layer.

[0013] Furthermore, the top of the through-substrate layer is in contact with the P+ layer, the P-well layer, and the doped N- layer, and the N-drift layer is located between the intermediate substrate layer and the gate.

[0014] Furthermore, the N substrate layer also includes a cover substrate layer, and the N drift layer also includes a central drift layer. The top of the cover substrate layer is in contact with the P+ layer, the P-well layer, the doped N- layer, and the central drift layer.

[0015] Furthermore, the centrally drifted layer is located in the region between two adjacent doped N-layers.

[0016] A fabrication process for a low on-resistance SiC MOSFET termination structure specifically includes:

[0017] S1. An N-drift layer is epitaxially grown on the N-substrate layer;

[0018] S2. An N-doped N-layer is formed in the N-drift layer by ion implantation, the N-doped N-layer being located below and in contact with the subsequent P-well layer;

[0019] S3. A P-well layer is formed above the doped N- layer by ion implantation, and P+ layers are formed by implantation on both sides of the P-well layer;

[0020] S4. A conducting P-region is injected in the region below the gate, so that its upper and lower ends only contact the gate and the N-drift layer, respectively.

[0021] S5. An overlay substrate is formed by ion implantation on both sides of the N drift layer to make the ion concentration consistent with the ion concentration of the N substrate layer. The overlay substrate is in contact with the P+ layer, the P well layer and the doped N- layer.

[0022] S6. An N+ well layer is formed within the P well layer by ion implantation;

[0023] S7. A gate oxide layer is grown on the semiconductor surface, and metal is deposited above the conducting P region to form a gate.

[0024] S8. Fabricate the drain on the back side of the device and the source on the front side of the device, so that the source contacts the P+ layer and the N+ well layer.

[0025] This invention provides a low on-resistance SiC MOSFET termination structure and its fabrication process. Compared with existing technologies, the advantages achieved by this method are:

[0026] 1. This invention forms a vertical low-resistance path by adding a doped N-layer below the P-well layer, and by combining the disruption of the gate electric field uniformity in the conducting P-region to weaken the gate's suppression of drain charge diffusion, the on-resistance is significantly reduced compared to the traditional structure, thereby significantly increasing the on-current.

[0027] 2. This invention isolates the electric field interference of adjacent cells by the side P region, and coordinates the terminal electric field by the covering substrate layer and the central drift layer to resolve the contradiction between low resistance and high withstand voltage, thereby increasing the breakdown voltage, reducing the peak value of the edge electric field, and avoiding the risk of local breakdown.

[0028] 3. This invention uses ion implantation technology to precisely locate key regions such as the doped N-layer and the conductive P-region, minimizing the deviation in doping concentration; and it is fully compatible with standard SiC manufacturing processes, eliminating the need for additional photolithography steps, thereby significantly reducing manufacturing costs.

[0029] 4. This invention shortens the substrate current path by penetrating the substrate layer, and reduces the contact resistance by using a source double-contact P+ layer and N+ well layer; furthermore, the gate oxide interface state density can be reduced, and combined with the electric field modulation effect of the conducting P region, the switching speed is greatly improved. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the structure of Embodiment 1 of the present invention;

[0031] Figure 2 This is a schematic diagram of the structure of Embodiment 2 of the present invention;

[0032] Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention;

[0033] Figure 4 This is a schematic diagram of the structure of Embodiment 4 of the present invention;

[0034] Figure 5 This is a schematic diagram of the structure of Embodiment 5 of the present invention;

[0035] Figure 6 In the diagram, A represents the electric field state of an existing SiC MOSFET structure. Figure 6 B in the diagram represents the electric field state of the structure in Example 1.

[0036] In the figure: 1. Drain; 2. Source; 3. Gate; 4. Gate oxide layer; 5. N-substrate layer; 6. N-drift layer; 7. P+ layer; 8. N-well layer; 9. P-well layer; 10. Doped N- layer; 11. Conductive P-region; 51. Intermediate substrate layer; 52. Through substrate layer; 53. Cover substrate layer; 61. Central drift layer; 101. Through N- layer; 1101. Side P-region. Detailed Implementation

[0037] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0038] The fabrication process for low on-resistance SiC MOSFET termination structures specifically includes:

[0039] Step 1: Epitaxially grow an N-drift layer 6 on the N-substrate layer 5.

[0040] By precisely controlling epitaxial growth parameters (such as doping concentration and thickness), a uniform N-drift layer 6 is formed, providing an ideal substrate for subsequent ion implantation and ensuring that the drift layer has both high voltage withstand capability and low resistance characteristics, laying the foundation for device performance.

[0041] Step 2: Form a doped N-layer 10 in the N-drift layer 6 by ion implantation. The doped N-layer 10 is located below and in contact with the subsequent P-well layer 9.

[0042] A high-concentration doped region is formed directly below the P-well layer 9, establishing a vertical low-resistance path, which significantly reduces the drift layer resistance (in traditional structures, current needs to flow through a high-resistance drift layer), while precise positioning avoids affecting the device's breakdown voltage capability.

[0043] Step 3: Form a P-well layer 9 above the doped N- layer 10 by ion implantation, and form a P+ layer 7 by implantation on both sides of the P-well layer 9.

[0044] The P-well layer 9 is in direct contact with the doped N-layer 10, optimizing the carrier transport path below the channel; the P+ layer 7 enhances the contact of the body region, reduces the source contact resistance and suppresses parasitic transistor effects, thereby improving device reliability.

[0045] Step 4: Inject and form a conducting P region 11 in the region below the gate 3, so that its upper and lower ends only contact the gate 3 and the N drift layer 6 respectively.

[0046] By turning on P region 11, the gate electric field uniformity is disrupted (see...). Figure 6 (In comparison), it weakens the gate's suppression of drain charge diffusion, increases the on-current, and its independent design avoids the introduction of additional parasitic capacitance.

[0047] Step 5: An overlay substrate 53 is formed by ion implantation on both sides of the N drift layer 6 to make the ion concentration consistent with that of the N substrate layer 5. The overlay substrate 53 is in contact with the P+ layer 7, the P well layer 9, and the doped N- layer 10.

[0048] Extending the high-concentration substrate to the surface reduces the resistance in the edge region. At the same time, connecting it with the P+ layer 7 and the doped N- layer 10 optimizes the terminal electric field distribution and improves the withstand voltage reliability.

[0049] Step 6: Form an N+ well layer 8 within the P well layer 9 by ion implantation.

[0050] Precise control of N+ implantation depth and concentration forms a low-resistance source region, which together with P-well layer 9 constitutes a highly efficient conductive channel, reducing channel resistance, and works with P+ layer 7 to achieve dual-path contact of the source.

[0051] Step 7: Grow a gate oxide layer 4 on the semiconductor surface and deposit metal over the conducting P region 11 to form a gate 3.

[0052] Gate metal is deposited directly above the P-region 11 to enhance gate control capability by utilizing its electric field modulation effect; high-quality gate oxide layer 4 reduces interface state density and improves channel mobility and switching speed.

[0053] Step 8: Fabricate drain 1 on the back side of the device and source 2 on the front side of the device, so that source 2 contacts P+ layer 7 and N+ well layer 8.

[0054] Example 1

[0055] like Figure 1 , 6As shown, according to one aspect of the present invention, a low on-resistance SiC MOSFET termination structure is provided. The SiC MOSFET termination structure is composed of a plurality of parallel MOS cells. The MOS cells include a drain 1, a semiconductor epitaxial layer, a source 2, a gate 3, and a gate oxide layer 4. The semiconductor epitaxial layer includes, from bottom to top, an N substrate layer 5, an N drift layer 6, a P well layer 9, and an N well layer 8. In a single MOS cell, P+ layers 7 are provided on both sides of the P well layer 9 and the N well layer 8. The characteristic feature is that a doped N- layer 10 is formed in the semiconductor epitaxial layer of a single MOS cell by ion implantation. The doped N- layer 10 is located below the P well layer 9 and is in contact with the P well layer 9.

[0056] A conductive P-region 11 is provided below the gate 3. The upper and lower ends of this conductive P-region 11 are in contact only with the gate 3 and the N-drift layer 6, respectively. This conductive P-region 11 is used to disrupt the stable gate electric field. Because the gate electric field in conventional devices inhibits the diffusion rate of charge from the drain 1 to the source 2, it reduces the conduction current between the drain and source. Figure 6 As shown in Figure A, the gate electric field is more directionally uniform at this point, thus its influence is greater. However, adding the conducting P-region 11 can disrupt the stable uniformity of the gate electric field, thereby significantly reducing the influence of the gate electric field. Figure 6 As shown in B in the diagram.

[0057] By adding a conductive P-region 11 below the gate 3, its upper and lower ends only contact the gate and the N-drift layer 6. This structure disrupts the stability of the gate electric field. Figure 6 The electric field distribution between A and B weakens the inhibitory effect of the gate electric field on the diffusion of charge from drain 1 to source 2, thereby reducing the on-resistance and improving the current capability.

[0058] Example 2

[0059] like Figure 2 As shown, the doped N-layer 10 is located inside the N-drift layer 6. The doped N-layer 10 also includes a connected N-layer 101, the bottom end of which is in contact with the N-substrate layer 5.

[0060] An N-layer 101 is extended and connected to the bottom of the doped N-layer 10, making it in direct contact with the N-substrate layer 5. This design forms a low-resistance vertical path from the substrate to below the P-well 9, utilizing the heavy doping characteristics to reduce the drift layer resistance and further reduce the overall on-resistance.

[0061] Example 3

[0062] like Figure 3As shown, the doped N-layer 10 is located inside the N-drift layer 6. The doped N-layer 10 also includes a connected N-layer 101, the bottom end of which is in contact with the N-substrate layer 5. The conductive P-region 11 also includes two side P-regions 1101, both of which are located in the region between the connected N-layer 101.

[0063] Two side P regions 1101 are added between the connected N-layers 101. The side P regions not only isolate the doped N-layers of adjacent cells to avoid electric field interference, but also optimize the depletion layer expansion of the P-well 9, enhance the lateral breakdown voltage capability, and maintain low on-resistance characteristics.

[0064] Example 4

[0065] like Figure 4 As shown, the N substrate layer 5 also includes an intermediate substrate layer 51 and a through substrate layer 52. The top end of the through substrate layer 52 is in contact with the P+ layer 7, the P-well layer 9, and the doped N- layer 10, and the N-drift layer 6 is located between the intermediate substrate layer 51 and the gate 3.

[0066] The N-substrate layer 5 is divided into an intermediate substrate layer 51 and a through substrate layer 52, the latter of which is connected to the P+ layer 7, the P-well layer 9, and the doped N- layer 10 at its top. The through substrate layer forms a vertical conductive channel, shortening the current path and reducing the substrate resistance; the intermediate substrate layer supports the voltage withstand requirements of the drift layer 6, balancing the conduction and blocking performance.

[0067] Example 5

[0068] like Figure 5 As shown, the N substrate layer 5 further includes a cover substrate layer 53, and the N drift layer 6 further includes a central drift layer 61. The top of the cover substrate layer 53 is in contact with the P+ layer 7, the P-well layer 9, the doped N- layer 10, and the central drift layer 61. The central drift layer 61 is located in the region between two adjacent doped N- layers 10.

[0069] A cover substrate layer 53 is formed on both sides of the drift layer 6 by ion implantation, and the top of the cover substrate layer 53 is connected to the P+ layer 7, the P-well layer 9, the doped N- layer 10, and the central drift layer 61. The central drift layer 61 is located between adjacent heavily doped regions and works with the cover substrate layer to optimize the edge electric field distribution, improve the terminal breakdown voltage reliability, and maintain low resistance characteristics.

[0070] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A low on-resistance SiC MOSFET termination structure, wherein the SiC MOSFET termination structure is composed of a plurality of parallel MOS cells, wherein each MOS cell includes a drain (1), a semiconductor epitaxial layer, a source (2), a gate (3), and a gate oxide layer (4), wherein the semiconductor epitaxial layer includes, from bottom to top, an N substrate layer (5), an N drift layer (6), a P well layer (9), and an N well layer (8), wherein a P+ layer (7) is provided on both sides of the P well layer (9) and the N well layer (8) in a single MOS cell, characterized in that: A doped N-layer (10) is formed in the semiconductor epitaxial layer of a single MOS cell by ion implantation. The doped N-layer (10) is located below the P-well layer (9) and is in contact with the P-well layer (9). The gate (3) is provided with a conductive P region (11) below it. The upper and lower ends of the conductive P region (11) are in contact with the gate (3) and the N drift layer (6) respectively. The N substrate layer (5) further includes a cover substrate layer (53), and the N drift layer (6) further includes a central drift layer (61). The top of the cover substrate layer (53) is in contact with the P+ layer (7), the P well layer (9), the doped N- layer (10), and the central drift layer (61). The central drift layer (61) is located in the region between two adjacent doped N-layers (10).

2. The low on-resistance SiC MOSFET termination structure according to claim 1, characterized in that: The doped N-layer (10) is located inside the N-drift layer (6).

3. The low on-resistance SiC MOSFET termination structure according to claim 2, characterized in that: The doped N-layer (10) further includes a connected N-layer (101), the bottom end of which is in contact with the N-substrate layer (5).

4. The low on-resistance SiC MOSFET termination structure according to claim 3, characterized in that: The conductive P-region (11) also includes two side P-regions (1101), both of which are located in the region between the connected N-layers (101).

5. The low on-resistance SiC MOSFET termination structure according to claim 1, characterized in that: The N substrate layer (5) also includes an intermediate substrate layer (51) and a through substrate layer (52).

6. The low on-resistance SiC MOSFET termination structure according to claim 5, characterized in that: The top of the through substrate layer (52) is in contact with the P+ layer (7), the P well layer (9), and the doped N- layer (10), and the N drift layer (6) is located between the intermediate substrate layer (51) and the gate (3).

7. A fabrication process for a low on-resistance SiC MOSFET termination structure, characterized in that, The fabrication process of the low on-resistance SiC MOSFET termination structure, applicable to any one of claims 1, specifically includes: S1. An N drift layer (6) is epitaxially grown on the N substrate layer (5). S2. A doped N-layer (10) is formed in the N-drift layer (6) by ion implantation. The doped N-layer (10) is located below and in contact with the subsequent P-well layer (9). S3. A P-well layer (9) is formed above the doped N- layer (10) by ion implantation, and a P+ layer (7) is formed on both sides of the P-well layer (9). S4. A conducting P region (11) is injected in the region below the gate (3) so that its upper and lower ends only contact the gate (3) and the N drift layer (6) respectively. S5. A cover substrate layer (53) is formed by ion implantation on both sides of the N drift layer (6) to make the ion concentration consistent with the ion concentration of the N substrate layer (5). The cover substrate layer (53) is in contact with the P+ layer (7), the P well layer (9), and the doped N- layer (10). S6. An N+ well layer (8) is formed in the P well layer (9) by ion implantation. S7. A gate oxide layer (4) is grown on the semiconductor surface, and a metal is deposited above the conducting P region (11) to form a gate (3). S8. A drain (1) is fabricated on the back side of the device, and a source (2) is fabricated on the front side of the device, so that the source (2) contacts the P+ layer (7) and the N+ well layer (8).

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