A self-aligned dual gate mosfet and its manufacturing process

Abstract

The application relates to the field of MOS semiconductor technology, and discloses a self-aligned double-gate MOSFET which is composed of a plurality of MOS cells connected in parallel, a single MOS cell sequentially comprises a drain, a semiconductor epitaxial layer, a gate and a source from bottom to top, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P well layer and a P+ layer, a P-type doped area is formed in the inside of the N drift layer and below the gate through ion implantation, and the P-type doped area is in ohmic contact with the gate. The application constructs the P-type doped area below the gate and realizes ohmic contact, so that the gate contact resistance is remarkably reduced; meanwhile, a self-aligned N-type doped gate is deposited in the P-type area, so that the gate control structure is accurately aligned with the channel position. The design not only improves the control ability of the gate on the channel carriers, but also simultaneously reduces the conduction loss and enhances the switching response speed.

Description

Technical Field

[0001] This invention relates to the field of MOS semiconductor technology, and in particular to a self-aligned dual-gate MOSFET and its manufacturing process. Background Technology

[0002] Current high-voltage MOSFET devices often face challenges in achieving high withstand voltage and low conduction losses, including insufficient gate control capability, uneven electric field distribution in the drift region, and complex manufacturing processes. Traditional structures suffer from increased switching losses due to high gate contact resistance, and the lack of effective charge balance design in the drift region easily leads to local electric field accumulation, reducing breakdown voltage. Furthermore, existing dual-gate processes rely on multiple photolithography alignments, which can introduce overlay errors, limiting device performance and increasing manufacturing costs.

[0003] Existing patents disclose a self-aligned dual-trench MOSFET structure and its manufacturing method (publication number CN115513288A). After forming a first semiconductor layer of a first conductivity type, a body layer of a second conductivity type, and a source layer of a first conductivity type on a substrate, different etching selectivity ratios between a first to a fourth hard mask are used in combination with sidewall technology to form an array of self-aligned gate trenches and source trenches in the first semiconductor layer in an alternating manner. This existing patent relies on trench sidewall technology to achieve gate / source trench self-alignment. Although this reduces photolithography steps, it does not optimize the gate contact resistance and electric field distribution, resulting in high switching losses and limited voltage withstand capability. Summary of the Invention

[0004] This invention provides a self-aligned dual-gate MOSFET and its manufacturing process to solve existing technical problems, thereby addressing the issue that prior art cannot simultaneously achieve low loss, high voltage withstand capability, and high frequency response.

[0005] To solve the above-mentioned technical problems, according to one aspect of the present invention, more specifically, a self-aligned dual-gate MOSFET is provided, which is composed of a plurality of MOS cells connected in parallel. Each MOS cell includes, from bottom to top, a drain, a semiconductor epitaxial layer, a gate, and a source. The semiconductor epitaxial layer includes an N-substrate layer, an N-drift layer, an N-well layer, a P-well layer, and a P+ layer. A P-type doped region is formed inside the N-drift layer and below the gate by ion implantation. The P-type doped region is in ohmic contact with the gate.

[0006] The P-type doped region contains several N-type doped gates deposited side by side.

[0007] Furthermore, a heavily doped N+ layer is formed inside the N drift layer through ion implantation.

[0008] Furthermore, the cross-sectional profile of the heavily doped N+ layer is U-shaped, and the two ends of the heavily doped N+ layer are in contact with the P-well layers on both sides.

[0009] Furthermore, the N-drift layer also includes a semi-circular drift layer, which is located below the P-well layer and in contact with the P-well layer.

[0010] Furthermore, a semi-circular P- layer is provided inside the N-drift layer and below the P-well layer and P+ layer, and the top of the semi-circular P- layer is in direct contact with both the P-well layer and P+ layer.

[0011] Furthermore, inside the N-drift layer and below the P-well layer, there are several P-type doped gates arranged side by side, with the top of the P-type doped gates in direct contact with the P-well layer.

[0012] Furthermore, the P-type doped gate is located inside the semi-circular P-layer.

[0013] A manufacturing process for a self-aligned dual-gate MOSFET specifically includes:

[0014] S1. Provide an N-type substrate and epitaxially grow an N-drift layer on its surface;

[0015] S2. Through photolithography and ion implantation processes, a P-type doped region, a semi-circular P-layer, and a P-type doped gate are formed in the N-drift layer, wherein the semi-circular P-layer is located below a predetermined region of the P-well layer, and the P-type doped gate is embedded in the semi-circular P-layer.

[0016] S3. Epitaxially grow an N-well layer on the surface of the N-drift layer;

[0017] S4. A P-well layer and a P+ layer are sequentially formed on the N-well layer, and a groove is made above the semi-circular P- layer by photolithography and etching processes to expose the top of the P-type doped gate.

[0018] S5. Deposit an N-type doped gate inside the P-type doped region to self-align it with the gate position;

[0019] S6. Sequentially deposit the drain, source, and gate metal layers to complete the ohmic contact and interconnection.

[0020] Furthermore, in step S2, the ion implantation energy of the P-type doped region is 50-200 keV; the implantation angle of the semi-circular P-layer is 7°-30° to achieve lateral diffusion and contact with the bottom of the P-well layer.

[0021] The present invention provides a self-aligned dual-gate MOSFET and its manufacturing process. Compared with the prior art, the advantages achieved by this method are as follows:

[0022] 1. This invention significantly reduces gate contact resistance by constructing a P-type doped region below the gate and achieving an ohmic contact; simultaneously, a self-aligned N-type doped gate is deposited within the P-type region, enabling precise alignment of the gate control structure with the channel position. This design not only enhances the gate's control over channel carriers but also simultaneously reduces conduction losses and improves switching response speed.

[0023] 2. This invention employs a U-shaped heavily doped N+ layer that penetrates the N drift layer and connects to the P-well layers on both sides, forming a low-resistance conductive path. Its unique U-shaped cross-section design expands the carrier flow area, effectively suppressing the parasitic JFET effect, thereby significantly improving the device's conduction characteristics and enhancing its current carrying capacity.

[0024] 3. This invention optimizes the longitudinal and lateral electric field distribution by introducing a semi-circular drift layer and a semi-circular P-layer, resulting in a more uniform expansion of the depletion region. This structure effectively alleviates the electric field accumulation phenomenon at the device edge, significantly improves the breakdown voltage and avalanche withstand capability, while reducing the risk of leakage current and ensuring reliability under high-voltage conditions.

[0025] 4. This invention features a vertically penetrating P-type doped gate beneath the P-well layer, forming a high-speed carrier extraction channel. This structure accelerates hole extraction during the turn-off phase, significantly shortening switching time and reducing switching losses, making it particularly suitable for high-frequency applications.

[0026] 5. The manufacturing process of this invention employs a triple-mask integrated technology to simultaneously form multiple types of doped regions, reducing photolithography steps; combined with tilted implantation and self-aligned deposition processes, it achieves precise control of key structures. This process not only improves the charge balance accuracy of the superjunction but also significantly reduces parameter dispersion, enhancing mass production yield and device consistency.

[0027] 6. In this invention, the nested design of the semi-circular P-layer and the internal P-type doped gate forms a synergistic optimization: the semi-circular layer improves the uniformity of the longitudinal electric field, and the P-type gate provides a lateral carrier pathway. The combination of the two effectively reduces the dynamic resistance, and the exposed contact ends through slotting improve the reliability of the ohmic connection, further enhancing the anti-latch-up capability. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of Embodiment 1 of the present invention;

[0029] Figure 2 This is a schematic diagram of Embodiment 2 of the present invention;

[0030] Figure 3 This is a schematic diagram of Embodiment 3 of the present invention;

[0031] Figure 4 This is a schematic diagram of Embodiment 4 of the present invention;

[0032] Figure 5This is a schematic diagram of Embodiment 5 of the present invention;

[0033] Figure 6 This is a schematic diagram of Embodiment Six of the present invention.

[0034] In the figure: 1. Drain; 2. Source; 3. Gate; 4. N-substrate layer; 5. N-drift layer; 6. N-well layer; 7. P-well layer; 8. P+ layer; 9. P-type doped region; 10. N-type doped gate; 11. Heavily doped N+ layer; 12. Semicircular P- layer; 13. P-type doped gate; 51. Semicircular drift layer. Detailed Implementation

[0035] To make the technical solution of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] like Figure 6 As shown, a manufacturing process for a self-aligned dual-gate MOSFET specifically includes:

[0037] Step 1: Provide an N-type substrate 4 and epitaxially grow an N-drift layer 5 on its surface. By selecting an N-type single-crystal silicon substrate with low defect density, a perfect lattice-matched foundation is provided for subsequent epitaxial layers. The N-drift layer 5 with controllable thickness (concentration gradient ≤ ±5%) is grown at 1050℃ using the hydrogen-reduction silane method, which improves the breakdown voltage uniformity to over 98% while avoiding the leakage risk caused by lattice mismatch.

[0038] Step 2: Through photolithography and ion implantation processes, a P-type doped region 9, a semi-circular P-layer 12, and a P-type doped gate 13 are formed in the N-drift layer 5. The semi-circular P-layer 12 is located below the predetermined region of the P-well layer, and the P-type doped gate 13 is embedded in the semi-circular P-layer 12. In step S2, the ion implantation energy of the P-type doped region 9 is 50-200 keV. The implantation angle of the semi-circular P-layer 12 is 7°-30° to achieve lateral diffusion and contact with the bottom of the P-well layer 7.

[0039] A triple-mask integrated process is used to simultaneously form three P-type structures, reducing photolithography steps by 30%. The vertical junction depth of the P-type doped region 9 is controlled (0.5-2μm) by energy gradient implantation, and the lateral diffusion of the semi-circular P-layer 12 is achieved by 7°-30° tilt implantation (width deviation <0.1μm), reducing the device parameter dispersion to within 5% and significantly improving the mass production yield.

[0040] Step 3: Epitaxially grow an N-well layer 6 on the surface of the N-drift layer 5; epitaxially grow a high-purity N-well layer 6 under low-temperature (900℃) and low-pressure (100Torr) conditions. This process suppresses the re-diffusion of impurities in the P-type region 9 caused by high temperature, maintains the doping steepness (transition region <0.05μm), ensures that the superjunction charge balance accuracy reaches more than 99.3%, and reduces the leakage current by an order of magnitude.

[0041] Step 4: P-well layer 7 and P+ layer 8 are sequentially formed on N-well layer 6, and a groove is made above the semi-circular P- layer 12 by photolithography and etching process to expose the top of P-type doped gate 13.

[0042] A concentration gradient P-well layer 7 is formed by boron / indium co-implantation, and a trench is created above the P-layer 12 by reactive ion etching. The trench depth is precisely controlled within ±5nm, accurately exposing the top of the P-type doped gate 13, thereby reducing the trap density at the contact interface and decreasing the contact resistance by 40%.

[0043] Step 5: Deposit an N-type doped gate 10 inside the P-type doped region 9, and align it with the gate 3.

[0044] An N-type doped gate 10 was selectively grown in the P-type doped region 9 using LPCVD, and a self-aligned process was used to ensure that the positional deviation between the gate 3 and the channel was less than 50 nm. This step eliminates the overlay error of traditional photolithography, increases the transconductance by 25%, and shortens the switching delay to the 5 ns level.

[0045] Step 6: Sequentially deposit the drain 1, source 2 and gate 3 metal layers to complete the ohmic contact and interconnection.

[0046] A low-resistivity ohmic contact is formed by depositing a multilayer Ti / TiN / W metal (thickness ratio 100:50:200nm) combined with rapid thermal annealing (650℃ / 30s). The thermal stability is improved to over 300℃, resulting in a 35% increase in device power density and a 3x extension in lifetime.

[0047] Example 1

[0048] like Figure 1 As shown, according to one aspect of the present invention, a self-aligned dual-gate MOSFET is provided, which is composed of a plurality of MOS cells connected in parallel. Each MOS cell includes, from bottom to top, a drain 1, a semiconductor epitaxial layer, a gate 3 and a source 2. The semiconductor epitaxial layer includes an N substrate layer 4, an N drift layer 5, an N well layer 6, a P well layer 7 and a P+ layer 8. The feature is that: a P-type doped region 9 is formed inside the N drift layer 5 and below the gate 3 by ion implantation. The P-type doped region 9 is in ohmic contact with the gate 3. A plurality of N-type doped gates 10 are deposited inside the P-type doped region 9.

[0049] By forming an ohmic contact between the P-type doped region 9 and the gate 3, the gate contact resistance is significantly reduced. Simultaneously, an N-type doped gate 10 is deposited within the P-type region, and a self-aligned process ensures the N-type gate is precisely positioned below the channel, enhancing gate control capability. This structure maintains low gate resistance while improving switching response speed and reducing conduction losses by more than 15%.

[0050] Example 2

[0051] like Figure 2 As shown, a heavily doped N+ layer 11 is formed inside the N drift layer 5 by ion implantation. The cross-sectional profile of the heavily doped N+ layer 11 is U-shaped, and the two ends of the heavily doped N+ layer 11 are in contact with the P well layers 7 on both sides.

[0052] A U-shaped heavily doped N+ layer 11 is used to penetrate the N drift layer 5 and connect to the two P-well layers 7 on both sides, forming a low-resistance current path. The U-shaped cross-section design increases the conductive cross-sectional area, reducing the on-resistance by 20%; at the same time, the contact between the N+ layer and the P-well suppresses the parasitic JFET effect, increasing the current density to 1.5 times that of the conventional MOSFET.

[0053] Example 3

[0054] like Figure 3 As shown, the N drift layer 5 also includes a semi-circular drift layer 51, which is located below the P-well layer 7 and in contact with the P-well layer 7.

[0055] The semi-circular drift layer 51 is embedded in the N-drift layer 5 and in direct contact with the P-well layer 7, and its arc-shaped profile optimizes the electric field distribution. This structure makes the depletion region expand more uniformly laterally, increases the breakdown voltage to over 650V, and reduces the reliability risks caused by electric field accumulation at the device edges.

[0056] Example 4

[0057] like Figure 4 As shown, a semi-circular P-layer 12 is provided inside the N drift layer 5 and below the P-well layer 7 and P+ layer 8. The top of the semi-circular P-layer 12 is in direct contact with both the P-well layer 7 and P+ layer 8.

[0058] The semi-circular P-layer 12 is located below the P-well layer 7 and the P+ layer 8, and is laterally diffused through tilted ion implantation. Its top end contacts the P-well or P+ layer to form a charge balance layer, which suppresses premature breakdown of the N-drift layer 5, reduces leakage current by one order of magnitude, and improves avalanche tolerance by 30%.

[0059] Example 5

[0060] like Figure 5 As shown, a number of P-type doped gates 13 are arranged side by side inside the N-drift layer 5 and below the P-well layer 7. The top of the P-type doped gate 13 is in direct contact with the P-well layer 7.

[0061] The P-type doped gate 13 vertically penetrates the N-drift layer 5 and directly connects to the P-well layer 7, forming a high-speed carrier extraction channel. During turn-off, this structure accelerates hole extraction, reducing the turn-off time to less than 15 ns and decreasing switching losses by 40%, making it particularly suitable for high-frequency applications.

[0062] Example 6

[0063] like Figure 6 As shown, a semi-circular P-layer 12 is provided inside the N-drift layer 5 and below the P-well layer 7 and P+ layer 8. The top of the semi-circular P-layer 12 is in direct contact with both the P-well layer 7 and P+ layer 8. A number of P-type doped gates 13 are provided inside the N-drift layer 5 and below the P-well layer 7. The top of the P-type doped gates 13 is in direct contact with the P-well layer 7. The P-type doped gates 13 are located inside the semi-circular P-layer 12.

[0064] The semi-circular P-layer 12 and the internal P-type doped gate 13 form a synergistic structure: the semi-circular layer optimizes the longitudinal electric field, and the P-type gate provides a lateral carrier pathway. The combination of the two reduces the dynamic resistance by 25%, and the S4 step of slotting exposes the top of the P-type gate, ensuring the reliability of the ohmic contact and improving the device's latch-up resistance.

[0065] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A self-aligned dual-gate MOSFET, comprising a plurality of MOS cells connected in parallel, wherein each MOS cell comprises, from bottom to top, a drain (1), a semiconductor epitaxial layer, a gate (3), and a source (2), wherein the semiconductor epitaxial layer comprises, from bottom to top, an N-substrate layer (4), an N-drift layer (5), a P-well layer (7), and an N-well layer (6), wherein the N-well layer (6) and the P-well layer (7) are located on both sides of the gate (3), and the semiconductor epitaxial layer further comprises a P+ layer (8), which is located on both sides of the N-well layer (6) and the P-well layer (7), characterized in that: A P-type doped region (9) is formed inside the N-drift layer (5) and below the gate (3) by ion implantation. The P-type doped region (9) is in ohmic contact with the gate (3). The P-type doped region (9) contains several N-type doped gates (10) arranged side by side.

2. The self-aligned dual-gate MOSFET according to claim 1, characterized in that: The interior of the N drift layer (5) is formed with a heavily doped N+ layer (11) by ion implantation.

3. The self-aligned dual-gate MOSFET according to claim 2, characterized in that: The cross-sectional profile of the heavily doped N+ layer (11) is U-shaped, and the two ends of the heavily doped N+ layer (11) are in contact with the P-well layers (7) on both sides respectively.

4. The self-aligned dual-gate MOSFET according to claim 1, characterized in that: The N-drift layer (5) also includes a semi-circular drift layer (51), which is located below the P-well layer (7) and in contact with the P-well layer (7).

5. The self-aligned dual-gate MOSFET according to claim 1, characterized in that: A semi-circular P-layer (12) is provided inside the N-drift layer (5) and below the P-well layer (7) and P+ layer (8). The top of the semi-circular P-layer (12) is in direct contact with the P-well layer (7) and P+ layer (8).

6. The self-aligned dual-gate MOSFET according to claim 5, characterized in that: Inside the N-drift layer (5) and below the P-well layer (7), there are several P-type doped gates (13) arranged side by side, with the top of the P-type doped gate (13) in direct contact with the P-well layer (7).

7. The self-aligned dual-gate MOSFET according to claim 6, characterized in that: The P-type doped gate (13) is located inside the semi-circular P-layer (12).

8. A manufacturing process for a self-aligned dual-gate MOSFET, characterized in that, The self-aligned dual-gate MOSFET described in claim 7 is further described in the manufacturing process of which includes: S1. Provide an N-type substrate (4) and epitaxially grow an N-drift layer (5) on its surface. S2. Through photolithography and ion implantation processes, a P-type doped region (9), a semi-circular P-layer (12), and a P-type doped gate (13) are formed in the N-drift layer (5), wherein the semi-circular P-layer (12) is located below the predetermined region of the P-well layer, and the P-type doped gate (13) is embedded in the semi-circular P-layer (12). S3. An N-well layer (6) is epitaxially grown on the surface of the N-drift layer (5). S4. A P-well layer (7) and a P+ layer (8) are formed sequentially on the N-well layer (6), and a groove is made above the semi-circular P- layer (12) by photolithography and etching process to expose the top of the P-type doped gate (13); S5. Deposit an N-type doped gate (10) inside the P-type doped region (9) to make it self-aligned with the gate (3); S6. Sequentially deposit the drain (1), source (2) and gate (3) metal layers to complete the ohmic contact and interconnection.

9. The manufacturing process of the self-aligned dual-gate MOSFET according to claim 8, characterized in that: The ion implantation energy of the P-type doped region (9) in step S2 is 50-200keV; the implantation angle of the semi-circular P-layer (12) is 7°-30°, so as to achieve lateral diffusion and bottom contact with the P-well layer (7).

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