Semiconductor device, display device, display module, and electronic apparatus

Abstract

The invention discloses a semiconductor device, a display device, a display module, and an electronic apparatus. According to one embodiment of the present invention, a semiconductor device includes a staggered transistor using an oxide semiconductor and a capacitor element. One embodiment of the present invention is a semiconductor device including a transistor and a capacitor element, wherein the transistor includes: an oxide semiconductor film; a gate insulating film over the oxide semiconductor film; a gate electrode over the gate insulating film; a second insulating film on the gate electrode; a third insulating film on the second insulating film; and a source electrode and a drain electrode over the third insulating film, the source electrode and the drain electrode being electrically connected to the oxide semiconductor film. A second conductive film; and a second insulating film, the first conductive film and the gate electrode are disposed on the same surface, the second conductive film and the source electrode and the drain electrode are disposed on the same surface, and the second insulating film is disposed between the first conductive film and the second conductive film.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device using an oxide semiconductor film and a display device using the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above-described technical field. The technical field of one embodiment of the invention disclosed in this specification and other aspects relates to an object, method, or manufacturing method. In addition, the present invention relates to a process, machine, product, or composition of matter. In particular, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, a driving method thereof, or a manufacturing method thereof.

[0003] Note that in this specification and other publications, the term "semiconductor device" refers to any device that operates by utilizing semiconductor properties. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and storage devices are all examples of semiconductor devices. Imaging devices, display devices, liquid crystal display devices, light-emitting devices, electro-optical devices, power generation devices (including thin-film solar cells and organic thin-film solar cells), and electronic devices sometimes include semiconductor devices. Background Art

[0004] The technology of forming a transistor (also called a field effect transistor (FET) or a thin film transistor (TFT)) by using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. This transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (display devices). As semiconductor thin films that can be applied to transistors, semiconductor materials represented by silicon are well known. In addition, as other materials, oxide semiconductors have attracted attention.

[0005] For example, a technology has been disclosed in which a transistor is manufactured using an amorphous oxide containing In, Zn, Ga, Sn, etc. as an oxide semiconductor (see Patent Document 1). In addition, a technology has been disclosed in which a transistor having a self-aligned top-gate structure is manufactured using an oxide thin film (see Patent Document 2).

[0006] [Patent Document 1] Japanese Patent Application Publication No. 2006-165529 [Patent Document 2] Japanese Patent Application Publication No. 2009-278115 As transistors using oxide semiconductor films, for example, inverted staggered (also called bottom gate structure) transistors or staggered (also called top gate structure) transistors can be cited. When transistors using oxide semiconductor films are used in display devices, inverted staggered transistors are used more often than staggered transistors. This is because the manufacturing process of the inverted staggered type is relatively simple and its manufacturing cost can be suppressed. However, there is the following problem: as the screens in display devices become larger or higher definition (for example, high-definition display devices represented by 4k×2k (3840 pixels in the horizontal direction and 2160 pixels in the vertical direction) or 8k×4k (7680 pixels in the horizontal direction and 4320 pixels in the vertical direction)), inverted staggered transistors have parasitic capacitance between the gate electrode and the source electrode and parasitic capacitance between the gate electrode and the drain electrode. Due to the parasitic capacitance, the signal delay increases, which leads to a decrease in the display quality of the display device. Another problem is that the area occupied by the transistor is larger when using inverted staggered transistors than when using staggered transistors. Therefore, there is a demand for staggered transistors using oxide thin films that have stable semiconductor characteristics and a highly reliable structure and can be manufactured using a simple manufacturing process.

[0007] Furthermore, as display screens become larger and higher-definition, the structure of the transistors formed in the pixels of the display devices and the capacitors connected to them becomes increasingly important. The capacitors serve as storage capacitors for storing data written into the pixels. Depending on the structure of the capacitors, there is a problem of deteriorating the display quality of the display device due to the inability to retain the data written into the pixels. Summary of the Invention

[0008] In view of the above problems, one of the objects of one embodiment of the present invention is to provide a novel semiconductor device including a transistor using an oxide semiconductor. In particular, one of the objects of one embodiment of the present invention is to provide a semiconductor device including a staggered transistor using an oxide semiconductor. One of other objects of one embodiment of the present invention is to provide a semiconductor device including a staggered transistor using an oxide semiconductor and a capacitor connected to the transistor. One of other objects of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having a large on-state current. One of other objects of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having a small off-state current. One of other objects of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and occupying a small area. One of other objects of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having stable electrical characteristics. One of other objects of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having high reliability. One of other objects of one embodiment of the present invention is to provide a novel semiconductor device. One of other objects of one embodiment of the present invention is to provide a novel display device.

[0009] Note that the inclusion of the above-mentioned purpose does not preclude the existence of other purposes. Furthermore, one embodiment of the present invention does not necessarily achieve all of the above-mentioned purposes. Purposes other than the above-mentioned purpose may be apparent from the description of the specification, etc., and may be extracted from the description of the specification, etc.

[0010] One embodiment of the present invention is a semiconductor device including a transistor and a capacitor, wherein the transistor includes: an oxide semiconductor film; a gate insulating film on the oxide semiconductor film; a gate electrode on the gate insulating film; a second insulating film on the gate electrode; a third insulating film on the second insulating film; a source electrode on the third insulating film; and a drain electrode on the third insulating film, the source electrode being electrically connected to the oxide semiconductor film, and the drain electrode being electrically connected to the oxide semiconductor film; and the capacitor includes: a first conductive film; a second conductive film; and a second insulating film, the first conductive film and the gate electrode being provided on the same surface, the second conductive film and the source electrode and the drain electrode being provided on the same surface, and the second insulating film being provided between the first conductive film and the second conductive film. For details, see below.

[0011] One embodiment of the present invention is a semiconductor device including a transistor and a capacitor, wherein the transistor includes: an oxide semiconductor film on a first insulating film; a gate insulating film on the oxide semiconductor film; a gate electrode on the gate insulating film; a second insulating film on the gate electrode; a third insulating film on the second insulating film; a source electrode on the third insulating film; and a drain electrode on the third insulating film, the first insulating film has oxygen, the second insulating film has nitrogen, the source electrode is electrically connected to the oxide semiconductor film, and the drain electrode is electrically connected to the oxide semiconductor film, and the capacitor includes: a first conductive film; a second conductive film; and a second insulating film, the first conductive film and the gate electrode are arranged on the same surface, the second conductive film and the source electrode and the drain electrode are arranged on the same surface, and the second insulating film is arranged between the first conductive film and the second conductive film.

[0012] In addition, another embodiment of the present invention is a semiconductor device including a transistor and a capacitor, wherein the transistor includes: a first gate electrode on a first insulating film; a first gate insulating film on the first gate electrode; an oxide semiconductor film on the first gate insulating film; a second gate insulating film on the oxide semiconductor film; a second gate electrode on the second gate insulating film; a second insulating film on the second gate electrode; a third insulating film on the second insulating film; a source electrode on the third insulating film; and a drain electrode on the third insulating film, the first gate insulating film has oxygen, the second insulating film has nitrogen, the source electrode is electrically connected to the oxide semiconductor film, and the drain electrode is electrically connected to the oxide semiconductor film, and the capacitor includes: a first conductive film; a second conductive film; and a second insulating film, the first conductive film and the second gate electrode are arranged on the same surface, the second conductive film and the source electrode and the drain electrode are arranged on the same surface, and the second insulating film is arranged between the first conductive film and the second conductive film.

[0013] Furthermore, in the above embodiment, it is preferred that the oxide semiconductor film includes a first region and a second region, the first region includes a region overlapping with the gate electrode, the second region includes a region not overlapping with the gate electrode, the first region includes a portion having a first impurity element concentration, the second region includes a portion having a second impurity element concentration, and the first concentration and the second concentration are different. Furthermore, in the above embodiment, it is preferred that the oxide semiconductor film includes a first region and a second region, the first region includes a region overlapping with the second gate electrode, the second region includes a region not overlapping with the second gate electrode, the first region includes a portion having the first impurity element concentration, the second region includes a portion having the second impurity element concentration, and the first concentration and the second concentration are different.

[0014] In the above embodiment, the impurity elements preferably include one or more of hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine, and a rare gas element. In the above embodiment, the impurity elements preferably include argon and hydrogen.

[0015] In the above embodiment, the second region preferably includes a region in contact with the second insulating film. In the above embodiment, the second region preferably includes a region having a higher impurity element concentration than the first region. In the above embodiment, the first region preferably includes a region having higher crystallinity than the second region.

[0016] In the above embodiment, the oxide semiconductor film preferably contains oxygen, In, Zn, and M (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). In the above embodiment, the oxide semiconductor film preferably includes a crystalline portion, and the crystalline portion preferably has a c-axis orientation and a portion whose c-axis is parallel to the normal vector of the formed surface of the oxide semiconductor film.

[0017] Another embodiment of the present invention is a display device comprising the semiconductor device described in any of the above embodiments and a display element. Another embodiment of the present invention is a display module comprising the display device and a touch sensor. Another embodiment of the present invention is an electronic device comprising: the semiconductor device described in any of the above embodiments, the display device or the display module; and an operation key or a battery.

[0018] According to one embodiment of the present invention, a novel semiconductor device including a transistor using an oxide semiconductor can be provided. In particular, according to one embodiment of the present invention, a semiconductor device including a staggered transistor using an oxide semiconductor can be provided. In addition, a semiconductor device can be provided, which includes a staggered transistor using an oxide semiconductor and a capacitor connected to the transistor. In addition, a semiconductor device can be provided, which includes a transistor using an oxide semiconductor and having a large on-state current. In addition, a semiconductor device can be provided, which includes a transistor using an oxide semiconductor and having a small off-state current. In addition, a semiconductor device can be provided, which includes a transistor using an oxide semiconductor and occupying a small area. One of the other purposes of one embodiment of the present invention is to provide a semiconductor device including a transistor using an oxide semiconductor and having stable electrical characteristics. In addition, a semiconductor device can be provided, which includes a transistor using an oxide semiconductor and having high reliability. In addition, a novel semiconductor device can be provided. In addition, a novel display device can be provided.

[0019] Note that the inclusion of these effects does not preclude the existence of other effects. Furthermore, one embodiment of the present invention does not necessarily have all of the aforementioned effects. Furthermore, effects other than these effects may be apparent from the description, drawings, claims, and the like, and thus may be extracted from the description, drawings, claims, and the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figures 1A to 1D 1 is a top view and a cross-sectional view showing one embodiment of a semiconductor device; Figure 2 is a cross-sectional view showing one embodiment of a semiconductor device; Figures 3A to 3D is a cross-sectional view showing one embodiment of a semiconductor device; Figure 4A and 4B is a cross-sectional view showing one embodiment of a semiconductor device; Figures 5A to 5D 1 is a top view and a cross-sectional view showing one embodiment of a semiconductor device; Figure 6 is a cross-sectional view showing one embodiment of a semiconductor device; Figures 7A to 7D is a cross-sectional view showing one embodiment of a semiconductor device; Figures 8A to 8D is a cross-sectional view showing one embodiment of a semiconductor device; Figures 9A to 9D is a cross-sectional view showing one embodiment of a semiconductor device; Figure 10 is a cross-sectional view showing one embodiment of a semiconductor device; Figures 11A to 11C A cross-sectional view showing one embodiment of a semiconductor device and a diagram showing one embodiment of an energy band structure; Figures 12A to 12H is a cross-sectional view showing an example of a manufacturing process of a semiconductor device; Figures 13A to 13F is a cross-sectional view showing an example of a manufacturing process of a semiconductor device; Figures 14A to 14F is a cross-sectional view showing an example of a manufacturing process of a semiconductor device; Figures 15A to 15F is a cross-sectional view showing an example of a manufacturing process of a semiconductor device; Figures 16A to 16F is a cross-sectional view showing an example of a manufacturing process of a semiconductor device; Figures 17A to 17C This is a cross-sectional TEM image of an oxide semiconductor and a local Fourier transform image. Figures 18A to 18D 1 is a diagram showing a nanobeam electron diffraction pattern of an oxide semiconductor film and an example of a transmission electron diffraction measurement apparatus; Figures 19A to 19C A diagram and a planar TEM image showing an example of structural analysis using transmission electron diffraction measurement; Figure 20 is a diagram illustrating the computational model; Figure 21A and21B It is a diagram illustrating the initial state and the final state; Figure 22 is a graph illustrating activation energy; Figure 23A and 23B It is a diagram illustrating the initial state and the final state; Figure 24 is a graph illustrating activation energy; Figure 25 Is to explain V O Diagram of the migration energy levels of H; Figure 26 is a top view showing one embodiment of a display device; Figure 27 is a cross-sectional view showing one embodiment of a display device; Figure 28 is a cross-sectional view showing one embodiment of a display device; Figure 29A and 29B is a diagram illustrating the structure of a pixel portion of a light-emitting device; Figures 30A to 30D is a cross-sectional view of a semiconductor device; Figures 31A to 31C is a top view and circuit diagram of the display device; Figure 32A and 32B It is a circuit diagram and timing diagram of the display device; Figure 33A and 33B It is a circuit diagram and timing diagram of the display device; Figure 34A and 34B It is a circuit diagram and timing diagram of the display device; Figure 35A and 35B It is a circuit diagram and timing diagram of the display device; Figure 36 is a diagram illustrating a display module; Figures 37A to 37H is a diagram illustrating an electronic device; Figure 38A and 38B is a cross-sectional TEM image in the embodiment; Figure 39 is a graph illustrating the temperature dependence of resistivity; Figures 40A to 40C Schematic diagram illustrating a film formation model of CAAC-OS, a particle, and a cross-sectional view of CAAC-OS; Figure 41 is a schematic diagram illustrating a film formation model of nc-OS, wherein particles are shown; Figure 42 is a diagram illustrating particles; Figure 43 is a diagram illustrating the forces applied to particles on the formed surface; Figure 44A and 44B It is a diagram illustrating the behavior of particles on the formed surface; Figure 45A and 45B is a diagram illustrating the crystallization of InGaZnO4; Figure 46A and 46B is a diagram showing the structure of InGaZnO4 before atomic collision; Figure 47A and 47B is a diagram showing the structure of InGaZnO4 after atomic collision; Figure 48A and 48B is a diagram showing the trajectories of atoms after an atomic collision; Figure 49A and 49B Cross-sectional HAADF-STEM images of the CAAC-OS film and target. DETAILED DESCRIPTION

[0021] The following describes the embodiments with reference to the accompanying drawings. However, those skilled in the art will readily appreciate that the embodiments may be implemented in a variety of different forms, and their methods and details may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited solely to the following embodiments.

[0022] In the drawings, sizes, layer thicknesses, or regions may be exaggerated for clarity of description. Therefore, the present invention is not necessarily limited to the aforementioned dimensions. Furthermore, the drawings schematically illustrate idealized examples, and therefore the present invention is not limited to the shapes or numerical values ​​shown in the drawings.

[0023] The ordinal numbers such as “first”, “second” and “third” used in this specification are added to avoid confusion among constituent elements, and are not intended to limit the number.

[0024] For convenience, this specification uses terms such as "upper" and "lower" to describe the positional relationships of components with reference to the accompanying drawings. The positional relationships of the components may vary depending on the orientation in which they are described. Therefore, the terms are not limited to those used in this specification and may be replaced as appropriate depending on the circumstances.

[0025] In this specification, etc., a transistor refers to an element that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain terminal, drain region, or drain electrode) and a source electrode (source terminal, source region, or source electrode), and current can flow through the drain, channel region, and source electrode. Note that in this specification, etc., the channel region refers to the region through which current primarily flows.

[0026] The functions of "source" and "drain" may be interchanged when using transistors with different polarities or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" may be interchanged.

[0027] In this specification, "electrically connected" includes connection via "an element having some electrical function." This "element having some electrical function" is not particularly limited as long as it enables the transfer of electrical signals between connected objects. For example, "an element having some electrical function" includes not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0028] Implementation Method 1 In this embodiment, referring to Figures 1A to 16F An example of a semiconductor device in which a transistor and a capacitor are provided over the same substrate and a method for manufacturing the semiconductor device will be described.

[0029] <Structure of Semiconductor Device 1> Figures 1A to 1D An example of a semiconductor device in which a transistor and a capacitor are provided over the same substrate is shown. Note that this transistor has a top-gate structure.

[0030] Figure 1A is a top view of a transistor 100 included in a semiconductor device. Figure 1B is a top view of a capacitor element 150 included in the semiconductor device. Figure 1C It is along Figure 1A The cross-sectional view along the dot-dash line X1-X2, Figure 1D It is along Figure 1B Note that for convenience, Figure 1A and 1B The substrate 102, insulating film 104, insulating film 108, insulating film 118, insulating film 120, etc. are omitted. Also note that in the top view of the transistor and capacitor element below, Figure 1A and 1B Similarly, some of the components are omitted. In addition, the direction of the dot-dash line X1-X2 is sometimes referred to as the channel length direction, and the direction of the dot-dash line Y1-Y2 is sometimes referred to as the channel width direction.

[0031] Figure 1A and 1C The transistor 100 shown includes an insulating film 108 formed on a substrate 102; an oxide semiconductor film 110 on the insulating film 108; an insulating film 112 on the oxide semiconductor film 110; a conductive film 114 overlapping the oxide semiconductor film 110 with the insulating film 112 interposed therebetween; an insulating film 118 covering the oxide semiconductor film 110, the insulating film 112, and the conductive film 114; an insulating film 120 on the insulating film 118; a conductive film 122 connected to the oxide semiconductor film 110 via openings 140a provided in the insulating film 118 and the insulating film 120; and a conductive film 124 connected to the oxide semiconductor film 110 via openings 140b provided in the insulating film 118 and the insulating film 120. Furthermore, an insulating film 128 may be provided on the transistor 100 to cover the insulating film 120, the conductive film 122, and the conductive film 124.

[0032] exist Figure 1C 1 , the insulating film 108 has a stacked-layer structure of an insulating film 108a and an insulating film 108b on the insulating film 108a. The conductive film 114 has a stacked-layer structure of a conductive film 114a and a conductive film 114b on the conductive film 114a. The conductive film 122 has a stacked-layer structure of a conductive film 122a and a conductive film 122b on the conductive film 122a. The conductive film 124 has a stacked-layer structure of a conductive film 124a and a conductive film 124b on the conductive film 124a.

[0033] In the transistor 100, the conductive film 114 functions as a gate electrode (also referred to as a top gate electrode), the conductive film 122 functions as one of a source electrode and a drain electrode, and the conductive film 124 functions as the other of the source electrode and the drain electrode. Furthermore, in the transistor 100, the insulating film 108 functions as a base film for the oxide semiconductor film 110, and the insulating film 112 functions as a gate insulating film.

[0034] also, Figure 1B and 1D The illustrated capacitor element 150 includes an insulating film 108 formed on a substrate 102; an insulating film 112 on the insulating film 108; a conductive film 116 on the insulating film 112; an insulating film 118 covering the insulating film 108, the insulating film 112, and the conductive film 116; an insulating film 120 on the insulating film 118; and a conductive film 126 overlapping the conductive film 116 with the insulating film 118 interposed therebetween in an opening 140c provided in the insulating film 120. Alternatively, an insulating film 128 covering the insulating film 120 and the conductive film 126 may be provided on the capacitor element 150.

[0035] exist Figure 1D1 , the insulating film 108 has a stacked-layer structure of an insulating film 108a and an insulating film 108b on the insulating film 108a. The conductive film 116 has a stacked-layer structure of a conductive film 116a and a conductive film 116b on the conductive film 116a. The conductive film 126 has a stacked-layer structure of a conductive film 126a and a conductive film 126b on the conductive film 126a.

[0036] Capacitor element 150 has a structure in which a dielectric is sandwiched between a pair of electrodes. More specifically, one of the pair of electrodes is a conductive film 116, the other of the pair of electrodes is a conductive film 126, and an insulating film 118 between the conductive films 116 and 126 serves as a dielectric.

[0037] The conductive film 114 serving as the gate electrode of the transistor 100 and the conductive film 116 serving as one of the pair of electrodes of the capacitor 150 are formed by the same process, and at least a portion of them are formed on the same surface. The conductive films 122 and 124 serving as the source and drain electrodes of the transistor 100, and the conductive film 126 serving as the other of the pair of electrodes of the capacitor 150 are formed by the same process, and at least a portion of the conductive films 122, 124, and 126 are formed on the same surface.

[0038] In this manner, by forming the conductive films serving as the electrodes of the transistor 100 and the capacitor 150 in the same process, manufacturing costs can be reduced.

[0039] Furthermore, in capacitor element 150, insulating film 120 has opening 140c. This allows insulating film 118 to function solely as a dielectric in the stack of insulating films 118 and 120. This structure increases the capacitance of capacitor element 150, thereby increasing the capacitance of the display device.

[0040] then, Figure 2 Shown along Figure 1A FIG. 1 is a cross-sectional view of the transistor 100 taken along the dashed line Y1 - Y2 (in the channel width direction).

[0041] like Figure 2 As shown, the end of the conductive film 114a is located outside the end of the conductive film 114b in the channel width direction. The end of the insulating film 112 is located outside the end of the conductive film 114a. The insulating film 108b has a recessed portion in the region that does not overlap with the insulating film 112. This structure improves the coverage of the insulating films 118, 120, and 128.

[0042] Next, the oxide semiconductor film 110 included in the transistor 100 will be described in detail below.

[0043] In the oxide semiconductor film 110 of the transistor 100, a region that does not overlap with the conductive film 114 contains an element that forms an oxygen vacancy. Hereinafter, elements that form oxygen vacancies are referred to as impurity elements. Typical examples of impurity elements include hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, chlorine, and rare gas elements. Typical examples of rare gas elements include helium, neon, argon, krypton, and xenon.

[0044] When an impurity element is added to an oxide semiconductor film, the bond between the metal element and oxygen in the oxide semiconductor film is severed, forming an oxygen vacancy. Alternatively, when an impurity element is added to an oxide semiconductor film, oxygen bonded to the metal element in the oxide semiconductor film bonds with the impurity element, and oxygen is separated from the metal element, thereby forming an oxygen vacancy. As a result, the carrier density of the oxide semiconductor film increases, thereby improving the conductivity.

[0045] When hydrogen is added to an oxide semiconductor to which an impurity element has been added to form an oxygen vacancy, hydrogen enters the oxygen vacancy and forms a donor energy level near the conduction band. As a result, the conductivity of the oxide semiconductor increases, and it becomes a conductor. An oxide semiconductor that can become a conductor is called an oxide conductor. Generally speaking, due to the large energy gap of oxide semiconductors, they are transparent to visible light. On the other hand, an oxide conductor is an oxide semiconductor with a donor energy level near the conduction band. Therefore, the influence of absorption due to the donor energy level is small, and it has the same degree of transparency to visible light as an oxide semiconductor.

[0046] Here, regarding a film formed using an oxide conductor (hereinafter referred to as an oxide conductor film), refer to Figure 39 Explain the temperature dependence of its resistivity.

[0047] Here, a sample having an oxide conductor film was manufactured. As the oxide conductor film, the following oxide conductor film (OC_SiN) was manufactured: an oxide conductor film in which an oxide semiconductor film and a silicon nitride film were in contact. x ) ; an oxide conductor film formed by adding argon to an oxide semiconductor film in contact with a silicon nitride film in a doping device (OC_Ar dope+SiN x ) ; an oxide conductor film (OC_Arplasma+SiN) formed by exposing an oxide semiconductor film to argon plasma in a plasma processing apparatus and contacting the oxide semiconductor film with a silicon nitride film x ). In addition, the silicon nitride film contains hydrogen.

[0048] The following describes the oxide conductor film (OC_SiN x) sample. After forming a 400nm thick silicon oxynitride film on a glass substrate by a plasma CVD method, the silicon oxynitride film is exposed to oxygen plasma, and then oxygen ions are added to the silicon oxynitride film to form an oxynitride silicon film that releases oxygen due to heating. Next, a 100nm thick In-Ga-Zn oxide film is formed on the silicon oxynitride film that releases oxygen due to heating by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2, and the oxide film is heat-treated in a nitrogen atmosphere at 450°C, and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450°C. Then, a 100nm thick silicon nitride film is formed by a plasma CVD method. Then, heat treatment is performed in a mixed gas atmosphere of nitrogen and oxygen at 350°C.

[0049] The following describes the oxide conductor film (OC_Ar dope + SiN x ) sample. After forming a 400nm thick silicon oxynitride film on a glass substrate by a plasma CVD method, the silicon oxynitride film is exposed to oxygen plasma, and then oxygen ions are added to the silicon oxynitride film to form an oxynitride silicon film that releases oxygen due to heating. Next, a 100nm thick In-Ga-Zn oxide film is formed on the silicon oxynitride film that releases oxygen due to heating by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2, and the oxide film is heat-treated in a nitrogen atmosphere at 450°C, and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450°C. Next, a doping device is used to add 5·10 14 ions / cm 2 Argon was added to form oxygen vacancies in the In-Ga-Zn oxide film. A 100 nm thick silicon nitride film was then formed by plasma CVD. Heat treatment was then performed at 350°C in a mixed gas atmosphere of nitrogen and oxygen.

[0050] The following describes the oxide conductor film (OC_Ar plasma + SiN x) sample. After forming a 400nm thick silicon oxynitride film on a glass substrate by a plasma CVD method, the silicon oxynitride film is exposed to oxygen plasma to form an oxynitride silicon film that releases oxygen due to heating. Next, a 100nm thick In-Ga-Zn oxide film is formed on the silicon oxynitride film that releases oxygen due to heating by a sputtering method using a sputtering target with an atomic ratio of In:Ga:Zn=1:1:1.2, and the oxide film is heat-treated in a nitrogen atmosphere at 450°C, and then heat-treated in a mixed gas atmosphere of nitrogen and oxygen at 450°C. Next, argon plasma is generated in a plasma processing device, and accelerated argon ions are caused to collide with the In-Ga-Zn oxide film to form oxygen vacancies. Then, a 100nm thick silicon nitride film is formed by a plasma CVD method. Then, heat treatment is performed in a mixed gas atmosphere of nitrogen and oxygen at 350°C.

[0051] Figure 39 The results of measuring the resistivity of each sample are shown. Here, the resistivity was measured using the four-terminal van der Pauw method. Figure 39 In the figure, the horizontal axis represents the measurement temperature and the vertical axis represents the resistivity. x ) measurement results, the circles show the oxide conductor film (OC_Ar dope+SiN x ) measurement results, the triangle shows the oxide semiconductor film (OC_Arplasma+SiN x )’s measurement results.

[0052] Note that although not shown in the drawings, the resistivity of the oxide semiconductor film not in contact with the silicon nitride film is high, making it difficult to measure its resistivity. This indicates that the resistivity of the oxide conductor film is lower than that of the oxide semiconductor film.

[0053] from Figure 39 It can be seen that when the oxide conductor film (OC_Ar dope+SiN x ) and oxide conductor film (OC_Arplasma+SiN x) contains oxygen vacancies and hydrogen, the change in resistivity is small. Typically, in the range of 80K or more and 290K or less, the change in resistivity is less than ±20%. Alternatively, in the range of 150K or more and 250K or less, the change in resistivity is less than ±10%. In other words, the oxide conductor is a degenerate semiconductor, and it can be inferred that its conduction band edge is consistent or roughly consistent with the Fermi level. Thus, by using the oxide conductor film as the source region and drain region of the transistor, the oxide conductor film can be made into ohmic contact with the conductive film used as the source electrode and drain electrode of the transistor, thereby reducing the contact resistance between the oxide conductor film and the conductive film used as the source electrode and drain electrode of the transistor. In addition, since the resistivity of the oxide conductor is not very dependent on temperature, the change in contact resistance between the oxide conductor film and the conductive film used as the source electrode and drain electrode of the transistor is small, thereby making it possible to manufacture transistors with high reliability.

[0054] Here, Figures 3A to 3D as well as Figure 4A and 4B FIG shows an enlarged view of the vicinity of the oxide semiconductor film 110. Note that for simplicity, Figures 3A to 3D as well as Figure 4A and 4B A part of the components is omitted.

[0055] In the cross-sectional shape of the oxide semiconductor film 110 in the channel length direction, a region (hereinafter referred to as a low resistance region) is formed where the conductivity is improved due to the increase in the carrier density of the oxide semiconductor film. Figures 3A to 3D as well as Figure 4A and 4B As shown in FIG. 1 , the low resistance region formed in the oxide semiconductor film 110 has a plurality of components. Figures 3A to 3D as well as Figure 4A and 4B In FIG, the channel length L is the length of the region sandwiched between a pair of low-resistance regions.

[0056] like Figure 3A As shown, the oxide semiconductor film 110 includes: a channel region 110a formed in a region overlapping with the conductive film 114; and regions sandwiching the channel region 110a and containing impurity elements, namely, low resistance regions 110b and 110c. Figure 3AAs shown, in the cross-sectional shape along the channel length direction, the boundary between the channel region 110a and the low-resistance region 110b, and the boundary between the channel region 110a and the low-resistance region 110c coincide with or substantially coincide with the lower end portion of the conductive film 114a via the insulating film 112. That is, in a plan view, the boundary between the channel region 110a and the low-resistance region 110b, and the boundary between the channel region 110a and the low-resistance region 110c coincide with or substantially coincide with the lower end portion of the conductive film 114a.

[0057] like Figure 3A As shown, in the cross-sectional shape along the channel length direction, the end of the conductive film 114a may be located outside the end of the conductive film 114b, and the conductive film 114b may have a tapered shape. Specifically, the angle θ1 formed between the contact surface of the conductive film 114a and the conductive film 114b and the side surface of the conductive film 114b may be less than 90°, 10° to 85°, 15° to 85°, 30° to 85°, 45° to 85°, or 60° to 85°. By setting the angle θ1 to less than 90°, 10° to 85°, 15° to 85°, 30° to 85°, 45° to 85°, or 60° to 85°, the coverage of the insulating film 118 on the side surface of the conductive film 114b can be improved.

[0058] like Figure 3A As shown, in the cross-sectional shape along the channel length direction, the end of the insulating film 112 may be located outside the ends of the conductive films 114a and 114b. Furthermore, a portion of the end of the insulating film 112 may have an arc shape. Furthermore, the insulating film 112 may have a tapered shape. Specifically, the angle θ2 formed between the contact surface of the oxide semiconductor film 110 and the insulating film 112 and the side surface of the insulating film 112 may be less than 90°, preferably not less than 30° and less than 90°.

[0059] like Figure 3B As shown, in the cross-sectional shape in the channel length direction, the low resistance regions 110b and 110c have a region that overlaps with the conductive film 114 via the insulating film 112. This region is used as the overlapping region. The length of the overlapping region in the channel length direction is represented by L. ov . L ov It is less than 20%, less than 10%, less than 5% or less than 2% of the channel length L.

[0060] like Figure 3C As shown, in the cross-sectional shape in the channel length direction, the channel region 110a has a region that does not overlap with the lower end of the conductive film 114a. This region is used as an offset region. The length of the offset region in the channel length direction is represented by L. offNote that when there are multiple bias regions, the length of one bias region is referred to as L. off . L off Included in the channel length L. L off It is less than 20%, less than 10%, less than 5% or less than 2% of the channel length L.

[0061] like Figure 3D As shown, in the cross-sectional shape along the channel length direction, the oxide semiconductor film 110 includes a low-resistance region 110d between the channel region 110a and the low-resistance region 110b, and a low-resistance region 110e between the channel region 110a and the low-resistance region 110c. The impurity element concentration in the low-resistance regions 110d and 110e is lower than that in the low-resistance regions 110b and 110c, and the resistivity in the low-resistance regions 110d and 110e is higher than that in the low-resistance regions 110b and 110c. Although the low-resistance regions 110d and 110e overlap with the insulating film 112, they may also overlap with the insulating film 112 and the conductive film 114.

[0062] like Figure 4A As shown, in the cross-sectional shape along the channel length direction, the oxide semiconductor film 110 includes regions 110f and 110g in the region overlapping with the conductive films 122 and 124. Impurity elements may not be added to the regions 110f and 110g. In this case, the oxide semiconductor film 110 includes regions containing impurity elements, namely, low-resistance regions 110b and 110c, between the regions 110f and 110g in contact with the conductive films 122 and 124 and the channel region 110a. When a voltage is applied to the conductive films 122 and 124, the regions 110f and 110g become conductive, thereby functioning as source regions and drain electrodes.

[0063] Furthermore, after the conductive films 122 and 124 are formed, an impurity element is added to the oxide semiconductor film 110 through the insulating film 120 and the insulating film 118 using the conductive films 114, 122, and 124 as masks to form an oxide semiconductor film 110. Figure 4A The structure shown.

[0064] like Figure 4B As shown, in the cross-sectional shape in the channel length direction, low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i may be provided sandwiching the channel region 110a.

[0065] Specifically, Figure 4BThe oxide semiconductor film 110 shown includes a channel region 110a; low-resistance regions 110h and 110i sandwiching the channel region 110a; low-resistance regions 110d and 110e sandwiching the low-resistance regions 110h and 110i; and low-resistance regions 110b and 110c sandwiching the low-resistance regions 110d and 110e. The low-resistance regions 110h and 110i are formed by adding impurity elements through the conductive film 114a and the insulating film 112 in regions that do not overlap with the conductive film 114b. The low-resistance regions 110d and 110e are formed by adding impurity elements through the insulating film 112 in regions that do not overlap with the conductive films 114a and 114b. The low-resistance regions 110b and 110c are formed by directly adding impurity elements. As a result, the impurity element concentration of the low-resistance regions 110h and 110i is lower than that of the low-resistance regions 110d and 110e and the low-resistance regions 110b and 110c, and the resistivity of the low-resistance regions 110h and 110i is higher than that of the low-resistance regions 110d and 110e and the low-resistance regions 110b and 110c. Furthermore, the impurity element concentration of the low-resistance regions 110d and 110e is lower than that of the low-resistance regions 110b and 110c, and the resistivity of the low-resistance regions 110d and 110e is higher than that of the low-resistance regions 110b and 110c.

[0066] exist Figure 4B In FIG. 1 , the channel region 110a overlaps the conductive film 114b. The low-resistance regions 110h and 110i overlap the conductive film 114a protruding outward from the conductive film 114b. The low-resistance regions 110d and 110e overlap the insulating film 112 protruding outward from the conductive film 114a. The low-resistance regions 110b and 110c protrude outward from the insulating film 112 and overlap the insulating film 118.

[0067] like Figure 3D and Figure 4B As shown, the oxide semiconductor film 110 includes low-resistance regions 110d, 110e, 110h, and 110i having a lower impurity concentration and a higher resistivity than the low-resistance regions 110b and 110c. This can mitigate the electric field in the drain region. Consequently, fluctuations in the threshold voltage of the transistor caused by the electric field in the drain region can be reduced.

[0068] Figures 3A to 3D as well as Figure 4A and 4B The oxide semiconductor film 110 shown includes a region where the film thickness of the region not overlapping with the insulating film 112 and the conductive film 114 is thinner than that of the region overlapping with the insulating film 112 and the conductive film 114. The film thickness of this thin region is thinner than that of the oxide semiconductor film in the region overlapping with the insulating film 112 and the conductive film 114, and the thickness of this thin region is greater than or equal to 0.1 nm and less than or equal to 5 nm.

[0069] The low-resistance regions 110b and 110c in the oxide semiconductor film 110 function as a source region and a drain region. The low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i contain an impurity element.

[0070] When the impurity element is a rare gas element and the oxide semiconductor film 110 is formed by sputtering, the channel region 110a and the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i all contain the rare gas element. Furthermore, the low-resistance regions 110b and 110c have a higher rare gas concentration than the channel region 110a. The low-resistance regions 110b and 110c have a higher rare gas concentration than the low-resistance regions 110d and 110e. The low-resistance regions 110d and 110e have a higher rare gas concentration than the low-resistance regions 110h and 110i.

[0071] This is due to two reasons: when the oxide semiconductor film 110 is formed by sputtering, a rare gas is used as a sputtering gas, thereby containing the rare gas in the oxide semiconductor film 110; and a rare gas is intentionally added to the low-resistance regions 110b and 110c to form oxygen vacancies in the oxide semiconductor film 110. The concentration of the rare gas added to form oxygen vacancies in the low-resistance regions 110d, 110e, 110h, and 110i varies depending on the film structure and film thickness formed on the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i. Alternatively, a rare gas element different from that of the channel region 110a may be added to the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i.

[0072] When the impurity element is boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, or chlorine, the low-resistance regions 110 b, 110 c, 110 d, 110 e, 110 h, and 110 i contain the impurity element. Thus, the impurity element concentration of the low-resistance regions 110 b, 110 c, 110 d, 110 e, 110 h, and 110 i is higher than that of the channel region 110 a. Furthermore, the impurity element concentration of the low-resistance regions 110 b, 110 c, 110 d, 110 e, 110 h, and 110 i obtained by secondary ion mass spectrometry (SIMS) can be 5×10 18 atoms / cm 3 Above and 1×10 22 atoms / cm 3 Below, 1×10 19 atoms / cm3 Above and 1×10 21 atoms / cm 3 Below, or 5×10 19 atoms / cm 3 Above and 5×10 20 atoms / cm 3 the following.

[0073] When the impurity element is hydrogen, the hydrogen concentration of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i is higher than that of the channel region 110a. In addition, the hydrogen concentration of the low resistance regions 110b, 110c, 110d, 110e, 110h, and 110i obtained by secondary ion mass spectrometry can be 8×10 19 atoms / cm 3 Above, 1×10 20 atoms / cm 3 Above, or 5×10 20 atoms / cm 3 above.

[0074] Since the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i contain the impurity element, oxygen vacancies increase and carrier density increases, thereby improving the conductivity of the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i.

[0075] The impurity element may be a combination of one or more of hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, and chlorine with a rare gas. In this case, in the low-resistance regions 110 b, 110 c, 110 d, 110 e, 110 h, and 110 i, oxygen vacancies formed by the rare gas interact with one or more of the added hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, and chlorine, thereby sometimes increasing the conductivity of the low-resistance regions 110 b, 110 c, 110 d, 110 e, 110 h, and 110 i.

[0076] When hydrogen is added to an oxide semiconductor containing oxygen vacancies due to the addition of an impurity element, the hydrogen enters the oxygen vacancies and forms donor levels near the conduction band. This results in an oxide conductor. Therefore, an oxide conductor has light transparency. Note that an oxide semiconductor that serves as a conductor is referred to herein as an oxide conductor.

[0077] Oxide conductors are degenerate semiconductors, and their conduction band edges are presumably aligned or approximately aligned with the Fermi level. This allows the oxide conductor film to form ohmic contact with the conductive films used as the source and drain electrodes of the transistor, thereby reducing contact resistance between the oxide conductor film and the conductive films used as the source and drain electrodes of the transistor.

[0078] The transistor 100 shown in this embodiment has a structure in which a channel region 110a is sandwiched between a low-resistance region 110b and a low-resistance region 110c, which serve as source and drain regions. Consequently, the transistor 100 has a large on-state current and high field-effect mobility. Furthermore, in the transistor 100, an impurity element is added to the oxide semiconductor film 110 using the conductive film 114 as a mask. This allows the low-resistance regions to be formed in a self-aligned manner.

[0079] The transistor 100 has a structure in which the conductive film 114, which does not function as a gate electrode, overlaps with the conductive films 122 and 124, which function as source and drain electrodes. This reduces parasitic capacitance between the conductive film 114, the conductive films 122, and the conductive films 124. Consequently, when a large-area substrate is used as the substrate 102, signal delay between the conductive film 114, the conductive films 122, and the conductive films 124 can be reduced.

[0080] Next, we will explain in detail Figures 1A to 1D Other structures of the semiconductor device shown.

[0081] As the substrate 102, various substrates can be used, and are not limited to a specific substrate. Examples of such substrates include semiconductor substrates (e.g., single crystal substrates or silicon substrates), SOI (Silicon on Insulator) substrates, glass substrates, quartz substrates, plastic substrates, metal substrates, stainless steel substrates, substrates including stainless steel foil, tungsten substrates, substrates including tungsten foil, flexible substrates, laminated films, paper including fibrous materials, or base films. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass. Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES); synthetic resins such as acrylic resins; polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride; polyamide, polyimide, aramid, epoxy, inorganic vapor-deposited films, or paper. In particular, by using semiconductor substrates, single crystal substrates, or SOI substrates to manufacture transistors and capacitors, it is possible to manufacture transistors and capacitors with small variations in characteristics, size, and shape, high current capabilities, and small size. When circuits are constructed using these transistors and capacitors, low power consumption and high circuit integration can be achieved.

[0082] Alternatively, a flexible substrate may be used as the substrate 102, and transistors and capacitors may be formed directly on the flexible substrate. Alternatively, a peeling layer may be provided between the substrate 102 and the transistors and capacitors. The peeling layer may be used in situations where part or all of a semiconductor device is manufactured thereon, and then part or all of the semiconductor device is separated from the substrate 102 and transferred to another substrate. In this case, the transistors and capacitors may also be transferred to a substrate with low heat resistance or a flexible substrate. Alternatively, the peeling layer may be a laminated structure of an inorganic film of a tungsten film and a silicon oxide film, or a structure in which an organic resin film such as polyimide is formed on a substrate.

[0083] Examples of substrates for the transferred transistors and capacitors include, in addition to the aforementioned substrates on which transistors and capacitors can be provided, paper substrates, cellophane substrates, aramid film substrates, polyimide film substrates, stone substrates, wood substrates, cloth substrates (including natural fibers (silk, cotton, linen), synthetic fibers (nylon, polyurethane, polyester), or regenerated fibers (acetate, cupro, rayon, regenerated polyester), etc.), leather substrates, and rubber substrates. By using the above-mentioned substrates, transistors with good characteristics or low power consumption can be formed, devices that are less prone to failure and have heat resistance can be manufactured, or lightweight or thin devices can be achieved.

[0084] The insulating film 108 can be formed by appropriately utilizing a sputtering method, a CVD method, an evaporation method, a pulsed laser deposition (PLD) method, a printing method, a coating method, or the like. Alternatively, the insulating film 108 can be formed using, for example, an oxide insulating film or a nitride insulating film in a single layer or a stacked layer. Furthermore, to improve the interface characteristics between the insulating film 108 and the oxide semiconductor film 110, it is preferable to form at least the region of the insulating film 108 that is in contact with the oxide semiconductor film 110 using an oxide insulating film. Furthermore, by using an oxide insulating film that releases oxygen when heated as the insulating film 108, oxygen contained in the insulating film 108 can be transferred to the oxide semiconductor film 110 by heat treatment.

[0085] The thickness of the insulating film 108 can be 50 nm or more, 100 nm or more and 3000 nm or less, or 200 nm or more and 1000 nm or less. Increasing the thickness of the insulating film 108 can increase the amount of oxygen released from the insulating film 108, and can also reduce the interface energy level density at the interface between the insulating film 108 and the oxide semiconductor film 110 and oxygen vacancies in the channel region 110 a of the oxide semiconductor film 110.

[0086] The insulating film 108 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and can be provided in a stacked layer or a single layer. In this embodiment, a silicon nitride film is used as the insulating film 108 a , and a silicon oxynitride film is used as the insulating film 108 b .

[0087] The oxide semiconductor film 110 is typically formed using a metal oxide such as In-Ga oxide, In-Zn oxide, or In-M-Zn oxide (M is Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). The oxide semiconductor film 110 is light-transmitting.

[0088] In addition, when the oxide semiconductor film 110 is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, the atomic percentages of In and M are as follows: In is greater than 25 atomic% and M is less than 75 atomic% or In is greater than 34 atomic% and M is less than 66 atomic%.

[0089] The energy gap of the oxide semiconductor film 110 is 2 eV or more, 2.5 eV or more, or 3 eV or more.

[0090] The thickness of the oxide semiconductor film 110 is greater than or equal to 3 nm and less than or equal to 200 nm, greater than or equal to 3 nm and less than or equal to 100 nm, or greater than or equal to 3 nm and less than or equal to 60 nm.

[0091] When the oxide semiconductor film 110 is an In-M-Zn oxide, the atomic ratio of the metal elements in the sputtering target used to form the In-M-Zn oxide film preferably satisfies In ≥ M and Zn ≥ M. The atomic ratio of the metal elements in the sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:1.5, In:M:Zn = 2:1:2.3, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, etc. The atomic ratio of the formed oxide semiconductor film 110 includes a ±40% variation in the atomic ratio of the metal elements in the sputtering target as an error.

[0092] When the oxide semiconductor film 110 contains silicon or carbon, which is one of the Group 14 elements, oxygen vacancies in the oxide semiconductor film 110 increase, so that the oxide semiconductor film 110 becomes n-type. Therefore, in the oxide semiconductor film 110, especially in the channel region 110a, the concentration of silicon or carbon (measured by secondary ion mass spectrometry) can be set to 2×10 18 atoms / cm 3 Below, or 2×10 17 atoms / cm 3As a result, the transistor has an electrical characteristic in which the threshold voltage becomes positive (also called a normally-off characteristic).

[0093] In addition, in the oxide semiconductor film 110, particularly in the channel region 110a, the concentration of the alkali metal or alkaline earth metal measured by secondary ion mass spectrometry can be set to 1×10 18 atoms / cm 3 Below, or 2×10 16 atoms / cm 3 When an alkali metal or alkaline earth metal bonds with an oxide semiconductor, carriers are generated, increasing the off-state current of the transistor. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the channel region 110a. As a result, the transistor has an electrical characteristic in which the threshold voltage becomes positive (also known as a normally-off characteristic).

[0094] When nitrogen is contained in the oxide semiconductor film 110, especially in the channel region 110a, electrons as carriers are sometimes generated, the carrier density increases, and the channel region 110a is converted to n-type. As a result, a transistor using an oxide semiconductor film containing nitrogen tends to have a normally-on characteristic. Therefore, in the oxide semiconductor film, especially in the channel region 110a, it is preferable to reduce nitrogen as much as possible. For example, the nitrogen concentration measured by secondary ion mass spectrometry can be set to 5×10 18 atoms / cm 3 the following.

[0095] By reducing the amount of impurity elements in the oxide semiconductor film 110, especially in the channel region 110a, the carrier density of the oxide semiconductor film can be reduced. In the oxide semiconductor film 110, especially in the channel region 110a, the carrier density can be set to 1×10 17 pieces / cm 3 Below, 1×10 15 pieces / cm 3 Below, 1×10 13 pieces / cm 3 Below, 1×10 11 pieces / cm 3 Below, or 1×10 -9 pieces / cm 3 Above and 1×10 10 pieces / cm 3 the following.

[0096] By using an oxide semiconductor film with a low impurity concentration and a low defect state density as the oxide semiconductor film 110, a transistor with better electrical characteristics can be manufactured. Here, the state with a low impurity concentration and a low defect state density (few oxygen vacancies) is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Because the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor has fewer carrier generation sources, it is possible to reduce the carrier density. Therefore, a transistor having a channel region formed in the oxide semiconductor film can easily achieve an electrical characteristic of a positive threshold voltage (also called a normally-off characteristic). Because the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density, it is possible to have a low trap state density. The off-state current of the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is significantly low. When the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1V to 10V, the off-state current can also be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 -13 A or less. Therefore, a transistor having a channel region formed in the oxide semiconductor film has less variation in electrical characteristics, and the transistor may have high reliability.

[0097] The oxide semiconductor film 110 may have a non-single-crystal structure. Examples of non-single-crystal structures include CAAC-OS (CAxis Aligned Crystalline Oxide Semiconductor), a polycrystalline structure, a microcrystalline structure, or an amorphous structure. Among non-single-crystal structures, the amorphous structure has the highest defect state density, while the CAAC-OS structure has the lowest defect state density.

[0098] Alternatively, the oxide semiconductor film 110 may be a mixed film having two or more of the following: an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. A mixed film may have, for example, a single-layer structure having two or more of the following: an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Alternatively, a mixed film may have, for example, a stacked-layer structure having two or more of the following: an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region.

[0099] In the oxide semiconductor film 110, the crystallinity of the channel region 110a may differ from that of the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i. Specifically, in the oxide semiconductor film 110, the crystallinity of the channel region 110a is higher than that of the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i. This is because when an impurity element is added to the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i, the low-resistance regions 110b, 110c, 110d, 110e, 110h, and 110i are damaged, thereby reducing the crystallinity.

[0100] The insulating film 112 can be formed using an oxide insulating film or a nitride insulating film in a single layer or a stacked layer. Furthermore, in order to improve the interface characteristics between the insulating film 112 and the oxide semiconductor film 110, it is preferable to form at least the region of the insulating film 112 that is in contact with the oxide semiconductor film 110 using an oxide insulating film. The insulating film 112 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and can be provided in a stacked layer or a single layer.

[0101] Furthermore, by providing an insulating film having a barrier effect against oxygen, hydrogen, water, and the like as the insulating film 112, oxygen can be prevented from diffusing from the oxide semiconductor film 110 to the outside, and hydrogen, water, and the like can be prevented from intruding from the outside into the oxide semiconductor film 110. Examples of the insulating film having a barrier effect against oxygen, hydrogen, water, and the like include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film.

[0102] In addition, by using hafnium silicate (HfSiO x ), nitrogen-doped hafnium silicate (HfSi x O y N z ), nitrogen-doped hafnium aluminate (HfAl x O y N z ), hafnium oxide, yttrium oxide and other high-k materials can reduce the gate leakage current of transistors.

[0103] In addition, by using an oxide insulating film that releases oxygen by heating as the insulating film 112 , oxygen contained in the insulating film 112 can be moved to the oxide semiconductor film 110 by heat treatment.

[0104] The thickness of the insulating film 112 can be, for example, greater than or equal to 5 nm and less than or equal to 400 nm, greater than or equal to 5 nm and less than or equal to 300 nm, or greater than or equal to 10 nm and less than or equal to 250 nm.

[0105] The conductive films 114, 116, 122, 124, and 126 can be formed using a sputtering method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, a thermal CVD method, or the like. The conductive films 114, 116, 122, 124, and 126 can be formed using, for example, a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, an alloy containing these metal elements, or an alloy combining these metal elements. Alternatively, one or more metal elements selected from manganese and zirconium can be used. The conductive films 114, 116, 122, 124, and 126 can have a single-layer structure or a stacked-layer structure of two or more layers. For example, there can be mentioned a single-layer structure of an aluminum film containing silicon, a single-layer structure of a copper film containing manganese, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, a two-layer structure in which a copper film is stacked on a copper film containing manganese, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and a three-layer structure in which a copper film containing manganese, a copper film, and a copper film containing manganese are stacked in this order. In addition, an alloy film or a nitride film formed by combining aluminum with one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can also be used.

[0106] The conductive films 114 and 116 are formed at the same time and thus have the same material and the same stacked structure. The conductive films 122, 124, and 126 are formed at the same time and thus have the same material and the same stacked structure.

[0107] Conductive films 114, 116, 122, 124, and 126 may also be formed using a light-transmitting conductive material such as indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide containing silicon oxide. Alternatively, a stacked structure of the above-mentioned light-transmitting conductive materials and the above-mentioned metal elements may be used.

[0108] The thickness of the conductive films 114 , 116 , 122 , 124 , and 126 can be, for example, greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

[0109] A nitride insulating film is used as the insulating film 118. The nitride insulating film can be formed using silicon nitride, silicon nitride oxide, aluminum nitride, aluminum nitride oxide, or the like. The hydrogen concentration of the insulating film 118 is preferably 1×10 22 atoms / cm 3Furthermore, the insulating film 118 is in contact with the low-resistance region of the oxide semiconductor film 110. Thus, hydrogen contained in the insulating film 118 diffuses into the low-resistance region of the oxide semiconductor film 110 within the oxide semiconductor film 110, so that the hydrogen concentration in the low-resistance region is higher than that in the channel region of the oxide semiconductor film 110.

[0110] The insulating film 120 can be formed using an oxide insulating film or a nitride insulating film in a single layer or a stacked layer. For example, the insulating film 120 can be formed using silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga—Zn oxide, and can be provided in a single layer or a stacked layer.

[0111] The insulating film 128 preferably has a function of blocking hydrogen, water, etc. from the outside. The insulating film 128 can be made of, for example, silicon nitride, silicon nitride oxide, aluminum oxide, or the like, and can be provided as a single layer or a stacked layer.

[0112] The thickness of each of the insulating film 118 , the insulating film 120 , and the insulating film 128 can be greater than or equal to 30 nm and less than or equal to 500 nm, or greater than or equal to 100 nm and less than or equal to 400 nm.

[0113] <Structure of Semiconductor Device 2> Next, refer to Figures 5A to 5D and Figure 6 Explain in detail Figures 1A to 1D Other structures of the semiconductor device shown.

[0114] Figure 5A is a top view of a transistor 100A included in a semiconductor device. Figure 5B is a top view of a capacitor element 150A included in the semiconductor device. Figure 5C It is along Figure 5A The cross-sectional view along the dot-dash line X1-X2, Figure 5D It is along Figure 5B Cross-sectional view along the dotted line X3-X4.

[0115] Figure 5A and 5CThe transistor 100A shown includes: an insulating film 104 formed on a substrate 102: a conductive film 106 on the insulating film 104; an insulating film 108 on the insulating film 104 and the conductive film 106; an oxide semiconductor film 110 overlapping with the conductive film 106 via the insulating film 108; an insulating film 112 on the oxide semiconductor film 110; a conductive film 114 overlapping with the oxide semiconductor film 110 via the insulating film 112; an insulating film 118 covering the oxide semiconductor film 110, the insulating film 112 and the conductive film 114; an insulating film 120 on the insulating film 118; a conductive film 122 connected to the oxide semiconductor film 110 through an opening 140a provided in the insulating film 118 and the insulating film 120; and a conductive film 124 connected to the oxide semiconductor film 110 through an opening 140b provided in the insulating film 118 and the insulating film 120. Furthermore, an insulating film 128 covering the insulating film 120 , the conductive film 122 , and the conductive film 124 may be provided over the transistor 100A.

[0116] exist Figure 5C 1 , the conductive film 106 has a stacked-layer structure comprising a conductive film 106a and a conductive film 106b on the conductive film 106a. The insulating film 108 has a stacked-layer structure comprising an insulating film 108a and an insulating film 108b on the insulating film 108a. The conductive film 114 has a stacked-layer structure comprising a conductive film 114a and a conductive film 114b on the conductive film 114a. The conductive film 122 has a stacked-layer structure comprising a conductive film 122a and a conductive film 122b on the conductive film 122a. The conductive film 124 has a stacked-layer structure comprising a conductive film 124a and a conductive film 124b on the conductive film 124a.

[0117] In the transistor 100A, the conductive film 106 functions as a first gate electrode (also referred to as a bottom gate electrode), the conductive film 114 functions as a second gate electrode (also referred to as a top gate electrode), the conductive film 122 functions as one of a source electrode and a drain electrode, and the conductive film 124 functions as the other of the source electrode and the drain electrode. Furthermore, in the transistor 100A, the insulating film 108 functions as a first gate insulating film, and the insulating film 112 functions as a second gate insulating film.

[0118] exist Figure 5A and 5C The transistor 100A shown has a structure having conductive films serving as gate electrodes above and below the oxide semiconductor film 110, which differs from the transistor 100 described above. As shown in the transistor 100A, the semiconductor device of one embodiment of the present invention may have two or more gate electrodes.

[0119] also, Figure 5B and 5DThe illustrated capacitor element 150A includes an insulating film 104 formed on a substrate 102; an insulating film 108 on the insulating film 104; an insulating film 112 on the insulating film 108; a conductive film 116 on the insulating film 112; an insulating film 118 covering the insulating film 108, the insulating film 112, and the conductive film 116; an insulating film 120 on the insulating film 118; and a conductive film 126 overlapping the conductive film 116 via the insulating film 118 in an opening 140c provided in the insulating film 120. Alternatively, an insulating film 128 covering the insulating film 120 and the conductive film 126 may be provided on the capacitor element 150A.

[0120] exist Figure 5D 1 , the insulating film 108 has a stacked-layer structure of an insulating film 108a and an insulating film 108b on the insulating film 108a. The conductive film 116 has a stacked-layer structure of a conductive film 116a and a conductive film 116b on the conductive film 116a. The conductive film 126 has a stacked-layer structure of a conductive film 126a and a conductive film 126b on the conductive film 126a.

[0121] Capacitor element 150A has a structure in which a dielectric is sandwiched between a pair of electrodes. More specifically, one of the pair of electrodes is a conductive film 116, the other of the pair of electrodes is a conductive film 126, and an insulating film 118 between conductive films 116 and 126 serves as a dielectric.

[0122] The conductive film 114 serving as the second gate electrode of the transistor 100A and the conductive film 116 serving as one of the pair of electrodes of the capacitor 150A are formed by the same process, and at least a portion of them are formed on the same surface. The conductive films 122 and 124 serving as the source and drain electrodes of the transistor 100A, and the conductive film 126 serving as the other of the pair of electrodes of the capacitor 150A are formed by the same process, and at least a portion of them are formed on the same surface.

[0123] In this manner, by forming the conductive films serving as the electrodes of the transistor 100A and the capacitor 150A in the same process, manufacturing costs can be reduced.

[0124] Furthermore, in capacitor element 150A, insulating film 120 has opening 140c. This allows insulating film 118 to function solely as a dielectric in the stack of insulating films 118 and 120. This structure increases the capacitance of capacitor element 150A, thereby increasing the capacitance of the display device.

[0125] then, Figure 6 Shown along Figure 5A FIG. 1 is a cross-sectional view of the transistor 100A taken along the dashed line Y3 - Y4 (in the channel width direction).

[0126] like Figure 6 As shown, the conductive film 114 serving as the second gate electrode is connected to the conductive film 106 serving as the first gate electrode through an opening 139 provided in the insulating film 108 and the insulating film 112. Thus, the conductive film 114 and the conductive film 106 are supplied with the same potential. Alternatively, a structure may be employed in which the opening 139 is not provided and the conductive film 114 and the conductive film 106 are not connected. Even when the conductive film 114 and the conductive film 106 are not connected, different potentials can be supplied to the conductive film 114 and the conductive film 106.

[0127] like Figure 6 As shown, the oxide semiconductor film 110 is disposed opposite the conductive film 106 serving as the first gate electrode and the conductive film 114 serving as the second gate electrode, sandwiching the two conductive films serving as gate electrodes. The conductive film 114 serving as the second gate electrode is longer in the channel width direction than the oxide semiconductor film 110, and the entire oxide semiconductor film 110 in the channel width direction is covered by the conductive film 114 with the insulating film 112 interposed therebetween. The conductive film 114 serving as the second gate electrode and the conductive film 106 serving as the first gate electrode are connected to each other through the openings 139 in the insulating films 108 and 112. As a result, one of the side surfaces of the oxide semiconductor film 110 in the channel width direction faces the conductive film 114 serving as the second gate electrode with the insulating film 112 interposed therebetween.

[0128] In other words, in the channel width direction of the transistor 100A, while the conductive film 106 serving as the first gate electrode and the conductive film 114 serving as the second gate electrode are connected to each other in the opening portions in the insulating film 108 serving as the first gate insulating film and the insulating film 112 serving as the second gate insulating film, the oxide semiconductor film 110 is surrounded by the insulating film 108 serving as the first gate insulating film and the insulating film 112 serving as the second gate insulating film.

[0129] By adopting the above structure, the oxide semiconductor film 110 included in the transistor 100A can be electrically surrounded by the electric field of the conductive film 106 serving as the first gate electrode and the conductive film 114 serving as the second gate electrode. As shown in the transistor 100A, the device structure of the above transistor can be called a surrounded channel structure (s-channel structure). The s-channel structure is as follows: the oxide semiconductor film having a channel region is electrically surrounded by the electric field of the first gate electrode and the second gate electrode.

[0130] The transistor 100A has an s-channel structure. Therefore, the conductive film 106 used as the first gate electrode or the conductive film 114 used as the second gate electrode can efficiently apply an electric field for moving electrons to the oxide semiconductor film 110, thereby improving the current driving capability of the transistor 100A and obtaining a high on-state current characteristic. In addition, because the on-state current can be increased, the transistor 100A can be miniaturized. In addition, the transistor 100A adopts a structure in which the oxide semiconductor film 110 is surrounded by the conductive film 106 used as the first gate electrode and the conductive film 114 used as the second gate electrode, thereby improving the mechanical strength of the transistor 100A.

[0131] In the channel width direction of the transistor 100A, an opening different from the opening 139 may be formed in the side surface of the oxide semiconductor film 110 where the opening 139 is not formed.

[0132] The insulating film 104 included in the transistor 100A and the capacitor 150A can use the same material as that of the insulating film 108. Here, a 100 nm-thick silicon nitride film is formed as the insulating film 104 using a PECVD apparatus.

[0133] The conductive film 106 included in the transistor 100A can use the same material as that of the conductive films 114, 122, and 124. Here, a 10-nm-thick tantalum nitride film is formed as the conductive film 106a using a sputtering apparatus, and a 300-nm-thick copper film is formed as the conductive film 106b using a sputtering apparatus.

[0134] Next, refer to 7A to 11A Explain in detail Figures 1A to 1D as well as Figures 5A to 5D Other structures of the semiconductor device shown. Note that 7A to 11A The semiconductor device shown is Figures 5A to 5D A modified example of the semiconductor device shown.

[0135] Figure 7A 1 is a cross-sectional view of a transistor 100B included in the semiconductor device. Figure 7B A cross-sectional view of a capacitor 150B included in a semiconductor device is shown. Note that the top views of the transistor 100B and the capacitor 150B are shown in FIG. Figure 5A and 5B The top view shown is the same and is omitted here. Figure 7C The transistor 100C shown, Figure 7D The capacitor element 150C shown, Figure 8A The transistor 100D shown, Figure 8B The capacitor element 150D shown, Figure 8C The transistor 100E shown, Figure 8D The capacitive element 150E shown, Figure 9A The transistor 100F shown, Figure 9B The capacitor element 150F shown, Figure 9C The transistor 100G shown, Figure 9D The top view of the capacitor element 150G is also shown with Figure 5A and 5B The top views shown are the same and are omitted here.

[0136] In addition, 7A to 11A In the illustrated structures, components having the same functions as those described above may be denoted by the same hatching without being specifically labeled.

[0137] <Structure of Semiconductor Device 3> Figure 7A The transistor 100B is shown with Figure 5C The difference between the transistor 100A shown in the figure lies in the shape of the conductive film 114. Specifically, the conductive film 114 of the transistor 100B has a stacked structure comprising a conductive film 114a and a conductive film 114b on the conductive film 114a. The lower end of the conductive film 114a is aligned or substantially aligned with the upper end of the insulating film 112, and the lower end of the conductive film 114b is located inward of the upper end of the conductive film 114a. A portion of the end of the conductive film 114b has an arc shape.

[0138] Figure 7B The capacitive element 150B is shown with Figure 5D The capacitor element 150A shown differs in the shape of the conductive film 116. Specifically, the conductive film 116 included in the capacitor element 150B has a stacked structure of a conductive film 116a and a conductive film 116b on the conductive film 116a, wherein the lower end of the conductive film 116a is aligned or substantially aligned with the upper end of the insulating film 112, and the lower end of the conductive film 116b is located inside the upper end of the conductive film 116a.

[0139] By adopting Figure 7A 、 7B The shapes of the insulating film 112 and / or the conductive films 114 and 116 shown can improve the coverage of the insulating film 118 .

[0140] <Structure of Semiconductor Device 4> Figure 7C The transistor 100C is shown with Figure 5CThe difference between the transistor 100A shown in the figure lies in the shape of the insulating film 112. Specifically, in the insulating film 112 included in the transistor 100C, the lower end and the upper end of the insulating film 112 are located outside the lower end of the conductive film 114. That is, the transistor 100C has the insulating film 112 extending outside the conductive film 114. By adopting Figure 7C The shape of the insulating film 112 shown can separate the channel region of the oxide semiconductor film 110 from the insulating film 118 , thereby preventing nitrogen, hydrogen, and the like contained in the insulating film 118 from entering the channel region of the oxide semiconductor film 110 .

[0141] Figure 7D The capacitive element 150C is shown with Figure 5D The capacitor 150A shown is different in the shape of the insulating film 112. Specifically, in the capacitor 150C, the lower and upper ends of the insulating film 112 are located outside the lower end of the conductive film 116.

[0142] By adopting Figure 7C 、 7D The shape of the insulating film 112 shown can improve the coverage of the insulating film 118.

[0143] <Structure of Semiconductor Device 5> Figure 8A The transistor 100D is shown with Figure 5C The difference between the transistor 100A shown in FIG. 1 and FIG. 1 is the structure of the insulating film 108 and the insulating film 112. Specifically, Figure 8A The insulating film 108 of the transistor 100D shown in FIG. 1 has a stacked structure of insulating films 108a, 108b, and 108c. Figure 8A The insulating film 112 included in the transistor 100D shown has a stacked-layer structure of an insulating film 112 a and an insulating film 112 b .

[0144] Figure 8B The capacitive element 150D is shown with Figure 5D The difference between the capacitor element 150A shown is the structure of the insulating film 108 and the insulating film 112. Specifically, Figure 8B The insulating film 108 of the capacitor element 150D shown in FIG. 1 has a stacked structure of insulating films 108a, 108b, and 108c. Figure 8B The insulating film 112 included in the illustrated capacitor 150D has a stacked-layer structure of an insulating film 112 a and an insulating film 112 b .

[0145] Figure 8A and 8BThe insulating film 108c and the insulating film 112a shown can be formed using an oxide insulating film having a low energy level density of nitride oxide. Note that the energy level density of the nitride oxide may sometimes be formed at the energy level of the valence band top (E v _ os ) and the energy of the conduction band bottom (E c _ os ) between the top of the valence band. v _ os ) and the energy of the conduction band bottom (E c _ os ) can be used as an oxide insulating film having a low energy level density of nitride oxide between the insulating film and the insulating film. A silicon oxynitride film or an aluminum oxynitride film with a low amount of nitride oxide released can be used. Furthermore, the average film thickness of the insulating film 108 c and the insulating film 112 a is greater than or equal to 0.1 nm and less than or equal to 50 nm, or greater than or equal to 0.5 nm and less than or equal to 10 nm.

[0146] In addition, in thermal desorption spectroscopy (TDS), a silicon oxynitride film that releases less nitrogen oxides is a film that releases more ammonia than nitrogen oxides. Typically, the ammonia release is 1×10 18 pieces / cm 3 Above and 5×10 19 pieces / cm 3 Note that the amount of ammonia released is the amount released when the film surface temperature is heated to a temperature of 50° C. to 650° C., preferably 50° C. to 550° C.

[0147] The insulating films 108b and 112b can be formed using an oxide insulating film that releases oxygen by heating. The insulating films 108b and 112b have an average thickness of 5 nm to 1000 nm, or 10 nm to 500 nm.

[0148] Typical examples of oxide insulating films that release oxygen by heating include silicon oxynitride films, aluminum oxynitride films, and the like.

[0149] Nitrogen oxides (NO x, x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO2 or NO, forms an energy level in the insulating film 108 and the insulating film 112. This energy level is located in the energy gap of the oxide semiconductor film 110. Therefore, when nitrogen oxide diffuses at the interface between the insulating film 108 and the oxide semiconductor film 110, the interface between the insulating film 112 and the oxide semiconductor film 110, and the interface between the insulating film 108 and the insulating film 112, this energy level sometimes captures electrons on one side of the insulating films 108 and 112. As a result, the captured electrons remain near the interface between the insulating film 108, the insulating film 112, and the oxide semiconductor film 110, thereby causing the threshold voltage of the transistor to drift in the positive direction.

[0150] Furthermore, during heat treatment, nitrogen oxides react with ammonia and oxygen. During heat treatment, nitrogen oxides contained in the insulating films 108 b and 112 b react with ammonia contained in the insulating films 108 c and 112 a, thereby reducing the amount of nitrogen oxides contained in the insulating films 108 b and 112 b. Consequently, electrons are less likely to be trapped at the interfaces between the insulating film 108 and the oxide semiconductor film 110, the interfaces between the insulating film 112 and the oxide semiconductor film 110, and the interfaces between the insulating films 108 and 112.

[0151] By using the energy at the top of the valence band (E v _ os ) and the energy of the conduction band bottom (E c _ os ) as insulating films 108c and 112a, which can reduce the drift of the threshold voltage of the transistor and thus reduce the variation of the electrical characteristics of the transistor.

[0152] By performing a heat treatment during the transistor manufacturing process, typically at a temperature of 300°C or higher but below the substrate strain point, the ESR spectrum of the insulating films 108 and 112 measured at an ESR temperature of 100K or lower is observed to include: a first signal with a g value of 2.037 to 2.039; a second signal with a g value of 2.001 to 2.003; and a third signal with a g value of 1.964 to 1.966. In the X-band ESR measurement, the splitting widths between the first and second signals, and between the second and third signals, are approximately 5 mT. Furthermore, the sum of the spin densities of the first signal with a g value of 2.037 to 2.039, the second signal with a g value of 2.001 to 2.003, and the third signal with a g value of 1.964 to 1.966 is less than 1×10 18 spins / cm 3 , typically 1×10 17 spins / cm 3 Above and below 1×1018 spins / cm 3 .

[0153] In the ESR spectrum at 100K or lower, a first signal having a g value of 2.037 to 2.039, a second signal having a g value of 2.001 to 2.003, and a third signal having a g value of 1.964 to 1.966 correspond to signals caused by nitrogen oxides (NOx, where x is 0 to 2, preferably 1 to 2). Typical examples of nitrogen oxides include nitric oxide and nitrogen dioxide. That is, the smaller the total number of spin densities of the first signal having a g value of 2.037 to 2.039, the second signal having a g value of 2.001 to 2.003, and the third signal having a g value of 1.964 to 1.966, the lower the nitrogen oxide content in the oxide insulating film.

[0154] In addition, the oxide insulating film containing nitrogen and having a small amount of defects is a film having a nitrogen concentration of 6×10 20 atoms / cm 3 The following membrane.

[0155] By forming an oxide insulating film containing nitrogen and having a low defect content by a PECVD method using silane and nitrous oxide at a substrate temperature of 220° C. or higher, 280° C. or higher, or 350° C. or higher, a dense and high-hardness film can be formed.

[0156] <Structure of Semiconductor Device 6> Figure 8C The transistor 100E is shown with Figure 5C The transistor 100A shown differs in the shapes of the insulating film 112 and the conductive film 114. Specifically, in the transistor 100E, the insulating film 112 has a partially arcuate end. Furthermore, the lower and upper ends of the conductive film 114a are located inward of the upper end of the insulating film 112. The lower end of the conductive film 114b is located inward of the upper end of the conductive film 114a. The ends of the conductive films 114a and 114b also have partially arcuate ends.

[0157] Figure 8D The capacitive element 150E shown is Figure 5D Capacitor element 150A shown differs in the shapes of insulating film 112 and conductive film 116. Specifically, in capacitor element 150E, a portion of the end of insulating film 112 has an arcuate shape. Furthermore, the lower and upper ends of conductive film 116a are located inward of the upper end of insulating film 112. The lower end of conductive film 116b is located inward of the upper end of conductive film 116a. Portions of the ends of conductive films 116a and 116b have an arcuate shape.

[0158] <Structure of Semiconductor Device 7> Figure 9A The transistor 100F is shown with Figure 5C The transistor 100A shown differs from the transistor 100F in the shapes of the insulating film 112 and the conductive film 114. Specifically, the insulating film 112 and the conductive film 114 of the transistor 100F have rectangular cross-sections. Furthermore, the transistor 100F includes the insulating film 117 between the oxide semiconductor film 110 and the insulating film 118.

[0159] Figure 9B The capacitive element 150F is shown with Figure 5D Capacitor 150A shown differs in the shapes of insulating film 112 and conductive film 116. Specifically, capacitor 150F also has insulating film 112 and conductive film 116 that are rectangular in cross-section. Furthermore, capacitor 150F includes insulating film 117 between conductive film 116 and insulating film 118.

[0160] Figure 9A and 9B The insulating film 117 shown may be used Figure 8A and 8B The oxide insulating film described in the transistor 100D and the capacitor 150D shown in the figure is formed. This oxide insulating film can be used for the insulating films 108c and 112a, contains nitrogen, and has a small amount of defects.

[0161] When the transistor 100F has Figure 9A When the shape shown in FIG. 1 is used, the shape of the low resistance region formed in the oxide semiconductor film 110 may be Figure 10 The structure shown.

[0162] Figure 10 yes Figure 9A FIG. 1 is an enlarged view of the vicinity of the oxide semiconductor film 110 of the transistor 100F. Figure 10 As shown in FIG. 1 , in the cross-sectional shape of the oxide semiconductor film 110 in the channel length direction, a region (low resistance region) is formed in which the conductivity is improved due to the increase in the carrier density of the oxide semiconductor film. Figure 10 In FIG, the channel length L is the length of the region sandwiched between a pair of low-resistance regions.

[0163] In the cross-sectional shape along the channel length direction, Figure 10The oxide semiconductor film 110 shown includes a low-resistance region 110d between the channel region 110a and the low-resistance region 110b, and a low-resistance region 110e between the channel region 110a and the low-resistance region 110c. The impurity element concentration in the low-resistance regions 110d and 110e is lower than that in the low-resistance regions 110b and 110c, and the resistivity in the low-resistance regions 110d and 110e is higher than that in the low-resistance regions 110b and 110c. Note that the low-resistance regions 110d and 110e overlap with the insulating film 117 that contacts the side surfaces of the insulating film 112 and the conductive film 114. Here, the low-resistance regions 110d and 110e may also overlap with the insulating film 112 and the conductive film 114.

[0164] The oxide semiconductor film 110 includes low-resistance regions 110d and 110e, which have a lower impurity concentration and a higher resistivity than the low-resistance regions 110b and 110c. This can mitigate the electric field in the drain region. This can reduce fluctuations in the threshold voltage of the transistor caused by the electric field in the drain region.

[0165] <Structure of Semiconductor Device 8> Figure 9C The transistor 100G is shown with Figure 5C The transistor 100A shown differs in the shapes of the insulating film 112 and the oxide semiconductor film 110. Specifically, the insulating film 112 included in the transistor 100G has two film thicknesses: one for the region overlapping with the conductive film 114, and the other for the region not overlapping with the conductive film 114. The film thickness of the region not overlapping with the conductive film 114 is thinner than that of the region overlapping with the conductive film 114. Furthermore, the insulating film 112 covers the oxide semiconductor film 110, so that the film thickness is substantially uniform throughout the entire portion of the oxide semiconductor film 110.

[0166] Figure 9D The capacitive element 150G is shown with Figure 5D The capacitor element 150A shown is different in the shape of the insulating film 112. Specifically, the insulating film 112 included in the capacitor element 150G has two film thicknesses: one is the film thickness of the region overlapping with the conductive film 116, and the other is the film thickness of the region not overlapping with the conductive film 116. The film thickness of the region not overlapping with the conductive film 116 is thinner than that of the region overlapping with the conductive film 116.

[0167] As a formation Figure 9C and 9D As a method for forming the insulating film 112 shown, for example, a method is exemplified in which, after processing the conductive film 114 , the insulating film 112 is removed so as to leave a region of the insulating film 112 that does not overlap with the conductive film 114 .

[0168] exist Figure 9C In the transistor 100G shown, the insulating film 112 is in contact with the channel region 110a and the low-resistance regions 110b and 110c of the oxide semiconductor film 110. Furthermore, the film thickness of the insulating film 112 in the region in contact with the low-resistance regions 110b and 110c is thinner than that in the region in contact with the channel region 110a. Typically, the average film thickness of the insulating film 112 is greater than or equal to 0.1 nm and less than or equal to 50 nm, or greater than or equal to 0.5 nm and less than or equal to 10 nm. As a result, impurity elements can be added to the oxide semiconductor film 110 through the insulating film 112, and hydrogen contained in the insulating film 118 can be transferred into the oxide semiconductor film 110 through the insulating film 112. Consequently, the low-resistance regions 110b and 110c can be formed.

[0169] By using an oxide insulating film containing nitrogen and having a low defect content as the insulating film 112, nitrogen oxides are less likely to form in the insulating film 112, thereby reducing carrier trapping at the interface between the insulating film 112 and the oxide semiconductor film 110. As a result, the drift of the threshold voltage of the transistor can be reduced, thereby reducing variations in the electrical characteristics of the transistor.

[0170] Furthermore, the insulating film 108 has a multilayer structure comprising an insulating film 108a, an insulating film 108b, and an insulating film 108c. For example, the insulating film 108a may be formed using a nitride insulating film, the insulating film 108b may be formed using a silicon oxynitride film that releases oxygen upon heating, and the insulating film 108c may be formed using an oxide insulating film containing nitrogen and having few defects. Furthermore, the insulating film 112 may be formed using an oxide insulating film containing nitrogen and having few defects. In other words, the oxide semiconductor film 110 may be covered with an oxide insulating film containing nitrogen and having few defects. As a result, oxygen contained in the insulating film 108b migrates to the oxide semiconductor film 110 upon heat treatment, thereby reducing oxygen vacancies in the channel region 110a of the oxide semiconductor film 110. This also reduces carrier traps at the interfaces between the insulating films 108c and 112 and the oxide semiconductor film 110. Consequently, the shift in the threshold voltage of the transistor can be reduced, thereby reducing variations in the electrical characteristics of the transistor.

[0171] <Structure of Semiconductor Device 9> Figure 11A The transistor 100H is shown with Figure 5C The transistor 100A shown is different in the structure of the oxide semiconductor film 110. Specifically, the oxide semiconductor film 110 included in the transistor 100H includes an oxide semiconductor film 110_1 and an oxide semiconductor film 110_2 in contact with the oxide semiconductor film 110_1. That is, the oxide semiconductor film 110 has a multilayer structure.

[0172] Figure 11A The oxide semiconductor film 110 of the transistor 100H shown includes the low resistance region described above. Specifically, the oxide semiconductor film 110 of the transistor 100H includes a channel region 110a_1, a channel region 110a_2, a low resistance region 110b_1, a low resistance region 110b_2, a low resistance region 110c_1, and a low resistance region 110c_2.

[0173] Energy Band Diagram Here, Figure 11B The energy band diagram of the AB cross section including the channel region of the transistor 100H is shown. Furthermore, the energy gap of the oxide semiconductor film 110_2 is larger than that of the oxide semiconductor film 110_1. The energy gaps of the insulating films 108a, 108b, and 112 are larger than those of the oxide semiconductor films 110_1 and 110_2. Furthermore, the Fermi levels (denoted as Ef) of the oxide semiconductor film 110_1, the oxide semiconductor film 110_2, the insulating films 108a, 108b, and the insulating film 112 are located at the positions of the intrinsic Fermi levels (denoted as Ei). The work functions of the conductive films 106 and 114 are the same as this Fermi level.

[0174] When the gate voltage is set to a value equal to or higher than the threshold voltage of the transistor, electrons flow preferentially through the oxide semiconductor film 110_1 due to the energy difference at the bottom of the conduction band between the oxide semiconductor film 110_1 and the oxide semiconductor film 110_2. In other words, it can be estimated that electrons are buried in the oxide semiconductor film 110_1. Note that the energy at the bottom of the conduction band is represented as Ec, and the energy at the top of the valence band is represented as Ev.

[0175] Thus, in the transistor according to one embodiment of the present invention, the influence of interface scattering can be reduced by embedding electrons. Therefore, the transistor according to one embodiment of the present invention has low channel resistance.

[0176] then, Figure 11C The energy band diagram for a CD cross section including the source or drain region of a transistor is shown. Note that the low-resistance region 110c_1 and the low-resistance region 110c_2 are in a degenerate state. Furthermore, in the low-resistance region 110c_1, the Fermi level of the oxide semiconductor film 110_1 is equal to the energy of the conduction band bottom. In the low-resistance region 110c_2, the Fermi level of the oxide semiconductor film 110_2 is equal to the energy of the conduction band bottom.

[0177] At this point, the potential barrier between the conductive film 124 (which functions as a source or drain electrode) and the low-resistance region 110 c_2 is sufficiently low, so the conductive film 124 and the low-resistance region 110 c_2 are in ohmic contact. The low-resistance region 110 c_2 is also in ohmic contact with the low-resistance region 110 c_1. This indicates that electron transfer is smooth between the conductive film 124 and the oxide semiconductor films 110_1 and 110_2.

[0178] In the region where the conductive film 122 having one of the functions of a source electrode and a drain electrode is in contact with the low-resistance region 110b_1 and the low-resistance region 110b_2 of the oxide semiconductor film 110, the conductive film 122 may be connected to the low-resistance region 110b_2 of the oxide semiconductor film 110. Figure 11C The same description is given.

[0179] As described above, the transistor according to one embodiment of the present invention is a transistor in which electron transfer between the source electrode and the drain electrode and the channel region is smooth and the channel resistance is low. In other words, it is known that the transistor has excellent switching characteristics.

[0180] <Connection Portions and Intersections of Conductive Films in Semiconductor Devices> Next, refer to Figures 30A to 30D illustrate Figures 5A to 5D The semiconductor device according to one embodiment of the present invention has structures of connection portions and intersection portions of conductive films. Figures 30A to 30C A cross-sectional view showing the structure of the connection portion of each conductive film, Figure 30D A cross-sectional view showing the structure of an intersection of two conductive films.

[0181] Figure 30A The connecting portion shown includes: an insulating film 104 on a substrate 102; a conductive film 306 on the insulating film 104; an insulating film 108 covering the conductive film 306; an insulating film 112 on the insulating film 108; a conductive film 314 arranged on the insulating film 112 and connected to the conductive film 306 in an opening 352 arranged in the insulating film 112 and the insulating film 108; an insulating film 118 covering the insulating films 108, 112 and the conductive film 314; an insulating film 120 on the insulating film 118; a conductive film 318 arranged on the insulating film 120 and connected to the conductive film 314 in an opening 353 arranged in the insulating film 118 and the insulating film 120; and an insulating film 128 covering the insulating film 120 and the conductive film 318.

[0182] Figure 30BThe connecting portion shown includes: an insulating film 104 on the substrate 102; an insulating film 108 on the insulating film 104; an insulating film 112 on the insulating film 108; a conductive film 324 on the insulating film 112; an insulating film 118 covering the insulating films 108, 112 and the conductive film 324; an insulating film 120 on the insulating film 118; a conductive film 328 arranged on the insulating film 120 and placed in the opening 354 in the insulating film 118 and the insulating film 120 and connected to the conductive film 324; and an insulating film 128 covering the insulating film 120 and the conductive film 328.

[0183] Figure 30C The connecting portion shown includes: an insulating film 104 on a substrate 102; a conductive film 316 on the insulating film 104; an insulating film 108 covering the conductive film 316; an insulating film 112 on the insulating film 108; a conductive film 334 arranged on the insulating film 112 and connected to the conductive film 316 in an opening 355 arranged in the insulating film 112 and the insulating film 108; an insulating film 118 covering the insulating film 108 and the conductive film 334; an insulating film 120 on the insulating film 118; and an insulating film 128 on the insulating film 120.

[0184] Figure 30D The intersection shown includes: insulating film 104 on substrate 102; conductive film 326 on insulating film 104; insulating film 108 covering conductive film 326; insulating film 118 on insulating film 108; insulating film 120 on insulating film 118; conductive film 338 on insulating film 120; and insulating film 128 on conductive film 338.

[0185] exist Figures 30A to 30D In FIG, the insulating film 108 has a stacked structure of an insulating film 108a and an insulating film 108b on the insulating film 108a. Figure 30A In the embodiment, the conductive film 306 has a stacked structure of a conductive film 306a and a conductive film 306b on the conductive film 306a, the conductive film 314 has a stacked structure of a conductive film 314a and a conductive film 314b on the conductive film 314a, and the conductive film 318 has a stacked structure of a conductive film 318a and a conductive film 318b on the conductive film 318a. Figure 30B In FIG, the conductive film 324 has a stacked structure of a conductive film 324a and a conductive film 324b on the conductive film 324a, and the conductive film 328 has a stacked structure of a conductive film 328a and a conductive film 328b on the conductive film 328a. Figure 30C In FIG, the conductive film 316 has a stacked structure of a conductive film 316a and a conductive film 316b on the conductive film 316a, and the conductive film 334 has a stacked structure of a conductive film 334a and a conductive film 334b ​​on the conductive film 334a. Figure 30DIn FIG. 3 , the conductive film 326 has a stacked-layer structure of a conductive film 326a and a conductive film 326b on the conductive film 326a, and the conductive film 338 has a stacked-layer structure of a conductive film 338a and a conductive film 338b on the conductive film 338a.

[0186] Conductive films 306, 316, and 326 are formed using the same process as the conductive film 106 of transistor 100A. That is, at least portions of the conductive films 106, 306, 316, and 326 are formed on the same surface. Furthermore, conductive films 314, 324, and 334 are formed using the same process as the conductive film 114 of transistor 100A and the conductive film 116 of capacitor 150A. That is, at least portions of the conductive films 114, 116, 314, 324, and 334 are formed on the same surface. Furthermore, conductive films 318, 328, and 338 are formed using the same process as the conductive films 122 and 124 of transistor 100A and the conductive film 126 of capacitor 150A. That is, at least portions of the conductive films 124, 126, 318, 328, and 338 are formed on the same surface.

[0187] like Figure 30D As shown in FIG. 1 , insulating films 108, 118, and 120 are provided between the conductive film 326 and the conductive film 338. That is, a plurality of insulating films are stacked between the conductive film 326 and the conductive film 338. Figure 30D The structure of the intersection of the conductive films shown above can reduce parasitic capacitance in the intersection of the conductive films, thereby reducing signal delay caused by parasitic capacitance.

[0188] <Method 1 for manufacturing a semiconductor device> Next, refer to Figures 12A to 16F illustrate Figures 1A to 1D An example of a method for manufacturing the transistor 100 and the capacitor 150 is shown.

[0189] The film (insulating film, oxide semiconductor film, conductive film, etc.) constituting the transistor 100 and the capacitor 150 can be formed by sputtering, chemical vapor deposition (CVD), vacuum evaporation, pulsed laser deposition (PLD). Alternatively, it can be formed by a coating method or a printing method. As typical film forming methods, there are sputtering and plasma chemical vapor deposition (PECVD), but thermal CVD can also be used. As an example of thermal CVD, MOCVD (metal organic chemical vapor deposition) or ALD (atomic layer deposition) can be used.

[0190] Thermal CVD deposition can be performed by setting the pressure within the process chamber to atmospheric pressure or reduced pressure, simultaneously supplying source gases and an oxidant into the process chamber, and allowing them to react with each other near or on the substrate, resulting in deposition on the substrate. Since thermal CVD forms films without generating plasma, it has the advantage of not causing defects due to plasma damage.

[0191] In addition, deposition by the ALD method can be performed as follows: the pressure in the processing chamber is set to atmospheric pressure or reduced pressure, the source gases for the reaction are introduced into the processing chamber in sequence, and then the gases are repeatedly introduced in this order. For example, two or more source gases are supplied into the processing chamber in sequence by switching respective switching valves (also called high-speed valves). In this case, an inert gas (argon or nitrogen, etc.) is introduced at the same time as or after the first source gas is introduced in a manner that prevents the mixing of multiple source gases, and then the second source gas is introduced. Note that when the first source gas and the inert gas are introduced at the same time, the inert gas is used as a carrier gas, and the inert gas can also be introduced at the same time as the second source gas is introduced. In addition, the first source gas can be discharged by vacuum pumping without introducing an inert gas, and then the second source gas can be introduced. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer; then the second source gas is introduced to react with the first monoatomic layer; as a result, the second monoatomic layer is stacked on the first monoatomic layer to form a thin film.

[0192] By repeatedly introducing the gases in this order until the desired thickness is achieved, a thin film with good step coverage can be formed. The film thickness can be adjusted by the number of times the gases are introduced in this order. Therefore, the ALD method allows for precise thickness control, making it suitable for manufacturing micro-transistors.

[0193] also, Figure 12A 、 12C 、12E、12G、 Figure 13A 、 13C 、13E、 Figure 14A 、 14C 、14E、 Figure 15A 、 15C , 15E and Figure 16A 、 16C 16E is a cross-sectional view illustrating a method for manufacturing the transistor 100. Figure 12B 、 12D 、12F、12H、 Figure 13B 、 13D , 13F, Figure 14B 、 14D 、14F、 Figure 15B 、 15D , 15F and Figure 16B 、 16D16F is a cross-sectional view illustrating a method for manufacturing the capacitor element 150 .

[0194] First, an insulating film 108 (insulating films 108a and 108b) is formed on the substrate 102 (see Figure 12A and 12B ).

[0195] The insulating film 108 can be formed by appropriately utilizing methods such as sputtering, CVD, vapor deposition, pulsed laser deposition (PLD), printing, and coating. In this embodiment, a 100 nm thick silicon nitride film is formed as the insulating film 108a using a PECVD device. A 400 nm thick silicon oxynitride film is formed as the insulating film 108b using a PECVD device.

[0196] Alternatively, oxygen may be added to the insulating film 108b after the insulating film 108b is formed. Examples of oxygen species that may be added to the insulating film 108b include oxygen radicals, oxygen atoms, oxygen atomic ions, and oxygen molecular ions. Examples of methods for adding oxygen include ion doping, ion implantation, and plasma treatment. Alternatively, after forming a film that suppresses oxygen release on the insulating film, oxygen may be added to the insulating film 108b through the film.

[0197] The insulating film 108b is formed by using a silicon oxide film or a silicon oxynitride film that can release oxygen by heat treatment under the following conditions: the substrate is maintained in a vacuum processing chamber of a plasma PECVD device at a temperature of 180° C. to 280° C. or 200° C. to 240° C., a source gas is introduced into the processing chamber, the pressure in the processing chamber is set to 100 Pa to 250 Pa or 100 Pa to 200 Pa, and 0.17 W / cm2 is supplied to an electrode provided in the processing chamber. 2 Above 0.5W / cm 2 Below or 0.25W / cm 2 Above and 0.35W / cm 2 The following high frequency power.

[0198] Here, a method is described in which a film that suppresses oxygen desorption is formed on the insulating film 108 b and then oxygen is added to the insulating film 108 b through the film.

[0199] A film 141 for suppressing oxygen release is formed on the insulating film 108b (see Figure 12C and 12D ).

[0200] Next, oxygen 142 is added to the insulating film 108b through the film 141 (see Figure 12E and 12F ).

[0201] A film 141 that inhibits oxygen detachment is formed using conductive materials such as metal elements selected from aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten, alloys containing the above metal elements, alloys combining the above metal elements, metal nitrides containing the above elements, metal oxides containing the above elements, or metal nitride oxides containing the above elements.

[0202] The thickness of the oxygen desorption suppressing film 141 can be set to 1 nm to 20 nm inclusive or 2 nm to 10 nm inclusive.

[0203] Methods for adding oxygen 142 to the insulating film 108b via the film 141 include ion doping, ion implantation, and plasma treatment. Providing the film 141 on the insulating film 108b to add oxygen allows the film 141 to function as a protective film that prevents oxygen from escaping from the insulating film 108b. This allows a greater amount of oxygen to be added to the insulating film 108b.

[0204] When oxygen is added by plasma treatment, the amount of oxygen added to the insulating film 108 b can be increased by exciting oxygen with microwaves to generate high-density oxygen plasma.

[0205] Then, the film 141 is removed (see Figure 12G and 12H ).

[0206] In addition, when the insulating film 108b can be formed to which oxygen is sufficiently added after film formation, the above process may not be performed. Figure 12C and 12D as well as Figure 12E and 12F Treatment with added oxygen is shown.

[0207] Next, an oxide semiconductor film is formed on the insulating film 108b and processed into a desired shape to form the oxide semiconductor film 110. Then, an insulating film 112 is formed on the insulating film 108b and the oxide semiconductor film 110 (see FIG. 1 ). Figure 13A and 13B ).

[0208] The following describes a method for forming the oxide semiconductor film 110. An oxide semiconductor film is formed on the insulating film 108b by sputtering, coating, pulsed laser evaporation, laser ablation, thermal CVD, or the like. Next, a mask is formed on the oxide semiconductor film by a photolithography process, and a portion of the oxide semiconductor film is etched using the mask, thereby forming a film. Figure 13A As shown in FIG. 1 , the oxide semiconductor film 110 can be formed. Then, the mask is removed. Alternatively, heat treatment may be performed after the oxide semiconductor film 110 is formed.

[0209] In addition, by forming the oxide semiconductor film 110 by a printing method, the oxide semiconductor film 110 for element isolation can be directly formed.

[0210] When forming an oxide semiconductor film by sputtering, an RF power supply, an AC power supply, a DC power supply, or the like can be used as a power supply for generating plasma. Using an AC power supply or a DC power supply allows formation of a CAAC-OS film. Compared to forming an oxide semiconductor film by sputtering using an RF power supply, sputtering using an AC power supply or a DC power supply is preferred because it allows formation of an oxide semiconductor film with uniform film thickness distribution, film composition distribution, or crystallinity distribution.

[0211] As a sputtering gas for forming an oxide semiconductor film, a rare gas (typically argon), an oxygen gas, or a mixed gas of a rare gas and oxygen gas is appropriately used. When a mixed gas of a rare gas and oxygen gas is used, the ratio of oxygen gas to the rare gas is preferably increased.

[0212] In addition, a sputtering target when forming an oxide semiconductor film may be appropriately selected according to the composition of the oxide semiconductor film to be formed.

[0213] Furthermore, when forming an oxide semiconductor film using, for example, a sputtering method, a CAAC-OS film can be formed by setting the substrate temperature to 150° C. to 750° C., 150° C. to 450° C., or 200° C. to 350° C. Furthermore, a microcrystalline oxide semiconductor film can be formed by setting the substrate temperature to 25° C. to less than 150° C.

[0214] In order to form the CAAC-OS film described below, the following conditions are preferably applied.

[0215] By suppressing the incorporation of impurities during film formation, it is possible to suppress the damage to the crystalline state caused by impurities. For example, the concentration of impurities (such as hydrogen, water, carbon dioxide, and nitrogen) present in the film formation chamber can be reduced. In addition, the concentration of impurities in the film formation gas can be reduced. Specifically, a film formation gas with a dew point below -80°C or below -100°C can be used.

[0216] Furthermore, it is preferable to increase the oxygen ratio in the film forming gas and optimize the power to reduce plasma damage during film formation. The oxygen ratio in the film forming gas is set to 30 vol.% or more, preferably 100 vol.%.

[0217] Alternatively, the oxide semiconductor film can be dehydrogenated or dehydrated by performing a heat treatment after formation. The heat treatment temperature is typically 150° C. or higher and lower than the strain point of the substrate, 250° C. or higher and 450° C. or lower, or 300° C. or higher and 450° C. or lower.

[0218] The heat treatment is performed in an inert gas atmosphere containing a rare gas such as helium, neon, argon, xenon, or krypton, or containing nitrogen. Alternatively, the heat treatment may be performed in an inert gas atmosphere followed by heating in an oxygen atmosphere. The inert gas atmosphere and oxygen atmosphere preferably do not contain hydrogen, water, or the like. The treatment time is 3 minutes or longer and 24 hours or shorter.

[0219] This heat treatment can be performed using an electric furnace, an RTA apparatus, or the like. Using an RTA apparatus allows the heat treatment to be performed at a temperature above the strain point of the substrate within a limited time period. This shortens the heat treatment time.

[0220] The oxide semiconductor film is formed while being heated, or the oxide semiconductor film is subjected to heat treatment after being formed, whereby the hydrogen concentration in the oxide semiconductor film measured by secondary ion mass spectrometry can be 5×10 19 atoms / cm 3 Below, 1×10 19 atoms / cm 3 Below, 5×10 18 atoms / cm 3 Below, 1×10 18 atoms / cm 3 Below, 5×10 17 atoms / cm 3 Below or 1×10 16 atoms / cm 3 the following.

[0221] For example, when an oxide semiconductor film such as InGaZnO is formed using a film forming apparatus using ALD, XWhen forming a (X>0) film, In(CH3)3 gas and O3 gas are repeatedly introduced in sequence to form an InO2 layer, Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a GaO layer, and then Zn(CH3)2 gas and O3 gas are simultaneously introduced to form a ZnO layer. Note that the order of these layers is not limited to the above example. In addition, these gases can also be mixed to form mixed compound layers such as InGaO2 layer, InZnO2 layer, GaInO layer, ZnInO layer, GaZnO layer, etc. Note that although H2O gas bubbled with an inert gas such as Ar can be used instead of O3 gas, it is preferable to use O3 gas that does not contain H. In(C2H5)3 gas can also be used instead of In(CH3)3 gas. Ga(C2H5)3 gas can also be used instead of Ga(CH3)3 gas. In addition, Zn(CH3)2 gas can also be used.

[0222] In this embodiment, the oxide semiconductor film 110 is formed by the following steps: a sputtering target of In-Ga-Zn metal oxide (In:Ga:Zn=1:1:1.2 [atomic ratio]) is used to form a 50 nm thick oxide semiconductor film, and then heat treatment is performed to transfer the oxygen contained in the insulating film 108b to the oxide semiconductor film. Finally, a mask is formed on the oxide semiconductor film, and the oxide semiconductor film is selectively etched.

[0223] Furthermore, by performing a heat treatment at a temperature higher than 350°C and lower than 650°C, or higher than 450°C and lower than 600°C, an oxide semiconductor film having a CAAC ratio (described later) of 60% to lower than 100%, 80% to lower than 100%, 90% to lower than 100%, or 95% to lower than 98% can be obtained. Furthermore, an oxide semiconductor film having reduced content of hydrogen, water, and the like can be obtained. In other words, an oxide semiconductor film having a low impurity concentration and a low defect density can be formed.

[0224] The insulating film 112 can be formed using the same method as the insulating film 108b as appropriate. A silicon oxide film or a silicon oxynitride film can be formed as the insulating film 112 using a PECVD method. In this case, a deposition gas containing silicon and an oxidizing gas are preferably used as source gases. Typical examples of deposition gases containing silicon include silane, disilane, trisilane, and fluorinated silane. Oxidizing gases include oxygen, ozone, nitrous oxide, and nitrogen dioxide.

[0225] A silicon oxynitride film with few defects can be formed as an insulating film 112 using the PECVD method under the following conditions: the ratio of the oxidizing gas to the deposition gas is greater than 20 times and less than 100 times or greater than 40 times and less than 80 times; and the pressure in the processing chamber is less than 100 Pa or less than 50 Pa.

[0226] A dense silicon oxide film or silicon oxynitride film can be formed as the insulating film 112 under the following conditions: the substrate is maintained in a vacuum processing chamber of a PECVD device at a temperature of not less than 280°C and not more than 400°C, the source gas is introduced into the processing chamber, the pressure in the processing chamber is set to not less than 20 Pa and not more than 250 Pa, preferably not less than 100 Pa and not more than 250 Pa, and high-frequency power is supplied to the electrode arranged in the processing chamber.

[0227] The insulating film 112 can be formed using a plasma CVD method using microwaves. Microwaves are in the frequency range of 300 MHz to 300 GHz. Microwaves have a low electron temperature and low electron energy. Furthermore, a small proportion of the supplied power is used to accelerate electrons, so the remaining power can be used to dissociate and ionize more molecules, thereby stimulating a high-density plasma (high-density plasma). Consequently, the insulating film 112 can be formed with minimal plasma damage to the film-forming surface and deposits and with few defects.

[0228] The insulating film 112 can be formed by a CVD method using an organosilane gas. Examples of the organosilane gas that can be used include tetraethyl orthosilicate (TEOS: chemical formula Si(OC2H5)4), tetramethylsilane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (TMCTS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisilazane (HMDS), triethoxysilane (SiH(OC2H5)3), and tris(dimethylamino)silane (SiH(N(CH3)2)3). The CVD method using an organosilane gas allows the insulating film 112 to be formed with improved coverage.

[0229] When a gallium oxide film is formed as the insulating film 112 , it can be formed by using a MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0230] When forming a hafnium oxide film as the insulating film 112 by a thermal CVD method such as MOCVD or ALD, two gases are used: ozone (O3) as an oxidizing agent and a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (a hafnium alkoxide solution, typically hafnium tetrakisdimethylamide (TDMAH)). Note that the chemical formula of hafnium tetrakisdimethylamide is Hf[N(CH3)2]4. Other material liquids include hafnium tetrakis(ethylmethylamide).

[0231] For example, when forming an aluminum oxide film as the insulating film 112 using a thermal CVD method such as MOCVD or ALD, two gases are used: H2O, which serves as an oxidizing agent, and a source gas obtained by vaporizing a liquid containing a solvent and an aluminum precursor compound (such as trimethylaluminum (TMA)). Note that the chemical formula of trimethylaluminum is Al(CH3)3. Other material liquids include tris(dimethylamide)aluminum, triisobutylaluminum, and aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedione). Furthermore, by using the ALD method, the insulating film 112 can be formed with high coverage and a thin film thickness.

[0232] For example, when a silicon oxide film is formed as the insulating film 112 by a thermal CVD method such as MOCVD or ALD, hexachlorodisilane is adsorbed on the film-forming surface, chlorine contained in the adsorbate is removed, and free radicals of an oxidizing gas (O2 or nitrous oxide) are supplied to react with the adsorbate.

[0233] Here, as the insulating film 112 , a silicon oxynitride film is formed to a thickness of 100 nm using a PECVD apparatus.

[0234] Next, the conductive film 113 (the conductive film 113a and the conductive film 113b) is formed on the insulating film 112 (see Figure 13C and 13D ).

[0235] The conductive film 113 can be formed by sputtering, vacuum evaporation, pulsed laser deposition (PLD), thermal CVD, or the like. In this embodiment, a 10 nm thick tantalum nitride film is formed as the conductive film 113 a using a sputtering apparatus. Furthermore, a 300 nm thick copper film is formed as the conductive film 113 b using a sputtering apparatus. Furthermore, it is preferable to form the conductive films 113 a and 113 b successively in a vacuum because this suppresses the ingress of impurities to the interface between the conductive films 113 a and 113 b.

[0236] Alternatively, a tungsten film can be formed as the conductive film 113 b using a film formation apparatus utilizing an ALD method. In this case, WF 6 gas and B 2 H 6 gas are repeatedly introduced sequentially to form an initial tungsten film, and then WF 6 gas and H 2 gas are simultaneously introduced to form a tungsten film. Note that SiH 4 gas can also be used instead of B 2 H 6 gas.

[0237] Next, a mask 145 is formed on the conductive film 113b by a photolithography process, and then the conductive film 113b, the conductive film 113a, and a portion of the insulating film 112 are etched (see FIG. 145 ). Figure 13E and 13F ).

[0238] As a method for etching the conductive film 113 and the insulating film 112 , a wet etching method and / or a dry etching method can be used as appropriate.

[0239] Next, the conductive film 113 and the insulating film 112 are processed while shrinking the mask 145 to form conductive films 114a, 114b, 116a, and 116b (see FIG. Figure 14A and 14B ).

[0240] Furthermore, the etching process of the conductive film 113 and the insulating film 112 exposes a portion of the oxide semiconductor film 110 in the transistor 100. Furthermore, due to the etching of the conductive film 114 and the insulating film 112, the thickness of the exposed region of the oxide semiconductor film 110 may be thinner than the region of the oxide semiconductor film 110 overlapping with the conductive film 114. Furthermore, the etching process of the conductive film 113 and the insulating film 112 removes a portion of the region of the insulating film 108 b serving as a base film that is not covered by the oxide semiconductor film 110 in the transistor 100. Consequently, the thickness of this region may be thinner than the region overlapping with the oxide semiconductor film 110. Furthermore, the etching process of the conductive film 113 and the insulating film 112 removes a portion of the region of the insulating film 108 b serving as a base film that is not covered by the insulating film 112 in the capacitor 150. Consequently, the thickness of this region may be thinner than the region overlapping with the insulating film 112.

[0241] Next, an impurity element 143 is added to the insulating film 108b, the insulating film 112, the oxide semiconductor film 110, the conductive film 114, and the mask 145 (see FIG. 14). Figure 14C and 14D ).

[0242] The impurity element 143 is added to the oxide semiconductor film 110 in a portion not covered by the conductive film 114, the insulating film 112, and the mask 145. Oxygen vacancies are formed in the oxide semiconductor film 110 by the addition of the impurity element 143.

[0243] Methods for adding the impurity element 143 include ion doping, ion implantation, and plasma treatment. When plasma treatment is used, the impurity element can be added by generating plasma in a gas atmosphere containing the impurity element to be added and performing the plasma treatment. Apparatus for generating plasma can include dry etching equipment, ashing equipment, plasma CVD equipment, and high-density plasma CVD equipment.

[0244] As a source gas for the impurity element 143, one or more of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF, H2, and a rare gas can be used. Alternatively, one or more of B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and H2 diluted with a rare gas can be used. By adding the impurity element 143 to the oxide semiconductor film 110 using one or more of B2H6, PH3, N2, NH3, AlH3, AlCl3, F2, HF, and H2 diluted with a rare gas, the rare gas and one or more of hydrogen, boron, carbon, nitrogen, fluorine, aluminum, silicon, phosphorus, and chlorine can be added to the oxide semiconductor film 110 simultaneously.

[0245] In addition, after adding a rare gas to the oxide semiconductor film 110, one or more of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF and H2 can be added to the oxide semiconductor film 110.

[0246] Alternatively, after one or more of B2H6, PH3, CH4, N2, NH3, AlH3, AlCl3, SiH4, Si2H6, F2, HF and H2 are added to the oxide semiconductor film 110, a rare gas may be added to the oxide semiconductor film 110.

[0247] The addition of the impurity element 143 can be controlled by appropriately setting the implantation conditions such as the acceleration voltage and the dose. For example, when argon is implanted by ion implantation, the acceleration voltage can be set to 10 kV and the dose can be set to 1×10 13 ions / cm 2 Above and 1×10 16 ions / cm 2 For example, the dose can be set to 1×10 14 ions / cm 2 In addition, when phosphorus ions are added by ion implantation, the acceleration voltage can be set to 30 kV and the dose can be set to 1×10 13 ions / cm 2 Above and 5×10 16 ions / cm 2 For example, the dose can be set to 1×10 15 ions / cm 2 .

[0248] When argon is added as the impurity element 143 using a dry etching apparatus, the substrate can be placed on the cathode side of the parallel plate and RF power can be supplied to apply a bias voltage to the substrate side. The power density of the RF power can be set to, for example, 0.1 W / cm 2 Above 2W / cm 2 the following.

[0249] Furthermore, as described in this embodiment, the impurity element 143 is preferably added while leaving the mask 145. By adding the impurity element 143 while leaving the mask 145, adhesion of constituent elements of the conductive film 114 to the side walls of the insulating film 112 can be suppressed. Note that the method of adding the impurity element 143 is not limited to the above method. For example, the impurity element 143 may be added by using the conductive film 114 and the insulating film 112 as masks after removing the mask 145.

[0250] Afterward, heat treatment may be performed to further improve the conductivity of the region to which the impurity element 143 is added. The temperature for this heat treatment is typically 150°C or higher and lower than the strain point of the substrate, 250°C or higher and 450°C or higher and 300°C or lower.

[0251] Next, the mask 145 is removed (see Figure 14E and 14F ).

[0252] Next, an insulating film 118 is formed over the insulating film 108b, the oxide semiconductor film 110, and the conductive films 114 and 116, and an insulating film 120 is formed over the insulating film 118 (see FIG. 1 ). Figure 15A and 15B ).

[0253] The insulating films 118 and 120 can utilize the formation method of the insulating films 108 a and 108 b as appropriate.

[0254] In this embodiment, a 100 nm thick silicon nitride film is formed using a PECVD device as the insulating film 118. A 300 nm thick silicon oxynitride film is formed using a PECVD device as the insulating film 120.

[0255] By using a silicon nitride film as the insulating film 118 , hydrogen in the silicon nitride film can be taken into the oxide semiconductor film 110 , whereby the carrier concentration of the oxide semiconductor film 110 in contact with the insulating film 118 can be further increased.

[0256] Next, a mask is formed on the insulating film 120 by a photolithography process, and then a portion of the insulating film 120 is etched to form an opening 140c reaching the insulating film 118 (see FIG. Figure 15C and 15D ).

[0257] As a method for etching the insulating film 120 , a wet etching method and / or a dry etching method can be used as appropriate.

[0258] Next, a mask is formed on the insulating film 120 by a photolithography process, and then a portion of the insulating films 118 and 120 is etched to form openings 140a and 140b reaching the oxide semiconductor film 110 (see FIG. 1 ). Figure 15E and 15F ).

[0259] In addition, in this embodiment, the method of forming the opening 140c and the openings 140a and 140b using different processes is described as an example, but the present invention is not limited to this. For example, the opening 140c and the openings 140a and 140b can also be formed simultaneously using a halftone mask or a gray tone mask. By using a halftone mask or a gray tone mask, one photolithography process can be eliminated, thereby reducing manufacturing costs.

[0260] Next, the conductive film 121 (the conductive film 121a and the conductive film 121b) is formed on the insulating film 120 so as to cover the opening 140a, the opening 140b, and the opening 140c (see FIG. 1 ). Figure 16A and 16B ).

[0261] The conductive film 121 can be formed by appropriately using the method used to form the conductive film 113. Here, a 50 nm thick tungsten film is formed as the conductive film 121a using a sputtering apparatus, and a 200 nm thick copper film is formed as the conductive film 121b using a sputtering apparatus.

[0262] Next, a mask is formed over the conductive film 121b by a photolithography process, and then portions of the conductive films 121a and 121b are etched to form the conductive films 122, 124, and 126 (see FIG. 1 ). Figure 16C and 16D ).

[0263] The conductive film 122 has a stacked-layer structure of a conductive film 122a and a conductive film 122b on the conductive film 122a. The conductive film 124 has a stacked-layer structure of a conductive film 124a and a conductive film 124b on the conductive film 124a. The conductive film 126 has a stacked-layer structure of a conductive film 126a and a conductive film 126b on the conductive film 126a.

[0264] Next, an insulating film 128 is formed over the insulating film 120, the conductive film 122, the conductive film 124, and the conductive film 126 (see FIG. Figure 16E and 16F ).

[0265] The insulating film 128 can be formed by appropriately using the same method as that used to form the insulating film 108a. Here, a 200 nm thick silicon nitride film is formed as the insulating film 128 using a PECVD apparatus.

[0266] Through the above steps, the transistor 100 and the capacitor 150 can be manufactured over the same substrate.

[0267] <Method for manufacturing semiconductor device 2> Next, the following explains Figures 5A to 5D FIG. 1 is an example of a method for manufacturing the transistor 100A and the capacitor 150A.

[0268] An insulating film 104 is formed on the substrate 102. Next, a conductive film is formed on the insulating film 104 and processed into a desired shape to form a conductive film 106. Figures 12A to 12H as well as Figure 13A and 13B Then, after forming a mask on the insulating film 112 by a photolithography process, a portion of the insulating film 112 is etched to form an opening 139 that reaches the conductive film 106. Figure 13C The same process as that shown in the following figures can be manufactured on the same substrate Figures 5A to 5D Transistor 100A and capacitor 150A are shown.

[0269] The structure and method described in this embodiment can be used in combination with the structure and method described in other embodiment modes as appropriate.

[0270] Implementation Method 2 In this embodiment, the structure of an oxide semiconductor film included in a semiconductor device according to one embodiment of the present invention is described in detail below.

[0271] First, possible structures of the oxide semiconductor film are described.

[0272] Oxide semiconductor films are broadly classified into non-single-crystal oxide semiconductor films and single-crystal oxide semiconductor films. Non-single-crystal oxide semiconductor films include CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) films, polycrystalline oxide semiconductor films, microcrystalline oxide semiconductor films, and amorphous oxide semiconductor films.

[0273] First, the CAAC-OS film will be described.

[0274] A CAAC-OS film is a type of oxide semiconductor film including a plurality of crystal portions aligned along the c-axis.

[0275] In a transmission electron microscope (TEM) image of a CAAC-OS film, clear boundaries between crystal parts, namely grain boundaries, are not observed. Therefore, in a CAAC-OS film, a decrease in electron mobility due to grain boundaries is less likely to occur.

[0276] TEM images of the CAAC-OS film observed from a direction roughly parallel to the sample surface (cross-sectional TEM images) reveal that the metal atoms are arranged in layers within the crystal structure. Each metal atomic layer has a shape that reflects the concavities and convexities of the surface forming the CAAC-OS film (also called the formed surface) or the top surface of the CAAC-OS film, and is arranged parallel to the formed surface or top surface of the CAAC-OS film.

[0277] Meanwhile, TEM images of the CAAC-OS film observed from a direction roughly perpendicular to the sample surface (planar TEM images) show that the metal atoms are arranged in triangular or hexagonal shapes within the crystal parts. However, the arrangement of the metal atoms is irregular between different crystal parts.

[0278] Figure 17A This is a cross-sectional TEM image of a CAAC-OS film. Figure 17B It is magnified Figure 17A Cross-sectional TEM image, emphasizing the atomic arrangement for easier understanding.

[0279] Figure 17C yes Figure 17A The local Fourier transform image of the area surrounded by a circle (approximately 4 nm in diameter) between AO-A'. Figure 17C The c-axis orientation can be confirmed in each of the regions shown. Furthermore, the c-axis direction between the AOs differs from the c-axis direction between the O-A's, indicating that the grains between the AOs differ from the grains between the O-A's. Furthermore, the c-axis angle between the AOs changes gradually and continuously, such as 14.3°, 16.6°, and 30.9°. Similarly, the c-axis angle between the O-A's also changes gradually and continuously, such as -18.3°, -17.6°, and -11.3°.

[0280] In addition, in the electron diffraction pattern of the CAAC-OS film, spots (bright spots) indicating orientation are observed. For example, in the electron diffraction pattern of the top surface of the CAAC-OS film obtained using an electron beam having a wavelength of 1 nm or more and 30 nm or less (also called a nanobeam electron diffraction pattern), spots are observed (see Figure 18A ).

[0281] Cross-sectional TEM observation and planar TEM observation revealed that the crystal parts of the CAAC-OS film had orientation.

[0282] Note that the crystalline portion contained in the CAAC-OS film is almost always of a size that can be accommodated in a cube with a side length of less than 100nm. Therefore, sometimes the size of the crystalline portion contained in the CAAC-OS film is a size that can be accommodated in a cube with a side length shorter than 10nm, shorter than 5nm, or shorter than 3nm. However, sometimes multiple crystalline portions contained in the CAAC-OS film are connected to form a large crystalline region. For example, a 2500nm crystalline region is sometimes observed in a planar TEM image. 2 Above, 5mm 2 Above or 1000mm 2 above the crystalline region.

[0283] The CAAC-OS film was structurally analyzed using an X-ray diffraction (XRD) device. For example, when a CAAC-OS film including InGaZnO4 crystals was analyzed using the out-of-plane method, a peak appeared at a diffraction angle (2θ) of approximately 31°. Since this peak originates from the (009) plane of the InGaZnO4 crystal, it can be seen that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis is oriented in a direction roughly perpendicular to the formed surface or top surface of the CAAC-OS film.

[0284] On the other hand, when the CAAC-OS film is analyzed using the in-plane method (in-plane method) in which X-rays are incident on the sample from a direction approximately perpendicular to the c-axis, a peak appears when 2θ is around 56°. This peak originates from the (110) plane of the InGaZnO4 crystal. Here, 2θ is fixed at around 56° and the analysis is performed under the condition of rotating the sample with the normal vector of the sample plane as the axis (φ axis) (φ scan). When the sample is a single crystal oxide semiconductor film of InGaZnO4, six peaks appear. The six peaks originate from a crystal plane equal to the (110) plane. On the other hand, when the sample is a CAAC-OS film, no clear peak can be observed even when φ scanning is performed with 2θ fixed at around 56°.

[0285] The above results show that in a CAAC-OS film with c-axis alignment, while the directions of the a-axis and b-axis vary between crystal parts, the c-axis is oriented parallel to the normal vector of the formed surface or top surface. Therefore, the layered metal atomic layers observed in the cross-sectional TEM image correspond to planes parallel to the ab plane of the crystal.

[0286] Note that the crystallized portion is formed during the formation of the CAAC-OS film or during a crystallization process such as heat treatment. As described above, the c-axis of the crystal is oriented parallel to the normal vector of the formed surface or top surface of the CAAC-OS film. Therefore, if the shape of the CAAC-OS film is changed by etching, for example, the c-axis of the crystal is not necessarily parallel to the normal vector of the formed surface or top surface of the CAAC-OS film.

[0287] Furthermore, the distribution of c-axis-oriented crystal parts within a CAAC-OS film is not necessarily uniform. For example, when a CAAC-OS film's crystal parts are formed by crystal growth near the top surface of the film, the proportion of c-axis-oriented crystal parts near the top surface may be higher than that near the surface where they are formed. Furthermore, when impurities are added to the CAAC-OS film, the regions where the impurities are added deteriorate, and the proportion of c-axis-oriented crystal parts within the CAAC-OS film may vary depending on the region.

[0288] Note that when analyzing a CAAC-OS film containing InGaZnO4 crystals using the out-of-plane method, a peak around 2θ of 36° may be observed in addition to a peak around 2θ of 31°. A peak around 2θ of 36° indicates that part of the CAAC-OS film contains crystals that lack c-axis alignment. Preferably, the CAAC-OS film exhibits a peak around 2θ of 31° and no peak around 2θ of 36°.

[0289] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities refer to elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements such as silicon, which have a stronger bonding force with oxygen than the metal elements constituting the oxide semiconductor film, will disrupt the atomic arrangement of the oxide semiconductor film because they will take oxygen from the oxide semiconductor film, resulting in a decrease in crystallinity. In addition, since heavy metals such as iron or nickel, argon, carbon dioxide, etc. have large atomic radii (or molecular radii), if they are contained in the oxide semiconductor film, they will also disrupt the atomic arrangement of the oxide semiconductor film, resulting in a decrease in crystallinity. Note that impurities contained in the oxide semiconductor film sometimes become carrier traps or carrier generation sources.

[0290] Furthermore, a CAAC-OS film is an oxide semiconductor film with a low defect state density. For example, oxygen vacancies in the oxide semiconductor film may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

[0291] Next, a microcrystalline oxide semiconductor film is described.

[0292] Sometimes, no clear crystal part can be observed in the TEM image of a microcrystalline oxide semiconductor film. The size of the crystal part contained in the microcrystalline oxide semiconductor film is mostly greater than 1 nm and less than 100 nm, or greater than 1 nm and less than 10 nm. In particular, an oxide semiconductor film having nanocrystalline (nc: nanocrystal) crystals with a size of greater than 1 nm and less than 10 nm or greater than 1 nm and less than 3 nm is called an nc-OS (nanocrystalline Oxide Semiconductor: nanocrystalline oxide semiconductor) film. In addition, for example, in the TEM image of an nc-OS film, sometimes, no clear grain boundary can be observed.

[0293] The atomic arrangement of the nc-OS film is periodic in a tiny area (for example, an area greater than 1 nm and less than 10 nm, in particular, an area greater than 1 nm and less than 3 nm). In addition, no regularity of crystal orientation is observed between different crystalline parts of the nc-OS film. Therefore, no orientation is observed in the film as a whole. Therefore, sometimes the nc-OS film is no different from the amorphous oxide semiconductor film in certain analysis methods. For example, when the nc-OS film is structurally analyzed using an XRD device using an X-ray having a beam diameter larger than that of the crystalline part by the out-of-plane method, no peak representing the crystalline plane is detected. In addition, when the nc-OS film is subjected to nanobeam electron diffraction (selected area electron diffraction) using electron rays having a beam diameter larger than that of the crystalline part (for example, greater than 50 nm), a diffraction pattern similar to a halo pattern is observed. On the other hand, when the nc-OS film is subjected to electron diffraction using electron rays having a beam diameter close to or smaller than that of the crystalline part, spots are observed. In addition, in the nanobeam electron diffraction pattern of the nc-OS film, a high brightness area such as a circle (ring-shaped) is sometimes observed. In addition, in the nanobeam electron diffraction pattern of the nc-OS film, multiple spots are sometimes observed in the ring-shaped area (refer to Figure 18B ).

[0294] nc-OS films are oxide semiconductor films with higher regularity than amorphous oxide semiconductor films. Therefore, nc-OS films have a lower defect state density than amorphous oxide semiconductor films. However, nc-OS films lack regularity in crystal orientation between different crystalline parts. Therefore, nc-OS films have a higher defect state density than CAAC-OS films.

[0295] Note that the oxide semiconductor film may be a stacked-layer film including two or more of an amorphous oxide semiconductor film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example.

[0296] When the oxide semiconductor film has multiple structures, the structure can sometimes be analyzed by using nanobeam electron diffraction.

[0297] Figure 18C A transmission electron diffraction measurement apparatus is shown. The apparatus includes: an electron gun chamber 210; an optical system 212 below the electron gun chamber 210; a sample chamber 214 below the optical system 212; an optical system 216 below the sample chamber 214; an observation chamber 220 below the optical system 216; a camera 218 disposed in the observation chamber 220; and a film chamber 222 below the observation chamber 220. The camera 218 is disposed so as to face the interior of the observation chamber 220. Alternatively, the transmission electron diffraction measurement apparatus may not include the film chamber 222.

[0298] also, Figure 18D Show Figure 18C The internal structure of a transmission electron diffraction measurement apparatus is shown. Inside the transmission electron diffraction measurement apparatus, electrons emitted from an electron gun located in an electron gun chamber 210 are irradiated via an optical system 212 onto a substance 228 located in a sample chamber 214. Electrons that have passed through substance 228 are incident on a fluorescent plate 232 located within an observation chamber 220 via an optical system 216. A pattern corresponding to the intensity of the incident electrons appears on fluorescent plate 232, allowing the measurement of a transmission electron diffraction pattern.

[0299] Because the camera 218 is positioned facing the fluorescent plate 232, it can capture the pattern appearing on the fluorescent plate 232. The angle formed by a straight line passing through the center of the lens of the camera 218 and the center of the fluorescent plate 232, and the fluorescent plate 232, is, for example, greater than 15° and less than 80°, greater than 30° and less than 75°, or greater than 45° and less than 70°. The smaller the angle, the greater the distortion of the transmission electron diffraction pattern captured by the camera 218. However, if the angle is known in advance, the distortion of the resulting transmission electron diffraction pattern can be corrected. Alternatively, the camera 218 can be positioned within the film chamber 222. For example, the camera 218 can be positioned within the film chamber 222 so as to face the incident direction of the electrons 224. In this case, a transmission electron diffraction pattern with minimal distortion can be captured from the back side of the fluorescent plate 232.

[0300] Sample chamber 214 is equipped with a holder for holding sample substance 228. The holder allows electrons to pass through substance 228. For example, the holder may have the function of moving substance 228 in the X-axis, Y-axis, Z-axis, or other directions. The holder may have the ability to move the substance within a range of, for example, 1 nm to 10 nm, 5 nm to 50 nm, 10 nm to 100 nm, 50 nm to 500 nm, or 100 nm to 1 μm. These ranges can be optimally set based on the structure of substance 228.

[0301] Next, a method for measuring a transmission electron diffraction pattern of a substance using the above-mentioned transmission electron diffraction measurement apparatus will be described.

[0302] For example, Figure 18D As shown in FIG. 1 , by changing the position of the electron 224 as the nanobeam irradiated on the material (scanning), it can be confirmed that the structure of the material gradually changes. At this time, if the material 228 is a CAAC-OS film, it can be observed that Figure 18A If the substance 228 is a nc-OS film, it can be observed that Figure 18B The diffraction pattern shown.

[0303] Even if substance 228 is a CAAC-OS film, a diffraction pattern similar to that of an nc-OS film or the like is sometimes partially observed. Therefore, the quality of the CAAC-OS film can sometimes be represented by the proportion of the area in which the diffraction pattern of the CAAC-OS film is observed in a certain area (also referred to as the CAACization rate). For example, the CAACization rate of an excellent CAAC-OS film is 60% or more, preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. In addition, the proportion of the area where a diffraction pattern different from that of the CAAC-OS film is observed is expressed as the non-CAACization rate.

[0304] As an example, the top surface of a sample having a CAAC-OS film just after film formation (expressed as-sputtered) and the top surface of a sample having a CAAC-OS film after heat treatment at 450°C in an atmosphere containing oxygen are scanned to obtain a transmission electron diffraction pattern. Here, the diffraction pattern is observed by scanning at a speed of 5 nm / second for 60 seconds, and the observed diffraction pattern is converted into a static image every 0.5 seconds to calculate the CAAC conversion rate. Note that a nanobeam with a beam diameter of 1 nm is used as the electron beam. In addition, the same measurement is performed on six samples. Moreover, the CAAC conversion rate is calculated by using the average value of the six samples.

[0305] Figure 19A The CAAC conversion rate of each sample is shown. The CAAC conversion rate of the CAAC-OS film just after film formation is 75.7% (the non-CAAC conversion rate is 24.3%). In addition, the CAAC conversion rate of the CAAC-OS film after the heat treatment at 450°C is 85.3% (the non-CAAC conversion rate is 14.7%). It can be seen that the CAAC conversion rate after the heat treatment at 450°C is higher than that just after the film formation is completed. In other words, it can be seen that heat treatment at high temperature (for example, above 400°C) reduces the non-CAAC conversion rate (increases the CAAC conversion rate). In addition, it can be seen that a CAAC-OS film with a high CAAC conversion rate can also be obtained when a heat treatment below 500°C is performed.

[0306] Here, most of the diffraction patterns that differ from those of the CAAC-OS film are identical to those of the nc-OS film. Furthermore, no amorphous oxide semiconductor film is observed in the measurement region. This suggests that the heat treatment causes regions with the same structure as the nc-OS film to rearrange due to the influence of the structures of adjacent regions, resulting in CAAC formation in these regions.

[0307] Figure 19B and Figure 19C This is a planar TEM image of the CAAC-OS film immediately after film formation and after heat treatment at 450°C. Figure 19B and Figure 19C Comparison shows that the film quality of the CAAC-OS film is more uniform after the heat treatment at 450° C. In other words, it is found that the film quality of the CAAC-OS film is improved by the high-temperature heat treatment.

[0308] By adopting this measurement method, it is sometimes possible to perform structural analysis on oxide semiconductor films having various structures.

[0309] By using an oxide semiconductor film having any of the above structures, a semiconductor device according to one embodiment of the present invention can be formed.

[0310] <Film Formation Model> Next, the film formation models of CAAC-OS and nc-OS are described.

[0311] Figure 40A FIG. 1 is a schematic diagram in a film formation chamber showing a case where CAAC-OS is formed by sputtering.

[0312] The target 1130 is bonded to a backing plate. Multiple magnets are placed under the target 1130 and the backing plate. These magnets generate a magnetic field on the target 1130. The sputtering method that uses the magnetic field of magnets to increase the film formation rate is called magnetron sputtering.

[0313] The target material 1130 has a polycrystalline structure, wherein at least one crystal grain includes a cleavage plane.

[0314] The substrate 1120 is arranged opposite to the target 1130, and the distance d therebetween (also called the target-substrate distance (TS distance)) is greater than 0.01m and less than 1m, preferably greater than 0.02m and less than 0.5m. Most of the film forming chamber is filled with a film forming gas (for example, oxygen, argon, or a mixed gas containing oxygen at a ratio of 50 vol.% or more), and the pressure in the film forming chamber is controlled to be greater than 0.01Pa and less than 100Pa, preferably greater than 0.1Pa and less than 10Pa. Here, when a voltage greater than a certain value is applied to the target 1130, discharge begins and plasma is confirmed. In addition, a high-density plasma region is formed by the magnetic field on the target 1130. In the high-density plasma region, ions 1101 are generated due to the ionization of the film forming gas. The ions 1101 are, for example, positive ions of oxygen (O + ) or cations of argon (Ar + )wait.

[0315] Ions 1101 are accelerated toward target 1130 by the electric field and collide with target 1130. At this point, flat or granular sputtered particles 1100a and 1100b are separated from the cleavage plane and ejected. Furthermore, the impact of ions 1101 colliding with the target 1130 may cause strain in the structures of particles 1100a and 1100b.

[0316] Particle 1100a is a flat or granular sputtered particle having a triangular, such as an equilateral triangle, plane. In addition, particle 1100b is a flat or granular sputtered particle having a hexagonal, such as an equilateral hexagon, plane. Note that the flat or granular sputtered particles such as particles 1100a and particles 1100b are collectively referred to as particles 1100. The planar shape of particle 1100 is not limited to a triangle or a hexagon. For example, it sometimes becomes a shape formed by combining two or more and six or less triangles. For example, it sometimes becomes a quadrangle (rhombus) formed by combining two triangles (equilateral triangles).

[0317] The thickness of the particles 1100 depends on the type of film-forming gas, etc. The thickness of the particles 1100 is preferably uniform, and the reason for this will be described later. In addition, regarding the shape of the sputtered particles, a thin particle shape is preferably used rather than a thick spherical shape.

[0318] When the particle 1100 passes through the plasma, it sometimes receives an electric charge and its side faces become negatively or positively charged. The side faces of the particle 1100 have oxygen atoms, and the oxygen atoms may be negatively charged. For example, Figure 42The example shows a particle 1100a with negatively charged oxygen atoms on its side surface. When the side surfaces have charges of the same polarity, the charges repel each other, maintaining a flat plate shape. Furthermore, when CAAC-OS is an In-Ga-Zn oxide, the oxygen atoms bonded to indium atoms may be negatively charged. Alternatively, the oxygen atoms bonded to indium, gallium, and zinc atoms may be negatively charged.

[0319] like Figure 40A As shown, for example, a particle 1100 flies like a kite in the plasma onto a substrate 1120. Because the particle 1100 is charged, a repulsive force is generated when it approaches an area where other particles 1100 have been deposited. Here, a magnetic field parallel to the top surface of the substrate 1120 is generated on the top surface of the substrate 1120. In addition, because there is a potential difference between the substrate 1120 and the target 1130, an electric current flows from the substrate 1120 to the target 1130. Therefore, the particle 1100 is subjected to a force (Lorentz force) caused by the action of the magnetic field and the electric current on the top surface of the substrate 1120 (see Figure 43 This can be understood using Fleming's left-hand rule. To increase the force applied to particle 1100, a region is preferably provided on the top surface of substrate 1120 where the magnetic field parallel to the top surface of substrate 1120 is 10 G or greater, preferably 20 G or greater, more preferably 30 G or greater, and even more preferably 50 G or greater. Alternatively, a region is preferably provided on the top surface of substrate 1120 where the magnetic field parallel to the top surface of substrate 1120 is 1.5 times greater, preferably 2 times greater, more preferably 3 times greater, and even more preferably 5 times greater than the magnetic field perpendicular to the top surface of substrate 1120.

[0320] In addition, since the substrate 1120 is heated, the resistance such as friction between the particles 1100 and the substrate 1120 is small. As a result, Figure 44A As shown in FIG. 1 , the particle 1100 slides down the top surface of the substrate 1120. The particle 1100 moves with the flat surface facing the substrate 1120. Then, as shown in FIG. Figure 44B As shown in FIG. 1 , when a particle 1100 reaches the side of another already deposited particle 1100, their side surfaces bond with each other. At this point, oxygen atoms on the side surfaces of particle 1100 are detached. The detached oxygen atoms sometimes fill oxygen vacancies in the CAAC-OS, forming a CAAC-OS with a low defect state density.

[0321] In addition, by heating the particles 1100 on the substrate 1120, the atoms are rearranged, and the strain of the structure caused by the collision of the ions 1101 is relaxed. The particles 1100 whose strain is relaxed are substantially single crystals. When the particles 1100 are substantially single crystals, even if the particles 1100 are heated after being bonded to each other, the particles 1100 themselves hardly expand or contract. Therefore, the amplification of the gaps between the particles 1100 does not occur, resulting in the formation of defects such as grain boundaries and becoming cracks (crevasse). In addition, it can be considered that metal atoms with elasticity are spread in the gaps, and they connect the sides of the particles 1100 that deviate from the direction like a highway.

[0322] Based on the model described above, it can be assumed that particles 1100 are deposited onto substrate 1120. Therefore, it can be seen that, unlike epitaxial growth, CAAC-OS can be formed even when the surface being formed does not have a crystalline structure. For example, CAAC-OS can be formed even if the structure of the top surface (the surface being formed) of substrate 1120 is amorphous.

[0323] In addition, it can be known that when CAAC-OS is formed, not only when the top surface of the substrate 1120 to be formed is a flat surface, but also when the top surface is concave-convex, the particles 1100 are arranged according to their shapes. For example, if the top surface of the substrate 1120 is flat at the atomic level, a layer with uniform thickness, flatness, and high crystallinity is formed because the particles 1100 are arranged with the flat surface parallel to the ab plane facing downward. Moreover, by stacking n (n is a natural number) layers, CAAC-OS can be obtained (refer to Figure 40B ).

[0324] On the other hand, even if the top surface of the substrate 1120 is concavo-convex, CAAC-OS has a structure in which n (n is a natural number) particles 1100 are stacked in layers arranged in parallel along the convex surface. Since the substrate 1120 is concavo-convex, gaps between the particles 1100 are sometimes easily generated in CAAC-OS. However, since intermolecular forces are generated between the particles 1100, even on the concavo-convex surface, the particles are arranged in such a way that the gaps between the particles are as small as possible. Thus, even if the film-forming surface is concavo-convex, a CAAC-OS with high crystallinity can be formed (see Figure 40C ).

[0325] Therefore, CAAC-OS does not require laser crystallization, and thus can be uniformly formed on a large-area glass substrate, etc.

[0326] Since CAAC-OS is formed according to this model, the sputtered particles are preferably in the form of small granules. In addition, if the sputtered particles are in the form of thick dice, the surface facing the substrate 1120 is not fixed, so uniform thickness and crystal orientation may not be achieved.

[0327] According to the above film formation model, a CAAC-OS having high crystallinity can be formed even on a surface having an amorphous structure.

[0328] In addition, CAAC-OS can also be described using a film formation model including zinc oxide particles in addition to the particles 1100 .

[0329] The mass of the zinc oxide particles is smaller than that of the particles 1100, so they reach the substrate 1120 earlier than the particles 1100. On the top surface of the substrate 1120, the zinc oxide particles preferentially grow crystals in the horizontal direction to form a thin zinc oxide layer. The zinc oxide layer has a c-axis orientation. The c-axis of the crystal of the zinc oxide layer is oriented in a direction parallel to the normal vector of the substrate 1120. The zinc oxide layer has the function of a seed layer for the growth of CAAC-OS, and therefore has the function of improving the crystallinity of CAAC-OS. In addition, the thickness of the zinc oxide layer is greater than 0.1 nm and less than 5 nm, and is mostly greater than 1 nm and less than 3 nm. The thickness of the zinc oxide layer is thin enough, so almost no grain boundaries are observed.

[0330] Therefore, in order to form a CAAC-OS with high crystallinity, it is preferable to use a target containing zinc at a higher ratio than the stoichiometric composition.

[0331] Likewise, nc-OS can utilize Figure 41 The film formation model shown is understood. Note that Figure 41 and Figure 40A The only difference is whether the substrate 1120 is heated.

[0332] Therefore, the substrate 1120 is not heated, and the frictional resistance between the particles 1100 and the substrate 1120 is large. As a result, the particles 1100 cannot slide down the top surface of the substrate 1120 and thus fall irregularly onto the top surface of the substrate 1120 to form nc-OS.

[0333] <Cleavage plane> Next, the cleavage plane of the target material described in the CAAC-OS film formation model will be described.

[0334] First, refer to Figure 45A and 45B Describe the cleavage plane of the target material. Figure 45A and 45B The structure of the InGaZnO4 crystal is shown. Figure 45A The structure of InGaZnO4 crystal is shown when the c-axis is directed upward and observed from a direction parallel to the b-axis. Figure 45B This is the structure of InGaZnO4 crystal when viewed from a direction parallel to the c-axis.

[0335] The energy required for cleavage of each crystal plane of an InGaZnO4 crystal was calculated using first-principles calculations. Note that the calculations were performed using a density functional program (CASTEP) using pseudopotentials and a plane wave basis. Note that an ultrasoft pseudopotential was used as the pseudopotential. Furthermore, GGA / PBE was used as the functional. The cutoff energy was set to 400 eV.

[0336] After optimizing the structure including the cell size, the energy of the structure in the initial state is derived. In addition, optimizing the atomic arrangement while keeping the cell size fixed is performed, and then the energy of the structure after cleavage on each surface is derived.

[0337] according to Figure 45A and 45B The structure of the InGaZnO4 crystal shown in FIG. 4 is a structure cleaved on any one of the first, second, third, and fourth faces and a structure optimization calculation with a fixed unit size is performed. Here, the first face is a crystal plane between the Ga-Zn-O layer and the In-O layer and is parallel to the (001) face (or ab face) (see FIG. Figure 45A The second surface is a crystal plane between Ga-Zn-O layers and is parallel to the (001) plane (or ab plane) (refer to Figure 45A The third plane is a crystal plane parallel to the (110) plane (refer to Figure 45B The fourth plane is a crystal plane parallel to the (100) plane (or bc plane) (refer to Figure 45B ).

[0338] The energy of the structure after cleavage was calculated on each surface under the above conditions. Next, the difference between the energy of the structure after cleavage and the energy of the structure in its initial state was divided by the area of ​​the cleavage plane to calculate the cleavage energy, an indicator of the ease of cleavage for each plane. Note that the energy of the structure is calculated based on the atoms and electrons included in the structure. That is, the calculation takes into account the kinetic energy of the electrons as well as the interactions between atoms, atoms and electrons, and electrons.

[0339] From the calculation results, we can see that the cleavage energy of the first surface is 2.60J / m 2 The cleavage energy of the second side is 0.68J / m 2 The cleavage energy of the third surface is 2.18 J / m 2 The cleavage energy of the fourth surface is 2.12 J / m 2 (See Table 1).

[0340] [Table 1] <![CDATA[Cleavage energy [J / m 2 > First side 2.60 Side 2 0.68 The third side 2.18 Side 4 2.12 From the above calculations, we can see that Figure 45A and45B In the InGaZnO4 crystal structure shown, the second surface has the lowest cleavage energy. In other words, the surface between the Ga-Zn-O layers (the cleavage plane) is the easiest to cleave. Therefore, in this specification, the cleavage plane refers to the second surface that is easiest to cleave.

[0341] Because the second surface between the Ga-Zn-O layer and the Ga-Zn-O layer is a cleavage surface, Figure 45A The InGaZnO4 crystal shown can be separated along two planes equal to the second plane. Therefore, when ions or the like collide with the target, it can be assumed that wafer-shaped units (called particles) cleaved along the plane with the lowest cleavage energy fly out as the smallest unit. In this case, the InGaZnO4 particle consists of three layers: a Ga-Zn-O layer, an In-O layer, and a Ga-Zn-O layer.

[0342] In addition, since the cleavage energy of the third plane (the crystal plane parallel to the (110) plane) and the fourth plane (the crystal plane parallel to the (100) plane (or bc plane)) is lower than the cleavage energy of the first plane (the crystal plane between the Ga-Zn-O layer and the In-O layer parallel to the (001) plane (or ab plane)), it can be seen that in many cases the planar shape of the particles is triangular or hexagonal.

[0343] Next, classical molecular dynamics calculations were performed, assuming a crystal of InGaZnO 4 having a homologous structure as a target, and evaluating the cleavage plane when the target was sputtered using argon (Ar) or oxygen (O). Figure 46A The cross-sectional structure of the InGaZnO4 crystal (2688 atoms) used for the calculation is shown. Figure 46B Shows its top view structure. Figure 46A The fixed layer shown is a layer that fixes the atomic configuration so that its position does not change. Figure 46A The temperature control layer shown is a layer that is always kept at a constant temperature (300K).

[0344] Classical molecular dynamics calculations were performed using Materials Explorer 5.0, manufactured by Fujitsu Limited. The initial temperature was set to 300 K, the cell size was constant, the time step was set to 0.01 femtoseconds, and the number of steps was set to 10 million. During the calculations, an energy of 300 eV was applied to the atoms under these conditions, and the atoms were incident on the cell perpendicular to the ab plane of the InGaZnO4 crystal.

[0345] Figure 47A Argon is incident on a Figure 46A and46B The atomic arrangement in the InGaZnO4 crystal unit cell shown in Figure 99.9 picoseconds (psec). Figure 47B The atomic arrangement of oxygen after it is injected into the cell is shown in Figure 99.9 picoseconds. Figure 47A and 47B omitted in Figure 46A A portion of the fixed layer is shown.

[0346] Depend on Figure 47A It can be seen that from the time when argon is incident into the cell to 99.9 picoseconds, the time corresponding to Figure 45A Therefore, it can be seen that when argon collides with the InGaZnO4 crystal, a large crack is generated in the second surface (the 0th second surface) with the top surface being the second surface (the 0th second surface).

[0347] On the other hand, by Figure 47B It can be seen that from the time when oxygen is incident into the cell to 99.9 picoseconds, the time corresponding to Figure 45A The cleavage plane of the second surface shown here shows cracks. Note that when oxygen collides with the cell, large cracks are generated in the second surface (first second surface) of the InGaZnO4 crystal.

[0348] This indicates that when atoms (ions) collide with the top surface of a target material composed of InGaZnO4 crystals having a homologous structure, the InGaZnO4 crystals cleave along the second surface, and flat-plate particles (grains) are exfoliated. Furthermore, it is also apparent that the particle size when oxygen is collided with the cell is smaller than when argon is collided with the cell.

[0349] Furthermore, the calculations above show that the peeled particles include damaged regions, and the damaged regions included in the particles can sometimes be repaired by reacting defects generated by the damage with oxygen.

[0350] Therefore, it was investigated whether the particle size varies depending on the type of colliding atoms.

[0351] Figure 48A shows the transition from argon incident to Figure 46A and 46B The trajectory of each atom in a cell of InGaZnO4 crystal from 0 picosecond to 0.3 picosecond is shown. Figure 48A Corresponding to Figure 46A and 46B to Figure 47A period.

[0352] Depend on Figure 48AIt is known that when argon collides with gallium (Ga) in the first layer (Ga-Zn-O layer), the gallium collides with zinc (Zn) in the third layer (Ga-Zn-O layer), and then the zinc reaches the vicinity of the sixth layer (Ga-Zn-O layer). In addition, oxygen colliding with gallium is ejected to the outside. Therefore, it is believed that when argon collides with a target material composed of InGaZnO4 crystals, Figure 46A Cracks occur on the second surface (the second second surface).

[0353] Figure 48B Shows the transition from oxygen incident to Figure 46A and 46B The trajectory of each atom in a cell of InGaZnO4 crystal from 0 picosecond to 0.3 picosecond is shown. Figure 48B Corresponding to Figure 46A and 46B to Figure 47A period.

[0354] On the other hand, by Figure 48B It is known that when oxygen collides with gallium (Ga) in the first layer (Ga-Zn-O layer), zinc (Zn) in the third layer (Ga-Zn-O layer) does not reach the fifth layer (In-O layer). In addition, the oxygen colliding with gallium is ejected to the outside. Therefore, it is believed that when oxygen collides with the target material composed of InGaZnO4 crystals, Figure 46A Cracks occur on the second surface (first second surface).

[0355] This calculation also shows that when atoms (ions) collide, the InGaZnO4 crystal peels off from the cleavage plane.

[0356] In addition, the depth of the crack is discussed from the perspective of conservation laws. The energy conservation law and momentum conservation law can be expressed by formula (1) and formula (2). Here, E is the energy of argon or oxygen before the collision (300 eV), m A is the mass of argon or oxygen, v A is the velocity of argon or oxygen before the collision, v′ A is the velocity of argon or oxygen after the collision, m Ga is the mass of gallium, v Ga is the velocity of gallium before the collision, v′ G a is the velocity of gallium after the collision. m A v A +m Ga v Ga =m A v′ A +m Ga v′ Ga (2)

[0357] When the collision of argon or oxygen is assumed to be elastic, v can be expressed by formula (3): A 、v′ A 、v Ga and v′ Ga relationship. v′ A =v′ Ga =-(v A -v Ga ) (3)

[0358] According to formula (1), formula (2) and formula (3), in v Ga When it is 0, the velocity v′ of gallium after collision with argon or oxygen can be expressed by formula (4): G a.

[0359] In formula (4), substitute the mass of argon or oxygen into m A The gallium velocities after each atomic collision were compared. When the energies of argon and oxygen before the collision were the same, the gallium velocity during the argon collision was 1.24 times greater than the gallium velocity during the oxygen collision. Therefore, the gallium energy during the argon collision was also higher than the gallium energy during the oxygen collision by the square of the gallium velocity.

[0360] It is known that the velocity (energy) of gallium after collision with argon is higher than that with oxygen. Therefore, it is thought that cracks are generated at deeper positions when argon collision occurs than when oxygen collision occurs.

[0361] From the above calculations, it can be seen that by sputtering a target material including a crystal of InGaZnO4 having a homologous structure, particles are peeled off from the cleavage plane to form particles. On the other hand, even if other structural areas of the target material without a cleavage plane are sputtered, particles are not formed, but sputtered particles with atomic-level sizes finer than the particles are formed. Because the sputtered particles are smaller than the particles, they are considered to be discharged by a vacuum pump connected to the sputtering device. Therefore, when sputtering a target material including a crystal of InGaZnO4 having a homologous structure, it is difficult to consider a model in which particles of various sizes or shapes fly to the substrate and are deposited to form a film. The sputtered particles are deposited to form CAAC-OS. Figure 40A The model shown in the following example makes more sense.

[0362] The density of the CAAC-OS formed by the above steps is roughly the same as that of the single-crystalline OS. For example, the density of the single-crystalline OS with the homologous structure of InGaZnO4 is 6.36 g / cm 3 , while the density of CAAC-OS with approximately the same atomic ratio is 6.3 g / cm 3about.

[0363] Figure 49A and 49B The In-Ga-Zn oxide of CAAC-OS formed by sputtering is shown (refer to Figure 49A ) and its target (refer to Figure 49B ) cross-section. The atomic arrangement was observed using high-angle annular dark field scanning transmission electron microscopy (HAADF-STEM). Note that in HAADF-STEM, the intensity of each atom's image is proportional to the square of its atomic number. Therefore, Zn (atomic number 30) and Ga (atomic number 31), which have similar atomic numbers, are almost indistinguishable. For HAADF-STEM, a Hitachi HD-2700 scanning transmission electron microscope was used.

[0364] In the pair Figure 49A and 49B When compared, it can be seen that both CAAC-OS and the target material have a homologous structure, and the configuration of atoms in CAAC-OS corresponds to that of the target material. Figure 40A As shown in the film formation model of

[15] , the crystal structure of the target is transferred to form CAAC-OS.

[0365] The structure and method described in this embodiment can be used in combination with the structure and method described in other embodiment modes as appropriate.

[0366] Implementation 3 In this embodiment, oxygen vacancies in an oxide semiconductor film are described in detail below.

[0367] 〈(1)V O H formation and stability When the oxide semiconductor film (hereinafter referred to as IGZO) is a complete crystal, H diffuses preferentially along the ab plane at room temperature. When heated at 450°C, H diffuses along the ab plane and the c-axis. This indicates that when oxygen vacancies V are present in IGZO, O Is it easy for H to enter the oxygen deficiency V O Here, the oxygen deficiency V O The state in which H exists is called V O H.

[0368] In calculations, use Figure 20 Here, the Nudged Elastic Band (NEB) method is used to analyze the crystal model of InGaZnO4. OThe H in H is from V O The activation energy of the reaction path for the released oxygen bond (E a Table 2 shows the calculation conditions.

[0369] [Table 2] software VASP Calculation method NEB method Functional GGA-PBE pseudopotential PAW Cutoff energy 500eV K point 2×2×3 In the crystal model of InGaZnO4, Figure 20 As shown, there are oxygen positions 1 to 4, each containing a metal element bonded to oxygen and a different number of metal elements. O The oxygen position 1 and oxygen position 2 are calculated.

[0370] First, as V is prone to forming oxygen vacancies O The oxygen position 1 of is calculated, and the oxygen position bonded to three In atoms and one Zn atom is calculated.

[0371] Figure 21A The model shows the initial state, Figure 21B The model of the final state is shown. In addition, Figure 22 The activation energy (E a Note that the “initial state” here refers to the state in which the oxygen deficiency V O The state where H exists (V O H), and the "final state" refers to the following structure: with oxygen deficiency V O And the state in which oxygen bonded to one Ga atom and two Zn atoms is bonded to H (HO).

[0372] From the calculation results, we can know that when the oxygen deficiency V O When H in the oxygen atom bonds with other O atoms, it requires an energy of about 1.52 eV. When H bonded to O enters the oxygen vacancy V O An energy of approximately 0.46 eV is required.

[0373] Here, according to the activation energy (E a ) and formula 5, calculate the reaction frequency (Γ). In formula 5, k B represents the Boltzmann constant, and T represents the absolute temperature.

[0374] [Formula 5] Assume frequency factor v = 10 13 [1 / sec], calculate the reaction frequency at 350℃. Figure 21A The position in the model shown is moved to Figure 21B The frequency of the position in the model shown is 5.52×10 0 [1 / sec]. In addition, H Figure 21B The position in the model shown is moved to Figure 21A The frequency of the positions in the model shown is 1.82×10 9 [1 / sec]. It can be seen from this that the H diffused in IGZO has oxygen vacancies V near it. O V is easily formed when O H, once V is formed O H is not easy to be lost from oxygen deficiency O Release H.

[0375] Next, as the oxygen vacancy V is easily formed O The oxygen positions 2 of are calculated for the oxygen positions bonded to one Ga atom and two Zn atoms.

[0376] Figure 23A The model shows the initial state, Figure 23B The model of the final state is shown. In addition, Figure 24 The activation energy (E a Note that the “initial state” here refers to the state in which the oxygen deficiency V O The state where H exists (V O H), and the "final state" refers to the following structure: with oxygen deficiency V O And the state in which oxygen bonded to one Ga atom and two Zn atoms is bonded to H (HO).

[0377] From the calculation results, we can know that when the oxygen deficiency V O When H in the O atom bonds with other O atoms, it requires an energy of about 1.75 eV. When H bonded to O enters the oxygen vacancy V O An energy of approximately 0.35 eV is required.

[0378] According to the activation energy (E a ) and the above formula 5, calculate the response frequency (Γ).

[0379] Assume frequency factor v = 10 13 [1 / sec], calculate the reaction frequency at 350℃. Figure 23A The position in the model shown is moved to Figure 23B The local frequency in the model shown is 7.53×10 -2 [1 / sec]. In addition, H Figure 23B The position in the model shown is moved to Figure 23A The frequency of the positions in the model shown is 1.44×10 10 [1 / sec]. It can be seen from this that once V is formed O H is not easy to be lost from oxygen deficiency O Release H.

[0380] From the above results, it can be seen that when annealing is performed, H in IGZO is easily diffused. O When H easily enters the oxygen deficiency V O And become V O H.

[0381] 〈(2)V O H migration level When there are oxygen vacancies in IGZO, V O When H, according to 〈(1)V O The calculation using the NEB method shown in the figure shows the ease of formation and stability of H. It can be considered that the oxygen deficiency V O It is easy to form V with H O H, and V O H is stable. So, in order to investigate V O Is H related to carrier traps? Calculate V O The migration energy level of H.

[0382] In the calculation, the crystal model of InGaZnO4 (112 atoms) was used. Figure 20 V at oxygen position 1 and oxygen position 2 shown O The migration energy levels were calculated based on the model of H. Table 3 shows the calculation conditions.

[0383] [Table 3] software VASP Model <![CDATA[Crystal model of InGaZnO4 (112 atoms)]]> Functional HSE06 Mixing ratio of exchange terms 0.25 pseudopotential GGA-PBE Cutoff energy 800eV K point 1×1×1 By adjusting the mixing ratio of the exchange term so as to form an energy gap close to the experimental value, the energy gap of the defect-free InGaZnO4 crystal model becomes 3.08 eV, which is close to the experimental value of 3.15 eV.

[0384] The transition energy level (ε(q / q')) of the model with defect D is calculated according to the following formula 6. In addition, ΔE(D q ) is the formation energy of the charge q of the defect D, which is calculated according to the following formula 7.

[0385] [Formula 6] [Formula 7] In equations 6 and 7, E tot (D q ) represents the total energy of the charge q of the model containing the defect D, E tot (bulk) represents the total energy of the model without defects (complete crystal), Δn i represents the increase or decrease in the number of atoms i due to defects, μ i represents the chemical potential of atom i, εVBM represents the energy of the valence band top in the model without defects, ΔV q represents the correction term related to the electrostatic potential, E f represents the Fermi energy.

[0386] Figure 25 The V calculated according to the above formula is shown O The migration energy level of H. Figure 25 The value in represents the depth from the bottom of the conduction band. Figure 25 It can be seen that V at oxygen position 1 O The migration energy level of H exists at 0.05eV below the conduction band, and the V O The migration energy level of H exists at 0.11eV below the conduction band, so each V O H is related to electron traps. That is, it is known that V O H is used as a donor. It can also be seen that V O H-IGZO has electrical conductivity.

[0387] The structure described in this embodiment can be used in combination with the structures described in other embodiment modes as appropriate.

[0388] Implementation 4 In this embodiment, the Figures 26 to 28 An example of a display device using the transistors and capacitors described as examples in the above embodiments will be described.

[0389] Figure 26 It is a plan view showing an example of a display device. Figure 26 The display device 700 shown includes: a pixel portion 702 provided on a first substrate 701; a source driver circuit portion 704 and a gate driver circuit portion 706 provided on the first substrate 701; a sealant 712 provided so as to surround the pixel portion 702, the source driver circuit portion 704 and the gate driver circuit portion 706; and a second substrate 705 provided so as to be opposite to the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealant 712. That is, the pixel portion 702, the source driver circuit portion 704 and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712 and the second substrate 705. Note that although in Figure 26 Although not shown in the figure, a display element is provided between the first substrate 701 and the second substrate 705.

[0390] In the display device 700, an FPC (Flexible Printed Circuit) terminal portion 708 is provided in an area on the first substrate 701 that is not surrounded by the sealant 712. The FPC terminal portion 708 is electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706. Furthermore, the FPC terminal portion 708 is connected to an FPC 716, and various signals are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 via the FPC 716. Furthermore, the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 are each connected to a signal line 710. Various signals supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portion 708 via the signal line 710.

[0391] In addition, a plurality of gate driver circuit portions 706 may be provided in the display device 700. In addition, as the display device 700, although an example is shown in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed on the same first substrate 701 as the pixel portion 702, it is not limited to this structure. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. In this case, a structure in which a substrate having a source driver circuit or a gate driver circuit formed thereon (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted on the first substrate 701 may also be adopted. In addition, there is no particular limitation on the connection method of the separately formed driver circuit substrate, and a COG (Chip On Glass) method, a wire bonding method, or the like may be adopted.

[0392] The pixel portion 702, source driver circuit portion 704, and gate driver circuit portion 706 included in the display device 700 include a plurality of transistors, and the transistors of the semiconductor device according to one embodiment of the present invention can be applied as the transistors. Furthermore, the transistors and capacitors of the semiconductor device according to one embodiment of the present invention can be applied to the pixel portion 702.

[0393] The display device 700 may include various elements. Examples of these elements include at least one of a liquid crystal element, an EL (electroluminescent) element (including organic and inorganic materials, organic EL elements, or inorganic EL elements), an LED (white, red, green, or blue), a transistor (a transistor that emits light in response to an electric current), an electron emitter, electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), a display element using a microelectromechanical system (MEMS), a digital micromirror device (DMD), a digital microshutter (DMS), a MIRASOL (registered trademark), an IMOD (interferometry modulation) element, a shutter-type MEMS display element, an optical interference-type MEMS display element, an electrowetting element, a piezoelectric ceramic display, or a carbon nanotube display element. Furthermore, the display device may include a display medium that changes contrast, brightness, reflectivity, transmittance, or the like through electrical or magnetic effects. Examples of display devices using EL elements include EL displays. As an example of a display device using an electron emission element, there are field emission displays (FED) or SED flat-panel displays (SED: Surface-conduction Electron-emitter Display: surface conduction electron emission display). As an example of a display device using a liquid crystal element, there are liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), etc. As an example of a display device using electronic ink or electrophoretic elements, there are electronic paper, etc. Note that when implementing a semi-transmissive liquid crystal display or a reflective liquid crystal display, it is sufficient to make part or all of the pixel electrodes have the function of a reflective electrode. For example, it is sufficient to make part or all of the pixel electrodes contain aluminum, silver, etc. In addition, at this time, a storage circuit such as SRAM can also be set under the reflective electrode. This can further reduce power consumption.

[0394] As a display mode of the display device 700, a progressive scanning mode or an interlaced scanning mode can be adopted. In addition, the color elements controlled in the pixel when performing color display are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it can be composed of four pixels of R pixel, G pixel, B pixel and W (white) pixel. Alternatively, as in the PenTile arrangement, a color element can be composed of two colors in RGB, and two different colors can be selected according to the color element. Alternatively, one or more colors such as yellow, cyan, magenta, etc. can be added to RGB. In addition, the size of the display area of ​​the point of each color element can be different. However, the disclosed invention is not limited to a display device for color display, but can also be applied to a display device for black and white display.

[0395] In addition, in order to use white light (W) for a backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) to enable the display device to perform full-color display, a coloring layer (also called a filter) can also be used. As a coloring layer, for example, red (R), green (G), blue (B), yellow (Y), etc. can be used in appropriate combinations. By using a coloring layer, the color reproducibility can be further improved compared to the case where a coloring layer is not used. At this time, it is also possible to directly use the white light in the area that does not include the coloring layer by setting an area that includes a coloring layer and an area that does not include a coloring layer. By partially setting an area that does not include a coloring layer, when displaying a bright image, the brightness reduction caused by the coloring layer can sometimes be reduced and the power consumption can be reduced by about 20% to 30%. However, when using self-luminous elements such as organic EL elements or inorganic EL elements for full-color display, R, G, B, Y, and W can also be emitted from elements with each luminous color. By using self-luminous elements, power consumption can sometimes be further reduced compared to the case where a coloring layer is used.

[0396] In this embodiment, the Figure 27 and Figure 28 A structure using a liquid crystal element and an EL element as a display element will be described. Figure 27 It is along Figure 26 The cross-sectional view along the dot-dash line QR shown in FIG. 1 shows a structure in which a liquid crystal element is used as a display element. Figure 28 It is along Figure 26 The cross-sectional view taken along the dashed-dotted line QR shows a structure in which an EL element is used as a display element.

[0397] Below, first explain Figure 27 and Figure 28 The common parts are shown, and then the different parts are described.

[0398] <Description of Common Parts of Display Devices> Figure 27 and Figure 28 The display device 700 shown includes a routing wiring section 711, a pixel section 702, a source driver circuit section 704, and an FPC terminal section 708. The routing wiring section 711 includes a signal line 710. The pixel section 702 includes a transistor 750 and a capacitor 790. The source driver circuit section 704 includes a transistor 752.

[0399] The transistor 750 and the transistor 752 have the same structure as the transistor 100A described above. The transistor 750 and the transistor 752 may also have a structure using other transistors described in the previous embodiment.

[0400] The transistor used in this embodiment includes an oxide semiconductor film that is highly purified and in which the formation of oxygen defects is suppressed. The transistor can reduce the current value in the off state (off-state current value). Therefore, the retention time of electrical signals such as image signals can be extended, and the write interval can also be extended in the power-on state. Therefore, the frequency of refresh operation can be reduced, thereby achieving the effect of suppressing power consumption.

[0401] In addition, the transistors used in this embodiment can obtain a high field-effect mobility and thus can be driven at high speed. For example, by using such a transistor capable of high-speed drive in a liquid crystal display device, a switching transistor for a pixel portion and a driving transistor for a driving circuit portion can be formed on the same substrate. In other words, because a semiconductor device formed of a silicon wafer or the like is not required as a driving circuit, the number of components of the semiconductor device can be reduced. In addition, high-quality images can be provided in the pixel portion by using a transistor capable of high-speed drive.

[0402] Capacitor element 790 has the same structure as capacitor element 150A described above.

[0403] In addition, Figure 27 and Figure 28 In FIG. 5 , an insulating film 766 and a planarizing insulating film 770 are provided over the transistor 750 , the transistor 752 , and the capacitor 790 .

[0404] The insulating film 766 can be formed using the same materials and manufacturing methods as those used for the insulating film 128 described in the previous embodiment. Alternatively, the planarizing insulating film 770 can be formed using a heat-resistant organic material such as a polyimide resin, acrylic resin, polyimideamide resin, benzocyclobutene resin, polyamide resin, or epoxy resin. The planarizing insulating film 770 can also be formed by stacking multiple insulating films made of these materials. Alternatively, a structure without the planarizing insulating film 770 can be employed.

[0405] The signal line 710 is formed in the same process as the conductive film used as the source and drain electrodes of the transistors 750 and 752. The signal line 710 may also be formed using the conductive film used as the gate electrode of the transistors 750 and 752, such as the conductive film used as the first gate electrode or the conductive film used as the second gate electrode. For example, using a material containing copper as the signal line 710 reduces signal delay due to wiring resistance, enabling large-screen displays.

[0406] Furthermore, the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and the FPC 716. The connection electrode 760 is formed in the same process as the conductive films serving as the source and drain electrodes of the transistors 750 and 752. Furthermore, the connection electrode 760 is electrically connected to the terminals included in the FPC 716 via the anisotropic conductive film 780.

[0407] Note that, for example, a glass substrate can be used as the first substrate 701 and the second substrate 705. Alternatively, a flexible substrate can be used as the first substrate 701 and the second substrate 705. Examples of such a flexible substrate include a plastic substrate.

[0408] A structure 778 is provided between the first substrate 701 and the second substrate 705. The structure 778 is a columnar spacer formed by selectively etching an insulating film and is used to control the distance (cell gap) between the first substrate 701 and the second substrate 705. Alternatively, a spherical spacer may be used as the structure 778.

[0409] Furthermore, on the second substrate 705 side, a light-shielding film 738 serving as a black matrix, a colored film 736 serving as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the colored film 736 are provided.

[0410] <Structural Example of a Display Device Using a Liquid Crystal Element as a Display Element> Figure 27 The display device 700 shown includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on the second substrate 705 side and functions as a counter electrode. Figure 27 The display device 700 shown can display an image by changing the alignment state of the liquid crystal layer 776 by applying voltage to the conductive films 772 and 774, thereby controlling the transmission and non-transmission of light.

[0411] The conductive film 772 is connected to a conductive film serving as a source electrode and a drain electrode included in the transistor 750. The conductive film 772 serves as a pixel electrode, that is, one electrode of the display element, formed on the planarizing insulating film 770. The conductive film 772 also functions as a reflective electrode. Figure 27 The display device 700 shown is a so-called reflective color liquid crystal display device that reflects external light from a conductive film 772 and transmits it through a colored film 736 to perform display.

[0412] The conductive film 772 can be a conductive film that is translucent to visible light or a conductive film that is reflective to visible light. For example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used as the conductive film that is translucent to visible light. For example, a material containing aluminum or silver is preferably used as the conductive film that is reflective to visible light. In this embodiment, a conductive film that is reflective to visible light is used as the conductive film 772.

[0413] In addition, Figure 27 In the display device 700 shown, a portion of the planarization insulating film 770 of the pixel portion 702 is provided with irregularities. This irregularity can be formed, for example, by forming the planarization insulating film 770 using an organic resin film or the like and providing concave or convex portions on the surface of the organic resin film. Furthermore, a conductive film 772 serving as a reflective electrode is formed along these irregularities. Therefore, when external light is incident on the conductive film 772, the light is diffusely reflected from the surface of the conductive film 772, thereby improving visibility.

[0414] Note that although Figure 27 The display device 700 shown in the figure exemplifies a reflective color liquid crystal display device, but the present invention is not limited to this. For example, a transmissive color liquid crystal display device can be fabricated by using a conductive film that is transmissive to visible light for the conductive film 772. When the display device is a transmissive color liquid crystal display device, a structure can be employed in which the planarization insulating film 770 is not provided with uneven surfaces.

[0415] Note that although Figure 27 Although not shown in the figure, an alignment film may be provided on each side of the conductive films 772 and 774 that contacts the liquid crystal layer 776. Figure 27 Although not shown in the figure, optical components (optical substrates) such as polarizing components, phase difference components, and anti-reflection components can be appropriately provided. For example, circular polarization using a polarizing substrate and a phase difference substrate can also be used. In addition, backlighting, sidelighting, etc. can also be used as the light source.

[0416] When a liquid crystal element is used as a display element, thermotropic liquid crystal, low molecular liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, etc. These liquid crystal materials exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, etc. depending on the conditions.

[0417] In addition, when the transverse electric field method is adopted, liquid crystals exhibiting a blue phase that do not require an orientation film can also be used. The blue phase is a type of liquid crystal phase that appears just before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase only appears within a narrow temperature range, a liquid crystal composition mixed with a chiral agent of several wt.% or more is used in the liquid crystal layer in order to improve the temperature range. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a fast response speed. In addition, the liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has optical isotropy, and thus does not require orientation treatment and has low viewing angle dependence. In addition, since there is no need to provide an orientation film, friction treatment is not required, and thus electrostatic damage caused by friction treatment can be prevented, thereby reducing defects and damage to the liquid crystal display device during the manufacturing process.

[0418] When a liquid crystal element is used as a display element, a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (Anti Ferroelectric Liquid Crystal) mode, or the like can be employed.

[0419] Alternatively, a normally black liquid crystal display device, such as a transmissive liquid crystal display device employing a vertical alignment (VA) mode, may be used. Examples of vertical alignment modes include the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, and the ASV (Advanced SuperView) mode.

[0420] <Display device using a light-emitting element as a display element> Figure 28 The display device 700 shown includes a light-emitting element 782. The light-emitting element 782 includes a conductive film 784, an EL layer 786, and a conductive film 788. Figure 28 In the display device 700 shown, an image can be displayed by causing the EL layer 786 included in the light-emitting element 782 to emit light.

[0421] In addition, the conductive film 784 is connected to a conductive film serving as a source electrode and a drain electrode included in the transistor 750. The conductive film 784 serves as a pixel electrode formed on the planarization insulating film 770, that is, one electrode of the display element. As the conductive film 784, a conductive film that is transmissive to visible light or a conductive film that is reflective to visible light can be used. As the conductive film that is transmissive to visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. As the conductive film that is reflective to visible light, for example, a material containing aluminum or silver is preferably used.

[0422] in addition, Figure 28 The display device 700 shown in the figure includes a planarizing insulating film 770 and an insulating film 730 on a conductive film 784. The insulating film 730 covers a portion of the conductive film 784. Note that the light-emitting element 782 has a top-emission structure. Therefore, the conductive film 788 is light-transmitting, allowing light emitted by the EL layer 786 to pass through. Note that while a top-emission structure is illustrated in this embodiment, the present invention is not limited to this. For example, a bottom-emission structure in which light is emitted from one side of the conductive film 784 or a dual-emission structure in which light is emitted from both the conductive film 784 and the conductive film 788 can also be used.

[0423] In addition, a coloring film 736 is provided at a position overlapping with the light emitting element 782, and a light shielding film 738 is provided at a position overlapping with the insulating film 730, the routing wiring portion 711, and the source driver circuit portion 704. The coloring film 736 and the light shielding film 738 are covered by the insulating film 734. The sealing film 732 is filled between the light emitting element 782 and the insulating film 734. Note that although Figure 28 The display device 700 shown in the figure is provided with the colored film 736 as an example, but the present invention is not limited to this. For example, when the EL layer 786 is formed by separate coating, the colored film 736 may not be provided.

[0424] The structure described in this embodiment can be implemented in combination with the structures described in other embodiment modes as appropriate.

[0425] Implementation 5 In this embodiment, one embodiment of a light-emitting device using a semiconductor device according to one embodiment of the present invention is described. Note that in this embodiment, Figure 29A and29B The structure of a pixel portion of a light-emitting device will be described.

[0426] exist Figure 29A In the embodiment, a plurality of FETs 500 are formed over a first substrate 502, and each FET 500 is electrically connected to each light-emitting element (504R, 504G, 504B, 504W). Specifically, each FET 500 is electrically connected to a first conductive film 506 included in the light-emitting element. Note that each light-emitting element (504R, 504G, 504B, 504W) is composed of the first conductive film 506, the second conductive film 507, the EL layer 510, and the third conductive film 512.

[0427] Furthermore, colored layers (514R, 514G, 514B, 514W) are provided at positions opposing the respective light-emitting elements (504R, 504G, 504B, 504W). Note that the colored layers (514R, 514G, 514B, 514W) are provided in contact with the second substrate 516. Furthermore, a sealing film 518 is provided between the first substrate 502 and the second substrate 516. The sealing film 518 can be made of, for example, a glass material such as glass frit, a curable resin such as a two-component mixed resin that cures at room temperature, a light-curable resin, or a thermosetting resin.

[0428] In addition, a partition wall 508 is provided so as to cover the ends of the adjacent first conductive film 506 and the second conductive film 507. In addition, a structure 509 is formed on the partition wall 508. Note that the first conductive film 506 has the function of a reflective electrode and the function of an anode of the light-emitting element. In addition, the second conductive film 507 has the function of adjusting the optical path length of each light-emitting element. In addition, an EL layer 510 is formed on the second conductive film 507, and a third conductive film 512 is formed on the EL layer 510. In addition, the third conductive film 512 has the function of a semi-transmissive and semi-reflective electrode and the function of a cathode of the light-emitting element. In addition, the structure 509 is provided between the light-emitting element and the colored layer and has the function of a spacer.

[0429] In addition, the EL layer 510 can be used in common by each light-emitting element (504R, 504G, 504B, 504W). Note that each light-emitting element (504R, 504G, 504B, 504W) has a so-called optical micro-resonator (also called micro-cavity) structure in which the light emitted from the EL layer 510 is resonated by the first conductive film 506 and the third conductive film 512. Even if the EL layer 510 is the same, the spectrum of different wavelengths can be extracted by narrowing the line width. Specifically, in each light-emitting element (504R, 504G, 504B, 504W), by adjusting the thickness of the second conductive film 507 provided below the EL layer 510, the spectrum obtained from the EL layer 510 becomes the desired emission spectrum, and light emission with high color purity can be obtained. Therefore, by adopting Figure 29A The structure shown does not require a separate coating step of the EL layer, and thus can achieve high definition.

[0430] In addition, Figure 29A The light-emitting device shown includes a coloring layer (color filter). Therefore, by combining the microcavity structure and the color filter, light with higher color purity can be obtained. Specifically, the optical path length of the light-emitting element 504R is adjusted so that red light can be obtained, and red light is emitted in the direction of the arrow via the coloring layer 514R. The optical path length of the light-emitting element 504G is adjusted so that green light can be obtained, and green light is emitted in the direction of the arrow via the coloring layer 514G. The optical path length of the light-emitting element 504B is adjusted so that blue light can be obtained, and blue light is emitted in the direction of the arrow via the coloring layer 514B. The optical path length of the light-emitting element 504W is adjusted so that white light can be obtained, and white light is emitted in the direction of the arrow via the coloring layer 514W.

[0431] Note that the method of adjusting the optical path length of each light-emitting element is not limited to this. For example, the optical path length can be adjusted by adjusting the thickness of the EL layer 510 in each light-emitting element.

[0432] The colored layers (514R, 514G, 514B) only need to transmit light in specific wavelength ranges. For example, a red (R) filter that transmits light in the red wavelength range, a green (G) filter that transmits light in the green wavelength range, and a blue (B) filter that transmits light in the blue wavelength range can be used. Furthermore, the colored layer 514W can be made of, for example, an acrylic resin material that does not contain pigments. The colored layers (514R, 514G, 514B, 514W) can be formed using various materials using printing, inkjet printing, etching using photolithography, and the like.

[0433] For example, a metal film having high reflectivity (visible light reflectivity of 40% to 100%, preferably 70% to 100%) can be used as the first conductive film 506. The first conductive film 506 can be formed using a single layer or a stack of aluminum, silver, or an alloy containing these metal materials (for example, an alloy of indium, palladium, and copper).

[0434] The second conductive film 507 can be formed using, for example, a conductive metal oxide. Examples of the conductive metal oxide include indium oxide, tin oxide, zinc oxide, indium tin oxide, indium zinc oxide, or materials containing silicon oxide or tungsten oxide in these metal oxide materials. Providing the second conductive film 507 is preferred because it prevents the formation of an insulating film between the EL layer 510 formed later and the first conductive film 506. Alternatively, a conductive metal oxide serving as the second conductive film 507 may be formed below the first conductive film 506.

[0435] Furthermore, the third conductive film 512 is formed using a reflective conductive material and a light-transmitting conductive material, and its reflectivity for visible light is preferably 20% to 80%, more preferably 40% to 70%. For example, the third conductive film 512 can be formed thinly (e.g., 10 nm or less) using silver, magnesium, or an alloy containing these metals, and then a conductive metal oxide that can be used for the second conductive film 507 can be formed.

[0436] In the structure described above, a structure in which light is extracted from the second substrate 516 side (a top emission structure) is employed. However, a structure in which light is extracted from the first substrate 501 side on which the FET 500 is formed (a bottom emission structure) or a structure in which light is extracted from both the first substrate 501 side and the second substrate 516 side (a dual emission structure) may also be employed. In the case of a bottom emission structure, for example, the colored layers (514R, 514G, 514B, 514W) may be formed below the first conductive film 506. Note that a light-transmitting substrate may be used as the substrate on the light-emitting side, and a light-transmitting substrate or a light-shielding substrate may be used as the substrate on the non-light-emitting side.

[0437] In addition, although Figure 29A The example shows a structure in which light emitting elements have four colors (red (R), green (G), blue (B), and white (W)), but the present invention is not limited to this. For example, a structure in which light emitting elements have three colors (red (R), green (G), and blue (B)) can also be used.

[0438] Here, use Figure 29B The connection relationship between each light emitting element and each FET is described in detail. Figure 29Byes Figure 29A An example of the structure of the region 520 surrounded by the dotted line is shown.

[0439] exist Figure 29B In the embodiment, an insulating film 522 serving as a planarizing film is formed on the FET 500. An opening 524 is formed in the insulating film 522, which reaches the conductive film serving as the source electrode or drain electrode of the FET 500. A first conductive film 506 connected to the conductive film serving as the source electrode or drain electrode of the FET 500 is formed on the insulating film 522. A second conductive film 507 is formed on the first conductive film 506.

[0440] The FET 500 has the same structure as the transistor 100A described in the previous embodiment, and therefore the description of the FET 500 is omitted here.

[0441] The structure described in this embodiment can be used in combination with the structures described in other embodiment modes as appropriate.

[0442] Implementation Method 6 In this embodiment, a structural example of a display device according to one embodiment of the present invention is described.

[0443] <Configuration Example of Display Device> Figure 31A A top view of a display device according to one embodiment of the present invention is shown. Figure 31B A pixel circuit is shown when a liquid crystal element is used for a pixel of a display device according to one embodiment of the present invention. Figure 31C A pixel circuit is shown when an organic EL element is used for a pixel of a display device according to one embodiment of the present invention.

[0444] The transistors used for pixels can use the above-mentioned transistors. An example of using an n-channel transistor is shown here. Note that a transistor manufactured by the same process as the transistors used for pixels can also be used as a driver circuit. Furthermore, the above-mentioned capacitor element can be used as a capacitor element for a pixel. In this way, by using the above-mentioned transistors and capacitor elements in pixels or driver circuits, a display device with high display quality and / or reliability can be manufactured.

[0445] Figure 31AAn example of a top view of an active matrix display device is shown. A pixel portion 5001, a first scan line driver circuit 5002, a second scan line driver circuit 5003, and a signal line driver circuit 5004 are provided on a substrate 5000 of the display device. The pixel portion 5001 is electrically connected to the signal line driver circuit 5004 via a plurality of signal lines and is electrically connected to the first scan line driver circuit 5002 and the second scan line driver circuit 5003 via a plurality of scan lines. Furthermore, pixels including display elements are provided in the regions demarcated by the scan lines and the signal lines. Furthermore, the substrate 5000 of the display device is electrically connected to a timing control circuit (also referred to as a controller or control IC) via a connection portion such as an FPC (flexible printed circuit).

[0446] The first scan line driver circuit 5002, the second scan line driver circuit 5003, and the signal line driver circuit 5004 are formed on the substrate 5000, similarly to the pixel portion 5001. Therefore, the cost of manufacturing the display device can be reduced compared to manufacturing the driver circuit separately. Furthermore, manufacturing the driver circuit separately increases the number of connections between wirings. Therefore, by providing the driver circuit on the same substrate 5000, the number of connections between wirings can be reduced, thereby improving reliability and / or yield.

[0447] <(1) Liquid crystal display device> also, Figure 31B An example of a pixel circuit structure is shown. Here, a pixel circuit that can be applied to pixels of a VA-type liquid crystal display device, etc. is shown.

[0448] This pixel circuit can be applied to a structure where a pixel includes multiple pixel electrodes. Each pixel electrode is connected to a different transistor, and each transistor is configured to be driven by a different gate signal. This allows the signal applied to each pixel electrode in a multi-domain pixel design to be independently controlled.

[0449] The gate wiring 5012 of transistor 5016 and the gate wiring 5013 of transistor 5017 are separated to supply different gate signals thereto. Meanwhile, transistors 5016 and 5017 share a source electrode or drain electrode 5014, which functions as a data line. The aforementioned transistors can be used as appropriate for transistor 5016 and transistor 5017. Furthermore, the aforementioned capacitors can be used as appropriate for capacitors 5023a and 5023b. This allows for a liquid crystal display device with high display quality and / or reliability.

[0450] The transistor 5016 is electrically connected to the first pixel electrode, and the transistor 5017 is electrically connected to the second pixel electrode. The first pixel electrode and the second pixel electrode are separated from each other. The shapes of the first pixel electrode and the second pixel electrode are not limited to this, and may be, for example, V-shaped.

[0451] The gate electrode of the transistor 5016 is electrically connected to the gate wiring 5012, and the gate electrode of the transistor 5017 is electrically connected to the gate wiring 5013. Different gate signals are supplied to the gate wiring 5012 and the gate wiring 5013 to synchronize the operation timings of the transistors 5016 and 5017, thereby controlling the alignment of liquid crystals.

[0452] Alternatively, a capacitor element may be formed using the capacitor wiring 5010, an insulating film serving as a dielectric, and a conductive film electrically connected to the first pixel electrode or the second pixel electrode.

[0453] In the multi-domain structure, one pixel includes a first liquid crystal element 5018 and a second liquid crystal element 5019. The first liquid crystal element 5018 is composed of a first pixel electrode, a counter electrode, and a liquid crystal layer therebetween, while the second liquid crystal element 5019 is composed of a second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

[0454] In addition, the display device according to one embodiment of the present invention is not limited to Figure 31B For example, the pixel circuit shown in FIG. Figure 31B The pixel circuit shown further provides switches, resistor elements, capacitor elements, transistors, sensors or logic circuits, etc.

[0455] <(2) Light-emitting device> Figure 31C Another example of a pixel circuit structure is shown. Here, a pixel structure of a display device (also referred to as a light-emitting device) using a light-emitting element, typically an organic EL element, is shown.

[0456] In an organic EL element, when a voltage is applied to the light-emitting element, electrons from one of a pair of electrodes and holes from the other electrode are injected into a layer containing a light-emitting organic compound, causing current to flow. The electrons and holes then recombine, causing the light-emitting organic compound to reach an excited state. When this excited state returns to its ground state, light is emitted. This mechanism is why such light-emitting elements are called current-excited light-emitting elements.

[0457] Figure 31C This figure shows an example of a pixel circuit. This shows an example of a pixel using two n-channel transistors and one capacitor. Alternatively, the n-channel transistors described above can be used. Furthermore, the capacitor described above can be used. Furthermore, this pixel circuit can be driven by digital time-based grayscale.

[0458] The structure of an applicable pixel circuit and the operation of a pixel when digital time grayscale driving is applied are described.

[0459] The pixel 5020 includes a switching transistor 5021, a driving transistor 5022, a light-emitting element 5024, and a capacitor 5023. In the switching transistor 5021, the gate electrode is connected to the scan line 5026, the first electrode (one of the source electrode and the drain electrode) is connected to the signal line 5025, and the second electrode (the other of the source electrode and the drain electrode) is connected to the gate electrode of the driving transistor 5022. In the driving transistor 5022, the gate electrode is connected to the power line 5027 via the capacitor 5023, the first electrode is connected to the power line 5027, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 5024. The second electrode of the light-emitting element 5024 is equivalent to the common electrode 5028. The common electrode 5028 is electrically connected to the common potential line formed on the same substrate.

[0460] The above-described transistors can be used as the switching transistor 5021 and the driving transistor 5022. Furthermore, the above-described capacitor element can be used as the capacitor 5023. This achieves an organic EL display device with high display quality and / or reliability.

[0461] The potential of the second electrode (common electrode 5028) of the light-emitting element 5024 is set to a low power supply potential. Note that the low power supply potential is a potential lower than the high power supply potential supplied to the power supply line 5027. For example, GND, 0V, or the like can be set as the low power supply potential. By setting the high power supply potential and the low power supply potential to be equal to or higher than the forward threshold voltage of the light-emitting element 5024 and applying the potential difference therebetween to the light-emitting element 5024, current flows through the light-emitting element 5024, causing the light-emitting element 5024 to emit light. Note that the forward voltage of the light-emitting element 5024 refers to the voltage required to achieve the desired brightness, and includes at least the forward threshold voltage.

[0462] In addition, the capacitor 5023 may be omitted by using the gate capacitor of the driver transistor 5022 instead. The gate capacitor of the driver transistor 5022 may be formed between the channel formation region and the gate electrode.

[0463] Next, the signal input to the driver transistor 5022 will be described. When a voltage-input voltage drive method is employed, a video signal is input to the driver transistor 5022, which turns the driver transistor 5022 on or off. Furthermore, to operate the driver transistor 5022 in a linear region, a voltage higher than the voltage of the power supply line 5027 is applied to the gate electrode of the driver transistor 5022. Furthermore, a voltage equal to or greater than the power supply line voltage plus the threshold voltage Vth of the driver transistor 5022 is applied to the signal line 5025.

[0464] When analog grayscale driving is performed, a voltage equal to or greater than the forward voltage applied to the light-emitting element 5024 plus the threshold voltage Vth of the driver transistor 5022 is applied to the gate electrode of the driver transistor 5022. Furthermore, a video signal is input so that the driver transistor 5022 operates in a saturation region, causing current to flow through the light-emitting element 5024. Furthermore, to cause the driver transistor 5022 to operate in a saturation region, the potential of the power supply line 5027 is set higher than the gate potential of the driver transistor 5022. By using an analog video signal, a current corresponding to the video signal can flow through the light-emitting element 5024, thereby performing analog grayscale driving.

[0465] In addition, the display device according to one embodiment of the present invention is not limited to Figure 31C For example, the pixel structure shown in FIG. Figure 31C The pixel circuit shown in the figure is supplemented with switches, resistors, capacitors, sensors, transistors, logic circuits, and the like.

[0466] For example, Figure 32A An example of a pixel circuit is shown in FIG. Here, an example is shown in which one pixel is formed using three n-channel transistors and one capacitor.

[0467] Figure 32A An example of a circuit diagram of a pixel 5111 is shown. The pixel 5111 includes a transistor 5155, a transistor 5156, a transistor 5157, a capacitor 5158, and a light-emitting element 5154.

[0468] The potential of the pixel electrode of the light-emitting element 5154 is controlled according to the pixel signal Sig input to the pixel 5111. The luminance of the light-emitting element 5154 is determined by the potential difference between the pixel electrode and the common electrode.

[0469] The transistor 5156 controls the conduction state between the wiring SL and the gate electrode of the transistor 5155. One of the source and drain electrodes of the transistor 5155 is electrically connected to the anode of the light-emitting element 5154, and the other of the source and drain electrodes of the transistor 5155 is electrically connected to the wiring VL. The transistor 5157 controls the conduction state between the wiring ML and one of the source and drain electrodes of the transistor 5155. One of the pair of electrodes of the capacitor 5158 is electrically connected to the gate electrode of the transistor 5155, and the other of the pair of electrodes of the capacitor 5158 is electrically connected to the anode of the light-emitting element 5154.

[0470] The transistor 5156 performs a switching operation according to the potential of the wiring GL electrically connected to the gate electrode of the transistor 5156. The transistor 5157 performs a switching operation according to the potential of the wiring GL electrically connected to the gate electrode of the transistor 5157.

[0471] Furthermore, the above-mentioned transistor can be used as at least one of the transistor 5155, the transistor 5156, and the transistor 5157. Furthermore, the above-mentioned capacitor can be used as the capacitor 5158.

[0472] For example, when the source (or first terminal, etc.) of the transistor is electrically connected to X through Z1 (or not through Z1) and the drain (or second terminal, etc.) of the transistor is electrically connected to Y through Z2 (or not through Z2), or when the source (or first terminal, etc.) of the transistor is directly connected to a part of Z1 and another part of Z1 is directly connected to X and the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2 and another part of Z2 is directly connected to Y, it can be expressed as follows.

[0473] For example, it can be expressed as “X, Y, the source (or first terminal, etc.) of the transistor, and the drain (or second terminal, etc.) of the transistor are electrically connected to each other and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y.” Alternatively, it can be expressed as “the source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y.” Alternatively, it can be expressed as “X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor and are connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y.” By specifying the connection order in the circuit structure using the same expression method as these examples, the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor can be distinguished and the technical scope can be determined. Note that the above expression method is only an example and is not limited to the above expression method. Here, X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0474] Below, the description Figure 32A An example of the operation of pixel 5111 is shown.

[0475] Figure 32B Examples with Figure 32A The potential of the wiring GL to which the pixel 5111 is electrically connected and the potential of the pixel signal Sig supplied to the wiring SL are shown in FIG. Figure 32B The timing diagram shown shows the example included in Figure 32A The transistors of the pixel 5111 shown are all n-channel transistors.

[0476] First, during period t1, a high-level potential is supplied to the wiring GL, thereby turning on the transistors 5156 and 5157. Furthermore, the potential Vdata of the pixel signal Sig is supplied to the wiring SL, and this potential Vdata is supplied to the gate electrode of the transistor 5155 via the transistor 5156.

[0477] Furthermore, the wiring VL is supplied with a potential Vano, and the wiring CL is supplied with a potential Vcat. The potential Vano is preferably higher than the potential Vcat plus the threshold voltage Vthe of the light-emitting element 5154 and the threshold voltage Vth of the transistor 5155. By providing this potential difference between the wiring VL and the wiring CL, the drain current value of the transistor 5155 is determined by the potential Vdata. This drain current is then supplied to the light-emitting element 5154, thereby determining the brightness of the light-emitting element 5154.

[0478] When the transistor 5155 is an n-channel transistor, during period t1, the potential of the wiring ML is preferably lower than a potential obtained by adding the threshold voltage Vthe of the light-emitting element 5154 to the potential of the wiring CL, and the potential of the wiring VL is preferably higher than a potential obtained by adding the threshold voltage Vth of the transistor 5155 to the potential of the wiring ML. With this structure, even when the transistor 5157 is on, the drain current of the transistor 5155 can flow preferentially through the wiring ML rather than through the light-emitting element 5154.

[0479] Next, during period t2, a low-level potential is supplied to wiring GL. Consequently, transistors 5156 and 5157 are turned off. With transistor 5156 turned off, the gate electrode of transistor 5155 maintains the potential Vdata. Furthermore, the potential Vano is supplied to wiring VL, and the potential Vcat is supplied to wiring CL. Consequently, light-emitting element 5154 emits light at the brightness specified during period t1.

[0480] Next, during period t3, a high-level potential is supplied to wiring GL. As a result, transistors 5156 and 5157 are turned on. Furthermore, a potential greater than the gate voltage of transistor 5155, Vth, is supplied to wiring SL. A potential Vcat is supplied to wiring CL. The potential of wiring ML is lower than the potential obtained by adding the threshold voltage Vthe of light-emitting element 5154 to the potential of wiring CL, while the potential of wiring VL is higher than the potential obtained by adding the threshold voltage Vth of transistor 5155 to the potential of wiring ML. This structure allows the drain current of transistor 5155 to flow preferentially through wiring ML rather than through light-emitting element 5154.

[0481] The drain current of the transistor 5155 is supplied to the monitor circuit via the wiring ML. The monitor circuit uses the drain current flowing through the wiring ML to generate a signal containing information regarding the value of the drain current. Furthermore, in the light-emitting device according to one embodiment of the present invention, this signal can be used to correct the value of the potential Vdata of the pixel signal Sig supplied to the pixel 5111.

[0482] In having Figure 32A In the light-emitting device of the pixel 5111 shown, the operation during period t2 may be performed without performing the operation during period t3. For example, the operation from period t1 to period t2 may be repeated in the pixel 5111, and then the operation during period t3 may be performed. Alternatively, the operation during period t3 may be performed in pixels 5111 of a row, and then pixel signals corresponding to the minimum grayscale value of 0 may be written to the pixels 5111 of the row where the operation was performed, so that the light-emitting element 5154 is placed in a non-luminous state, and then the operation during period t3 may be performed in pixels 5111 of the next row.

[0483] In addition, you can also use Figure 33A The structure of the pixel circuit shown. Figure 33A An example of a pixel circuit is shown in FIG. Here, an example is shown in which one pixel is formed using four n-channel transistors and one capacitor.

[0484] Figure 33A The pixel 5211 shown includes a transistor 5215 , a transistor 5216 , a transistor 5217 , a capacitor 5218 , a light-emitting element 5214 , and a transistor 5219 .

[0485] The potential of the pixel electrode of the light-emitting element 5214 is controlled according to the pixel signal Sig input to the pixel 5211. The luminance of the light-emitting element 5214 is determined by the potential difference between the pixel electrode and the common electrode.

[0486] The transistor 5219 controls the conduction state between the wiring SL and the gate electrode of the transistor 5215. One of the source and drain electrodes of the transistor 5215 is electrically connected to the anode of the light-emitting element 5214. The transistor 5216 controls the conduction state between the wiring VL and the other of the source and drain electrodes of the transistor 5215. The transistor 5217 controls the conduction state between the wiring ML and the other of the source and drain electrodes of the transistor 5215. One of the pair of electrodes of the capacitor 5218 is electrically connected to the gate electrode of the transistor 5215, and the other of the pair of electrodes is electrically connected to the anode of the light-emitting element 5214.

[0487] The switching operation of the transistor 5219 is performed according to the potential of the wiring GLa electrically connected to the gate electrode of the transistor 5219. The switching operation of the transistor 5216 is performed according to the potential of the wiring GLb electrically connected to the gate electrode of the transistor 5216. The switching operation of the transistor 5217 is performed according to the potential of the wiring GLc electrically connected to the gate electrode of the transistor 5217.

[0488] Alternatively, the above-described transistor can be used as at least one of the transistor 5215, the transistor 5216, the transistor 5217, and the transistor 5219. Furthermore, the above-described capacitor can be used as the capacitor 5218.

[0489] Below, the description Figure 33A A working example of external correction for pixel 5211 is shown.

[0490] Figure 33B Examples with Figure 33A The potentials of the wiring GLa, wiring GLb, and wiring GLc electrically connected to the pixel 5211 shown in FIG. 5 and the potential of the pixel signal Sig supplied to the wiring SL are shown in FIG. Figure 33B The timing diagram shown shows the example included in Figure 33A The transistors of the pixel 5211 shown are all n-channel transistors.

[0491] First, during period t1, a high-level potential is supplied to wiring GLa, a high-level potential is supplied to wiring GLb, and a low-level potential is supplied to wiring GLc. Consequently, transistors 5219 and 5216 are turned on, and transistor 5217 is turned off. The potential Vdata of pixel signal Sig is supplied to wiring SL, and this potential Vdata is supplied to the gate electrode of transistor 5215 via transistor 5219.

[0492] Furthermore, the potential Vano is supplied to the wiring VL, and the potential Vcat is supplied to the wiring CL. The potential Vano is preferably higher than the potential Vcat plus the threshold voltage Vthe of the light-emitting element 5214. The potential Vano of the wiring VL is supplied to the other of the source and drain of the transistor 5215 via the transistor 5216. Thus, the value of the drain current of the transistor 5215 is determined by the potential Vdata. This drain current is then supplied to the light-emitting element 5214, thereby determining the brightness of the light-emitting element 5214.

[0493] Next, during period t2, a low-level potential is supplied to wiring GLa, a high-level potential is supplied to wiring GLb, and a low-level potential is supplied to wiring GLc. Consequently, transistor 5216 is turned on, while transistors 5219 and 5217 are turned off. With transistor 5219 turned off, the gate electrode of transistor 5215 maintains the potential Vdata. Furthermore, potential Vano is supplied to wiring VL, and potential Vcat is supplied to wiring CL. Consequently, light-emitting element 5214 maintains the brightness specified during period t1.

[0494] Next, during period t3, a low-level potential is supplied to wiring GLa, a low-level potential is supplied to wiring GLb, and a high-level potential is supplied to wiring GLc. Consequently, transistor 5217 is turned on, while transistors 5219 and 5216 are turned off. Wiring CL is supplied with potential Vcat. Wiring ML is supplied with potential Vano and connected to the monitor circuit.

[0495] Through the above operation, the drain current of transistor 5215 is supplied to light-emitting element 5214 via transistor 5217. Furthermore, this drain current is also supplied to the monitor circuit via wiring ML. The monitor circuit uses the drain current flowing through wiring ML to generate a signal containing information about the value of the drain current. Furthermore, in the light-emitting device according to one embodiment of the present invention, this signal can be used to correct the value of the potential Vdata of pixel signal Sig supplied to pixel 5211.

[0496] In having Figure 33A In the light-emitting device of the pixel 5211 shown, the operation during period t2 may be performed without performing the operation during period t3. For example, the operation from period t1 to period t2 may be repeated in the light-emitting device, and then the operation during period t3 may be performed. Alternatively, the operation during period t3 may be performed in pixels 5211 in a row, and then pixel signals corresponding to the minimum grayscale value of 0 may be written to the pixels 5211 in the row where the operation was performed. After the light-emitting element 5214 is placed in a non-luminous state, the operation during period t3 may be performed in pixels 5211 in the next row.

[0497] In addition, you can also use Figure 34A The structure of the pixel circuit shown. Figure 34A 1 is a diagram showing an example of a pixel circuit, in which five n-channel transistors and one capacitor are used for one pixel.

[0498] Figure 34A The pixel 5311 shown includes a transistor 5315 , a transistor 5316 , a transistor 5317 , a capacitor 5318 , a light-emitting element 5314 , a transistor 5319 , and a transistor 5320 .

[0499] The transistor 5320 controls the conduction state between the wiring RL and the anode of the light-emitting element 5314. The transistor 5319 controls the conduction state between the wiring SL and the gate electrode of the transistor 5315. One of the source and drain of the transistor 5315 is electrically connected to the anode of the light-emitting element 5314. The transistor 5316 controls the conduction state between the wiring VL and the other of the source and drain of the transistor 5315. The transistor 5317 controls the conduction state between the wiring ML and the other of the source and drain of the transistor 5315. One of the pair of electrodes of the capacitor 5318 is electrically connected to the gate electrode of the transistor 5315, and the other of the pair of electrodes is electrically connected to the anode of the light-emitting element 5314.

[0500] The switching operation of the transistor 5319 is performed according to the potential of the wiring GLa connected to the gate electrode of the transistor 5319. The switching operation of the transistor 5316 is performed according to the potential of the wiring GLb electrically connected to the gate electrode of the transistor 5316. The switching operation of the transistor 5317 is performed according to the potential of the wiring GLc electrically connected to the gate electrode of the transistor 5317. The switching operation of the transistor 5320 is performed according to the potential of the wiring GLd electrically connected to the gate electrode of the transistor 5320.

[0501] Alternatively, the above-mentioned transistor can be used as at least one of the transistor 5315, the transistor 5316, the transistor 5317, the transistor 5319, and the transistor 5320. Furthermore, the above-mentioned capacitor can be used as the capacitor 5318.

[0502] Below, the description Figure 34A A working example of external correction for pixel 5311 is shown.

[0503] Figure 34B Examples with Figure 34A The potentials of the wiring GLa, wiring GLb, wiring GLc, and wiring GLd electrically connected to the pixel 5311 shown in FIG. 5 and the potential of the pixel signal Sig supplied to the wiring SL are shown in FIG. Figure 34B The timing diagram shown shows the example included in Figure 34A The transistors of the pixel 5311 shown are all n-channel transistors.

[0504] First, during period t1, a high-level potential is supplied to wiring GLa, a high-level potential is supplied to wiring GLb, a low-level potential is supplied to wiring GLc, and a high-level potential is supplied to wiring GLd. Consequently, transistors 5319, 5316, and 5320 are turned on, and transistor 5317 is turned off. Furthermore, the potential Vdata of pixel signal Sig is supplied to wiring SL, and this potential Vdata is supplied to the gate electrode of transistor 5315 via transistor 5319. Consequently, the value of the drain current of transistor 5315 is determined by the potential Vdata. The potential Vdata of pixel signal Sig is supplied to wiring SL, and this potential Vdata is supplied to the gate electrode of transistor 5315 via transistor 5319. Furthermore, the potential Vano is supplied to wiring VL, and the potential V1 is supplied to wiring RL. This drain current flows between wiring VL and wiring RL via transistors 5316 and 5320.

[0505] The potential Vano is preferably higher than the potential Vcat plus the threshold voltage Vthe of the light-emitting element 5314. The potential Vano of the wiring VL is supplied to the other of the source and drain of the transistor 5315 via the transistor 5316. The potential V1 supplied to the wiring RL is supplied to one of the source and drain of the transistor 5315 via the transistor 5320. The potential Vcat is supplied to the wiring CL.

[0506] The potential V1 is preferably sufficiently lower than the potential V0 minus the threshold voltage Vth of the transistor 5315. During the period t1, the potential V1 can be sufficiently lower than the potential Vcat minus the threshold voltage Vthe of the light-emitting element 5314, so that the light-emitting element 5314 does not emit light.

[0507] Next, during period t2, a low-level potential is supplied to wiring GLa, a high-level potential is supplied to wiring GLb, a low-level potential is supplied to wiring GLc, and a low-level potential is supplied to wiring GLd. Consequently, transistor 5316 is turned on, while transistors 5319, 5317, and 5320 are turned off. With transistor 5319 turned off, the potential Vdata is maintained at the gate electrode of transistor 5315.

[0508] Furthermore, the potential Vano is supplied to the wiring VL, and the potential Vcat is supplied to the wiring CL. Consequently, the transistor 5320 is turned off, and during period t1, a drain current of the transistor 5315 having a predetermined value is supplied to the light-emitting element 5314. Furthermore, the luminance of the light-emitting element 5314 is predetermined by supplying this drain current to the light-emitting element 5314, and this luminance is maintained during period t2.

[0509] Next, during period t3, a low-level potential is supplied to wiring GLa, a low-level potential is supplied to wiring GLb, a high-level potential is supplied to wiring GLc, and a low-level potential is supplied to wiring GLd. Consequently, transistor 5317 is turned on, while transistors 5319, 5316, and 5320 are turned off. Wiring CL is supplied with potential Vcat. Wiring ML is supplied with potential Vano and is electrically connected to the monitor circuit.

[0510] Through the above operation, the drain current of transistor 5315 is supplied to light-emitting element 5314 via transistor 5317. Furthermore, this drain current is also supplied to the monitor circuit via wiring ML. The monitor circuit uses the drain current flowing through wiring ML to generate a signal containing information about the value of the drain current. Furthermore, in the light-emitting device according to one embodiment of the present invention, this signal can be used to correct the value of the potential Vdata of pixel signal Sig supplied to pixel 5311.

[0511] In having Figure 34A In the light-emitting device of the pixel 5311 shown, the operation during period t2 may be performed without performing the operation during period t3. For example, the operation during period t1 to period t2 may be repeated in the light-emitting device, and then the operation during period t3 may be performed. Alternatively, the operation during period t3 may be performed in pixels 5311 in a row, and then pixel signals corresponding to the minimum grayscale value of 0 may be written to the pixels 5311 in the row where the operation was performed, so that the light-emitting element 5314 is placed in a non-luminous state, and then the operation during period t3 may be performed in pixels 5311 in the next row.

[0512] In addition, Figure 34A In the illustrated pixel 5311, even if the resistance values ​​of the anode and cathode of the light-emitting element 5314 differ among pixels due to degradation of the light-emitting element 5314 or the like, the source potential of the transistor 5315 can be set to a predetermined potential V1 when the potential Vdata is supplied to the gate electrode of the transistor 5315. This prevents the luminance of the light-emitting element 5314 from varying among pixels.

[0513] In addition, you can also use Figure 35A The structure of the pixel circuit shown. Figure 35A 1 is a diagram showing an example of a pixel circuit, in which six n-channel transistors and one capacitor are used for one pixel.

[0514] Figure 35A The pixel 5411 shown includes a transistor 5415 , a transistor 5416 , a transistor 5417 , a capacitor 5418 , a light-emitting element 5414 , a transistor 5440 , a transistor 5441 , and a transistor 5442 .

[0515] The potential of the pixel electrode of the light-emitting element 5414 is controlled according to the pixel signal Sig input to the pixel 5411. The luminance of the light-emitting element 5414 is determined by the potential difference between the pixel electrode and the common electrode.

[0516] The transistor 5440 controls the conduction state between the wiring SL and one of the pair of electrodes of the capacitor 5418. The other of the pair of electrodes of the capacitor 5418 is electrically connected to one of the source and drain of the transistor 5415. The transistor 5416 controls the conduction state between the wiring VL1 and the gate electrode of the transistor 5415. The transistor 5441 controls the conduction state between one of the pair of electrodes of the capacitor 5418 and the gate electrode of the transistor 5415. The transistor 5442 controls the conduction state between one of the source and drain of the transistor 5415 and the anode of the light-emitting element 5414. The transistor 5417 controls the conduction state between one of the source and drain of the transistor 5415 and the wiring ML.

[0517] Furthermore, in Figure 35A In the embodiment, the other of the source and the drain of the transistor 5415 is electrically connected to the wiring VL.

[0518] The switching operation of the transistor 5440 is performed according to the potential of the wiring GLa connected to the gate electrode of the transistor 5440. The on / off operation of the transistor 5416 is performed according to the potential of the wiring GLa electrically connected to the gate electrode of the transistor 5416. The switching operation of the transistor 5441 is performed according to the potential of the wiring GLb electrically connected to the gate electrode of the transistor 5441. The switching operation of the transistor 5442 is performed according to the potential of the wiring GLb electrically connected to the gate electrode of the transistor 5442. The switching operation of the transistor 5417 is performed according to the potential of the wiring GLc electrically connected to the gate electrode of the transistor 5417.

[0519] Figure 35B exemplify Figure 35A The potentials of the wirings GLa, GLb, and GLc electrically connected to the pixel 5411 and the potential of the pixel signal Sig supplied to the wiring SL are shown in FIG. Figure 35B The timing diagram shown shows the example included in Figure 35A The transistors of the pixel 5411 shown are all n-channel transistors.

[0520] First, during period t1, a low-level potential is supplied to wiring GLa, a high-level potential is supplied to wiring GLb, and a high-level potential is supplied to wiring GLc. Consequently, transistors 5441, 5442, and 5417 are turned on, while transistors 5440 and 5416 are turned off. Since transistors 5442 and 5417 are turned on, the potential V0 of wiring ML is supplied to one of the source and drain of transistor 5415 and the other of the pair of electrodes of capacitor 5418 (indicated as node A in the figure).

[0521] Furthermore, the wiring VL is supplied with a potential Vano, and the wiring CL is supplied with a potential Vcat. The potential Vano is preferably higher than the potential V0 plus the threshold voltage Vthe of the light-emitting element 5414. The potential V0 is preferably lower than the potential Vcat plus the threshold voltage Vthe of the light-emitting element 5414. Setting the potential V0 to these values ​​prevents current from flowing through the light-emitting element 5414 during period t1.

[0522] By supplying a low potential to the wiring GLb, the transistor 5441 and the transistor 5442 are turned off, and the node A is maintained at the potential V0.

[0523] Next, in period t2, a high potential is supplied to wiring GLa, a low potential is supplied to wiring GLb, and a low potential is supplied to wiring GLc. As a result, transistors 5440 and 5416 are turned on, and transistors 5441, 5442, and 5417 are turned off.

[0524] Furthermore, when transitioning from period t1 to period t2, it is preferable to switch the potential supplied to wiring GLa from a low potential to a high potential, and then switch the potential supplied to wiring GLc from a high potential to a low potential. By performing these steps, it is possible to prevent the potential of node A from fluctuating due to the switching of the potential supplied to wiring GLa.

[0525] Furthermore, the potential Vano is supplied to the wiring VL, and the potential Vcat is supplied to the wiring CL. The potential Vdata of the pixel signal Sig is supplied to the wiring SL, and the potential V1 is supplied to the wiring VL1. The potential V1 is preferably higher than the threshold voltage Vth of the transistor 5415 added to the potential Vcat, and lower than the threshold voltage Vth of the transistor 5415 added to the potential Vano.

[0526] exist Figure 35AIn the pixel structure shown, even if the potential V1 is set higher than the potential obtained by adding the threshold voltage Vthe of the light-emitting element 5414 to the potential Vcat, the light-emitting element 5414 does not emit light as long as the transistor 5442 is in the off state. This expands the range of values ​​that can be set for the potential V0, thereby expanding the range of values ​​that can be set between V1 and V0. Consequently, since the degree of freedom in the value of V1-V0 is increased, the threshold voltage Vth of the transistor 5415 can be accurately obtained even when the time required to obtain the threshold voltage Vth of the transistor 5415 is shortened or when the time required to obtain the threshold voltage Vth is limited.

[0527] After the above operation, a potential V1 higher than the potential of node A plus the threshold voltage Vth is input to the gate electrode of transistor 5415 (indicated as node B in the figure), turning on transistor 5415. As a result, the charge of capacitor 5418 is discharged through transistor 5415, and the potential of node A, which was at potential V0, begins to rise. Ultimately, the potential of node A converges to V1-Vth, and the gate voltage of transistor 5415 converges to the threshold voltage Vth, turning off transistor 5415.

[0528] A potential Vdata of the pixel signal Sig supplied to the wiring SL is supplied to one of a pair of electrodes of the capacitor 5418 (indicated as a node C in the drawing) via the transistor 5440 .

[0529] Next, in period t3, a low potential is supplied to wiring GLa, a high potential is supplied to wiring GLb, and a low potential is supplied to wiring GLc. As a result, transistors 5441 and 5442 are turned on, and transistors 5440, 5416, and 5417 are turned off.

[0530] Furthermore, when transitioning from period t2 to period t3, it is preferred that the potential supplied to wiring GLa be switched from a high potential to a low potential, and then the potential supplied to wiring GLb be switched from a low potential to a high potential. This configuration prevents the potential of node A from fluctuating due to the switching of the potential supplied to wiring GLa.

[0531] Furthermore, the potential Vano is supplied to the wiring VL, and the potential Vcat is supplied to the wiring CL.

[0532] By performing the above operation, the potential Vdata is applied to node B, and the gate voltage of transistor 5415 becomes Vdata-V1+Vth. Therefore, the gate voltage of transistor 5415 can be set to a value obtained by adding the threshold voltage Vth to the potential of the node B. Furthermore, the above structure can suppress variations in the threshold voltage Vth of transistor 5415. This can suppress variations in the current supplied to light-emitting element 5414, thereby reducing uneven brightness in the light-emitting device.

[0533] Here, by increasing the amount of change in the potential applied to the wiring GLb, variations in the threshold voltage of the transistor 5442 can be prevented from affecting the current value supplied to the light-emitting element 5414. In other words, by setting the high-level potential supplied to the wiring GLb to be sufficiently higher than the threshold voltage of the transistor 5442 and setting the low-level potential supplied to the wiring GLb to be sufficiently lower than the threshold voltage of the transistor 5442, the switching operation of the transistor 5442 is ensured, thereby preventing variations in the threshold voltage of the transistor 5442 from affecting the current value of the light-emitting element 5414.

[0534] Next, in period t4, a low potential is supplied to wiring GLa, a low potential is supplied to wiring GLb, and a high potential is supplied to wiring GLc. As a result, transistor 5417 is turned on, and transistors 5416, 5440, 5441, and 5442 are turned off.

[0535] The potential Vano is supplied to the wiring VL, and the wiring ML is electrically connected to the monitor circuit.

[0536] By performing the above operation, the drain current Id of the transistor 5415 can flow through the wiring ML via the transistor 5417, rather than through the light-emitting element 5414. The monitor circuit uses the drain current Id flowing through the wiring ML to generate a signal containing information about the value of the drain current Id. The magnitude of the drain current Id is determined by factors such as the mobility and dimensions (channel length, channel width) of the transistor 5415. Furthermore, in the light-emitting device according to one embodiment of the present invention, the above signal can be used to correct the value of the potential Vdata of the pixel signal Sig supplied to the pixel 5411. This means that the influence of a bias on the mobility of the transistor 5415 can be reduced.

[0537] In having Figure 35AIn the light-emitting device of the pixel 5411 shown, the operation during period t3 may be performed without performing the operation during period t4. For example, the light-emitting device may repeatedly perform the operation from period t1 to period t3 and then perform the operation during period t4. Alternatively, the operation during period t4 may be performed in pixels 5411 of a row, and then pixel signals corresponding to the minimum grayscale value of 0 may be written to the pixels 5411 of the row where the operation was performed. After the light-emitting element 5414 is placed in a non-luminous state, the operation during period t4 may be performed in pixels 5411 of the next row.

[0538] In having Figure 35A In the light-emitting device of pixel 5411 shown, because the other of the source and drain of transistor 5415 is electrically isolated from the gate electrode of transistor 5415, the potentials of each can be controlled separately. Consequently, during period t2, the potential of the other of the source and drain of transistor 5415 can be set to a value higher than the potential of the gate of transistor 5415 plus the threshold voltage Vth. Therefore, when transistor 5415 is normally on, that is, when threshold voltage Vth has a negative value, charge can be accumulated in capacitor 5418 until the potential of the source of transistor 5415 exceeds the gate potential V1. Thus, in the light-emitting device according to one embodiment of the present invention, even when transistor 5415 is normally on, threshold voltage Vth can be achieved during period t2, and during period t3, the gate voltage of transistor 5415 can be set to a value that includes threshold voltage Vth.

[0539] Therefore, in the light-emitting device according to one embodiment of the present invention, even when the transistor 5415 is normally off, display unevenness can be reduced and high-quality image display can be achieved.

[0540] Alternatively, the characteristics of the transistor 5415 and the characteristics of the light-emitting element 5414 can be monitored. In this case, it is preferable to prevent current from flowing through the transistor 5415 by controlling the potential Vdata of the pixel signal Sig, for example. This allows the current of the light-emitting element 5414 to be extracted. Consequently, degradation and nonuniformity of the current characteristics of the light-emitting element 5414 can be detected.

[0541] The structure described in this embodiment can be used in combination with the structures described in other embodiment modes as appropriate.

[0542] Implementation 7 In this embodiment, referring to Figure 36 as well as Figures 37A to 37H A display module and an electronic device that can use the semiconductor device of one embodiment of the present invention will be described.

[0543] Figure 36The display module 8000 shown includes a touch panel 8004 connected to an FPC 8003 , a display panel 8006 connected to an FPC 8005 , a backlight unit 8007 , a frame 8009 , a printed circuit board 8010 , and a battery 8011 between an upper cover 8001 and a lower cover 8002 .

[0544] The semiconductor device of one embodiment of the present invention can be used for the display panel 8006, for example.

[0545] The shapes and sizes of the upper cover 8001 and the lower cover 8002 can be appropriately changed according to the sizes of the touch panel 8004 and the display panel 8006 .

[0546] The touch panel 8004 can be a resistive touch panel or a capacitive touch panel, and can be formed so as to overlap with the display panel 8006. Alternatively, the opposing substrate (sealing substrate) of the display panel 8006 may have touch panel functionality. Alternatively, a photosensor may be provided within each pixel of the display panel 8006 to serve as an optical touch panel.

[0547] The backlight unit 8007 has a light source 8008. Note that although Figure 36 , the light source 8008 is disposed on the backlight unit 8007, but the present invention is not limited thereto. For example, the light source 8008 may be disposed at the end of the backlight unit 8007, and a light diffusion plate may be used. Furthermore, when a self-luminous light-emitting element such as an organic EL or a reflective panel is used, a structure without the backlight unit 8007 may be employed.

[0548] The frame 8009 not only protects the display panel 8006 but also serves as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. The frame 8009 also serves as a heat sink.

[0549] Printed circuit board 8010 includes a power supply circuit and a signal processing circuit for outputting video signals and clock signals. The power supply circuit can be supplied with power from either an external commercial power source or a separately provided battery 8011. When using a commercial power source, battery 8011 can be omitted.

[0550] In addition, components such as a polarizing plate, a phase difference plate, and a prism sheet may also be provided in the display module 8000 .

[0551] Figures 37A to 37H9001, a speaker 9003, an LED lamp 9004, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (which has the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays), a microphone 9008, etc.

[0552] Figure 37A A mobile computer is shown, which may include a switch 9009, an infrared port 9010, etc. in addition to the above. Figure 37B A portable image reproduction device (for example, a DVD reproduction device) including a recording medium is shown. In addition to the above, the portable image reproduction device may further include a second display portion 9002, a recording medium reading portion 9011, and the like. Figure 37C 14. A goggle-type display is shown, which may include a second display portion 9002, a support portion 9012, an earphone 9013, and the like in addition to the above. Figure 37D 1 and 2. The portable game machine is shown, and this portable game machine may include a recording medium reading unit 9011 and the like in addition to the above. Figure 37E 10 shows a digital camera having a television reception function, which may include an antenna 9014, a shutter button 9015, an image receiving unit 9016, and the like in addition to the above. Figure 37F 1 and 2 show a portable game machine, which may include a second display portion 9002, a recording medium reading portion 9011, and the like in addition to the above. Figure 37G A television receiver is shown, which may include a tuner, an image processing unit, and the like in addition to the above. Figure 37H The portable television receiver is shown, and in addition to the above, the portable television receiver may include a charger 9017 capable of transmitting and receiving signals, and the like.

[0553] Figures 37A to 37HThe electronic device shown may have various functions. For example, it may have the following functions: displaying various information (static images, dynamic images, text images, etc.) on the display unit; touch panel; displaying calendar, date or time, etc.; controlling processing by using various software (programs); performing wireless communication; connecting to various computer networks by using the wireless communication function; sending or receiving various data by using the wireless communication function; reading out programs or data stored in a recording medium to display them on the display unit, etc. Furthermore, in an electronic device having multiple display units, it may have the following functions: one display unit mainly displays image information, while another display unit mainly displays text information; or, images taking into account parallax are displayed on multiple display units to display stereoscopic images, etc. Furthermore, in an electronic device having an image receiving unit, it may have the following functions: shooting static images; shooting dynamic images; automatically or manually correcting the shot images; storing the shot images in a recording medium (external or built-in to the camera); displaying the shot images on the display unit, etc. Note that, Figures 37A to 37H The functions that the electronic device shown may have are not limited to the functions described above, but may have various functions.

[0554] The electronic device described in this embodiment is characterized by having a display portion for displaying certain information. In addition, the semiconductor device of one embodiment of the present invention can also be applied to electronic devices without a display portion.

[0555] The structure described in this embodiment can be implemented in combination with the structures described in other embodiment modes as appropriate. Example

[0556] In this example, a cross-sectional shape of a transistor according to one embodiment of the present invention is observed.

[0557] The following describes the method for manufacturing the sample observed in this embodiment. Figure 1A and 1C The transistor 100 is shown as a transistor.

[0558] First, a substrate 102 was prepared. A glass substrate was used as the substrate 102. Next, a 100 nm thick silicon nitride film (SiN-1) was formed on the substrate 102 as the insulating film 108a. Next, a 400 nm thick silicon oxynitride film (SiON-1) was formed on the insulating film 108a as the insulating film 108b. Furthermore, the insulating films 108a and 108b were formed continuously under vacuum using a PECVD apparatus.

[0559] Next, a 5 nm thick tantalum nitride film was formed on the insulating film 108b as a film to inhibit oxygen desorption. This tantalum nitride film was formed using a sputtering device. Subsequently, oxygen was added to the insulating film 108b through the tantalum nitride film using an ashing device. Subsequently, this tantalum nitride film was removed using a dry etching device.

[0560] Next, a 50 nm thick oxide semiconductor film (IGZO) was formed on the insulating film 108 b as the oxide semiconductor film 110. The oxide semiconductor film 110 was formed under the following conditions: a sputtering device was used; a metal oxide with a ratio of In:Ga:Zn = 1:1:1.2 [atomic %] was used as a sputtering target; and an AC power supply was used as a power source for the sputtering target. The substrate on which the oxide semiconductor film 110 was formed was then heat treated. This heat treatment was performed at 450°C for one hour in a nitrogen atmosphere, followed by heat treatment at 450°C for one hour in a mixed atmosphere of nitrogen and oxygen.

[0561] Next, a mask is formed over the oxide semiconductor film 110 by a photolithography process, and the oxide semiconductor film 110 is processed into an island shape using the mask. Furthermore, the oxide semiconductor film 110 is processed by a wet etching method using a chemical solution.

[0562] Next, a 100-nm-thick silicon oxynitride film (SiON-2) is formed as the insulating film 112 over the island-shaped oxide semiconductor film 110. The insulating film 112 is formed using a PECVD apparatus.

[0563] Next, a 30 nm thick tantalum nitride film (TaN) is formed as the conductive film 114a on the insulating film 112. Then, a 150 nm thick tungsten film (W) is formed as the conductive film 114b on the conductive film 114a. The conductive films 114a and 114b are continuously formed in a vacuum using a sputtering apparatus.

[0564] Next, a mask is formed over the conductive film 114b by a photolithography process, and the conductive films 114b, 114a, and the insulating film 112 are processed into island shapes using this mask. The conductive films 114a, 114b, and the insulating film 112 are processed using a dry etching apparatus. Then, while leaving the mask in place, an impurity element is added to the oxide semiconductor film 110. Regarding the method for adding the impurity element, an etching apparatus is used to place a substrate between parallel plates within a processing chamber of the etching apparatus. Argon gas is then introduced into the processing chamber, and RF power is applied between the parallel plates to bias the substrate toward one side.

[0565] Next, a 100 nm thick silicon nitride film (SiN-2) is formed as the insulating film 118 to cover the insulating film 108 b, the oxide semiconductor film 110, the insulating film 112, and the conductive films 114 a and 114 b. Next, a 300 nm thick silicon oxynitride film (SiON-3) is formed on the insulating film 118 as the insulating film 120. The insulating films 118 and 120 are sequentially formed under vacuum using a PECVD apparatus.

[0566] Next, a mask is formed on the insulating film 120 by a photolithography process, and openings are formed in the insulating films 120 and 118 using the mask. The openings reach the oxide semiconductor film 110. The openings are processed using a dry etching apparatus.

[0567] Next, a conductive film is formed to cover the insulating film 120 and the opening. This conductive film is formed by sequentially stacking a 50 nm thick tungsten film, a 400 nm thick aluminum film, and a 100 nm thick titanium film. This conductive film is formed continuously under vacuum using a sputtering apparatus.

[0568] Next, a mask is formed over the conductive film by a photolithography step, and the conductive film 122 and the conductive film 124 are formed using the mask.

[0569] Through the above steps, the sample of this embodiment for observing its cross section was manufactured.

[0570] Figure 38A and 38B The results of cross-sectional observation are shown. In addition, a transmission electron microscope (TEM: Transmission Electron Microscope) was used for cross-sectional observation.

[0571] Figure 38A is a cross-sectional TEM image showing the Figure 1A Near the conductive film 114 in the dotted line X1-X2 direction. Figure 38B is a cross-sectional TEM image showing the Figure 1A Near the conductive film 114 in the dotted line Y1-Y2 direction.

[0572] Notice, Figure 38A and 38B The SiN-1, SiN-2, SiON-1, SiON-2, SiON-3, TaN, and W shown correspond to the film types described in parentheses in the above examples. Figure 38A and 38B The Pt shown indicates platinum as a surface coating used for observing the cross section.

[0573] Depend on Figure 38AThe cross-sectional TEM image shows that the end of the tantalum nitride film (TaN) is located outside the end of the tungsten film (W); and the end of the silicon oxynitride film (SiON-2) is located outside the end of the tantalum nitride film (TaN). Figure 38B The cross-sectional TEM image shows that the end of the tantalum nitride film (TaN) is located outside the end of the tungsten film (W); the end of the silicon oxynitride film (SiON-2) is located outside the end of the tantalum nitride film (TaN); and there is a concave portion in the area where the silicon oxynitride film (SiON-1) does not overlap with the silicon oxynitride film (SiON-2). Figure 38A and 38B As can be seen from the cross-sectional TEM image shown, in the sample manufactured in this example, the silicon nitride film (SiN-2) has excellent coverage and a good cross-sectional shape.

[0574] The structure described in this embodiment can be used in combination with the structures described in other embodiment modes as appropriate.

[0575] Explanation of symbols 100 transistors 100A transistor 100B transistor 100C transistor 100D transistor 100E transistor 100F transistor 100G transistors 100H transistor 102 substrate 104 Insulation Film 106 conductive film 106a Conductive film 106b conductive film 108 insulating film 108a Insulating film 108b Insulation film 108c Insulation Film 110 oxide semiconductor film 110_1 oxide semiconductor film 110_2 oxide semiconductor film 110a channel region 110a_1 channel region 110a_2 channel region 110b low resistance area 110b_1 low resistance area 110b_2 low resistance area 110c low resistance area 110c_1 low resistance area 110c_2 low resistance area 110d low resistance area 110e low resistance area 110f area 110g area 110h low resistance area 110i Low resistance area 112 Insulation Film 112a Insulating film 112b Insulation film 113 conductive film 113a Conductive film 113b Conductive film 114 conductive film 114a Conductive film 114b conductive film 116 Conductive Film 116a Conductive film 116b conductive film 117 Insulation Film 118 insulating film 120 Insulation Film 121 Conductive Film 121a Conductive film 121b Conductive film 122 conductive film 122a Conductive film 122b Conductive film 124 conductive film 124a Conductive film 124b conductive film 126 Conductive Film 126a Conductive film 126b Conductive film 128 Insulation Film 139 opening 140a opening 140b opening 140c opening 141 membrane 142 Oxygen 143 impurity elements 145 Mask 150 Capacitor Components 150A capacitor element 150B capacitor element 150C capacitor element 150D capacitor element 150E capacitor element 150F capacitor element 150G capacitor element 210 Electron Gun Room 212 Optical System 214 Sample Room 216 Optical System 218 Photographic Device 220 Observation Room 222 Film Room 224 Electronics 228 Matter 232 fluorescent plate 306 conductive film 306a conductive film 306b conductive film 314 conductive film 314a conductive film 314b conductive film 316 conductive film 316a Conductive film 316b conductive film 318 conductive film 318a Conductive film 318b conductive film 324 conductive film 324a Conductive film 324b conductive film 326 Conductive Film 326a Conductive film 326b conductive film 328 conductive film 328a Conductive film 328b conductive film 334 conductive film 334a Conductive film 334b conductive film 338 conductive film 338a Conductive film 338b conductive film 352 opening 353 opening 354 opening 355 opening 500FET 501 substrate 502 substrate 504B light emitting element 504G light emitting element 504R light emitting element 504W light emitting element 506 conductive film 507 conductive film 508 partition wall 509 Structure 510 EL layer 512 conductive film 514B coloring layer 514G coloring layer 514R coloring layer 514W coloring layer 516 substrate 518 Sealing Film 520 Area 522 Insulation Film 524 opening 700 display device 701 substrate 702 Pixel Department 704 Source driver circuit unit 705 substrate 706 Gate drive circuit unit 708 FPC terminal part 710 signal line 711 Wiring Department 712 sealant 716FPC 730 Insulation Film 732 Sealing Film 734 Insulation Film 736 Coloring Film 738 shading film 750 transistors 752 transistors 760 Connecting electrodes 766 Insulation Film 770 planarization insulating film 772 Conductive Film 774 Conductive Film 775 Liquid Crystal Element 776 Liquid Crystal Layer 778 Structure 780 Anisotropic Conductive Film 782 Light-emitting elements 784 Conductive Film 786 EL layer 788 Conductive Film 790 Capacitor Components 1100 particles 1100a particles 1100b particles 1101 particles 1120 substrate 1130 Target 5000 substrate 5001 Pixel Department 5002 scan line driver circuit 5003 scan line driver circuit 5004 signal line driver circuit 5010 Capacitor Wiring 5012 Gate Wiring 5013 Gate Wiring 5014 drain electrode 5016 transistor 5017 transistor 5018 Liquid Crystal Element 5019 Liquid Crystal Element 5020 pixels 5021 switching transistor 5022 driver transistor 5023 capacitor element 5023a capacitor element 5023b capacitor element 5024 light emitting element 5025 signal line 5026 scan lines 5027 Power Cord 5028 common electrode 5111 pixels 5154 Light-emitting element 5155 transistor 5156 transistor 5157 transistor 5158 capacitor element 5211 pixels 5214 Light-emitting element 5215 transistor 5216 transistor 5217 transistor 5218 capacitor element 5219 transistor 5311 pixels 5314 Light-emitting components 5315 transistor 5316 transistors 5317 transistor 5318 Capacitor Components 5319 transistors 5320 transistor 5411 pixels 5414 Light-emitting element 5415 transistor 5416 transistors 5417 transistor 5418 capacitor element 5440 transistor 5441 transistor 5442 transistor 8000 Display Module 8001 Top Cover 8002 lower cover 8003FPC 8004 touch panel 8005FPC 8006 Display Panel 8007 backlight unit 8008 Light Source 8009 Framework 8010 printed circuit board 8011 Battery 9000 frame 9001 Display 9002 Display 9003 Speaker 9004 LED lights 9005 Operation keys 9006 connection terminal 9007 Sensor 9008 Microphone 9009 Switch 9010 infrared port 9011 Recording Medium Reading Unit 9012 Support 9013 Headphones 9014 Antenna 9015 Shutter Button 9016 Image Receiving Unit 9017 Charger.

Claims

1. A semiconductor device comprising: oxide semiconductor film; a first insulating film on the oxide semiconductor film; a gate electrode on the first insulating film; as well as a second insulating film on the gate electrode, wherein the second insulating film is in contact with the gate electrode, the first insulating film, and the oxide semiconductor film, wherein the gate electrode includes a first conductive film and a second conductive film on and in contact with the first conductive film, wherein the first conductive film includes an end portion that does not overlap with the second conductive film and does not overlap with the oxide semiconductor film, and The first insulating film includes an end portion that does not overlap with the first conductive film and does not overlap with the oxide semiconductor film.

2. The semiconductor device according to claim 1, further comprising: A light-emitting element is electrically connected to the oxide semiconductor film.

Images