Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface, a second surface, a first two-dimensional material layer, a well region and a first region, and the first surface is provided with a first groove; the first two-dimensional material layer is of a first conductive type and is located at the bottom of the first groove; the carrier mobility of the first two-dimensional material layer is greater than that of silicon carbide; the voltage-withstanding layer is located on the side, away from the first region, of the well region and located at the bottom of the first groove; the insulating layer is located on the first surface and is in contact with the first two-dimensional material layer, the voltage-withstanding layer and part of the first area; a gate electrode; the insulating layer is used for insulating the semiconductor body and the gate; a source electrode; and a drain electrode. According to the technical scheme provided by the embodiment of the invention, the problems that the on-resistance of the semiconductor device is too large, the interface state is increased and the carrier mobility of the channel region is reduced are solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide-bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in power electronics, automotive, aerospace, and other fields due to their excellent high-temperature performance, chemical stability, and electronic properties. For planar metal-oxide-semiconductor field-effect transistors (MOSFETs), the semiconductor body on one side of the well region is the junction field-effect transistor (JFET) region.

[0003] In the prior art, a positive voltage is applied to the gate of a SiC or GaN MOSFET. When the threshold voltage is reached, an inversion layer is formed in the well region. Current flows from the metal conductive layer through the doped region formed by ion implantation to the inversion layer, then through the JFET region and the drift region, and finally through the silicon carbide substrate to reach the drain.

[0004] However, in the prior art, ion implantation to form doped regions causes lattice damage to the semiconductor body, resulting in an increase in interface states, reduced carrier mobility in the channel region, and excessively high on-resistance of the SiC or GaN MOSFET. Summary of the Invention

[0005] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle to solve the problems of excessive on-resistance, increased interface states and reduced carrier mobility in the channel region of the semiconductor device.

[0006] According to one aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor body, comprising a first surface and a second surface arranged opposite to each other, the first surface being provided with a first groove; the semiconductor body further comprising a first two-dimensional material layer, a well region, and a first region, the first two-dimensional material layer being configured as a first conductivity type and being located at a bottom of the first groove; the first region being configured as the first conductivity type and being located on the first surface, the well region being configured as the second conductivity type and being located on a side of the first region away from the first surface and extending along an edge of the first region to the first two-dimensional material layer; the carrier mobility of the first two-dimensional material layer being greater than the carrier mobility of silicon carbide;

[0007] a voltage-resistant layer, located at a side of the well region away from the first region and at a bottom of the first groove;

[0008] an insulating layer, located on the first surface, contacting the first two-dimensional material layer, the voltage-resistant layer, and a portion of the first region;

[0009] The gate is located on the side of the insulating layer away from the semiconductor body; the insulating layer is used to insulate the semiconductor body and the gate;

[0010] a source electrode, located on the first surface;

[0011] The drain is located on the second surface.

[0012] Optionally, the insulating layer includes a first insulating portion, a second insulating portion and a third insulating portion;

[0013] The first insulating portion is located in the first groove and contacts the first two-dimensional material layer;

[0014] The second insulating portion is located in the first groove, contacts the voltage-resistant layer, and is connected to the first insulating portion;

[0015] The third insulating portion is located on the first surface, contacts a portion of the first region, and is connected to the first insulating portion and the second insulating portion.

[0016] Optionally, the voltage-resistant layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and zirconium oxide.

[0017] Optionally, the semiconductor device further includes a second two-dimensional material layer; the second two-dimensional material layer is set to the first conductivity type, connected to the first two-dimensional material layer, located on the side of the well region away from the first region, and located between the voltage-resistant layer and the well region.

[0018] Optionally, the first two-dimensional material layer has the same carrier mobility in different directions;

[0019] And / or, the carrier mobility of the second two-dimensional material layer in different directions is the same.

[0020] Optionally, the semiconductor body further includes a second region; the second region is set to the second conductivity type and is located on the first surface; the ion concentration of the second region is greater than the ion concentration of the well region; and the second region is in contact with the first region.

[0021] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0022] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising:

[0023] A semiconductor body is provided, comprising a first surface and a second surface disposed opposite to each other, wherein the first surface is provided with a first groove; the semiconductor body further comprising a first two-dimensional material layer, a well region, and a first region, wherein the first two-dimensional material layer is configured to be of a first conductivity type and is located at a bottom of the first groove; the first region is configured to be of the first conductivity type and is located on the first surface, and the well region is configured to be of a second conductivity type and is located on a side of the first region away from the first surface and extends along an edge of the first region to the first two-dimensional material layer; the carrier mobility of the first two-dimensional material layer is greater than that of silicon carbide;

[0024] forming a voltage-resistant layer on a side of the well region away from the first region; the voltage-resistant layer is located at the bottom of the first groove;

[0025] forming an insulating layer on the first surface, wherein the insulating layer is in contact with the first two-dimensional material layer, the voltage-resistant layer, and a portion of the first region;

[0026] A gate is formed on a side of the insulating layer away from the semiconductor body; the insulating layer is used to insulate the semiconductor body and the gate;

[0027] forming a source electrode on the first surface;

[0028] A drain electrode is formed on the second surface.

[0029] Optionally, the insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion; and forming the insulating layer on the first surface includes:

[0030] forming a first insulating portion in the first groove;

[0031] A second insulating portion is formed in the first groove; the second insulating portion is connected to the first insulating portion;

[0032] A third insulating portion is formed on the first surface; the third insulating portion is connected to the first insulating portion and the second insulating portion.

[0033] Optionally, forming a voltage-resistant layer on a side of the well region away from the first region includes:

[0034] A voltage-resistant layer including at least one of silicon oxide, silicon nitride, aluminum oxide, and zirconium oxide is formed on a side of the well region away from the first region.

[0035] Optionally, before forming the voltage-resistant layer on the side of the well region away from the first region, the method further includes:

[0036] A second two-dimensional material layer is formed on a side of the well region away from the first region. The second two-dimensional material layer is set to the first conductivity type, connected to the first two-dimensional material layer, and located between the voltage-resistant layer and the well region.

[0037] Optionally, providing a semiconductor body includes:

[0038] Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other;

[0039] forming a well region on the first surface, wherein the well region is set to a second conductivity type;

[0040] forming a first region on the first surface, wherein the first region is configured as a first conductivity type;

[0041] A first groove is formed in the first surface, and the first groove extends from the first surface into the semiconductor body.

[0042] Optionally, providing a semiconductor body includes:

[0043] Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other;

[0044] forming a first groove in the first surface, the first groove extending from the first surface into the semiconductor body;

[0045] forming a well region on the first surface, wherein the well region is set to a second conductivity type;

[0046] A first region is formed on the first surface, and the first region is set to be of a first conductivity type.

[0047] Optionally, after forming the first area on the first surface, the method further includes:

[0048] A second region is formed on the first surface. The second region is set to the second conductive type and contacts the first region. The ion concentration of the second region is greater than the ion concentration of the well region.

[0049] Optionally, providing a semiconductor body includes:

[0050] A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0051] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used to support the semiconductor device.

[0052] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0053] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0054] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0055] The technical solution of the embodiment of the present invention is to set a first groove on the first surface of the semiconductor body, and set a first two-dimensional material layer at the bottom of the first groove. The first two-dimensional material layer serves as the channel of the semiconductor device, and the carrier mobility of the first two-dimensional material layer is greater than the carrier mobility of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. In addition, the well region forms a PN junction contact with the first two-dimensional material layer, generating a depletion region at the channel, thereby reducing the off-state leakage current of the semiconductor device. A voltage-resistant layer is set at the bottom of the first groove to ensure the voltage resistance performance of the device. In addition, an insulating layer is set on the first surface, and the insulating layer is in contact with the first two-dimensional material layer, the voltage-resistant layer and part of the first region. Increasing the thickness of the insulating layer can increase the threshold voltage of the semiconductor device without affecting the resistance between the drain and the source, improve the control performance of the semiconductor device, and enhance the competitiveness of the product. Among them, since the carrier mobility of the first two-dimensional material layer is greater than that of silicon carbide, it can effectively improve the carrier mobility of the channel of the semiconductor device, and the effects of lattice damage to the semiconductor body, increase in interface states and reduction in carrier mobility in the channel region caused by ion implantation when the first region is formed can be ignored.

[0056] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0058] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0059] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0060] Figure 3-Figure 7 is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0061] Figure 8 According to an embodiment of the present invention, Figure 2 A schematic diagram of the process included in S130;

[0062] Figure 9 According to an embodiment of the present invention, Figure 2 Schematic diagram of the process before S120;

[0063] Figure 10 According to an embodiment of the present invention, Figure 9 Cross-sectional views corresponding to the steps in ;

[0064] Figure 11 According to an embodiment of the present invention, Figure 2 A schematic diagram of the process included in S110;

[0065] Figure 12-15 According to an embodiment of the present invention, Figure 11 Cross-sectional views corresponding to each step in the process;

[0066] Figure 16 According to an embodiment of the present invention, Figure 2 Another flow chart of S110 included in FIG.

[0067] Figure 17-18 According to an embodiment of the present invention, Figure 16 Cross-sectional diagram corresponding to each step in . DETAILED DESCRIPTION

[0068] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0069] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0070] In order to solve the problem of low threshold voltage of semiconductor devices and affected device control capability, the embodiments of the present invention provide the following technical solutions:

[0071] Figure 1 FIG. 1 is a schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present invention. Figure 1 As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other; the first surface 101 is provided with a first groove 105; the semiconductor body 100 also includes a first two-dimensional material layer 107, a well region 103 and a first region 104, the first two-dimensional material layer 107 is set to the first conductive type and is located at the bottom of the first groove 105; the first region 104 is set to the first conductive type and is located on the first surface 101, the well region 103 is set to the second conductive type and is located on the side of the first region 104 away from the first surface 101, and extends along the edge of the first region 104 to the first region 104. A two-dimensional material layer 107; the carrier mobility of the first two-dimensional material layer 107 is greater than the carrier mobility of silicon carbide; a voltage-resistant layer 30 is located on the side of the well region 103 away from the first region 104 and is located at the bottom of the first groove 105; an insulating layer 200 is located on the first surface 101 and is in contact with the first two-dimensional material layer 107, the voltage-resistant layer 30 and a portion of the first region 104; a gate 300 is located on the side of the insulating layer 200 away from the semiconductor body 100; the insulating layer 200 is used to insulate the semiconductor body 100 and the gate 300; a source 400 is located on the first surface 101; and a drain 500 is located on the second surface 102.

[0072] In the embodiment of the present invention, Figure 1As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through one or more epitaxial processes, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0073] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type dopant ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type dopant ions in the P-well region may be aluminum (Al) ions or boron (B) ions; the first two-dimensional material layer 107 is an N-type channel layer, and the carrier mobility of the first two-dimensional material layer 107 is greater than the carrier mobility of silicon carbide, thereby improving the carrier mobility of the semiconductor device.

[0074] The gate 300 may be made of polysilicon. The insulating layer 200 is used to insulate the semiconductor body 100 from the gate 300. The insulating layer 200 may be a gate oxide layer.

[0075] In an embodiment of the present invention, the voltage-resistant layer 30 may be formed by depositing a high dielectric constant material on the bottom of the first groove 105. The high dielectric constant material includes but is not limited to silicon oxide, silicon nitride, aluminum oxide, and zirconium oxide.

[0076] In an optional embodiment of the present invention, the voltage-resistant layer 30 includes at least one of silicon oxide, silicon nitride, aluminum oxide, and zirconium oxide.

[0077] In an embodiment of the present invention, the semiconductor device further includes an interlayer dielectric layer 301. Interlayer dielectric layer 301 provides electrical isolation between gate 300 and source 400, preventing electron migration between different metal layers and preventing diffusion or penetration between substances. Interlayer dielectric layer 301 can be made of silicon dioxide. Interlayer dielectric layer 301 can be formed by plasma-enhanced chemical vapor deposition.

[0078] The technical solution of the embodiment of the present invention provides a first groove 105 on the first surface 101 of the semiconductor body 100. A first two-dimensional material layer 107 is disposed at the bottom of the first groove 105. The first two-dimensional material layer 107 serves as the channel of the semiconductor device. The carrier mobility of the first two-dimensional material layer 107 is greater than that of silicon carbide, effectively improving the carrier mobility of the semiconductor device channel and reducing the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the first two-dimensional material layer 107, generating a depletion region in the channel and reducing the off-state leakage current of the semiconductor device. A voltage-resistant layer 30 is disposed at the bottom of the first groove 105 to ensure the device's voltage resistance. Furthermore, an insulating layer 200 is disposed on the first surface 101, and the insulating layer 200 contacts the first two-dimensional material layer 107, the voltage-resistant layer 20, and a portion of the first region 104. Increasing the thickness of the insulating layer 200 can increase the threshold voltage of the semiconductor device, improve the control performance of the semiconductor device, and enhance the competitiveness of the product without affecting the resistance between the drain 500 and the source 400. Because the carrier mobility of the first two-dimensional material layer 107 is greater than that of silicon carbide, it can effectively improve the carrier mobility of the semiconductor device channel, negligible the effects of lattice damage to the semiconductor body 100, increased interface states, and reduced carrier mobility in the channel region caused by ion implantation to form the first region 104.

[0079] In an optional embodiment of the present invention, reference Figure 1 The insulating layer 200 includes a first insulating portion 201, a second insulating portion 202 and a third insulating portion 203; the first insulating portion 201 is located in the first groove 105 and contacts the first two-dimensional material layer 107; the second insulating portion 202 is located in the first groove 105, contacts the voltage-resistant layer 30, and is connected to the first insulating portion 201; the third insulating portion 203 is located on the first surface 101, contacts a portion of the first area 104, and is connected to the first insulating portion 201 and the second insulating portion 202.

[0080] In an embodiment of the present invention, compared with a semiconductor device in which only an insulating layer is provided on the first surface 101, the thickness of the insulating layer 200 is increased in the semiconductor device. Without affecting the resistance between the drain 500 and the source 400, the threshold voltage of the semiconductor device can be increased, the control performance of the semiconductor device can be improved, and the competitiveness of the product can be enhanced.

[0081] In an optional embodiment of the present invention, reference Figure 1 The semiconductor device also includes a second two-dimensional material layer 108; the second two-dimensional material layer 108 is set to the first conductivity type, connected to the first two-dimensional material layer 107, located on the side of the well region 103 away from the first region 104, and located between the voltage-resistant layer 30 and the well region 103.

[0082] In an embodiment of the present invention, the second two-dimensional material layer 108 is connected to the first two-dimensional material layer 107 and both have high carrier mobility. This provides a low-resistance conductive channel between the first surface 101 and the drift region, allowing carriers to flow through this channel without being affected by the narrowing of the effective conductive area caused by the expansion of the depletion layer in the JFET structure. This solves the problems of increased resistance between the source 100 and the drain 500 in the MOSFET device, increased energy consumption, and increased device temperature during operation, thereby reducing the on-resistance of the device. Furthermore, the second two-dimensional material layer 108 has high conductivity and carrier mobility, replacing the JFET region as the current channel. This eliminates the need to provide a JFET region of sufficient lateral dimension X on one side of the well region 103 in the planar MOSFET device to ensure that the JFET region has a resistance that matches the on-current. Furthermore, a voltage-resistant layer 30 is provided at the bottom of the first recess 105. While ensuring the device's voltage resistance, the lateral dimension X of the semiconductor body 100 on the well region 103 side can be reduced, thereby reducing the lateral dimensions of the semiconductor device. It should be noted that, in the embodiment of the present invention, the lateral dimension X refers to the dimension in a direction perpendicular to the first surface 101 and pointing to the second surface 102 .

[0083] In an optional embodiment of the present invention, reference Figure 1 , the carrier mobility of the first two-dimensional material layer 107 in different directions is the same; and / or, the carrier mobility of the second two-dimensional material layer 108 in different directions is the same.

[0084] In an optional embodiment of the present invention, the first two-dimensional material layer 107 includes a two-dimensional material semiconductor layer; and / or the second two-dimensional material layer 108 includes a two-dimensional material semiconductor layer.

[0085] Specifically, in crystallography, a two-dimensional material semiconductor layer refers to a material that is only a single atomic layer or two atomic layers thick, with a thickness on the order of a few nanometers. Two-dimensional material semiconductor layers have high carrier mobility, and common two-dimensional material semiconductor layers include graphene and graphene derivatives. The carrier mobility of a two-dimensional material semiconductor layer is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the first two-dimensional material layer 107, generating a depletion region in the channel, thereby reducing the off-state leakage current of the semiconductor device.

[0086] In an optional embodiment of the present invention, reference Figure 1 The semiconductor body 100 further includes a second region 109 ; the second region 109 is set to the second conductivity type and is located on the first surface 101 ; the ion concentration of the second region 109 is greater than the ion concentration of the well region 103 ; the second region 109 is in contact with the first region 104 .

[0087] In the embodiment of the present invention, the conductivity type of the second region 109 is the same as that of the well region 103, and both are set to the second conductivity type. For an N-type MOSFET, the second region 109 can be a P+ doped region, and its ion concentration is greater than the ion concentration of the well region 103. The second region 109 can form a good ohmic contact with the source 400.

[0088] In an optional embodiment of the present invention, reference Figure 1 , the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0089] The semiconductor body 100 includes a silicon carbide semiconductor body, the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device, the semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0090] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0091] Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0092] S110. Provide a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other, the first surface being provided with a first groove; the semiconductor body also including a first two-dimensional material layer, a well region and a first region, the first two-dimensional material layer being set to a first conductive type and being located at the bottom of the first groove; the first region being set to a first conductive type and being located on the first surface, the well region being set to a second conductive type and being located on a side of the first region away from the first surface, and extending along an edge of the first region to the first two-dimensional material layer; the carrier mobility of the first two-dimensional material layer is greater than the carrier mobility of silicon carbide.

[0093] refer to Figure 3 and Figure 4, providing a semiconductor body 100, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the first surface 101 is provided with a first groove 105; the semiconductor body 100 also includes a first two-dimensional material layer 107, a well region 103 and a first region 104, the first two-dimensional material layer 107 is set to a first conductive type, and is located at the bottom of the first groove 105; the first region 104 is set to the first conductive type and is located on the first surface 101, the well region 103 is set to the second conductive type and is located on the side of the first region 104 away from the first surface 101, and extends along the edge of the first region 104 to the first two-dimensional material layer 107; the carrier mobility of the first two-dimensional material layer 107 is greater than the carrier mobility of silicon carbide.

[0094] In the embodiment of the present invention, Figure 3 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through one or more epitaxial processes, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0095] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0096] In an optional embodiment of the present invention, reference Figure 3 The semiconductor body 100 further includes a second region 109 , which is set to the second conductivity type and is located on the first surface 101 ; the ion concentration of the second region 109 is greater than the ion concentration of the well region 103 ; the second region 109 is in contact with the first region 104 .

[0097] Specifically, the conductivity type of the second region 109 is the same as that of the well region 103, and both are set to the second conductivity type. For an N-type MOSFET, the second region 109 can be a P+ doped region, and its ion concentration is greater than the ion concentration of the well region 103. The second region 109 can form a good ohmic contact with the source.

[0098] refer to Figure 4 A first two-dimensional material layer 107 is formed at the bottom of the first groove 105. The first two-dimensional material layer 107 is configured as a first conductivity type. The carrier mobility of the first two-dimensional material layer 107 is greater than that of silicon carbide. For example, for an N-type MOSFET, the first two-dimensional material layer 107 is an N-type channel layer, and the carrier mobility of the first two-dimensional material layer 107 is greater than that of silicon carbide, thereby improving the carrier mobility of the semiconductor device and reducing the on-resistance of the semiconductor device.

[0099] In an optional embodiment of the present invention, a first two-dimensional material layer 107 including a two-dimensional material semiconductor layer can be formed at the bottom of the first groove 105. Specifically, in crystallography, a two-dimensional material semiconductor layer refers to a material with a thickness of only a single atomic layer or two atomic layers, and its thickness is on the order of a few nanometers. The two-dimensional material semiconductor layer has a high carrier mobility, and common two-dimensional material semiconductor layers include graphene, graphene derivatives, etc. The carrier mobility of the two-dimensional material semiconductor layer is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. The well region 103 forms a PN junction contact with the first two-dimensional material layer 107, generating a depletion region at the channel, thereby reducing the off-state leakage current of the semiconductor device.

[0100] S120 , forming a voltage-resistant layer on a side of the well region away from the first region; the voltage-resistant layer is located at the bottom of the first groove.

[0101] refer to Figure 5 A high dielectric constant material is deposited on a side of the well region 103 away from the first region 104 and at the bottom of the first groove 105 to form a voltage-resistant layer 30 .

[0102] In an optional embodiment of the present invention, S120, forming a voltage-resistant layer on a side of the well region away from the first region, includes: forming a voltage-resistant layer including at least one of silicon oxide, silicon nitride, aluminum oxide and zirconium oxide on a side of the well region away from the first region.

[0103] The voltage-resistant layer 30 is formed by depositing at least one high dielectric constant material selected from silicon oxide, silicon nitride, aluminum oxide, and zirconium oxide to ensure the voltage-resistant performance of the device.

[0104] S130 , forming an insulating layer on the first surface, wherein the insulating layer is in contact with the first two-dimensional material layer, the voltage-resistant layer, and a portion of the first region.

[0105] refer to Figure 6 An insulating layer 200 is formed on the first surface 101. The insulating layer 200 contacts the first two-dimensional material layer 107, the voltage-resistant layer 30, and a portion of the first region 104. The insulating layer 200 can be formed by a high-temperature oxidation or deposition process. The insulating layer 200 can be a gate oxide layer.

[0106] S140, forming a gate on a side of the insulating layer away from the semiconductor body; the insulating layer is used to insulate the semiconductor body and the gate.

[0107] refer to Figure 7 The gate 300 is formed on the side of the insulating layer 200 away from the semiconductor body 100. The insulating layer 200 is used to insulate the semiconductor body 100 from the gate 300. The gate 300 can be formed by depositing polysilicon on the side of the insulating layer 200 away from the semiconductor body 100.

[0108] S150 , forming a source electrode on the first surface.

[0109] refer to Figure 1 , metal is deposited on the first surface 101 to form the source electrode 400. Before forming the source electrode 400, an interlayer dielectric layer 301 is formed on the side of the gate 300 away from the semiconductor body 100. The interlayer dielectric layer 301 electrically isolates the gate 300 from the source electrode 400, preventing electron migration between different metal layers and diffusion or penetration between substances. The material of the interlayer dielectric layer 301 can be silicon dioxide. The interlayer dielectric layer 301 can be formed by plasma-enhanced chemical vapor deposition.

[0110] S160 , forming a drain on the second surface.

[0111] refer to Figure 1 , metal is deposited on the second surface 102 to form a drain 500. The deposited metal includes but is not limited to titanium (Ti), nickel (Ni) or silver (Ag).

[0112] In an optional embodiment of the present invention, before forming the drain 500 on the second surface 102 , the second surface 102 is further thinned.

[0113] Specifically, before forming the drain 500 on the second surface 102 , thinning the second surface 102 can reduce the on-resistance of the semiconductor device and improve the quality of the formed drain 500 .

[0114] The technical solution of the embodiment of the present invention provides a first groove 105 on the first surface 101 of the semiconductor body 100. A first two-dimensional material layer 107 is formed at the bottom of the first groove 105. The first two-dimensional material layer 107 serves as the channel of the semiconductor device. The carrier mobility of the first two-dimensional material layer 107 is greater than that of silicon carbide, effectively improving the carrier mobility of the semiconductor device channel and reducing the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the first two-dimensional material layer 107, generating a depletion region in the channel and reducing the off-state leakage current of the semiconductor device. A voltage-resistant layer 30 is formed at the bottom of the first groove 105 to ensure the device's voltage resistance. Furthermore, an insulating layer 200 is formed on the first surface 101, and the insulating layer 200 contacts the first two-dimensional material layer 107, the voltage-resistant layer 20, and a portion of the first region 104. Increasing the thickness of the insulating layer 200 can increase the threshold voltage of the semiconductor device, improve the control performance of the semiconductor device, and enhance the competitiveness of the product without affecting the resistance between the drain 500 and the source 400. Because the carrier mobility of the first two-dimensional material layer 107 is greater than that of silicon carbide, it can effectively improve the carrier mobility of the semiconductor device channel, negligible the effects of lattice damage to the semiconductor body 100, increased interface states, and reduced carrier mobility in the channel region caused by ion implantation to form the first region 104.

[0115] Figure 8 According to an embodiment of the present invention, Figure 2 Schematic diagram of the process included in S130. Figure 6 and Figure 8 The insulating layer 200 includes a first insulating portion 201, a second insulating portion 202, and a third insulating portion 203; S130, forming an insulating layer on the first surface includes:

[0116] S1401. Form a first insulating portion in the first groove.

[0117] refer to Figure 6 , the first insulating portion 201 may be formed in the first groove 105 by a thermal oxidation process.

[0118] S1402. Form a second insulating portion in the first groove; the second insulating portion is connected to the first insulating portion.

[0119] refer to Figure 6 The second insulating portion 202 may be formed in the first groove 105 by a thermal oxidation process. The second insulating portion 202 is connected to the first insulating portion 201 .

[0120] It should be noted that the first insulating portion 201 and the second insulating portion 202 may also be formed simultaneously in the first groove 105 , which is not specifically limited here.

[0121] S1403. Form a third insulating portion on the first surface; the third insulating portion is connected to the first insulating portion and the second insulating portion.

[0122] refer to Figure 6 After the first insulating portion 201 and the second insulating portion 202 are formed, the third insulating portion 203 is formed on the first surface 101. The first insulating portion 201, the second insulating portion 202 and the third insulating portion 203 together constitute the insulating portion 200.

[0123] Figure 9 According to an embodiment of the present invention, Figure 2 The flow chart before S120 is shown in FIG. Figure 9 As shown, in an optional embodiment of the present invention, before S120, forming the voltage-resistant layer on the side of the well region away from the first region, the process further includes:

[0124] S1301 , forming a second two-dimensional material layer on a side of the well region away from the first region, wherein the second two-dimensional material layer is set to be of the first conductivity type, connected to the first two-dimensional material layer, and located between the voltage-resistant layer and the well region.

[0125] In the formation Figure 4 After the structure shown and in the formation Figure 5 Before the structure shown, refer to Figure 10 A second two-dimensional material layer 108 is formed on the side of the well region 103 away from the first region 104 . The second two-dimensional material layer 108 is set to the first conductivity type, connected to the first two-dimensional material layer 107 , and located between the voltage-resistant layer 30 and the well region 103 .

[0126] In an embodiment of the present invention, the second two-dimensional material layer 108 is connected to the first two-dimensional material layer 107 and both have high carrier mobility. This provides a low-resistance conductive channel between the first surface 101 and the drift region, allowing carriers to flow through this channel without being affected by the narrowing of the effective conductive area caused by the expansion of the depletion layer in the JFET structure. This solves the problems of increased resistance between the source 100 and the drain 500 in the MOSFET device, increased energy consumption, and increased temperature during device operation, thereby reducing the on-resistance of the device. Furthermore, the second two-dimensional material layer 108 has high conductivity and carrier mobility, replacing the JFET region as the current channel. This eliminates the need to provide a JFET region of sufficient lateral dimensions on one side of the well region 103 in a planar MOSFET device to ensure that the JFET region has a resistance that matches the on-current. This reduces the lateral dimensions of the semiconductor body 100 on the side of the well region 103, thereby reducing the lateral dimensions of the semiconductor device.

[0127] Figure 11 According to an embodiment of the present invention, Figure 2 The flow chart of S110 is shown in FIG. Figure 11 As shown, in an optional embodiment of the present invention, S110, providing a semiconductor body includes:

[0128] S1101 , provide a semiconductor body, wherein the semiconductor body includes a first surface and a second surface arranged opposite to each other.

[0129] refer to Figure 12 , providing a semiconductor body 100, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 through one or more epitaxial processes, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0130] S1102 , forming a well region on the first surface, wherein the well region is set to a second conductivity type.

[0131] refer to Figure 13 In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, a well region 103 is formed by ion implantation, and the well region 103 is a P-well region. The P-type dopant ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0132] S1103 , forming a first region on the first surface, wherein the first region is set to a first conductive type.

[0133] refer to Figure 14 For example, for an N-type MOSFET, a first region 104 is formed on the first surface 101 by ion implantation. The first region 104 is an N+ doped region. The N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions.

[0134] In an optional embodiment of the present invention, after forming the first region on the first surface, the method further includes: forming a second region on the first surface, the second region being set to a second conductive type and contacting the first region; and the ion concentration of the second region is greater than the ion concentration of the well region.

[0135] refer to Figure 15 A second region 109 is formed on the first surface 101 . The second region 109 is configured as a second conductive type and contacts the first region 104 . The ion concentration of the second region 109 is greater than the ion concentration of the well region 103 .

[0136] S1104 , forming a first groove on the first surface, wherein the first groove extends from the first surface into the semiconductor body.

[0137] refer to Figure 3 A first groove 105 is formed on the first surface 101, and the first groove 105 extends from the first surface 101 into the semiconductor body 100. The first groove 105 can be formed by photolithography and etching processes.

[0138] Figure 16 According to an embodiment of the present invention, Figure 2 Another flow chart of S110 included in FIG. Figure 16 As shown, in an optional embodiment of the present invention, S110, providing a semiconductor body includes:

[0139] S1106 , providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other.

[0140] refer to Figure 12 , providing a semiconductor body 100, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 through one or more epitaxial processes, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0141] S1107 , forming a first groove on the first surface, wherein the first groove extends from the first surface into the semiconductor body.

[0142] refer to Figure 17 A first groove 105 is formed on the first surface 101 , and the first groove 105 extends from the first surface 101 into the semiconductor body 100 .

[0143] S1108 , forming a well region on the first surface, wherein the well region is set to the second conductivity type.

[0144] refer to Figure 18 A well region 103 is formed on the first surface 101 by an ion implantation process, and the well region 103 is set to the second conductivity type.

[0145] S1109 , forming a first region on the first surface, wherein the first region is set to a first conductive type.

[0146] refer to Figure 3 A first region 104 is formed on the first surface 101 , and the first region 104 is set to a first conductivity type.

[0147] In an optional embodiment of the present invention, after forming the first region on the first surface, the method further includes: forming a second region on the first surface, the second region being set to a second conductive type and contacting the first region; and the ion concentration of the second region is greater than the ion concentration of the well region.

[0148] refer to Figure 3 A second region 109 is formed on the first surface 101 . The second region 109 is configured as a second conductive type and contacts the first region 104 . The ion concentration of the second region 109 is greater than the ion concentration of the well region 103 .

[0149] In other optional embodiments of the present invention, providing the semiconductor body includes providing a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0150] Among them, reference Figure 1 The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0151] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0152] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further elaborated herein.

[0153] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0154] Therefore, the power conversion circuit includes the beneficial effects of the semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0155] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0156] Therefore, the beneficial effects of the vehicle including any power conversion circuit package described in any embodiment of the present invention will not be repeated here.

[0157] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0158] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a first surface and a second surface arranged opposite to each other, wherein the first surface is provided with a first groove; the semiconductor body further comprising a first two-dimensional material layer, a well region, and a first region, wherein the first two-dimensional material layer is configured to be of a first conductivity type and is located at a bottom of the first groove; the first region is configured to be of the first conductivity type and is located on the first surface, the well region is configured to be of a second conductivity type and is located on a side of the first region away from the first surface, and extends along an edge of the first region to the first two-dimensional material layer; the carrier mobility of the first two-dimensional material layer is greater than the carrier mobility of silicon carbide; a voltage-resistant layer, located on a side of the well region away from the first region and located at a bottom of the first groove; an insulating layer, located on the first surface, contacting the first two-dimensional material layer, the voltage-resistant layer, and a portion of the first region; a gate, located on a side of the insulating layer away from the semiconductor body; The insulating layer is used to insulate the semiconductor body and the gate; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The insulating layer includes a first insulating portion, a second insulating portion and a third insulating portion; The first insulating portion is located in the first groove and contacts the first two-dimensional material layer; The second insulating portion is located in the first groove, contacts the voltage-resistant layer, and is connected to the first insulating portion; The third insulating portion is located on the first surface, contacts a portion of the first region, and is connected to the first insulating portion and the second insulating portion.

3. The semiconductor device according to claim 1, wherein The voltage-resistant layer includes at least one of silicon oxide, silicon nitride, aluminum oxide and zirconium oxide.

4. The semiconductor device according to claim 1, wherein The semiconductor device also includes a second two-dimensional material layer; the second two-dimensional material layer is set to the first conductivity type, connected to the first two-dimensional material layer, located on the side of the well region away from the first region, and located between the voltage-resistant layer and the well region.

5. The semiconductor device according to claim 4, wherein The carrier mobility of the first two-dimensional material layer in different directions is the same; And / or, the carrier mobility of the second two-dimensional material layer in different directions is the same. The semiconductor device according to claim 1 , wherein: The semiconductor body further includes a second region; the second region is set to a second conductivity type and is located on the first surface; the ion concentration of the second region is greater than the ion concentration of the well region; and the second region is in contact with the first region.

7. The semiconductor device according to claim 1, wherein The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

8. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, comprising a first surface and a second surface arranged opposite to each other, wherein the first surface is provided with a first groove; the semiconductor body further comprising a first two-dimensional material layer, a well region, and a first region, wherein the first two-dimensional material layer is configured to be of a first conductivity type and is located at a bottom of the first groove; the first region is configured to be of the first conductivity type and is located on the first surface, the well region is configured to be of a second conductivity type and is located on a side of the first region away from the first surface, and extends along an edge of the first region to the first two-dimensional material layer; the carrier mobility of the first two-dimensional material layer is greater than that of silicon carbide; forming a voltage-resistant layer on a side of the well region away from the first region; The pressure-resistant layer is located at the bottom of the first groove; forming an insulating layer on the first surface, wherein the insulating layer is in contact with the first two-dimensional material layer, the voltage-resistant layer, and a portion of the first region; forming a gate on a side of the insulating layer away from the semiconductor body; The insulating layer is used to insulate the semiconductor body and the gate; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The insulating layer includes a first insulating portion, a second insulating portion, and a third insulating portion; and forming the insulating layer on the first surface includes: forming a first insulating portion in the first groove; forming a second insulating portion in the first groove; the second insulating portion being connected to the first insulating portion; A third insulating portion is formed on the first surface; the third insulating portion is connected to the first insulating portion and the second insulating portion.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: Forming a voltage-resistant layer on a side of the well region away from the first region, comprising: A voltage-resistant layer including at least one of silicon oxide, silicon nitride, aluminum oxide, and zirconium oxide is formed on a side of the well region away from the first region.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: Before forming the voltage-resistant layer on the side of the well region away from the first region, the method further includes: A second two-dimensional material layer is formed on a side of the well region away from the first region. The second two-dimensional material layer is set to the first conductivity type, connected to the first two-dimensional material layer, and located between the voltage-resistant layer and the well region.

12. The method for manufacturing a semiconductor device according to claim 8, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; forming a well region on the first surface, wherein the well region is set to a second conductivity type; forming a first region on the first surface, wherein the first region is configured as a first conductive type; A first groove is formed in the first surface, and the first groove extends from the first surface into the semiconductor body.

13. The method for manufacturing a semiconductor device according to claim 8, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; forming a first groove on the first surface, wherein the first groove extends from the first surface into the semiconductor body; forming a well region on the first surface, wherein the well region is set to a second conductivity type; A first region is formed on the first surface, and the first region is set to be of a first conductivity type.

14. The method for manufacturing a semiconductor device according to claim 12 or 13, wherein: After forming the first area on the first surface, the method further includes: A second region is formed on the first surface. The second region is configured as a second conductive type and contacts the first region. The ion concentration of the second region is greater than the ion concentration of the well region.

15. The method for manufacturing a semiconductor device according to claim 8, wherein: The semiconductor body provided includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

16. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 7, wherein the substrate is used to support the semiconductor device.

17. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

18. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 17, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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