Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, and the semiconductor body comprises a first region which is arranged to be of a first conduction type and is located on a first surface; the well region is of the second conduction type and located on the side, away from the first surface, of the first region; the first surface is provided with a groove, and the groove extends into the well region from the first surface; the semiconductor body further comprises an insulating layer, the insulating layer comprises a first insulating part and a second insulating part, the first insulating part is located in the groove, and the second insulating part is located on the first surface and connected with the first insulating part. The two-dimensional material is arranged to be of the first conduction type, is located on the bottom surface of the groove and is located on the side, away from the second insulation part, of the first insulation part, and the carrier mobility of the two-dimensional material is larger than that of silicon carbide; a gate electrode; a source electrode; and a drain electrode. According to the technical scheme of the embodiment of the invention, the on-resistance of the semiconductor device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in power electronics, automobiles, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] In the prior art, a positive voltage is applied to the gate of a SiC or GaN metal-oxide-semiconductor field-effect transistor (MOSFET). When the threshold voltage is reached, an inversion layer is formed in the well region. The direction of electron movement is from the first region formed by ion implantation of the metal conductive layer to the inversion layer of the well region, and then through the silicon carbide substrate to reach the drain.

[0004] However, in the prior art, ion implantation to form the first region causes lattice damage to the semiconductor body, resulting in an increase in interface states, reduced electron mobility in the channel region, and excessively large on-resistance of the SiC or GaN MOSFET. Summary of the Invention

[0005] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the on-resistance of the semiconductor device.

[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0007] A semiconductor body comprising a first surface and a second surface disposed opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, and the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a groove being provided on the first surface, the groove extending from the first surface into the well region; and an insulating layer comprising a first insulating portion and a second insulating portion, the first insulating portion being located within the groove, and the second insulating portion being located on the first surface and connected to the first insulating portion.

[0008] a two-dimensional material, the two-dimensional material being of the first conductivity type and being located on the bottom surface of the groove and on a side of the first insulating portion away from the second insulating portion; the carrier mobility of the two-dimensional material being greater than the carrier mobility of silicon carbide;

[0009] A gate, the gate being located on a side of the insulating layer away from the semiconductor body;

[0010] a source electrode, located on the first surface;

[0011] The drain is located on the second surface.

[0012] Optionally, the two-dimensional material includes a two-dimensional material semiconductor layer.

[0013] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0014] Optionally, the semiconductor body further includes a second region, the second region is set to the second conductivity type and is located on the first surface, and the second region is connected to the first region.

[0015] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising:

[0016] A semiconductor body is provided, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body further including a well region and a first region, the first region being configured to have a first conductivity type and being located on the first surface, and the well region being configured to have a second conductivity type and being located on a side of the first region away from the first surface; a groove being provided on the first surface, the groove extending from the first surface into the well region;

[0017] forming a two-dimensional material on the bottom surface of the groove, wherein the two-dimensional material is set to be a first conductive type; the carrier mobility of the two-dimensional material is greater than the carrier mobility of silicon carbide;

[0018] forming an insulating layer on the first surface, the insulating layer comprising a first insulating portion and a second insulating portion, the first insulating portion being located on a side of the two-dimensional material in the groove away from the semiconductor body, and the second insulating portion being located on the first surface and connected to the first insulating portion;

[0019] forming a gate on a side of the insulating layer away from the semiconductor body;

[0020] forming a source electrode on the first surface;

[0021] A drain electrode is formed on the second surface.

[0022] Optionally, forming a two-dimensional material on the bottom surface of the groove includes:

[0023] A two-dimensional material including a two-dimensional material semiconductor layer is formed on the bottom surface of the groove.

[0024] Optionally, providing a semiconductor body includes:

[0025] Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other;

[0026] forming a well region on the first surface, wherein the well region is set to a second conductivity type;

[0027] forming a first region on the first surface, wherein the first region is configured as a first conductivity type;

[0028] A groove is formed on the first surface, and the groove extends from the first surface into the well region.

[0029] Optionally, providing a semiconductor body includes:

[0030] Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other;

[0031] forming a groove in the first surface, the groove extending from the first surface into the semiconductor body;

[0032] forming a well region on the first surface, wherein the well region is set to a second conductivity type;

[0033] A first region is formed on the first surface, and the first region is set to be of a first conductivity type.

[0034] Optionally, forming a two-dimensional material on the bottom surface of the groove includes:

[0035] A two-dimensional material is formed on the bottom surface of the groove through a deposition process. The two-dimensional material is set to a first conductive type, and the carrier mobility of the two-dimensional material is greater than the carrier mobility of silicon carbide.

[0036] Optionally, providing the semiconductor body further includes:

[0037] A semiconductor body including a second region is provided. The second region is set to a second conductivity type and is located on the first surface. The second region is connected to the first region.

[0038] Optionally, providing a semiconductor body includes:

[0039] A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0040] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used to support the semiconductor device.

[0041] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0042] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0043] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0044] The technical solution of an embodiment of the present invention provides a groove on the first surface of the semiconductor body, and a two-dimensional material is provided on the bottom surface of the groove. The two-dimensional material serves as the channel of the semiconductor device, and the carrier mobility of the two-dimensional material is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. The well region forms a PN junction contact with the two-dimensional material, generating a depletion region in the channel, thereby reducing the off-state leakage current of the semiconductor device. In addition, the gate insulating layer includes a first insulating portion and a second insulating portion, the first insulating portion being located within the groove and the second insulating portion being located on the first surface and connected to the first insulating portion. This increases the thickness of the gate insulating layer, thereby increasing the threshold voltage of the semiconductor device without affecting the resistance between the drain and source, improving the control performance of the semiconductor device, and enhancing the competitiveness of the product. In particular, because the carrier mobility of the two-dimensional material is greater than that of silicon carbide, the carrier mobility of the semiconductor device channel can be effectively improved, and the effects of lattice damage to the semiconductor body, increase in interface states, and reduction in carrier mobility in the channel region caused by ion implantation on the first region can be ignored.

[0045] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0048] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0049] Figure 3-Figure 5 is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0050] Figure 6 yes Figure 2 A schematic diagram of the process included in S110;

[0051] Figure 7-10 1 is a cross-sectional view corresponding to each step of providing a semiconductor body in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0052] Figure 11 yes Figure 2 Another flow chart of S110 included in FIG.

[0053] Figure 12 yes Figure 11 The cross-sectional view corresponding to S1107. DETAILED DESCRIPTION

[0054] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0055] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0056] In order to reduce the on-resistance of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0057] Figure 1 FIG. 1 is a schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present invention. Figure 1As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other, the semiconductor body 100 also includes a well region 103 and a first region 104, the first region 104 is set to a first conductivity type and is located on the first surface 101, the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101; the first surface 101 is provided with a groove 107, the groove 107 extends from the first surface 101 to the well region 103; the semiconductor body also includes an insulating layer 201, the insulating layer 201 includes a first insulating portion 2011 and a second insulating portion 2012, the first insulating portion 2011 is located in the groove 107, and the second insulating portion 2012 is located on the first surface 101 and connected to the first insulating portion 2011; the two-dimensional material 105, the two-dimensional material 105 is set to the first conductive type and is located on the bottom surface of the groove 107, and is located on the side of the first insulating portion 2011 away from the second insulating portion 2012; the carrier mobility of the two-dimensional material 105 is greater than the carrier mobility of silicon carbide; the gate 200, the gate 200 is located on the side of the insulating layer 201 away from the semiconductor body 100; the source 300 is located on the first surface 101; the drain 400 is located on the second surface 102.

[0058] In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0059] For example, for an N-type MOSFET, first region 104 is an N+ doped region, where the N-type dopant ions may be phosphorus (P) or nitrogen (N). Well region 103 is a P-well region, where the P-type dopant ions may be aluminum (Al) or boron (B). Two-dimensional material 105 is an N-type channel layer, and the carrier mobility of two-dimensional material 105 is greater than that of silicon carbide, thereby improving the electron mobility of the semiconductor device.

[0060] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0061] The technical solution of the embodiment of the present invention provides a recess 107 on the first surface 101 of the semiconductor body 100. A two-dimensional material 105 is disposed on the bottom surface of the recess 107. The two-dimensional material 105 serves as the channel of the semiconductor device. The carrier mobility of the two-dimensional material 105 is greater than that of silicon carbide, effectively improving the carrier mobility of the semiconductor device channel and reducing the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the two-dimensional material 105, generating a depletion region in the channel and reducing the off-state leakage current of the semiconductor device. Furthermore, the insulating layer 201 includes a first insulating portion 2011 and a second insulating portion 2012. The first insulating portion 2011 is located within the recess 107, and the second insulating portion 2012 is located on the first surface 101 and connected to the first insulating portion 2011. This increases the thickness of the insulating layer 201. This increases the threshold voltage of the semiconductor device without affecting the resistance between the drain 400 and the source 300, thereby improving the control performance of the semiconductor device and enhancing the product's competitiveness. Among them, since the carrier mobility of the two-dimensional material 105 is greater than that of silicon carbide, it can effectively improve the carrier mobility of the channel of the semiconductor device, and the effects of lattice damage to the semiconductor body 100, increase in interface states and reduction in carrier mobility in the channel region caused by ion implantation when the first region is formed can be ignored.

[0062] In other optional embodiments of the present invention, refer to Figure 1 , the two-dimensional material 105 includes a two-dimensional material semiconductor layer.

[0063] Specifically, in crystallography, a two-dimensional material semiconductor layer refers to a material that is only a single atomic layer or two atomic layers thick, with a thickness on the order of a few nanometers. Two-dimensional material semiconductor layers have high carrier mobility, and common two-dimensional material semiconductor layers include graphene and graphene derivatives. The carrier mobility of the two-dimensional material semiconductor layer is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the two-dimensional material 105, generating a depletion region in the channel, thereby reducing the off-state leakage current of the semiconductor device.

[0064] In other optional embodiments of the present invention, refer to Figure 1 , the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0065] The semiconductor body 100 includes a silicon carbide semiconductor body, the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device, the semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0066] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0067] In other optional embodiments of the present invention, refer to Figure 1 The semiconductor body 100 further includes a second region 106 . The second region 106 is configured to be of the second conductivity type and is located on the first surface 101 . The second region 106 is connected to the first region 104 .

[0068] Specifically, the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, and both are set to the second conductivity type. For an N-type MOSFET, the second region 106 is a P+ doped region, and its doping concentration is greater than the doping concentration of the well region 103, and can form a good ohmic contact with the source 300.

[0069] In other optional embodiments of the present invention, refer to Figure 1 An interlayer insulating layer 500 is further included between the gate 200 and the source 300. The interlayer insulating layer 500 is used to insulate the gate 200 and the source 300. The insulating layer 201 may be a gate oxide layer. The material of the gate 200 may be polysilicon.

[0070] Figure 2 The flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention is shown.

[0071] like Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0072] S110. Provide a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body also including a well region and a first region, the first region is set to a first conductive type and is located on the first surface, the well region is set to a second conductive type and is located on a side of the first region away from the first surface; the first surface is provided with a groove, the groove extending from the first surface to the well region.

[0073] refer to Figure 3 , a semiconductor body 100 is provided, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other, the semiconductor body 100 also includes a well region 103 and a first region 104, the first region 104 is set to a first conductivity type and is located on the first surface 101, the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101; the first surface 101 is provided with a groove 107, the groove 107 extends from the first surface 101 to the well region 103.

[0074] In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0075] Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0076] In other optional embodiments of the present invention, refer to Figure 3 The semiconductor body 100 further includes a second region 106 . The second region 106 is configured to be of the second conductivity type and is located on the first surface 101 . The second region 106 is connected to the first region 104 .

[0077] Specifically, the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, and both are set to the second conductivity type. For an N-type MOSFET, the second region 106 is a P+ doped region, and its doping concentration is greater than the doping concentration of the well region 103, and can form a good ohmic contact with the source 300.

[0078] By performing trench etching, sacrificial oxidation, and oxide layer removal processes on the first surface 101 , a recess 107 is formed on the first surface 101 . The recess 107 extends from the first surface 101 into the well region 103 .

[0079] like Figure 3 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0080] S120. Form a two-dimensional material on the bottom surface of the groove, wherein the two-dimensional material is set to a first conductive type; the carrier mobility of the two-dimensional material is greater than the carrier mobility of silicon carbide.

[0081] In other optional embodiments of the present invention, forming a two-dimensional material on the bottom surface of the groove 107 includes: forming a two-dimensional material including a two-dimensional material semiconductor layer on the bottom surface of the groove 107 .

[0082] refer to Figure 4 A two-dimensional semiconductor layer is deposited at the bottom of the groove 107 to form a two-dimensional material 105. The two-dimensional material 105 serves as a channel layer, and the carrier mobility of the two-dimensional material 105 is greater than that of silicon carbide, thereby improving the electron mobility of the semiconductor device and reducing the on-resistance of the semiconductor device.

[0083] Specifically, in crystallography, a two-dimensional material semiconductor layer refers to a material that is only a single atomic layer or two atomic layers thick, with a thickness on the order of a few nanometers. Two-dimensional material semiconductor layers have high carrier mobility, and common two-dimensional material semiconductor layers include graphene and graphene derivatives. The carrier mobility of the two-dimensional material semiconductor layer is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the two-dimensional material 105, generating a depletion region in the channel, thereby reducing the off-state leakage current of the semiconductor device.

[0084] S130. Form an insulating layer on the first surface, the insulating layer including a first insulating portion and a second insulating portion, the first insulating portion being located on a side of the two-dimensional material in the groove away from the semiconductor body, and the second insulating portion being located on the first surface and connected to the first insulating portion.

[0085] refer to Figure 5 A first insulating portion 2011 is formed on the side of the two-dimensional material 105 in the recess 107 away from the semiconductor body 100 by a high-temperature oxidation or deposition process. A second insulating portion 2012 is formed on the first surface 101 and connected to the first insulating portion 2011 by a high-temperature oxidation or deposition process. The first insulating portion 2011 and the second insulating portion 2012 together constitute the insulating layer 201.

[0086] S140 , forming a gate on a side of the insulating layer away from the semiconductor body.

[0087] refer to Figure 5 , a gate 200 is formed on the insulating layer 201 by a polysilicon thin film deposition process.

[0088] S150 , forming a source electrode on the first surface.

[0089] refer to Figure 1 An interlayer insulating layer 500 is formed on the gate 200 by a deposition process to insulate and isolate the gate 200. Metal is deposited on the first surface 101 of the semiconductor body 100 to form a source 300.

[0090] S160 , forming a drain on the second surface.

[0091] refer to Figure 1 , metal is deposited on the second surface 102 of the semiconductor body 100 to form a drain 400 .

[0092] The semiconductor device fabricated in accordance with an embodiment of the present invention comprises a recess 107 disposed on the first surface 101 of the semiconductor body 100. A two-dimensional material 105 is formed at the bottom of the recess 107. The two-dimensional material 105 serves as the semiconductor device's channel. The carrier mobility of the two-dimensional material 105 is greater than that of silicon carbide, effectively improving the carrier mobility of the semiconductor device's channel and reducing on-resistance. Furthermore, the well region 103 forms a PN junction with the two-dimensional material 105, generating a depletion region in the channel and reducing the semiconductor device's off-state leakage current. Furthermore, the insulating layer 201 comprises a first insulating portion 2011 and a second insulating portion 2012. The first insulating portion 2011 is located within the recess 107, while the second insulating portion 2012 is located on the first surface 101 and connected to the first insulating portion 2011. This increases the thickness of the insulating layer 201, thereby increasing the threshold voltage of the semiconductor device without affecting the resistance between the drain 400 and the source 300, thereby improving the control performance of the semiconductor device and enhancing the product's competitiveness. Among them, since the carrier mobility of the two-dimensional material 105 is greater than that of silicon carbide, it can effectively improve the carrier mobility of the channel of the semiconductor device, and the effects of lattice damage to the semiconductor body 100, increase in interface states and reduction in carrier mobility in the channel region caused by ion implantation when the first region is formed can be ignored.

[0093] Figure 6 yes Figure 2 The flow chart of S110 is shown in FIG. Figure 6 As shown, in other optional embodiments of the present invention, S110 providing a semiconductor body includes:

[0094] S1101 , provide a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other.

[0095] refer to Figure 7 , providing a semiconductor body 100, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0096] S1102 , forming a well region on the first surface, wherein the well region is set to a second conductivity type.

[0097] refer to Figure 8 In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0098] For example, for an N-type MOSFET, the well region 103 is formed by ion implantation. The well region 103 is a P-well region. The P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0099] S1103 , forming a first region on the first surface, wherein the first region is set to a first conductive type.

[0100] refer to Figure 9 For example, for an N-type MOSFET, a first region 104 is formed on the first surface 101 by ion implantation. The first region 104 is an N+ doped region. The N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions.

[0101] S1104 , forming a groove on the first surface, wherein the groove extends from the first surface to the well region.

[0102] refer to Figure 10 , by performing trench etching, sacrificial oxidation, and oxide layer removal processes on the first surface 101, a groove 107 is formed on the first surface 101, and the groove 107 extends from the first surface 101 to the well region 103. First, the first region 104 is formed on the first surface 101 through an ion implantation process, and then the groove 107 is formed on the first surface 101. This allows the two-dimensional material to be deposited at the location with the highest ion implantation concentration, which is beneficial to improving the electron mobility of the semiconductor device. In other optional embodiments of the present invention, S110 provides the semiconductor body and further includes:

[0103] S1105 , providing a semiconductor body including a second region, wherein the second region is set to a second conductivity type and is located on the first surface, and the second region is connected to the first region.

[0104] refer to Figure 3A semiconductor body 100 is provided, including a second region 106. The second region 106 is configured as a second conductivity type and is located on the first surface 101. The second region 106 is connected to the first region 104. Specifically, the conductivity type of the second region 106 is the same as the conductivity type of the well region 103, both being configured as the second conductivity type. For an N-type MOSFET, the second region 106 is a P+ doped region with a doping concentration greater than that of the well region 103, thereby forming a good ohmic contact with the source.

[0105] Figure 11 yes Figure 2 Another flow chart of S110 included in FIG. Figure 11 As shown, in other optional embodiments of the present invention, S110 providing a semiconductor body further includes:

[0106] S1106 , providing a semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other.

[0107] refer to Figure 7 , providing a semiconductor body 100, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other. The semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include a substrate 10 and a semiconductor layer formed by other processes. Among them, the epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 through a single epitaxial process, and the epitaxial process includes chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD) and atomic layer epitaxy (ALE) and other processes.

[0108] S1107 , forming a groove on the first surface, wherein the groove extends from the first surface into the semiconductor body.

[0109] refer to Figure 12 By performing trench etching, sacrificial oxidation, and oxide layer removal processes on the first surface 101 , a recess 107 is formed on the first surface 101 , and the recess 107 extends from the first surface 101 into the semiconductor body 100 .

[0110] S1108 , forming a well region on the first surface, wherein the well region is set to the second conductivity type.

[0111] refer to Figure 10 For example, for an N-type MOSFET, a well region 103 is formed by ion implantation. The well region 103 is a P-well region. The P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions.

[0112] S1109 , forming a first region on the first surface, wherein the first region is set to a first conductive type.

[0113] refer to Figure 10 For example, for an N-type MOSFET, a first region 104 is formed on the first surface 101 by ion implantation. The first region 104 is an N+ doped region. The N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions.

[0114] In an optional embodiment of the present invention, a groove 107 is first formed on the first surface 101, and the groove 107 extends from the first surface 101 into the semiconductor body 100. Then, an ion implantation process is performed to form a well region 103 and a first region 104 on the first surface 101. The first region 104 is set to the first conductive type, which can prevent the implantation diffusion or ion scattering of the well region 103 from affecting the first region 104.

[0115] In another optional embodiment of the present invention, S120 forming a two-dimensional material on the bottom surface of the groove includes:

[0116] S1201. Form a two-dimensional material on the bottom surface of the groove through a deposition process. The two-dimensional material is set to a first conductive type, and the carrier mobility of the two-dimensional material is greater than the carrier mobility of silicon carbide.

[0117] refer to Figure 4 A two-dimensional material 105 is deposited at the bottom of the groove 107. The carrier mobility of the two-dimensional material 105 is greater than that of silicon carbide, thereby improving the electron mobility of the semiconductor device.

[0118] In other optional embodiments of the present invention, before forming the drain on the second surface in S150, the method further includes:

[0119] S1500, performing thinning processing on the second surface.

[0120] Specifically, refer to Figure 1 , thinning the second surface 102 can reduce the conductive resistance of the semiconductor device.

[0121] In other optional embodiments of the present invention, providing the semiconductor body includes providing a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0122] Among them, reference Figure 1 The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0123] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0124] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further elaborated herein.

[0125] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0126] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0127] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0128] Therefore, the beneficial effects of the vehicle including any power conversion circuit package described in any embodiment of the present invention will not be repeated here.

[0129] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0130] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a first surface and a second surface disposed opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, the well region being of a second conductivity type and located on a side of the first region away from the first surface; the first surface being provided with a groove extending from the first surface into the well region; the semiconductor body further comprising an insulating layer, the insulating layer comprising a first insulating portion and a second insulating portion, the first insulating portion being located within the groove, and the second insulating portion being located on the first surface and connected to the first insulating portion; a two-dimensional material, the two-dimensional material being of a first conductivity type and being located on a bottom surface of the groove and on a side of the first insulating portion away from the second insulating portion; the carrier mobility of the two-dimensional material being greater than that of silicon carbide; a gate, the gate being located on a side of the insulating layer away from the semiconductor body; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The two-dimensional material includes a two-dimensional material semiconductor layer.

3. The semiconductor device according to claim 1, wherein The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

4. The semiconductor device according to claim 1, wherein The semiconductor body further includes a second region, which is configured as a second conductivity type and is located on the first surface, and is connected to the first region.

5. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured to be of a first conductivity type and located on the first surface, the well region being configured to be of a second conductivity type and located on a side of the first region away from the first surface; a groove being provided on the first surface, the groove extending from the first surface into the well region; forming a two-dimensional material on the bottom surface of the groove, wherein the two-dimensional material is set to a first conductivity type; the carrier mobility of the two-dimensional material is greater than the carrier mobility of silicon carbide; forming an insulating layer on the first surface, the insulating layer comprising a first insulating portion and a second insulating portion, the first insulating portion being located on a side of the two-dimensional material in the groove away from the semiconductor body, and the second insulating portion being located on the first surface and connected to the first insulating portion; forming a gate on a side of the insulating layer away from the semiconductor body; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

6. The method for manufacturing a semiconductor device according to claim 5, wherein: Forming a two-dimensional material on the bottom surface of the groove includes: A two-dimensional material including a two-dimensional material semiconductor layer is formed on the bottom surface of the groove.

7. The method for manufacturing a semiconductor device according to claim 5, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; forming a well region on the first surface, wherein the well region is set to a second conductivity type; forming a first region on the first surface, wherein the first region is configured as a first conductive type; A groove is formed on the first surface, and the groove extends from the first surface into the well region.

8. The method for manufacturing a semiconductor device according to claim 5, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; forming a groove on the first surface, the groove extending from the first surface into the semiconductor body; forming a well region on the first surface, wherein the well region is set to a second conductivity type; A first region is formed on the first surface, and the first region is set to be of a first conductivity type.

9. The method for manufacturing a semiconductor device according to claim 5, wherein: forming a two-dimensional material on the bottom surface of the groove, comprising: A two-dimensional material is formed on the bottom surface of the groove through a deposition process. The two-dimensional material is set to a first conductive type, and the carrier mobility of the two-dimensional material is greater than the carrier mobility of silicon carbide.

10. The method for manufacturing a semiconductor device according to claim 5, wherein: Providing a semiconductor body also includes: A semiconductor body including a second region is provided. The second region is configured to be of a second conductivity type and is located on the first surface. The second region is connected to the first region.

11. The method for manufacturing a semiconductor device according to claim 5, wherein: The semiconductor body provided includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

12. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 4, wherein the substrate is used to support the semiconductor device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 4, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and the power conversion circuit as claimed in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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