Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device includes: a semiconductor body; the semiconductor body comprises a well region and a first region; the first surface is provided with a gate trench; the gate trench comprises a first gate trench and a second gate trench which are communicated, and the second gate trench is located at one side, far away from the first surface, of the first gate trench; the first gate trench extends into the first region and the well region from the first surface, and the second gate trench is located at one side, far away from the first region, of the well region; the semiconductor body further comprises a first insulating layer and a second insulating layer, the first insulating layer is located on the side wall of the first gate trench, the second gate trench is filled with the second insulating layer, and the thickness of the second insulating layer is larger than or equal to that of the first insulating layer; and a trench gate located in the first gate trench. According to the technical scheme, the breakdown voltage of the semiconductor device is improved, and the device performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in power electronics, automobiles, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] like Figure 1 As shown, Figure 1 This is a structural schematic diagram of a semiconductor device provided by the prior art. For a trench-type SiC or GaN metal-oxide-semiconductor field-effect transistor (MOSFET), the semiconductor device includes: a semiconductor body 100, the semiconductor body 100 includes a first surface 101 and a second surface 102, the semiconductor body 100 is composed of a substrate 10 and an epitaxial layer 11, and the semiconductor body 100 also includes a first region 103, a second region 104 and a well region 105. The breakdown voltage (BV) of the semiconductor device is relatively low, which in turn affects the performance of the device. The semiconductor device also includes a gate insulating layer 106, a gate 200, an interlayer insulating layer 201, a source 300 and a drain 400, wherein the gate 200 is located in the gate trench T1. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to increase the breakdown voltage of the semiconductor device and enhance the device performance.

[0005] According to one aspect of the present invention, a semiconductor device is provided, comprising: a semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, and the well region being of a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; the gate trench comprising a first gate trench and a second gate trench connected to each other, the second gate trench being located on a side of the first gate trench away from the first surface, the vertical projection of the first gate trench on the first surface overlapping the vertical projection of the second gate trench on the first surface; the first gate trench extending from the first surface into the first region and the well region, the second gate trench being located on a side of the well region away from the first region; the semiconductor body further comprising a first insulating layer and a second insulating layer, the first insulating layer being located on a sidewall of the first gate trench, the second insulating layer filling the second gate trench, the thickness of the second insulating layer being greater than or equal to the thickness of the first insulating layer;

[0006] a trench gate located in the first gate trench on a side of the first insulating layer away from the semiconductor body;

[0007] a source electrode, located on the first surface;

[0008] The drain is located on the second surface.

[0009] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0010] A semiconductor body is provided, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, and the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; the gate trench comprising a first gate trench and a second gate trench being connected, the second gate trench being located on a side of the first gate trench away from the first surface, the vertical projection of the first gate trench on the first surface overlapping the vertical projection of the second gate trench on the first surface; the first gate trench extending from the first surface into the first region and the well region, the second gate trench being located on a side of the well region away from the first region; the semiconductor body further comprising a first insulating layer and a second insulating layer, the first insulating layer being located on a sidewall of the first gate trench, the second insulating layer filling the second gate trench, the thickness of the second insulating layer being greater than the thickness of the first insulating layer;

[0011] forming a trench gate on a side of the first insulating layer away from the semiconductor body in the first gate trench;

[0012] forming a source electrode on the first surface;

[0013] A drain electrode is formed on the second surface.

[0014] According to another aspect of the present invention, a power module is provided, comprising a substrate and the semiconductor device according to any one of the embodiments of the present invention, wherein the substrate is used to support the semiconductor device.

[0015] According to another aspect of the present invention, there is provided a power conversion circuit, wherein the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0016] The power conversion circuit includes a circuit board and at least one semiconductor device as described in any of the embodiments of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0017] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in another aspect of the present invention, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0018] In a semiconductor device and manufacturing method, power module, power conversion circuit, and vehicle provided by an embodiment of the present invention, a gate trench includes a first gate trench and a second gate trench connected to each other, a first insulating layer is located on the sidewalls of the first gate trench, and a second insulating layer fills the second gate trench, the thickness of the second insulating layer being greater than or equal to the thickness of the first insulating layer. The above technical solution, on the one hand, ensures that the thickness of the first insulating layer between the first region and the sidewalls of the first gate trench and between the well region and the sidewalls of the first gate trench is not too thick, thereby preventing excessive on-resistance (Rdson) and threshold voltage (Vth) of the device. On the other hand, the above technical solution, by filling the second gate trench with the second insulating layer, increases the thickness of the second insulating layer on the bottom surface and sidewalls of the second gate trench, thereby improving the withstand voltage capability of the insulating layer at the bottom of the gate trench, thereby improving the breakdown voltage of the semiconductor device and enhancing device performance. The vertical projection of the first gate trench on the first surface overlaps the vertical projection of the second gate trench on the first surface, which is equivalent to reducing the area of ​​the semiconductor body occupied by the second gate trench in the extension direction of the second gate trench, thereby reducing gate capacitance, thereby improving the switching speed of the device and reducing switching loss.

[0019] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 It is a structural schematic diagram of a semiconductor device provided by the prior art;

[0022] Figure 2 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0023] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0024] Figure 4 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0025] Figure 5 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0026] Figure 6 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0027] Figure 7 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0028] Figure 8 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0029] Figure 9 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0030] Figure 10 yes Figure 9 A schematic diagram of the process included in S110;

[0031] Figures 11-18 yes Figure 9 Structural diagram corresponding to each relevant step in;

[0032] Figures 19-24 yes Figure 3 A schematic structural diagram corresponding to each relevant step of the method for manufacturing a semiconductor device is shown;

[0033] Figures 25-31 yes Figure 7 The structure diagrams corresponding to the relevant steps of the manufacturing method of the semiconductor device are shown. DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] In order to increase the breakdown voltage of semiconductor devices and enhance device performance, the embodiments of the present invention provide the following technical solutions:

[0037] like Figure 2 As shown, Figure 2 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 500, comprising a first surface 501 and a second surface 502 arranged opposite to each other; the semiconductor body 500 further comprising a well region 503 and a first region 504, the first region 504 being set to a first conductivity type and being located on the first surface 501, the well region 503 being set to a second conductivity type and being located on a side of the first region 504 away from the first surface 501; a gate trench T2 being provided on the first surface 501, the gate trench T2 extending from the first surface 501 into the semiconductor body 500; the gate trench T2 comprising a first gate trench T20 and a second gate trench T21 being connected, the second gate trench T21 being located on a side of the first gate trench T20 away from the first surface 501, the first gate trench T20 being located on the first surface 501, A vertical projection of a surface 501 covers a vertical projection of the second gate trench T21 on the first surface 501; the first gate trench T20 extends from the first surface 501 to the first region 504 and the well region 503, and the second gate trench T21 is located on a side of the well region 503 away from the first region 504; the semiconductor body 500 also includes a first insulating layer 505 and a second insulating layer 506, the first insulating layer 505 is located on the sidewall of the first gate trench T20, and the second insulating layer 506 fills the second gate trench T21, and the thickness of the second insulating layer 506 is greater than or equal to the thickness of the first insulating layer 505; a trench gate 600 is located in the first gate trench T20 on a side of the first insulating layer 505 away from the semiconductor body 500; a source 700 is located on the first surface 501; and a drain 800 is located on the second surface 502.

[0038] In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 500 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0039] For example, for an N-type MOSFET, the first region 504 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 503 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions. The ion doping process includes ion implantation, ion diffusion, or vapor deposition.

[0040] like Figure 2 As shown, the semiconductor body 500 includes a substrate 50 and a semiconductor epitaxial layer 51. In other optional embodiments, the semiconductor body 500 may also include only the semiconductor epitaxial layer 51. The semiconductor epitaxial layer 51 may be an epitaxial layer formed by an epitaxial process or a semiconductor layer formed by other processes. Among them, epitaxial processes include chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0041] like Figure 2 In the illustrated semiconductor device, using an N-type MOSFET as an example, a positive voltage is applied to the trench gate 600. When the threshold voltage is reached, an inversion layer forms on the side of the well region 503 near the first insulating layer 505. The electrons then move in the following direction: source 700 - first region 504 - well region 503 - semiconductor epitaxial layer 51 - substrate 50 - drain 800. Therefore, the thinner the thickness of the first insulating layer 505 between the first region 504 and the sidewalls of the first gate trench T20, and between the well region 503 and the sidewalls of the first gate trench T20, the lower the on-resistance (Rdson) and threshold voltage (Vth) of the device. Since the second gate trench T21 is located on the side of the first gate trench T20 away from the first surface 501, the thicker the second insulating layer 506 on the bottom and sidewalls of the second gate trench T21, the better the withstand voltage performance of the semiconductor device.

[0042] like Figure 1As shown, for trench-type SiC or GaN MOSFETs, in order to avoid excessive on-resistance (Rdson) and threshold voltage (Vth) of the device, the thickness of the insulating layer 106 on the sidewall of the gate trench T1 is relatively thin. In actual devices, during the process of simultaneously forming a gate oxide layer at the bottom and sidewall of the gate trench T1 through a thermal oxidation process, for example, in a silicon carbide semiconductor body, the anisotropy of the silicon carbide lattice parameter causes the thickness of the insulating layer 106 on the sidewall and bottom of the gate trench T1 to be inconsistent. Specifically, the thickness of the insulating layer 106 at the bottom of the gate trench T1 is thinner than the thickness of the insulating layer 106 on the sidewall of the gate trench T1, and the electric field strength of the insulating layer at the bottom of the gate trench T1 is relatively high, resulting in a relatively low breakdown voltage (BV) of the semiconductor device, which in turn affects the performance of the device.

[0043] In the technical solution provided by the embodiment of the present invention, the gate trench T2 includes a first gate trench T20 and a second gate trench T21 that are connected. The first insulating layer 505 is located on the sidewalls of the first gate trench T20, and the second insulating layer 506 fills the second gate trench T21. The thickness of the second insulating layer 506 is greater than or equal to the thickness of the first insulating layer 505. The above technical solution, on the one hand, ensures that the thickness of the first insulating layer 505 between the first region 504 and the sidewalls of the first gate trench T20 and between the well region 503 and the sidewalls of the first gate trench T20 is not too thick, which can prevent the on-resistance (Rdson) and threshold voltage (Vth) of the device from being too large. On the other hand, the above technical solution, the second insulating layer 506 fills the second gate trench T21, increases the thickness of the second insulating layer 506 on the bottom surface and sidewalls of the second gate trench T21, and improves the withstand voltage capability of the insulating layer at the bottom of the gate trench T2, thereby increasing the breakdown voltage of the semiconductor device and improving the device performance. The vertical projection of the first gate trench T20 on the first surface 501 covers the vertical projection of the second gate trench T21 on the first surface 501, which is equivalent to reducing the area of ​​the semiconductor body 500 occupied by the second gate trench T21 in the extension direction of the second gate trench T21, thereby reducing the gate capacitance, thereby improving the switching speed of the device and reducing the switching loss.

[0044] Optionally, the first insulating layer 505 and the second insulating layer 506 are gate oxide layers, which can be formed by a gate oxide process. In the drawings of the embodiment of the present invention, a schematic diagram of a structure in which the thickness of the second insulating layer 506 is greater than that of the first insulating layer 505 is exemplarily shown.

[0045] Optionally, based on the above technical solution, Figure 2As shown, the semiconductor body 500 further includes a second region 507 ; the second region 507 is configured to be of the second conductivity type and is located on a side of the second insulating layer 506 in the second gate trench T21 away from the trench gate 600 .

[0046] Specifically, the second conductivity type second region 507 and the first conductivity type drift region can form a depletion layer, which is used to improve the electric field distribution at the bottom of the gate trench T2, further improving the withstand voltage of the insulating layer at the bottom of the gate trench T2, thereby further increasing the breakdown voltage of the semiconductor device and improving device performance. For example, for an N-type MOSFET, the second region 507 is a P+ doped region.

[0047] Optionally, along the direction from the first surface 501 to the second surface 502 , the distance between the two trench walls of the second gate trench T21 becomes narrower, and the shape of the second gate trench T21 includes a V-shape or a trapezoidal shape.

[0048] Specifically, the V-shaped or trapezoidal grooves point from the first surface 501 toward the second surface 502, and the spacing between the two groove walls of the second gate trench T21 is narrowed, reducing the area occupied by the semiconductor body 500. This can reduce gate capacitance, thereby improving device switching speed and reducing switching losses. Furthermore, the V-shaped or trapezoidal grooves allow the second gate trench T21 to point from the first surface 501 toward the second surface 502. The narrow spacing between the two groove walls also widens the path for electrons to flow, thereby reducing the on-resistance of the device.

[0049] Optionally, based on the above technical solution, Figure 2 As shown, the semiconductor body 500 further includes a third region 508 . The third region 508 is set to the second conductivity type. The ion concentration of the third region 508 is greater than the ion concentration of the well region 503 . The third region 508 is connected to the first region 504 .

[0050] Specifically, the ion concentration of the third region 508 is greater than the ion concentration of the well region 503. The third region 508 is provided to form a better ohmic contact between the source 700 and the semiconductor body 500. For example, for an N-type MOSFET, the third region 508 is a P+ doped region.

[0051] It should be noted that, in addition to the single trench MOSFET, the embodiment of the present invention also includes a double trench MOSFET. Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention, Figure 4 is a structural diagram of another semiconductor device provided by an embodiment of the present invention, Figure 5 is a structural diagram of another semiconductor device provided by an embodiment of the present invention, Figure 6This is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. Figure 3-Figure 6 Schematic diagrams of the structures of four types of dual trench MOSFETs are shown.

[0052] Optionally, based on the above technical solution, Figure 3-Figure 6 As shown, the semiconductor body 500 is also provided with a source trench T3; the source trench T3 extends from the first surface 501 into the semiconductor body 500; the semiconductor device also includes a source trench structure; the source trench structure includes a filling layer 701; the filling layer 701 and the second insulating layer 506 are located in the same layer and have the same material and are prepared by the same process.

[0053] For example, when the second insulating layer 506 is silicon oxide, the filling layer 701 is also silicon oxide. In other optional embodiments, the filling layer 701 and the second insulating layer 506 may also include materials such as gallium nitride and polysilicon.

[0054] Specifically, the filling layer 701 is prepared while the second insulating layer 506 is prepared, which simplifies the preparation process and reduces the preparation cost.

[0055] The embodiments of the present invention introduce four types of dual-trench MOSFET structures, among which the setting of the source trench T3 and the source trench structure helps to improve the electric field distribution at the bottom of the gate trench T2, further improve the voltage resistance of the insulating layer at the bottom of the gate trench T2, thereby further improving the breakdown voltage of the semiconductor device and enhancing the device performance.

[0056] Optionally, based on the above technical solution, Figure 3-Figure 6 As shown, the semiconductor body 500 further includes a fourth region 509 . The fourth region 509 is configured to be of the second conductivity type and is located on the bottom surface and sidewalls of the source trench T3 .

[0057] Specifically, the fourth region 509 of the second conductivity type and the drift region of the first conductivity type can form a depletion layer, which is used to improve the electric field distribution at the bottom of the gate trench T2, further improving the withstand voltage of the insulating layer at the bottom of the gate trench T2, thereby further increasing the breakdown voltage of the semiconductor device and improving device performance. For example, for an N-type MOSFET, the fourth region 509 is a P+ doped region.

[0058] exist Figure 3-Figure 6 In the double-trench MOSFET structure shown, the specific position of the source trench T3 in the semiconductor body 500 is further described below.

[0059] like Figure 5 and Figure 6 As shown, the third region 508 and the fourth region 509 are connected, and the source trench T3 passes through the third region 508. Figure 3 and Figure 4 As shown, the source trench T3 penetrates the first region 504 and the well region 503 .

[0060] The specific shape setting of the source trench T3 is further described below.

[0061] Optionally, based on the above technical solution, the shape of the source trench T3 includes V-shape, trapezoidal shape or U-shape. Figure 3-Figure 6 The source trench T3 is shown to be V-shaped.

[0062] Specifically, the V-shaped groove or the trapezoidal groove reduces the area of ​​the semiconductor body 500 occupied compared to the U-shaped groove, thereby reducing the on-resistance of the semiconductor device.

[0063] For dual trench MOSFET devices, such as Figure 3 and Figure 6 As shown, the semiconductor body 500 further includes a fifth region 510 ; the fifth region 510 is configured to be of the second conductivity type and is located on the bottom surface and sidewalls of the second gate trench T21 .

[0064] The fifth region 510 of the second conductivity type and the drift region of the first conductivity type can form a depletion layer, which is used to improve the electric field distribution at the bottom of the gate trench T2, further improving the withstand voltage capability of the insulating layer at the bottom of the gate trench T2, thereby further increasing the breakdown voltage of the semiconductor device and improving device performance. For example, for an N-type MOSFET, the fifth region 510 is a P+ doped region.

[0065] It should be noted that if Figure 4 and Figure 5 As shown, the bottom surface and sidewall of the second gate trench T21 can also achieve high voltage resistance only through the second insulating layer 506 .

[0066] like Figure 7 and Figure 8 As shown, Figure 7 is a structural diagram of another semiconductor device provided by an embodiment of the present invention, Figure 8 This is a structural schematic diagram of another semiconductor device provided by an embodiment of the present invention, wherein the semiconductor body includes a plurality of gate trenches T2; the plurality of gate trenches T2 are all located on the first surface 501 and spaced apart; a second region 507 is provided on the bottom surface and sidewall of a second gate trench T21 of at least one of the plurality of gate trenches T2.

[0067] Specifically, a semiconductor device with multiple gate trenches T2 can further enhance the gate control capability of the trench gate 600, thereby improving the performance of the semiconductor device. Furthermore, a second region 507 is provided on the bottom surface and sidewalls of at least one second gate trench T21 of the multiple gate trenches T2. The second region 507 of the second conductivity type and the drift region of the first conductivity type can form a depletion layer, which is used to improve the electric field distribution at the bottom of the gate trench T2, further enhancing the withstand voltage capability of the insulating layer at the bottom of the gate trench T2, and thereby further improving the breakdown voltage of the semiconductor device.

[0068] Optionally, based on the above technical solution, the semiconductor body 500 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0069] The semiconductor body 500 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 500 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0070] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0071] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 9 As shown, Figure 9 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, the method for manufacturing a semiconductor device comprising the following steps:

[0072] S110. Provide a semiconductor body, including a first surface and a second surface arranged opposite to each other; the semiconductor body also includes a well region and a first area, the first area is set to a first conductive type and is located on the first surface, and the well region is set to a second conductive type and is located on a side of the first area away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; the gate trench includes a first gate trench and a second gate trench that are connected, and the second gate trench is located on a side of the first gate trench away from the first surface; the first gate trench extends from the first surface to the first area and the well region, and the second gate trench is located on a side of the well region away from the first area, and the vertical projection of the first gate trench on the first surface covers the vertical projection of the second gate trench on the first surface; the semiconductor body also includes a first insulating layer and a second insulating layer, the first insulating layer is located on the sidewall of the first gate trench, the second insulating layer fills the second gate trench, and the thickness of the second insulating layer is greater than the thickness of the first insulating layer.

[0073] like Figure 16The semiconductor body 500 is provided, and the semiconductor body 500 includes a first surface 501 and a second surface 502 arranged opposite to each other; the semiconductor body 500 also includes a well region 503 and a first region 504, the first region 504 is set to a first conductivity type and is located on the first surface 501, and the well region 503 is set to a second conductivity type and is located on a side of the first region 504 away from the first surface 501; the first surface 501 is provided with a gate trench T2, and the gate trench T2 extends from the first surface 501 into the semiconductor body 500; the gate trench T2 includes a first gate trench T20 and a second gate trench T21 connected to each other, and the second gate trench T21 is located in the first gate trench. T20 is located on a side away from the first surface 501, and the vertical projection of the first gate trench T20 on the first surface 501 covers the vertical projection of the second gate trench T21 on the first surface 501; the first gate trench T20 extends from the first surface 501 to the first region 504 and the well region 503, and the second gate trench T21 is located on a side of the well region 503 away from the first region 504; the semiconductor body 500 also includes a first insulating layer 505 and a second insulating layer 506, the first insulating layer 505 is located on the sidewall of the first gate trench T20, and the second insulating layer 506 fills the second gate trench T21, and the thickness of the second insulating layer 506 is greater than or equal to the thickness of the first insulating layer 505.

[0074] Alternatively, as Figure 10 As shown, Figure 10 yes Figure 9 The process diagram of S110 includes: S110 provides a semiconductor body including:

[0075] S1101 , forming a transition gate trench on the first surface, wherein the transition gate trench extends from the first surface into the semiconductor body.

[0076] like Figure 11 As shown, a substrate 50 and a semiconductor epitaxial layer 51 are provided. The semiconductor epitaxial layer 51 is formed on the surface of the substrate 50 by an epitaxial process. The substrate 50 and the semiconductor epitaxial layer 51 include third-generation wide bandgap semiconductor materials such as silicon carbide or gallium nitride semiconductor.

[0077] like Figure 12 As shown, a transition gate trench T23 is formed on the first surface 501 by an etching process, and the transition gate trench T23 extends from the first surface 501 into the semiconductor body 500 .

[0078] Optionally, before forming the transition gate trench on the first surface at S1101, the method further includes:

[0079] like Figure 13As shown, a first region 504 and a well region 503 are formed in the semiconductor body 500 . Alternatively, after forming the transition gate trench T23 on the first surface 501 , the process further includes forming the first region 504 and the well region 503 in the semiconductor body 500 .

[0080] S1102 , filling a second insulating layer in the transition gate trench.

[0081] like Figure 13 and Figure 14 As shown, before filling the transition gate trench T23 with the second insulating layer 506, a second region 507 is formed on the bottom surface and sidewalls of the second gate trench T21 through an ion doping process and a high-temperature annealing process. Specifically, the second region 507 of the second conductivity type and the drift region of the first conductivity type can form a depletion layer, which is used to improve the electric field distribution at the bottom of the gate trench T2, further improving the withstand voltage of the insulating layer at the bottom of the gate trench T2, thereby further increasing the breakdown voltage of the semiconductor device and enhancing device performance. For example, for an N-type MOSFET, the second region 507 is a P+ doped region.

[0082] like Figure 14 As shown, a sacrificial oxidation process and an oxide layer removal process are used to form a flat surface on the bottom surface and sidewalls of the transition gate trench T23. When the semiconductor body 500 is made of silicon carbide and the second insulating layer 506 is made of silicon oxide, the second insulating layer 506 is formed by a gate oxide process, and the second insulating layer 506 fills the transition gate trench T23.

[0083] S1103, forming a first gate trench on the first surface, the portion of the transition gate trench excluding the first gate trench is a second gate trench, and the first gate trench and the second gate trench are connected; the opening of the first gate trench is larger than or equal to the opening of the transition gate trench.

[0084] In the direction from the first surface to the second surface, the distance between the two groove walls of the second gate groove becomes narrower, and the shape of the second gate groove includes V-shape or trapezoidal shape.

[0085] like Figure 15 As shown, a first gate trench T20 is formed on the first surface 501 through a secondary trench etching process. The portion of the transition gate trench T23 excluding the first gate trench T20 forms a second gate trench T21, and the first gate trench T20 and the second gate trench T21 are connected. The distance between the two groove walls of the second gate trench T21 decreases along the direction from the first surface 501 to the second surface 502. The shape of the second gate trench T21 includes a V-shape or a trapezoidal shape.

[0086] Specifically, the V-shaped or trapezoidal grooves point from the first surface 501 toward the second surface 502, and the spacing between the two groove walls of the second gate trench T21 is narrowed, reducing the area occupied by the semiconductor body 500. This can reduce gate capacitance, thereby improving device switching speed and reducing switching losses. Furthermore, the V-shaped or trapezoidal grooves allow the second gate trench T21 to point from the first surface 501 toward the second surface 502. The narrow spacing between the two groove walls also widens the path for electrons to flow, thereby reducing the on-resistance of the device.

[0087] S1104 , forming a first insulating layer on the sidewall of the first gate trench, wherein the thickness of the second insulating layer is greater than or equal to the thickness of the first insulating layer.

[0088] like Figure 16 As shown, a flat surface is formed on the sidewall of the first gate trench T20 by a sacrificial oxidation process and an oxide layer removal process. When the semiconductor body 500 is silicon carbide and the first insulating layer 505 is silicon oxide, the first insulating layer 505 is formed by a gate oxide process.

[0089] Specifically, the first gate trench T20 and the second gate trench T21 are formed through two trench etching processes. When forming the first insulating layer 505 located in the first gate trench T20, the process parameters can be controlled to match the thickness of the first insulating layer 505 with the on-resistance and threshold voltage of the device, ensuring that the thickness of the first insulating layer 505 between the first region 504 and the sidewall of the first gate trench T20 and between the well region 503 and the sidewall of the first gate trench T20 is not too thick. Furthermore, the second insulating layer 506 fills the second gate trench T21, increasing the thickness of the second insulating layer 506 within the second gate trench T21 and improving the withstand voltage capability of the insulating layer at the bottom of the gate trench T2, thereby increasing the breakdown voltage of the semiconductor device and enhancing device performance.

[0090] S120 , forming a trench gate in the first gate trench on a side of the first insulating layer away from the semiconductor body.

[0091] like Figure 17 As shown, a trench gate 600 is formed in the first gate trench T20 on a side of the first insulating layer 505 away from the semiconductor body 500 through a deposition process. The trench gate 600 can be made of polysilicon.

[0092] S130 , forming a source electrode on the first surface.

[0093] like Figure 2 As shown, a source electrode 700 is formed on the first surface 501 by a metal deposition process. Figure 18As shown, before forming the source 700 , an interlayer insulating layer 601 is formed on the first surface to insulate the trench gate 600 from the source 700 .

[0094] S140 , forming a drain on the second surface.

[0095] like Figure 2 As shown, after the substrate 50 is thinned, a drain 800 may be formed on the second surface 502 by a metal deposition process.

[0096] In the technical solution provided by the embodiment of the present invention, the gate trench T2 includes a first gate trench T20 and a second gate trench T21 that are connected. The first insulating layer 505 is located on the sidewall of the first gate trench T20, and the second insulating layer 506 fills the second gate trench T21. The thickness of the second insulating layer 506 is greater than or equal to the thickness of the first insulating layer 505. The above technical solution, on the one hand, ensures that the thickness of the first insulating layer 505 between the first region 504 and the sidewall of the first gate trench T20 and between the well region 503 and the sidewall of the first gate trench T20 is not too thick, which can prevent the on-resistance (Rdson) and threshold voltage (Vth) of the device from being too large. On the other hand, the above technical solution, the second insulating layer 506 fills the second gate trench T21, increases the thickness of the second insulating layer 506 in the second gate trench T21, and improves the withstand voltage capability of the insulating layer at the bottom of the gate trench T2, thereby increasing the breakdown voltage of the semiconductor device and improving the device performance. The vertical projection of the first gate trench T20 on the first surface 501 covers the vertical projection of the second gate trench T21 on the first surface 501, reducing the area of ​​the semiconductor body 500 occupied by the second gate trench T21, which can reduce gate capacitance, thereby improving the switching speed of the device and reducing switching loss.

[0097] Optionally, for Figure 3 The double trench MOSFET semiconductor device shown in FIG. 1 includes the following steps:

[0098] like Figure 19 A substrate 50 and a semiconductor epitaxial layer 51 are provided. The semiconductor epitaxial layer 51 is formed on the surface of the substrate 50 through an epitaxial process. The substrate 50 and the semiconductor epitaxial layer 51 include third-generation wide-bandgap semiconductor materials such as silicon carbide or gallium nitride semiconductors. A transition gate trench T23 and a source trench T3 are formed on the surface of the semiconductor epitaxial layer 51 away from the substrate 50 through an etching process.

[0099] like Figure 20As shown, a fifth region 510 of the second conductivity type can be formed in the transition gate trench T23 in the semiconductor epitaxial layer 51 by a doping implantation process and a high-temperature annealing process. A fourth region 509 of the second conductivity type can be formed on the bottom surface and sidewalls of the source trench T3 by an ion doping and a high-temperature annealing process. Before or after forming the transition gate trench T23, a well region 503, a first region 504, and a third region 508 can be formed in the semiconductor epitaxial layer 51 by a doping implantation process and a high-temperature annealing process.

[0100] like Figure 21 As shown, a sacrificial oxidation process and an oxide layer removal process are used to form a flat surface on the bottom surface and sidewalls of the transition gate trench T23 and the source trench T3. A second insulating layer 506 is formed in the transition gate trench T23 by a gate oxide process, and a filling layer 701 is formed in the source trench T3.

[0101] like Figure 22 As shown, a first gate trench T20 is formed in the transition gate trench T23 on the first surface 501 through a secondary trench etching process, and a portion of the transition gate trench T23 excluding the first gate trench T20 is a second gate trench T21, and the first gate trench T20 and the second gate trench T21 are connected; the opening of the first gate trench T20 is greater than or equal to the opening of the transition gate trench T23.

[0102] like Figure 22 As shown, a flat surface is formed on the sidewall of the first gate trench T20 by a sacrificial oxidation process and an oxide layer removal process. When the semiconductor body 500 is silicon carbide and the first insulating layer 505 is silicon oxide, the first insulating layer 505 is formed by a gate oxide process.

[0103] like Figure 23 As shown, a trench gate 600 is formed in the first gate trench T20 on a side of the first insulating layer 505 away from the semiconductor body 500 through a deposition process. The trench gate 600 can be made of polysilicon.

[0104] like Figure 24 As shown, before forming the source 700 , an interlayer insulating layer 601 is formed on the first surface to insulate the trench gate 600 from the source 700 .

[0105] like Figure 3 As shown, a source electrode 700 is formed on the first surface 501 by a metal deposition process. After the substrate 50 is thinned, a drain electrode 800 may be formed on the second surface 502 by a metal deposition process.

[0106] It should be noted that Figure 4 The fabrication process of the dual trench MOSFET device is shown and Figures 19-24 The differences in the preparation processes provided are as follows:

[0107] like Figure 4 As shown, there is no need to form the fifth region 510 of the second conductivity type in the semiconductor epitaxial layer 51 within the transition gate trench T23 through a doping implantation process and a high-temperature annealing process.

[0108] It should be noted that Figure 5 The fabrication process of the dual trench MOSFET device is shown and Figures 18-23 The differences in the preparation processes provided are as follows:

[0109] like Figure 5 As shown, there is no need to form the fifth region 510 of the second conductivity type in the semiconductor epitaxial layer 51 within the transition gate trench T23 through a doping implantation process and a high-temperature annealing process.

[0110] When the transition gate trench T23 and the source trench T3 are formed on the surface of the semiconductor epitaxial layer 51 away from the substrate 50 through an etching process, the source trench T3 penetrates the third region 508 .

[0111] It should be noted that Figure 6 The fabrication process of the dual trench MOSFET device is shown and Figures 18-23 The differences in the preparation processes provided are as follows:

[0112] like Figure 6 As shown, when the transition gate trench T23 and the source trench T3 are formed on the surface of the semiconductor epitaxial layer 51 away from the substrate 50 by an etching process, the source trench T3 penetrates the third region 508 .

[0113] Optionally, for Figure 7 The manufacturing method of the semiconductor device having multiple gate trenches T2 shown includes the following steps:

[0114] like Figure 25 As shown, a substrate 50 and a semiconductor epitaxial layer 51 are provided. The semiconductor epitaxial layer 51 is formed on the surface of the substrate 50 through an epitaxial process. The substrate 50 and the semiconductor epitaxial layer 51 include third-generation wide-bandgap semiconductor materials such as silicon carbide or gallium nitride semiconductors. A plurality of transition gate trenches T23 are formed on the first surface 501 through an etching process. The transition gate trenches T23 extend from the first surface 501 into the semiconductor body 500 and are spaced apart on the first surface 501.

[0115] like Figure 26 As shown, a first region 504 and a well region 503 are formed in the semiconductor body 500 . Alternatively, after forming the transition gate trench T23 on the first surface 501 , the process further includes forming the first region 504 and the well region 503 in the semiconductor body 500 .

[0116] like Figure 26As shown, before filling the transition gate trench T23 with the second insulating layer 506, a second region 507 is formed on a sidewall of the second insulating layer 506 in the second gate trench T21 away from the trench gate 600 through an ion doping process and a high-temperature annealing process. Specifically, the second region 507 of the second conductivity type and the drift region of the first conductivity type can form a depletion layer, which is used to improve the electric field distribution at the bottom of the gate trench T2, further improving the withstand voltage capability of the insulating layer at the bottom of the gate trench T2, thereby further increasing the breakdown voltage of the semiconductor device and enhancing device performance. For example, for an N-type MOSFET, the second region 507 is a P+ doped region.

[0117] like Figure 27 As shown, a sacrificial oxidation process and an oxide layer removal process are used to form a flat surface on the bottom surface and sidewalls of the transition gate trench T23. When the semiconductor body 500 is made of silicon carbide and the second insulating layer 506 is made of silicon oxide, the second insulating layer 506 is formed by a gate oxide process, and the second insulating layer 506 fills the transition gate trench T23.

[0118] like Figure 28 As shown, a first gate trench T20 is formed in the transition gate trench T23 on the first surface 501 through a secondary trench etching process, and a portion of the transition gate trench T23 excluding the first gate trench T20 is a second gate trench T21, and the first gate trench T20 and the second gate trench T21 are connected; the opening of the first gate trench T20 is greater than or equal to the opening of the transition gate trench T23.

[0119] like Figure 29 As shown, a flat surface is formed on the sidewall of the first gate trench T20 by a sacrificial oxidation process and an oxide layer removal process. When the semiconductor body 500 is silicon carbide and the first insulating layer 505 is silicon oxide, the first insulating layer 505 is formed by a gate oxide process.

[0120] Specifically, the first gate trench T20 and the second gate trench T21 are completed through two trench etching processes. When forming the first insulating layer 505 located in the first gate trench T20, the process parameters can be controlled to match the thickness of the first insulating layer 505 with the on-resistance and threshold voltage of the device, thereby ensuring that the thickness of the first insulating layer 505 between the first region 504 and the side wall of the first gate trench T20 and between the well region 503 and the side wall of the first gate trench T20 is not too thick.

[0121] like Figure 30 As shown, a source electrode 700 is formed on the first surface 501 by a metal deposition process. Figure 31 As shown, before forming the source 700 , an interlayer insulating layer 601 is formed on the first surface to insulate the trench gate 600 from the source 700 .

[0122] like Figure 7 As shown, a source electrode 700 is formed on the first surface 501 by a metal deposition process. After the substrate 50 is thinned, a drain electrode 800 may be formed on the second surface 502 by a metal deposition process.

[0123] It should be noted that Figure 8 The preparation process of the semiconductor device with multiple gate trenches T2 is shown Figures 25-31 The differences in the preparation processes provided are as follows:

[0124] like Figure 8 As shown, there is no need to form the fifth region 510 of the second conductivity type in the semiconductor epitaxial layer 51 within the transition gate trench T23 through a doping implantation process and a high-temperature annealing process.

[0125] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further elaborated herein.

[0126] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0127] Therefore, the power conversion circuit includes the beneficial effects of any semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0128] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0129] Therefore, the beneficial effects of the vehicle including any power conversion circuit package described in any embodiment of the present invention will not be repeated here.

[0130] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0131] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being set to a first conductivity type and located on the first surface, and the well region being set to a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; the gate trench comprising a first gate trench and a second gate trench being connected, the second gate trench being located on a side of the first gate trench away from the first surface; the first gate trench extending from the first surface into the first region and the well region, the second gate trench being located on a side of the well region away from the first region, the vertical projection of the first gate trench on the first surface covering the vertical projection of the second gate trench on the first surface; the semiconductor body further comprising a first insulating layer and a second insulating layer, the first insulating layer being located on a sidewall of the first gate trench, the second insulating layer filling the second gate trench, the thickness of the second insulating layer being greater than or equal to the thickness of the first insulating layer; a trench gate located in the first gate trench on a side of the first insulating layer away from the semiconductor body; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The semiconductor body further includes a second region; the second region is configured as a second conductivity type and is located in the second gate trench on a side of the second insulating layer away from the trench gate.

3. The semiconductor device according to claim 1, wherein Along the direction from the first surface to the second surface, the distance between the two groove walls of the second gate groove becomes narrower, and the shape of the second gate groove includes V-shape or trapezoidal shape.

4. The semiconductor device according to claim 1, wherein The semiconductor body further includes a third region, which is set to be of the second conductivity type and has an ion concentration greater than that of the well region; and the third region is connected to the first region.

5. The semiconductor device according to claim 4, wherein The semiconductor body is further provided with a source trench; the source trench extends from the first surface into the semiconductor body; The semiconductor device further includes a source trench structure; the source trench structure includes a filling layer; the filling layer and the second insulating layer are located in the same layer.

6. The semiconductor device according to claim 5, wherein The semiconductor body further includes a fourth region, which is configured as a second conductivity type and is located on a bottom surface and sidewalls of the source trench; And / or, the semiconductor body further includes a fifth region; the fifth region is set to the second conductivity type and is located on the bottom surface and sidewalls of the second gate trench.

7. The semiconductor device according to claim 6, wherein: The third region is connected to the fourth region, the source trench passes through the third region and / or, The source trench penetrates the first region and the well region.

8. The semiconductor device according to claim 2, wherein: The semiconductor body includes a plurality of gate trenches; the plurality of gate trenches are located on the first surface and spaced apart; The second region is provided on a bottom surface and sidewalls of at least one second gate trench among the plurality of gate trenches.

9. The semiconductor device according to claim 1, wherein The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

10. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, and the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; the gate trench comprising a first gate trench and a second gate trench being connected, the second gate trench being located on a side of the first gate trench away from the first surface; a vertical projection of the first gate trench on the first surface overlapping a vertical projection of the second gate trench on the first surface; the semiconductor body further comprising a first insulating layer and a second insulating layer, the first insulating layer being located on a sidewall of the first gate trench, the second insulating layer filling the second gate trench, the thickness of the second insulating layer being greater than the thickness of the first insulating layer; forming a trench gate on a side of the first insulating layer away from the semiconductor body in the first gate trench; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The semiconductor body provided includes: forming a transition gate trench on the first surface, wherein the transition gate trench extends from the first surface into the semiconductor body; Filling a second insulating layer in the transition gate trench; forming a first gate trench on the first surface, wherein a portion of the transition gate trench excluding the first gate trench is a second gate trench, and the first gate trench and the second gate trench are connected; Along the direction from the first surface to the second surface, the distance between the two groove walls of the second gate groove becomes narrower, and the shape of the second gate groove includes V-shape or trapezoidal shape.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: Before forming the transition gate trench on the first surface, the method further includes: forming a first region and a well region in the semiconductor body; Alternatively, after forming the transition gate trench on the first surface, the method further includes: A first region and a well region are formed in the semiconductor body.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: Before filling the second insulating layer in the transition gate trench, the method further includes: A second region is formed on the bottom surface and sidewalls of the transition gate trench, and the second region is set to be of a second conductivity type.

14. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 9, wherein the substrate is used to support the semiconductor device.

15. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is electrically connected to the circuit board.

16. A vehicle, characterized in that: It includes a load and the power conversion circuit as claimed in claim 15, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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