Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device comprises a semiconductor body, wherein the semiconductor body further comprises a well region and a first region; the first surface is also provided with a gate trench, and the gate trench extends into the semiconductor body from the first surface; the two-dimensional material layer is arranged to be of the first conduction type and is located on the side wall of the gate trench; the carrier mobility of the two-dimensional material layer is greater than that of silicon carbide; the trench gate is located on the side, away from the semiconductor body, of the first insulating layer in the gate trench; the source electrode is located on the first surface; the drain electrode is located on the second surface. According to the technical scheme of the embodiment of the invention, the on-resistance of the semiconductor device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in power electronics, automobiles, aerospace and other fields due to their excellent high-temperature performance, chemical stability and electronic properties.

[0003] In the prior art, a positive voltage is applied to the gate of a SiC or GaN metal-oxide-semiconductor field-effect transistor (MOSFET). When the threshold voltage is reached, an inversion layer is formed in the well region. The direction of electron movement is from the first region formed by ion implantation of the metal conductive layer to the inversion layer in the well region, and then through the semiconductor body to reach the drain.

[0004] However, in the prior art, ion implantation to form the first region causes lattice damage to the semiconductor body, resulting in an increase in interface states, reduced electron mobility in the channel region, and excessively large on-resistance of the SiC or GaN MOSFET. Summary of the Invention

[0005] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, so as to reduce the on-resistance of the semiconductor device.

[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0007] A semiconductor body comprising a first surface and a second surface disposed opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, the well region being of a second conductivity type and located on a side of the first region away from the first surface; a gate trench being further disposed on the first surface, the gate trench extending from the first surface into the semiconductor body; and a first insulating layer being disposed on sidewalls of the gate trench.

[0008] a two-dimensional material layer, the two-dimensional material layer being of a first conductivity type and being located on a sidewall of the gate trench; the two-dimensional material layer being located between the first region and the first insulating layer, and the two-dimensional material layer being located between the well region and the first insulating layer; and the carrier mobility of the two-dimensional material layer being greater than the carrier mobility of silicon carbide;

[0009] a trench gate, the trench gate being located in the gate trench on a side of the first insulating layer away from the semiconductor body;

[0010] a source electrode, located on the first surface;

[0011] The drain is located on the second surface.

[0012] According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising:

[0013] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured as a first conductivity type and located on the first surface, the well region being configured as a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; a two-dimensional material layer being formed on a sidewall of the gate trench, the two-dimensional material layer being configured as the first conductivity type, the carrier mobility of the two-dimensional material layer being greater than the carrier mobility of silicon carbide;

[0014] forming a first insulating layer on a sidewall of the gate trench, wherein the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer;

[0015] forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench;

[0016] forming a source electrode on the first surface;

[0017] A drain electrode is formed on the second surface.

[0018] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used to support the semiconductor device.

[0019] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0020] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0021] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0022] In the semiconductor device and manufacturing method, power module, power conversion circuit and vehicle of the embodiment of the present invention, the trench gate extends from the first surface into the semiconductor body, and there is no need to set a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device. A two-dimensional material layer with a carrier mobility greater than that of silicon carbide is located on the sidewall of the gate trench. The two-dimensional material layer serves as the channel of the semiconductor device, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. The well region forms a PN junction contact with the two-dimensional material layer, generating a depletion region at the channel, thereby reducing the off-state leakage current of the semiconductor device. Among them, since the carrier mobility of the two-dimensional material layer is greater than that of silicon carbide, the carrier mobility of the semiconductor device channel can be effectively improved, and the effects of lattice damage to the semiconductor body, increase in interface states and reduction in carrier mobility in the channel region caused by the ion doping process when the first region is formed can be ignored. Furthermore, there is no need to limit the thickness of the first insulating layer to be not too thick in order to reduce the on-resistance, thereby increasing the threshold voltage of the semiconductor device and improving the control performance of the semiconductor device.

[0023] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0025] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0026] Figure 2 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0027] Figure 3 is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention;

[0028] Figure 4 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0029] Figure 5-Figure 8 yes Figure 4Schematic diagram of the structure corresponding to each step;

[0030] Figure 9 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0031] Figure 10-13 yes Figure 9 Schematic diagram of the structure corresponding to each step;

[0032] Figure 14 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0033] Figures 15-19 yes Figure 14 Schematic diagram of the structure corresponding to each step in . DETAILED DESCRIPTION

[0034] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0036] In order to reduce the on-resistance of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0037] like Figure 1 As shown, Figure 11 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention, the semiconductor device comprising: a semiconductor body 100, comprising a first surface 101 and a second surface 102 arranged opposite to each other, the semiconductor body 100 further comprising a well region 103 and a first region 104, the first region 104 being configured as a first conductivity type and being located on the first surface 101, the well region 103 being configured as a second conductivity type and being located on a side of the first region 104 away from the first surface 101; the first surface 101 further comprising a gate trench T1, the gate trench T1 extending from the first surface 101 into the semiconductor body 100; the semiconductor body 100 further comprising a first insulating layer 301, the first insulating layer 302 and the second insulating layer 304. An insulating layer 301 is located on the side wall of the gate trench T1; a two-dimensional material layer 200, the two-dimensional material layer 200 is set to a first conductive type and is located on the side wall of the gate trench T1; the two-dimensional material layer 200 is located between the first region 104 and the first insulating layer 301, and the two-dimensional material layer 200 is located between the well region 103 and the first insulating layer 301; the carrier mobility of the two-dimensional material layer 200 is greater than the carrier mobility of silicon carbide; a trench gate 302, the trench gate 302 is located on the side of the first insulating layer 301 in the gate trench T1 away from the semiconductor body 100; a source 404, located on the first surface 101; and a drain 500, located on the second surface 102.

[0038] In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. Semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material, such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0039] For example, for an N-type MOSFET, first region 104 is an N+ doped region, where the N-type dopant ions may be phosphorus (P) or nitrogen (N). Well region 103 is a P-well region, where the P-type dopant ions may be aluminum (Al) or boron (B). Two-dimensional material layer 200 is an N-type channel layer, and the carrier mobility of two-dimensional material layer 200 is greater than that of silicon carbide, thereby improving the electron mobility of the semiconductor device.

[0040] like Figure 1As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0041] Optionally, an interlayer insulating layer 303 is used to insulate the gate and source.

[0042] In an embodiment of the present invention, the two-dimensional material layer 200 includes a semiconductor layer and may also include a non-semiconductor layer. In crystallography, the two-dimensional material layer 200 refers to a material with a thickness of only a single atomic layer or two atomic layers, and its thickness is on the order of a few nanometers. The two-dimensional material layer 200 has a high carrier mobility. The carrier mobility of the two-dimensional material layer 200 is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. In addition, the well region 103 and the two-dimensional material layer 200 have different conductivity types, and can form a PN junction contact, generate a depletion region at the channel, and reduce the off-state leakage current of the semiconductor device.

[0043] In the semiconductor device of the embodiment of the present invention, the trench gate 302 extends from the first surface 101 into the semiconductor body 100, eliminating the need for a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device. A two-dimensional material layer 200 having a carrier mobility greater than that of silicon carbide is located on the sidewalls of the gate trench T1. The two-dimensional material layer 200 serves as the channel of the semiconductor device, effectively improving the carrier mobility of the semiconductor device channel and reducing the on-resistance. The well region 103 forms a PN junction contact with the two-dimensional material layer 200, generating a depletion region at the channel, thereby reducing the off-state leakage current of the semiconductor device. Since the carrier mobility of the two-dimensional material layer 200 is greater than that of silicon carbide, the carrier mobility of the semiconductor device channel can be effectively improved, and the effects of lattice damage, increased interface states, and reduced carrier mobility in the channel region caused to the semiconductor body 100 by the ion doping process when forming the first region 104 can be ignored. Furthermore, there is no need to limit the thickness of the first insulating layer 301 to reduce the on-resistance, thereby increasing the threshold voltage of the semiconductor device and improving the control performance of the semiconductor device.

[0044] In other optional embodiments of the present invention, refer to Figure 1 , the carrier mobility of the two-dimensional material layer 200 in different directions is the same.

[0045] Optionally, based on the above technical solution, Figure 1 As shown, the two-dimensional material layer 200 includes a two-dimensional material semiconductor layer.

[0046] Specifically, in crystallography, a two-dimensional material semiconductor layer refers to a material that is only a single atomic layer or two atomic layers thick, with a thickness on the order of a few nanometers. Two-dimensional material semiconductor layers have high carrier mobility, and common two-dimensional material semiconductor layers include graphene and graphene derivatives. The carrier mobility of a two-dimensional material semiconductor layer is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the two-dimensional material layer 200, generating a depletion region in the channel, thereby reducing the off-state leakage current of the semiconductor device.

[0047] Optionally, based on the above technical solution, the gate trench T1 includes a V-shaped trench or a U-shaped trench.

[0048] like Figure 1 As shown, the gate trench T1 is a V-shaped trench. In other optional embodiments of the present invention, the gate trench T1 may also be a U-shaped trench. The first surface 101 is provided with a gate trench T1 including a V-shaped trench or a U-shaped trench, so that the trench gate T1 extends from the first surface 101 into the semiconductor body 100, eliminating the need to provide a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device.

[0049] Optionally, based on the above technical solution, Figure 2 As shown, Figure 2 This is a schematic diagram of the structure of another semiconductor device provided by an embodiment of the present invention. At least two spaced-apart gate trenches T1 are provided on one side of the source electrode 404. Two-dimensional material layers 200 are disposed in a one-to-one correspondence within the sidewalls of the gate trenches T1. Trench gates T1 are also disposed in a one-to-one correspondence within the gate trenches T1. This further reduces the area of ​​the semiconductor body 100, thereby further reducing the on-resistance of the semiconductor device. The greater the number of gate trenches T1, the greater the control capability of the trench gates T1 over the conductive channel.

[0050] Optionally, based on the above technical solution, Figure 3 As shown, Figure 3This is a structural schematic diagram of another semiconductor device provided by an embodiment of the present invention, wherein a source trench T2 is further provided on the first surface 101, and the source trench T2 extends from the first surface 101 into the semiconductor body; the semiconductor device also includes a source trench structure 400, and the source trench structure 400 includes a filling layer 402 and a second insulating layer 401; the second insulating layer 401 is located on the bottom surface and sidewall of the source trench T2; the filling layer 402 is located in the source trench T2 on a side away from the second insulating layer 401 and away from the semiconductor body 100.

[0051] Specifically, the provision of the source trench structure 400 can effectively reduce the peak electric field below the first insulating layer 301 of the trench-type trench gate 302 close to the second surface 102 , thereby improving the withstand voltage performance of the semiconductor device.

[0052] Optionally, the source trench T2 includes a V-shaped trench or a U-shaped trench. Compared with the U-shaped trench, the V-shaped trench reduces the occupied area of ​​the semiconductor body 100 and reduces the on-resistance of the semiconductor device.

[0053] Optionally, based on the above technical solution, Figure 3 As shown, the semiconductor body 100 also includes a second region 105, which is set to the second conductivity type and surrounds the bottom surface and side walls of the source trench T2, and the ion concentration of the second region 105 is greater than the ion concentration of the well region 103; the vertical distance d1 between the second region 105 and the second surface 102 is less than the vertical distance d2 between the gate trench T1 and the second surface 102.

[0054] Specifically, on the one hand, the second region 105 can form a good ohmic contact with the source 404; on the other hand, the vertical distance d1 between the second region 105 and the second surface 102 is smaller than the vertical distance d2 between the gate trench T1 and the second surface 102. The drift layer between the second region 105 and the second surface 102 forms a depletion layer, which can further reduce the peak electric field under the first insulating layer 301 of the trench-type gate trench T1 close to the second surface 102, thereby further improving the voltage resistance performance of the semiconductor device.

[0055] Optionally, based on the above technical solution, Figure 1-Figure 3 As shown, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0056] The semiconductor body 100 includes a silicon carbide semiconductor body, the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device, the semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0057] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0058] It should be noted that in the semiconductor device provided by an embodiment of the present invention, a two-dimensional material layer 200 having a carrier mobility greater than that of silicon carbide is located on the sidewalls of the gate trench T1. The two-dimensional material layer 200, serving as the channel of the semiconductor device, can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. When the gate trench T1 extends to the drift layer, the two-dimensional material layer 200 can be disposed only on the sidewalls of the gate trench T1 that contact the first region 104 and the well region 103, thereby achieving the effect of improving the carrier mobility within the channel and reducing the on-resistance of the semiconductor device.

[0059] The embodiment of the present invention also provides a method for manufacturing a semiconductor device. Figure 4 As shown, Figure 4 1 is a flow chart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention, the manufacturing method comprising the following steps:

[0060] S110. Provide a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body also including a well region and a first region, the first region is set to a first conductive type and is located on the first surface, the well region is set to a second conductive type and is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body.

[0061] like Figure 5As shown, a semiconductor body 100 is provided. The semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite each other. A well region 103 and a first region 104 are formed in the semiconductor body 100 through ion doping and high-temperature annealing processes. The first region 104 is configured as a first conductivity type and is located on the first surface 101, while the well region 103 is configured as a second conductivity type and is located on a side of the first region 104 away from the first surface 101. Optionally, a second region 105 is formed in the semiconductor body 100. The second region 105 is configured as the second conductivity type and is located on the first surface 101. The ion concentration of the second region 105 is greater than that of the well region 103. The second region 105 can form a good ohmic contact with the source 404. In embodiments of the present invention, semiconductor devices include, but are not limited to, N-type MOSFETs or P-type MOSFETs. The semiconductor body 100 may be made of a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type, and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type, and the second conductivity type is N-type.

[0062] Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region can be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region and in the second region 105 can be aluminum (Al) ions or boron (B) ions.

[0063] like Figure 5 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through a single epitaxial process, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0064] Optionally, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0065] The semiconductor body 100 includes a silicon carbide semiconductor body, the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device, the semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0066] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0067] It should be noted that in the semiconductor device provided by an embodiment of the present invention, a two-dimensional material layer 200 having a carrier mobility greater than that of silicon carbide is located on the sidewalls of the gate trench T1. The two-dimensional material layer 200, serving as the channel of the semiconductor device, can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. When the gate trench T1 extends to the drift layer, the two-dimensional material layer 200 can be disposed only on the sidewalls of the gate trench T1 that contact the first region 104 and the well region 103, thereby achieving the effect of improving the carrier mobility within the channel and reducing the on-resistance of the semiconductor device.

[0068] like Figure 6 As shown, a gate trench T1 is formed on the first surface 101 by a trench etching process, a sacrificial oxide layer preparation process, and an oxide layer removal process. The gate trench T1 extends from the first surface into the semiconductor body 100 .

[0069] In other optional embodiments provided in the embodiment of the present invention, the gate trench T1 may be formed before forming the well region 103 and the first region 104 .

[0070] S120 , forming a two-dimensional material layer on a sidewall of the gate trench, wherein the two-dimensional material layer is set to a first conductive type, and the carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide.

[0071] like Figure 7 As shown, a two-dimensional material layer 200 is formed on the sidewall of the gate trench T1 through a deposition process. The two-dimensional material layer 200 is set to a first conductivity type, and the carrier mobility of the two-dimensional material layer 200 is greater than the carrier mobility of silicon carbide.

[0072] For example, for an N-type MOSFET, the two-dimensional material layer 200 is an N-type channel layer, and the carrier mobility of the two-dimensional material layer 200 is greater than that of silicon carbide, thereby improving the electron mobility of the semiconductor device.

[0073] S130 , forming a first insulating layer on the sidewall of the gate trench, the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer.

[0074] like Figure 8 As shown, a first insulating layer 301 is formed in the gate trench T1 by oxidation or deposition process.

[0075] S140 , forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench.

[0076] like Figure 8 As shown, a trench gate 302 is formed in the gate trench T1 by a deposition process. A first insulating layer 301 is located on the sidewalls and bottom of the gate trench T1 and covers the two-dimensional material layer 200. The trench gate 302 is located on the side of the first insulating layer 301 in the gate trench T1 away from the semiconductor body 100.

[0077] The first insulating layer 301 may include a high-k dielectric layer such as silicon dioxide, HfO, or ZrO 2 . The trench gate 302 may be made of polysilicon.

[0078] S150 , forming a source electrode on the first surface.

[0079] like Figure 1 As shown, a source 404 is formed on the first surface 101 .

[0080] Optionally, before forming the source 404 , an interlayer insulating layer 303 is further formed. The interlayer insulating layer 303 is provided with a contact hole for placing the source 404 . The interlayer insulating layer 303 is used to insulate the trench gate 302 from the source 404 .

[0081] S160 , forming a drain on the second surface.

[0082] like Figure 1 As shown, a drain electrode 500 is formed on the second surface 102 by a back metal conductive layer deposition process. The drain electrode 500 may include a metal stack material composed of Ti, Ni, and Ag. Optionally, before forming the drain electrode 500, the second surface 102 may be thinned to reduce the on-resistance of the semiconductor device.

[0083] In an embodiment of the present invention, the two-dimensional material layer 200 includes a semiconductor layer and may also include a non-semiconductor layer. In crystallography, the two-dimensional material layer 200 refers to a material with a thickness of only a single atomic layer or two atomic layers, and its thickness is on the order of a few nanometers. The two-dimensional material layer 200 has a high carrier mobility. The carrier mobility of the two-dimensional material layer 200 is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. In addition, the well region 103 and the two-dimensional material layer 200 have different conductivity types, and can form a PN junction contact, generate a depletion region at the channel, and reduce the off-state leakage current of the semiconductor device.

[0084] In the semiconductor device manufactured by the embodiment of the present invention, the trench gate 302 extends from the first surface 101 into the semiconductor body 100, eliminating the need for a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device. A two-dimensional material layer 200 having a carrier mobility greater than that of silicon carbide is located on the sidewalls of the gate trench T1. The two-dimensional material layer 200 serves as the channel of the semiconductor device, effectively improving the carrier mobility of the semiconductor device channel and reducing the on-resistance. The well region 103 forms a PN junction contact with the two-dimensional material layer 200, generating a depletion region at the channel, thereby reducing the off-state leakage current of the semiconductor device. Since the carrier mobility of the two-dimensional material layer 200 is greater than that of silicon carbide, the carrier mobility of the semiconductor device channel can be effectively improved, and the effects of lattice damage, increased interface states, and reduced carrier mobility in the channel region on the semiconductor body 100 caused by ion doping to form the first region 104 can be ignored. Furthermore, there is no need to limit the thickness of the first insulating layer 301 to reduce the on-resistance, thereby increasing the threshold voltage of the semiconductor device and improving the control performance of the semiconductor device.

[0085] In other optional embodiments of the present invention, refer to Figure 1 , the carrier mobility of the two-dimensional material layer 200 in different directions is the same.

[0086] Optionally, based on the above technical solution, S120 forming a two-dimensional material layer on the sidewall of the gate trench includes:

[0087] A two-dimensional material layer including a two-dimensional material semiconductor layer is formed on the sidewall of the gate trench.

[0088] like Figure 7 As shown, a two-dimensional material layer 200 including a two-dimensional material semiconductor layer is formed on the sidewall of the gate trench T1.

[0089] Specifically, in crystallography, a two-dimensional material semiconductor layer refers to a material that is only a single atomic layer or two atomic layers thick, with a thickness on the order of a few nanometers. Two-dimensional material semiconductor layers have high carrier mobility, and common two-dimensional material semiconductor layers include graphene and graphene derivatives. The carrier mobility of a two-dimensional material semiconductor layer is greater than that of silicon carbide, which can effectively improve the carrier mobility of the semiconductor device channel and reduce the on-resistance. Furthermore, the well region 103 forms a PN junction contact with the two-dimensional material layer 200, generating a depletion region in the channel, thereby reducing the off-state leakage current of the semiconductor device.

[0090] Optionally, based on the above technical solution, S120 forming a gate trench on the first surface includes:

[0091] A gate trench including a V-shaped trench or a U-shaped trench is formed on the first surface.

[0092] like Figure 6 As shown, a gate trench including a V-shaped trench or a U-shaped trench is formed on the first surface 101 .

[0093] like Figure 6 As shown, the gate trench T1 is a V-shaped trench. In other optional embodiments of the present invention, the gate trench T1 may also be a U-shaped trench. The first surface 101 is provided with a gate trench T1 including a V-shaped trench or a U-shaped trench, so that the trench gate 302 extends from the first surface 101 into the semiconductor body 100, eliminating the need to provide a junction field-effect transistor (JFET) region, thereby reducing the on-resistance of the semiconductor device.

[0094] like Figure 9 As shown, Figure 9 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, the method comprising the following steps:

[0095] S210. Provide a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other, the semiconductor body also including a well region and a first region, the first region is set to a first conductive type and is located on the first surface, the well region is set to a second conductive type and is located on a side of the first region away from the first surface; the first surface is provided with at least two spaced-apart gate trenches, and the gate trenches extend from the first surface into the semiconductor body.

[0096] like Figure 10 As shown, a semiconductor body 100 is provided, comprising a first surface 101 and a second surface 102 disposed opposite each other. A well region 103 and a first region 104 are formed in the semiconductor body 100 through ion doping and high-temperature annealing processes. The first region 104 is configured to be of the first conductivity type and is located on the first surface 101, while the well region 103 is configured to be of the second conductivity type and is located on a side of the first region 104 away from the first surface 101. Optionally, a second region 105 is further formed in the semiconductor body 100. The second region 105 is configured to be of the second conductivity type and is located on the first surface 101. The doping concentration of the second region 105 is greater than the doping concentration of the well region 103. The second region 105 can form a good ohmic contact with the source 404.

[0097] like Figure 11As shown, at least two spaced-apart gate trenches T1 are formed on the first surface 101 by trench etching, sacrificial oxide layer preparation, and oxide layer removal processes. The gate trenches T1 extend from the first surface into the semiconductor body 100 .

[0098] In other optional embodiments provided in the embodiment of the present invention, the gate trench T1 may be formed before forming the well region 103 and the first region 104 .

[0099] S220: Form a two-dimensional material layer on the sidewall of the gate trench, wherein the two-dimensional material layer is configured to be of the first conductivity type, and the carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide. The two-dimensional material layer is disposed in a one-to-one correspondence within the sidewall of the gate trench.

[0100] like Figure 12 As shown, a two-dimensional material layer 200 is formed on the sidewalls of the gate trench T1 through a deposition process. The two-dimensional material layer 200 is configured as a first conductivity type, and the carrier mobility of the two-dimensional material layer 200 is greater than the carrier mobility of silicon carbide. The two-dimensional material layer 200 is disposed in a one-to-one correspondence within the sidewalls of the gate trench T1.

[0101] S230 , forming a first insulating layer on the sidewall of the gate trench, the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer.

[0102] like Figure 13 As shown, a first insulating layer 301 is formed in the gate trench T1 by oxidation or deposition process.

[0103] S240 , forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench.

[0104] like Figure 13 As shown, a trench gate 302 is formed in the gate trench T1 through a deposition process. The first insulating layer 301 is located on the sidewalls and bottom surface of the gate trench T1 and covers the two-dimensional material layer 200. The trench gate 302 is located on the side of the first insulating layer 301 in the gate trench T1 away from the semiconductor body 100. Gates are arranged in a one-to-one correspondence in the gate trenches T1.

[0105] S250 , forming a source electrode on the first surface.

[0106] like Figure 2 As shown, a source 404 is formed on the first surface 101 .

[0107] Optionally, before forming the source, an interlayer insulating layer 303 is further formed. The interlayer insulating layer 303 is provided with a contact hole for placing the source 404 . The interlayer insulating layer 303 is used to insulate the trench gate 302 and the source 404 .

[0108] S260 , forming a drain on the second surface.

[0109] like Figure 2 As shown, a drain electrode 500 is formed on the second surface 102 by a back metal conductive layer deposition process. The drain electrode 500 may include a metal stack material composed of Ti, Ni, and Ag. Optionally, before forming the drain electrode 500, the second surface 102 may be thinned to reduce the on-resistance of the semiconductor device.

[0110] On the basis of the above technical solution, at least two spaced-apart gate trenches T1 are provided on one side of the source, two-dimensional material layers 200 are provided in correspondence with each other in the side walls of the gate trenches T1, and trench gates 302 are provided in correspondence with each other in the gate trenches T1, thereby further reducing the area of ​​the semiconductor body 100 and further reducing the on-resistance of the semiconductor device.

[0111] like Figure 14 As shown, Figure 14 FIG. 1 is a flow chart of another method for manufacturing a semiconductor device provided by an embodiment of the present invention, the method comprising the following steps:

[0112] S310. Provide a semiconductor body, the semiconductor body including a first surface and a second surface disposed opposite to each other, the semiconductor body further including a well region and a first region, the first region being configured to have a first conductivity type and located on the first surface, and the well region being configured to have a second conductivity type and located on a side of the first region away from the first surface. A gate trench and a source trench are provided on the first surface, the gate trench and the source trench extending from the first surface into the semiconductor body.

[0113] like Figure 15 As shown, a semiconductor body 100 is provided, and the semiconductor body 100 includes a first surface 101 and a second surface 102 disposed opposite to each other. A well region 103 and a first region 104 are formed in the semiconductor body 100 by ion implantation and high-temperature annealing processes. The first region 104 is configured to have a first conductivity type and is located on the first surface 101. The well region 103 is configured to have a second conductivity type and is located on a side of the first region 104 away from the first surface 101.

[0114] like Figure 16 As shown, a source trench T2 is formed on the first surface 101 by a trench etching process, a sacrificial oxide layer preparation process, and an oxide layer removal process. The source trench T2 extends from the first surface 101 into the semiconductor body 100 .

[0115] Alternatively, as Figure 17A second region 105 is formed in the semiconductor body 100 through ion doping and high-temperature annealing processes. The second region 105 is configured as the second conductivity type and surrounds the bottom surface and sidewalls of the source trench T2. The ion concentration of the second region 105 is greater than the ion concentration of the well region 103. Optionally, the source trench T2 includes a V-shaped trench or a U-shaped trench. Compared to a U-shaped trench, a V-shaped trench reduces the area occupied by the semiconductor body 100, thereby reducing the on-resistance of the semiconductor device.

[0116] like Figure 18 As shown, a gate trench T1 is formed on the first surface 101 by a trench etching process, a sacrificial oxide layer preparation process, and an oxide layer removal process. The gate trench T1 extends from the first surface 101 into the semiconductor body 100 .

[0117] In other optional embodiments provided in the embodiment of the present invention, the gate trench T1 and the source trench T2 may be formed before forming the well region 103 , the first region 104 , and the second region 105 .

[0118] S320 , forming a two-dimensional material layer on a sidewall of the gate trench, wherein the two-dimensional material layer is set to a first conductive type, and the carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide.

[0119] like Figure 19 As shown, a two-dimensional material layer 200 is formed on the sidewall of the gate trench T1 through a deposition process. The two-dimensional material layer 200 is set to a first conductivity type, and the carrier mobility of the two-dimensional material layer 200 is greater than the carrier mobility of silicon carbide.

[0120] S330 , forming a first insulating layer on the sidewall of the gate trench, the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer.

[0121] S340 , forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench.

[0122] S350 , forming a second insulating layer on the bottom surface and sidewalls of the source trench.

[0123] S360 , forming a filling layer on a side of the second insulating layer in the source trench away from the semiconductor body.

[0124] like Figure 19 As shown, a first insulating layer 301 is formed in the gate trench T1 by oxidation or deposition. A trench gate 302 is also formed in the gate trench T1 by deposition. The first insulating layer 301 is located on the sidewalls and bottom of the gate trench T1 and covers the two-dimensional material layer 200. The trench gate 302 is located in the gate trench T1 on the side of the first insulating layer 301 away from the semiconductor body 100.

[0125] like Figure 19 As shown, a second insulating layer 401 is formed on the bottom surface and sidewalls of the source trench T2 by oxidation or deposition. For example, the second insulating layer 401 can be made of insulating materials such as silicon oxide or silicon nitride.

[0126] like Figure 19 As shown, a filling layer 402 is formed by a deposition process on the side of the second insulating layer 401 in the source trench T2 away from the semiconductor body 100. For example, the filling layer 402 can be made of polysilicon. The second insulating layer 401 and the filling layer 402 constitute the source trench structure 400.

[0127] S370 , forming a source on the first surface.

[0128] like Figure 3 As shown, a metal layer deposition process forms a source electrode 404 on the first surface 101 , and the source electrode 404 covers the second insulating layer 401 and the filling layer 402 .

[0129] S380 , forming a drain on the second surface.

[0130] like Figure 3 As shown, a drain electrode 500 is formed on the second surface 102 by a backside metal deposition process.

[0131] Based on the above technical solution, the source trench structure 400 can effectively reduce the peak electric field below the first insulating layer 301 of the trench-type gate trench T1 close to the second surface 102 , thereby improving the withstand voltage performance of the semiconductor device.

[0132] In other optional embodiments, the number of gate trenches T1 may also be multiple. Two-dimensional material layers 200 are disposed in a one-to-one correspondence within the sidewalls of the gate trenches T1, and trench gates 302 are disposed in a one-to-one correspondence within the gate trenches T1, further reducing the area of ​​the semiconductor body 100, thereby further reducing the on-resistance of the semiconductor device, while also increasing the gate control capability of the trench gates 302.

[0133] Optionally, based on the above technical solution, before forming the second insulating layer on the bottom surface and sidewalls of the source trench, S350 further includes:

[0134] A second region is formed in the semiconductor body, the second region is set to the second conductivity type and surrounds the bottom surface and side walls of the source trench, the doping concentration of the second region is greater than the doping concentration of the well region; the vertical distance between the second region and the second surface is less than the vertical distance between the gate trench and the second surface.

[0135] like Figure 17 and Figure 19As shown, a second region 105 is formed in the semiconductor body 100, the second region 105 is set to the second conductivity type and surrounds the bottom surface and sidewall of the source trench T2, and the doping concentration of the second region 105 is greater than the doping concentration of the well region 103; the vertical distance d1 between the second region 105 and the second surface 102 is less than the vertical distance d2 between the gate trench T1 and the second surface 102.

[0136] Specifically, on the one hand, the second region 105 can form a good ohmic contact with the source 404; on the other hand, the vertical distance d1 between the second region 105 and the second surface 102 is smaller than the vertical distance d2 between the gate trench T1 and the second surface 102. The drift layer between the second region 105 and the second surface 102 forms a depletion layer, which can further reduce the peak electric field below the first insulating layer 301 of the trench gate 302 close to the second surface 102, thereby further improving the voltage resistance performance of the semiconductor device.

[0137] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further elaborated herein.

[0138] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0139] Therefore, the power conversion circuit includes the beneficial effects of the semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0140] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0141] Therefore, the beneficial effects of the vehicle including any power conversion circuit package described in any embodiment of the present invention will not be repeated here.

[0142] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0143] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body comprising a first surface and a second surface disposed opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being of a first conductivity type and located on the first surface, the well region being of a second conductivity type and located on a side of the first region away from the first surface; a gate trench being further disposed on the first surface, the gate trench extending from the first surface into the semiconductor body; and a first insulating layer being disposed on sidewalls of the gate trench. a two-dimensional material layer, the two-dimensional material layer being of a first conductivity type and being located on a sidewall of the gate trench; the two-dimensional material layer being located between the first region and the first insulating layer, and the two-dimensional material layer being located between the well region and the first insulating layer; The carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide; a trench gate, the trench gate being located in the gate trench on a side of the first insulating layer away from the semiconductor body; a source electrode, located on the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The two-dimensional material layer has the same carrier mobility in different directions.

3. The semiconductor device according to claim 1, wherein The gate trench includes a V-shaped trench or a U-shaped trench.

4. The semiconductor device according to claim 1, wherein The first surface is provided with a plurality of gate trenches, and the plurality of gate trenches are located on the first surface and are arranged at intervals.

5. The semiconductor device according to claim 1, wherein The first surface is further provided with a source trench, wherein the source trench extends from the first surface into the semiconductor body; The semiconductor device further includes a source trench structure, wherein the source trench structure includes a filling layer and a second insulating layer; The second insulating layer is located on the bottom surface and sidewalls of the source trench; the filling layer is located on a side of the source trench away from the second insulating layer and away from the semiconductor body.

6. The semiconductor device according to claim 5, wherein The semiconductor body further includes a second region, which is set to a second conductivity type and surrounds the bottom surface and sidewalls of the source trench, and the ion concentration of the second region is greater than the ion concentration of the well region; A vertical distance between the second region and the second surface is smaller than a vertical distance between the gate trench and the second surface.

7. The semiconductor device according to claim 5, wherein The source trench includes a V-shaped trench or a U-shaped trench.

8. The semiconductor device according to claim 1, wherein The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

9. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface disposed opposite to each other, the semiconductor body further comprising a well region and a first region, the first region being configured to be of a first conductivity type and located on the first surface, the well region being configured to be of a second conductivity type and located on a side of the first region away from the first surface; a gate trench being provided on the first surface, the gate trench extending from the first surface into the semiconductor body; forming a two-dimensional material layer on a sidewall of the gate trench, wherein the two-dimensional material layer is set to a first conductivity type, and the carrier mobility of the two-dimensional material layer is greater than the carrier mobility of silicon carbide; forming a first insulating layer on a sidewall of the gate trench, wherein the two-dimensional material layer is located between the first region and the first insulating layer, and the two-dimensional material layer is located between the well region and the first insulating layer; forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; forming a source electrode on the first surface; A drain electrode is formed on the second surface.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a two-dimensional material layer on the sidewall of the gate trench includes: A two-dimensional material layer having the same carrier mobility in different directions is formed on the sidewall of the gate trench.

11. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a gate trench on the first surface includes: A gate trench including a V-shaped trench or a U-shaped trench is formed on the first surface.

12. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a gate trench on the first surface includes: A plurality of gate trenches are formed on the first surface. The plurality of gate trenches are located on the first surface and are spaced apart.

13. The method for manufacturing a semiconductor device according to claim 9, wherein: Before forming a source electrode on the first surface, the method includes: forming a source trench on the first surface, wherein the source trench extends from the first surface into the semiconductor body; forming a second insulating layer on the bottom surface and sidewalls of the source trench; A filling layer is formed on a side of the second insulating layer in the source trench away from the semiconductor body.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: Before forming the second insulating layer on the bottom surface and sidewalls of the source trench, the method further includes: forming a second region in the semiconductor body, wherein the second region is set to a second conductivity type and surrounds the bottom surface and sidewalls of the source trench, and the doping concentration of the second region is greater than the doping concentration of the well region; A vertical distance between the second region and the second surface is smaller than a vertical distance between the gate trench and the second surface.

15. The method for manufacturing a semiconductor device according to claim 13, wherein: Forming a source trench on the first surface includes: A source trench including a V-shaped trench or a U-shaped trench is formed on the first surface.

16. The method for manufacturing a semiconductor device according to claim 9, wherein: Semiconductors provided include: A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

17. The method for manufacturing a semiconductor device according to claim 9, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; forming a well region on the first surface, wherein the well region is set to a second conductivity type; forming a first region on the first surface, wherein the first region is set to be of a first conductivity type; and the well region is located on a side of the first region away from the first surface; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body; Alternatively, providing the semiconductor body comprises: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body; forming a well region on the first surface, wherein the well region is set to a second conductivity type; A first region is formed on the first surface, and the first region is set to be of a first conductivity type; the well region is located on a side of the first region away from the first surface.

18. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 8, wherein the substrate is used to support the semiconductor device.

19. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 8, wherein the semiconductor device is electrically connected to the circuit board.

20. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 19, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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